Merge branch 'for-rmk/hw-breakpoint' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into devel-stable

4 files changed, 62 insertions, 18 deletions

diff --git a/arch/arm/include/asm/cti.h b/arch/arm/include/asm/cti.h
index f2e5cad3f306..2381199acb7d 100644
--- a/arch/arm/include/asm/cti.h
+++ b/arch/arm/include/asm/cti.h
@@ -2,6 +2,7 @@
 #define __ASMARM_CTI_H
 
 #include        <asm/io.h>
+#include        <asm/hardware/coresight.h>
 
 /* The registers' definition is from section 3.2 of
  * Embedded Cross Trigger Revision: r0p0
@@ -35,11 +36,6 @@
 #define         LOCKACCESS              0xFB0
 #define         LOCKSTATUS              0xFB4
 
-/* write this value to LOCKACCESS will unlock the module, and
- * other value will lock the module
- */
-#define         LOCKCODE                0xC5ACCE55
-
 /**
  * struct cti - cross trigger interface struct
  * @base: mapped virtual address for the cti base
@@ -146,7 +142,7 @@ static inline void cti_irq_ack(struct cti *cti)
  */
 static inline void cti_unlock(struct cti *cti)
 {
-        __raw_writel(LOCKCODE, cti->base + LOCKACCESS);
+        __raw_writel(CS_LAR_KEY, cti->base + LOCKACCESS);
 }
 
 /**
@@ -158,6 +154,6 @@ static inline void cti_unlock(struct cti *cti)
  */
 static inline void cti_lock(struct cti *cti)
 {
-        __raw_writel(~LOCKCODE, cti->base + LOCKACCESS);
+        __raw_writel(~CS_LAR_KEY, cti->base + LOCKACCESS);
 }
 #endif
diff --git a/arch/arm/include/asm/hardware/coresight.h b/arch/arm/include/asm/hardware/coresight.h
index 7ecd793b8f5a..0cf7a6b842ff 100644
--- a/arch/arm/include/asm/hardware/coresight.h
+++ b/arch/arm/include/asm/hardware/coresight.h
@@ -36,7 +36,7 @@
 /* CoreSight Component Registers */
 #define CSCR_CLASS      0xff4
 
-#define UNLOCK_MAGIC    0xc5acce55
+#define CS_LAR_KEY      0xc5acce55
 
 /* ETM control register, "ETM Architecture", 3.3.1 */
 #define ETMR_CTRL               0
@@ -147,11 +147,11 @@
 
 #define etm_lock(t) do { etm_writel((t), 0, CSMR_LOCKACCESS); } while (0)
 #define etm_unlock(t) \
-        do { etm_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+        do { etm_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
 
 #define etb_lock(t) do { etb_writel((t), 0, CSMR_LOCKACCESS); } while (0)
 #define etb_unlock(t) \
-        do { etb_writel((t), UNLOCK_MAGIC, CSMR_LOCKACCESS); } while (0)
+        do { etb_writel((t), CS_LAR_KEY, CSMR_LOCKACCESS); } while (0)
 
 #endif /* __ASM_HARDWARE_CORESIGHT_H */
 
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index 01169dd723f1..eef55ea9ef00 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -85,6 +85,9 @@ static inline void decode_ctrl_reg(u32 reg,
 #define ARM_DSCR_HDBGEN         (1 << 14)
 #define ARM_DSCR_MDBGEN         (1 << 15)
 
+/* OSLSR os lock model bits */
+#define ARM_OSLSR_OSLM0         (1 << 0)
+
 /* opcode2 numbers for the co-processor instructions. */
 #define ARM_OP2_BVR             4
 #define ARM_OP2_BCR             5
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index 5ff2e77782b1..5eae53e7a2e1 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -28,6 +28,7 @@
 #include <linux/perf_event.h>
 #include <linux/hw_breakpoint.h>
 #include <linux/smp.h>
+#include <linux/cpu_pm.h>
 
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
@@ -35,6 +36,7 @@
 #include <asm/hw_breakpoint.h>
 #include <asm/kdebug.h>
 #include <asm/traps.h>
+#include <asm/hardware/coresight.h>
 
 /* Breakpoint currently in use for each BRP. */
 static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
@@ -49,6 +51,9 @@ static int core_num_wrps;
 /* Debug architecture version. */
 static u8 debug_arch;
 
+/* Does debug architecture support OS Save and Restore? */
+static bool has_ossr;
+
 /* Maximum supported watchpoint length. */
 static u8 max_watchpoint_len;
 
@@ -903,6 +908,23 @@ static struct undef_hook debug_reg_hook = {
         .fn             = debug_reg_trap,
 };
 
+/* Does this core support OS Save and Restore? */
+static bool core_has_os_save_restore(void)
+{
+        u32 oslsr;
+
+        switch (get_debug_arch()) {
+        case ARM_DEBUG_ARCH_V7_1:
+                return true;
+        case ARM_DEBUG_ARCH_V7_ECP14:
+                ARM_DBG_READ(c1, c1, 4, oslsr);
+                if (oslsr & ARM_OSLSR_OSLM0)
+                        return true;
+        default:
+                return false;
+        }
+}
+
 static void reset_ctrl_regs(void *unused)
 {
         int i, raw_num_brps, err = 0, cpu = smp_processor_id();
@@ -930,11 +952,7 @@ static void reset_ctrl_regs(void *unused)
                 if ((val & 0x1) == 0)
                         err = -EPERM;
 
-                /*
-                 * Check whether we implement OS save and restore.
-                 */
-                ARM_DBG_READ(c1, c1, 4, val);
-                if ((val & 0x9) == 0)
+                if (!has_ossr)
                         goto clear_vcr;
                 break;
         case ARM_DEBUG_ARCH_V7_1:
@@ -955,9 +973,9 @@ static void reset_ctrl_regs(void *unused)
 
         /*
          * Unconditionally clear the OS lock by writing a value
-         * other than 0xC5ACCE55 to the access register.
+         * other than CS_LAR_KEY to the access register.
          */
-        ARM_DBG_WRITE(c1, c0, 4, 0);
+        ARM_DBG_WRITE(c1, c0, 4, ~CS_LAR_KEY);
         isb();
 
         /*
@@ -1015,6 +1033,30 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = {
         .notifier_call = dbg_reset_notify,
 };
 
+#ifdef CONFIG_CPU_PM
+static int dbg_cpu_pm_notify(struct notifier_block *self, unsigned long action,
+                             void *v)
+{
+        if (action == CPU_PM_EXIT)
+                reset_ctrl_regs(NULL);
+
+        return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata dbg_cpu_pm_nb = {
+        .notifier_call = dbg_cpu_pm_notify,
+};
+
+static void __init pm_init(void)
+{
+        cpu_pm_register_notifier(&dbg_cpu_pm_nb);
+}
+#else
+static inline void pm_init(void)
+{
+}
+#endif
+
 static int __init arch_hw_breakpoint_init(void)
 {
         debug_arch = get_debug_arch();
@@ -1024,6 +1066,8 @@ static int __init arch_hw_breakpoint_init(void)
                 return 0;
         }
 
+        has_ossr = core_has_os_save_restore();
+
         /* Determine how many BRPs/WRPs are available. */
         core_num_brps = get_num_brps();
         core_num_wrps = get_num_wrps();
@@ -1062,8 +1106,9 @@ static int __init arch_hw_breakpoint_init(void)
         hook_ifault_code(FAULT_CODE_DEBUG, hw_breakpoint_pending, SIGTRAP,
                         TRAP_HWBKPT, "breakpoint debug exception");
 
-        /* Register hotplug notifier. */
+        /* Register hotplug and PM notifiers. */
         register_cpu_notifier(&dbg_reset_nb);
+        pm_init();
         return 0;
 }
 arch_initcall(arch_hw_breakpoint_init);