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authorJan Beulich <jbeulich@novell.com>2009-03-12 08:37:34 -0400
committerIngo Molnar <mingo@elte.hu>2009-03-12 21:37:17 -0400
commit13c6c53282d99c82e79b02477efd2c1e30a991ef (patch)
tree71c7b82f94e23ead15f49e4081937bd8d748cef5
parent46d50c98d90cd7feaa5977a09c574063e5c99b3d (diff)
x86, 32-bit: also use cpuinfo_x86's x86_{phys,virt}_bits members
Impact: 32/64-bit consolidation In a first step, this allows fixing phys_addr_valid() for PAE (which until now reported all addresses to be valid). Subsequently, this will also allow simplifying some MTRR handling code. Signed-off-by: Jan Beulich <jbeulich@novell.com> LKML-Reference: <49B9101E.76E4.0078.0@novell.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
-rw-r--r--arch/x86/include/asm/processor.h2
-rw-r--r--arch/x86/kernel/cpu/common.c12
-rw-r--r--arch/x86/kernel/cpu/intel.c5
-rw-r--r--arch/x86/mm/ioremap.c17
4 files changed, 25 insertions, 11 deletions
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 76139506c3e4..bd3406db1d68 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -75,9 +75,9 @@ struct cpuinfo_x86 {
75#else 75#else
76 /* Number of 4K pages in DTLB/ITLB combined(in pages): */ 76 /* Number of 4K pages in DTLB/ITLB combined(in pages): */
77 int x86_tlbsize; 77 int x86_tlbsize;
78#endif
78 __u8 x86_virt_bits; 79 __u8 x86_virt_bits;
79 __u8 x86_phys_bits; 80 __u8 x86_phys_bits;
80#endif
81 /* CPUID returned core id bits: */ 81 /* CPUID returned core id bits: */
82 __u8 x86_coreid_bits; 82 __u8 x86_coreid_bits;
83 /* Max extended CPUID function supported: */ 83 /* Max extended CPUID function supported: */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 826d5c876278..a95e9480bb9c 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -549,13 +549,15 @@ static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
549 } 549 }
550 } 550 }
551 551
552#ifdef CONFIG_X86_64
553 if (c->extended_cpuid_level >= 0x80000008) { 552 if (c->extended_cpuid_level >= 0x80000008) {
554 u32 eax = cpuid_eax(0x80000008); 553 u32 eax = cpuid_eax(0x80000008);
555 554
556 c->x86_virt_bits = (eax >> 8) & 0xff; 555 c->x86_virt_bits = (eax >> 8) & 0xff;
557 c->x86_phys_bits = eax & 0xff; 556 c->x86_phys_bits = eax & 0xff;
558 } 557 }
558#ifdef CONFIG_X86_32
559 else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
560 c->x86_phys_bits = 36;
559#endif 561#endif
560 562
561 if (c->extended_cpuid_level >= 0x80000007) 563 if (c->extended_cpuid_level >= 0x80000007)
@@ -602,8 +604,12 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
602{ 604{
603#ifdef CONFIG_X86_64 605#ifdef CONFIG_X86_64
604 c->x86_clflush_size = 64; 606 c->x86_clflush_size = 64;
607 c->x86_phys_bits = 36;
608 c->x86_virt_bits = 48;
605#else 609#else
606 c->x86_clflush_size = 32; 610 c->x86_clflush_size = 32;
611 c->x86_phys_bits = 32;
612 c->x86_virt_bits = 32;
607#endif 613#endif
608 c->x86_cache_alignment = c->x86_clflush_size; 614 c->x86_cache_alignment = c->x86_clflush_size;
609 615
@@ -726,9 +732,13 @@ static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
726 c->x86_coreid_bits = 0; 732 c->x86_coreid_bits = 0;
727#ifdef CONFIG_X86_64 733#ifdef CONFIG_X86_64
728 c->x86_clflush_size = 64; 734 c->x86_clflush_size = 64;
735 c->x86_phys_bits = 36;
736 c->x86_virt_bits = 48;
729#else 737#else
730 c->cpuid_level = -1; /* CPUID not detected */ 738 c->cpuid_level = -1; /* CPUID not detected */
731 c->x86_clflush_size = 32; 739 c->x86_clflush_size = 32;
740 c->x86_phys_bits = 32;
741 c->x86_virt_bits = 32;
732#endif 742#endif
733 c->x86_cache_alignment = c->x86_clflush_size; 743 c->x86_cache_alignment = c->x86_clflush_size;
734 memset(&c->x86_capability, 0, sizeof c->x86_capability); 744 memset(&c->x86_capability, 0, sizeof c->x86_capability);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 191117f1ad51..ae769471042e 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -54,6 +54,11 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
54 c->x86_cache_alignment = 128; 54 c->x86_cache_alignment = 128;
55#endif 55#endif
56 56
57 /* CPUID workaround for 0F33/0F34 CPU */
58 if (c->x86 == 0xF && c->x86_model == 0x3
59 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
60 c->x86_phys_bits = 36;
61
57 /* 62 /*
58 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 63 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
59 * with P/T states and does not stop in deep C-states 64 * with P/T states and does not stop in deep C-states
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index aca924a30ee6..83ed74affba9 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -22,13 +22,17 @@
22#include <asm/pgalloc.h> 22#include <asm/pgalloc.h>
23#include <asm/pat.h> 23#include <asm/pat.h>
24 24
25#ifdef CONFIG_X86_64 25static inline int phys_addr_valid(resource_size_t addr)
26
27static inline int phys_addr_valid(unsigned long addr)
28{ 26{
29 return addr < (1UL << boot_cpu_data.x86_phys_bits); 27#ifdef CONFIG_PHYS_ADDR_T_64BIT
28 return !(addr >> boot_cpu_data.x86_phys_bits);
29#else
30 return 1;
31#endif
30} 32}
31 33
34#ifdef CONFIG_X86_64
35
32unsigned long __phys_addr(unsigned long x) 36unsigned long __phys_addr(unsigned long x)
33{ 37{
34 if (x >= __START_KERNEL_map) { 38 if (x >= __START_KERNEL_map) {
@@ -65,11 +69,6 @@ EXPORT_SYMBOL(__virt_addr_valid);
65 69
66#else 70#else
67 71
68static inline int phys_addr_valid(unsigned long addr)
69{
70 return 1;
71}
72
73#ifdef CONFIG_DEBUG_VIRTUAL 72#ifdef CONFIG_DEBUG_VIRTUAL
74unsigned long __phys_addr(unsigned long x) 73unsigned long __phys_addr(unsigned long x)
75{ 74{