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authorPaul Walmsley <paul@pwsan.com>2012-10-21 03:01:10 -0400
committerPaul Walmsley <paul@pwsan.com>2012-10-21 03:01:10 -0400
commit139563ad27e7baad7935b8113940f0d804cf513b (patch)
treef367d3813f1fb83773782537ad658f3cf3bb0508
parent7a0c19337c38a1ffa7587272e7784e6431e78eaa (diff)
ARM: OMAP2+: PRM: split PRM functions into OMAP2, OMAP3-specific files
Move OMAP3xxx-specific PRM functions & macros into prm3xxx.[ch] and OMAP2xxx-specific macros into prm2xxx.h. (prm2xxx.c will be created by a subsequent patch when it's needed.) Move basic PRM register access functions into static inline functions in prm2xxx_3xxx.h, leaving only OMAP2/3 hardreset functions in prm2xxx_3xxx.c. Also clarify the initcall function naming to reinforce that this code is specifically for the PRM IP block. This is in preparation for the upcoming powerdomain series and the upcoming move of this code to drivers/. Signed-off-by: Paul Walmsley <paul@pwsan.com> Reviewed-by: Russ Dill <Russ.Dill@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/Makefile100
-rw-r--r--arch/arm/mach-omap2/control.c2
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c2
-rw-r--r--arch/arm/mach-omap2/pm24xx.c2
-rw-r--r--arch/arm/mach-omap2/pm34xx.c2
-rw-r--r--arch/arm/mach-omap2/prm-regbits-24xx.h2
-rw-r--r--arch/arm/mach-omap2/prm-regbits-34xx.h2
-rw-r--r--arch/arm/mach-omap2/prm2xxx.h122
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.c265
-rw-r--r--arch/arm/mach-omap2/prm2xxx_3xxx.h256
-rw-r--r--arch/arm/mach-omap2/prm3xxx.c233
-rw-r--r--arch/arm/mach-omap2/prm3xxx.h158
-rw-r--r--arch/arm/mach-omap2/prm44xx.c15
-rw-r--r--arch/arm/mach-omap2/sdrc2xxx.c2
-rw-r--r--arch/arm/mach-omap2/sleep34xx.S2
-rw-r--r--arch/arm/mach-omap2/sram242x.S2
-rw-r--r--arch/arm/mach-omap2/sram243x.S2
17 files changed, 638 insertions, 531 deletions
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fe40d9e488c9..20849604be94 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,30 +4,36 @@
4 4
5# Common support 5# Common support
6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \ 6obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
7 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o 7 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
8 8
9# INTCPS IP block support - XXX should be moved to drivers/ 9omap-2-3-common = irq.o
10obj-$(CONFIG_ARCH_OMAP2) += irq.o 10hwmod-common = omap_hwmod.o \
11obj-$(CONFIG_ARCH_OMAP3) += irq.o 11 omap_hwmod_common_data.o
12obj-$(CONFIG_SOC_AM33XX) += irq.o 12clock-common = clock.o clock_common_data.o \
13 clkt_dpll.o clkt_clksel.o
14secure-common = omap-smc.o omap-secure.o
13 15
14# Secure monitor API support 16obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
15obj-$(CONFIG_ARCH_OMAP3) += omap-smc.o omap-secure.o 17obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
16obj-$(CONFIG_ARCH_OMAP4) += omap-smc.o omap-secure.o 18obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
17obj-$(CONFIG_SOC_OMAP5) += omap-smc.o omap-secure.o 19obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
20obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
18 21
19ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) 22ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
20obj-y += mcbsp.o 23obj-y += mcbsp.o
21endif 24endif
22 25
23obj-$(CONFIG_TWL4030_CORE) += omap_twl.o 26obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
27obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
24 28
25# SMP support ONLY available for OMAP4 29# SMP support ONLY available for OMAP4
26 30
27obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o 31obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
28obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o 32obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
29obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o 33omap-4-5-common = omap4-common.o omap-wakeupgen.o \
30obj-$(CONFIG_SOC_OMAP5) += omap4-common.o omap-wakeupgen.o 34 sleep44xx.o
35obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
36obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common)
31 37
32plus_sec := $(call as-instr,.arch_extension sec,+sec) 38plus_sec := $(call as-instr,.arch_extension sec,+sec)
33AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) 39AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -52,7 +58,6 @@ obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
52# SMS/SDRC 58# SMS/SDRC
53obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o 59obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
54# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o 60# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
55obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
56 61
57# OPP table initialization 62# OPP table initialization
58ifeq ($(CONFIG_PM_OPP),y) 63ifeq ($(CONFIG_PM_OPP),y)
@@ -63,15 +68,15 @@ endif
63 68
64# Power Management 69# Power Management
65ifeq ($(CONFIG_PM),y) 70ifeq ($(CONFIG_PM),y)
66obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o sleep24xx.o 71obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
72obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
67obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o 73obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
68obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o 74obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
69obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o 75obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
70obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o sleep44xx.o
71obj-$(CONFIG_PM_DEBUG) += pm-debug.o 76obj-$(CONFIG_PM_DEBUG) += pm-debug.o
72 77
73obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o 78obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
74obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o 79obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
75 80
76AFLAGS_sleep24xx.o :=-Wa,-march=armv6 81AFLAGS_sleep24xx.o :=-Wa,-march=armv6
77AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec) 82AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -83,76 +88,88 @@ endif
83endif 88endif
84 89
85ifeq ($(CONFIG_CPU_IDLE),y) 90ifeq ($(CONFIG_CPU_IDLE),y)
86obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o 91obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
87obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o 92obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
88endif 93endif
89 94
90# PRCM 95# PRCM
91obj-y += prcm.o prm_common.o 96obj-y += prcm.o prm_common.o
92obj-$(CONFIG_ARCH_OMAP2) += cm2xxx_3xxx.o prm2xxx_3xxx.o 97obj-$(CONFIG_ARCH_OMAP2) += cm2xxx_3xxx.o prm2xxx_3xxx.o
93obj-$(CONFIG_ARCH_OMAP3) += cm2xxx_3xxx.o prm2xxx_3xxx.o 98obj-$(CONFIG_ARCH_OMAP3) += cm2xxx_3xxx.o prm2xxx_3xxx.o
99obj-$(CONFIG_ARCH_OMAP3) += prm3xxx.o
94obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o 100obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
95obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o 101obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
96omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \ 102omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
97 prcm_mpu44xx.o prminst44xx.o \ 103 prcm_mpu44xx.o prminst44xx.o \
98 vc44xx_data.o vp44xx_data.o \ 104 vc44xx_data.o vp44xx_data.o
99 prm44xx.o
100obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) 105obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
101obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) 106obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
102 107
103# OMAP voltage domains 108# OMAP voltage domains
104obj-y += voltage.o vc.o vp.o 109voltagedomain-common := voltage.o vc.o vp.o
110obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
105obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o 111obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o
112obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
106obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o 113obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
114obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
107obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o 115obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
108obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o 116obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
117obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
118obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
109 119
110# OMAP powerdomain framework 120# OMAP powerdomain framework
111obj-y += powerdomain.o powerdomain-common.o 121powerdomain-common += powerdomain.o powerdomain-common.o
122obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common)
112obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o 123obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o
113obj-$(CONFIG_ARCH_OMAP2) += powerdomain2xxx_3xxx.o
114obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o 124obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o
115obj-$(CONFIG_ARCH_OMAP3) += powerdomain2xxx_3xxx.o 125obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common)
116obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o 126obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o
117obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o 127obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
118obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o 128obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
119obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o 129obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
120obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o 130obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
121obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o 131obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
122obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o 132obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
123 133
124# PRCM clockdomain control 134# PRCM clockdomain control
125obj-y += clockdomain.o 135clockdomain-common += clockdomain.o
136obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
126obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o 137obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o
127obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o 138obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
128obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o 139obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
129obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o 140obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
141obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common)
130obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o 142obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o
131obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o 143obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
132obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o 144obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
145obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
133obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o 146obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
134obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o 147obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
148obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
135obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o 149obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
136obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o 150obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
151obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
137obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o 152obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o
138 153
139# Clock framework 154# Clock framework
140obj-y += clock.o clock_common_data.o \ 155obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
141 clkt_dpll.o clkt_clksel.o 156obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o
142obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o 157obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
143obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o clkt2xxx_sys.o
144obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o 158obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
145obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o 159obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o
146obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o 160obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
147obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o 161obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o
148obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o 162obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o
149obj-$(CONFIG_ARCH_OMAP3) += clock3xxx.o 163obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
150obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o 164obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
151obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o clkt_iclk.o 165obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
152obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o 166obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o
153obj-$(CONFIG_ARCH_OMAP4) += clock44xx_data.o 167obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
168obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
154obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o 169obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
155obj-$(CONFIG_SOC_AM33XX) += dpll3xxx.o clock33xx_data.o 170obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
171obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o
172obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
156obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o 173obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
157 174
158# OMAP2 clock rate set data (old "OPP" data) 175# OMAP2 clock rate set data (old "OPP" data)
@@ -160,7 +177,6 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
160obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o 177obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
161 178
162# hwmod data 179# hwmod data
163obj-y += omap_hwmod_common_data.o
164obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o 180obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
165obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o 181obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
166obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o 182obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
@@ -206,10 +222,10 @@ obj-$(CONFIG_MACH_OMAP_H4) += board-h4.o
206obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o 222obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
207obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o 223obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
208obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o 224obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
209obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o 225obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o
210obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o 226obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
211obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o 227obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
212obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o 228obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
213obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o 229obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o
214obj-$(CONFIG_MACH_OVERO) += board-overo.o 230obj-$(CONFIG_MACH_OVERO) += board-overo.o
215obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o 231obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index d1ff8399a222..1220e0ef0b86 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -22,7 +22,7 @@
22#include "common.h" 22#include "common.h"
23#include "cm-regbits-34xx.h" 23#include "cm-regbits-34xx.h"
24#include "prm-regbits-34xx.h" 24#include "prm-regbits-34xx.h"
25#include "prm2xxx_3xxx.h" 25#include "prm3xxx.h"
26#include "cm2xxx_3xxx.h" 26#include "cm2xxx_3xxx.h"
27#include "sdrc.h" 27#include "sdrc.h"
28#include "pm.h" 28#include "pm.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index b969ab1d258b..525c58d25730 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -150,7 +150,7 @@
150#include "cm2xxx_3xxx.h" 150#include "cm2xxx_3xxx.h"
151#include "cminst44xx.h" 151#include "cminst44xx.h"
152#include "cm33xx.h" 152#include "cm33xx.h"
153#include "prm2xxx_3xxx.h" 153#include "prm3xxx.h"
154#include "prm44xx.h" 154#include "prm44xx.h"
155#include "prm33xx.h" 155#include "prm33xx.h"
156#include "prminst44xx.h" 156#include "prminst44xx.h"
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 8af6cd6ac331..78405a7fb99e 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -41,7 +41,7 @@
41#include <plat/dma.h> 41#include <plat/dma.h>
42 42
43#include "common.h" 43#include "common.h"
44#include "prm2xxx_3xxx.h" 44#include "prm2xxx.h"
45#include "prm-regbits-24xx.h" 45#include "prm-regbits-24xx.h"
46#include "cm2xxx_3xxx.h" 46#include "cm2xxx_3xxx.h"
47#include "cm-regbits-24xx.h" 47#include "cm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index ba670db1fd37..c02c9ca9ef05 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -48,7 +48,7 @@
48#include "cm-regbits-34xx.h" 48#include "cm-regbits-34xx.h"
49#include "prm-regbits-34xx.h" 49#include "prm-regbits-34xx.h"
50 50
51#include "prm2xxx_3xxx.h" 51#include "prm3xxx.h"
52#include "pm.h" 52#include "pm.h"
53#include "sdrc.h" 53#include "sdrc.h"
54#include "control.h" 54#include "control.h"
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 6ac966103f34..bd70a5a04291 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -14,7 +14,7 @@
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17#include "prm2xxx_3xxx.h" 17#include "prm2xxx.h"
18 18
19/* Bits shared between registers */ 19/* Bits shared between registers */
20 20
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index 64c087af6a8b..073d4db8aa5c 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -14,7 +14,7 @@
14#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H 14#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H
15 15
16 16
17#include "prm2xxx_3xxx.h" 17#include "prm3xxx.h"
18 18
19/* Shared register bits */ 19/* Shared register bits */
20 20
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
new file mode 100644
index 000000000000..6490e1a580e8
--- /dev/null
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -0,0 +1,122 @@
1/*
2 * OMAP2xxx Power/Reset Management (PRM) register definitions
3 *
4 * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The PRM hardware modules on the OMAP2/3 are quite similar to each
13 * other. The PRM on OMAP4 has a new register layout, and is handled
14 * in a separate file.
15 */
16#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
17#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_H
18
19#include "prcm-common.h"
20#include "prm.h"
21#include "prm2xxx_3xxx.h"
22
23#define OMAP2420_PRM_REGADDR(module, reg) \
24 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
25#define OMAP2430_PRM_REGADDR(module, reg) \
26 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
27
28/*
29 * OMAP2-specific global PRM registers
30 * Use __raw_{read,write}l() with these registers.
31 *
32 * With a few exceptions, these are the register names beginning with
33 * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
34 * bits.)
35 *
36 */
37
38#define OMAP2_PRCM_REVISION_OFFSET 0x0000
39#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
40#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
41#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
42
43#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
44#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
45#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
46#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
47
48#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
49#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
50#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
51#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
52#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
53#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
54#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
55#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
56#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
57#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
58#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
59#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
60#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
61#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
62#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
63#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
64#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
65#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
66#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
67#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
68
69#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
70#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
71
72#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
73#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
74
75#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
76#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
77#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
78#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
79#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
80#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
81#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
82#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
83#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
84#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
85
86/*
87 * Module specific PRM register offsets from PRM_BASE + domain offset
88 *
89 * Use prm_{read,write}_mod_reg() with these registers.
90 *
91 * With a few exceptions, these are the register names beginning with
92 * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the
93 * IRQSTATUS and IRQENABLE bits.)
94 */
95
96/* Register offsets appearing on both OMAP2 and OMAP3 */
97
98#define OMAP2_RM_RSTCTRL 0x0050
99#define OMAP2_RM_RSTTIME 0x0054
100#define OMAP2_RM_RSTST 0x0058
101#define OMAP2_PM_PWSTCTRL 0x00e0
102#define OMAP2_PM_PWSTST 0x00e4
103
104#define PM_WKEN 0x00a0
105#define PM_WKEN1 PM_WKEN
106#define PM_WKST 0x00b0
107#define PM_WKST1 PM_WKST
108#define PM_WKDEP 0x00c8
109#define PM_EVGENCTRL 0x00d4
110#define PM_EVGENONTIM 0x00d8
111#define PM_EVGENOFFTIM 0x00dc
112
113/* OMAP2xxx specific register offsets */
114#define OMAP24XX_PM_WKEN2 0x00a4
115#define OMAP24XX_PM_WKST2 0x00b4
116
117#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
118#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
119#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
120#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
121
122#endif
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 9529984d8d2b..0d6cc543987d 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -15,82 +15,11 @@
15#include <linux/errno.h> 15#include <linux/errno.h>
16#include <linux/err.h> 16#include <linux/err.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/irq.h>
19 18
20#include <plat/prcm.h>
21
22#include "soc.h"
23#include "common.h" 19#include "common.h"
24#include "vp.h"
25 20
26#include "prm2xxx_3xxx.h" 21#include "prm2xxx_3xxx.h"
27#include "cm2xxx_3xxx.h"
28#include "prm-regbits-24xx.h" 22#include "prm-regbits-24xx.h"
29#include "prm-regbits-34xx.h"
30
31static const struct omap_prcm_irq omap3_prcm_irqs[] = {
32 OMAP_PRCM_IRQ("wkup", 0, 0),
33 OMAP_PRCM_IRQ("io", 9, 1),
34};
35
36static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
37 .ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
38 .mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
39 .nr_regs = 1,
40 .irqs = omap3_prcm_irqs,
41 .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs),
42 .irq = 11 + OMAP_INTC_START,
43 .read_pending_irqs = &omap3xxx_prm_read_pending_irqs,
44 .ocp_barrier = &omap3xxx_prm_ocp_barrier,
45 .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen,
46 .restore_irqen = &omap3xxx_prm_restore_irqen,
47};
48
49u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
50{
51 return __raw_readl(prm_base + module + idx);
52}
53
54void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
55{
56 __raw_writel(val, prm_base + module + idx);
57}
58
59/* Read-modify-write a register in a PRM module. Caller must lock */
60u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
61{
62 u32 v;
63
64 v = omap2_prm_read_mod_reg(module, idx);
65 v &= ~mask;
66 v |= bits;
67 omap2_prm_write_mod_reg(v, module, idx);
68
69 return v;
70}
71
72/* Read a PRM register, AND it, and shift the result down to bit 0 */
73u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
74{
75 u32 v;
76
77 v = omap2_prm_read_mod_reg(domain, idx);
78 v &= mask;
79 v >>= __ffs(mask);
80
81 return v;
82}
83
84u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
85{
86 return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
87}
88
89u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
90{
91 return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
92}
93
94 23
95/** 24/**
96 * omap2_prm_is_hardreset_asserted - read the HW reset line state of 25 * omap2_prm_is_hardreset_asserted - read the HW reset line state of
@@ -104,9 +33,6 @@ u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
104 */ 33 */
105int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) 34int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift)
106{ 35{
107 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
108 return -EINVAL;
109
110 return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, 36 return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL,
111 (1 << shift)); 37 (1 << shift));
112} 38}
@@ -127,9 +53,6 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift)
127{ 53{
128 u32 mask; 54 u32 mask;
129 55
130 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
131 return -EINVAL;
132
133 mask = 1 << shift; 56 mask = 1 << shift;
134 omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); 57 omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL);
135 58
@@ -156,9 +79,6 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
156 u32 rst, st; 79 u32 rst, st;
157 int c; 80 int c;
158 81
159 if (!(cpu_is_omap24xx() || cpu_is_omap34xx()))
160 return -EINVAL;
161
162 rst = 1 << rst_shift; 82 rst = 1 << rst_shift;
163 st = 1 << st_shift; 83 st = 1 << st_shift;
164 84
@@ -178,188 +98,3 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift)
178 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; 98 return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
179} 99}
180 100
181/* PRM VP */
182
183/*
184 * struct omap3_vp - OMAP3 VP register access description.
185 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
186 */
187struct omap3_vp {
188 u32 tranxdone_status;
189};
190
191static struct omap3_vp omap3_vp[] = {
192 [OMAP3_VP_VDD_MPU_ID] = {
193 .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
194 },
195 [OMAP3_VP_VDD_CORE_ID] = {
196 .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
197 },
198};
199
200#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
201
202u32 omap3_prm_vp_check_txdone(u8 vp_id)
203{
204 struct omap3_vp *vp = &omap3_vp[vp_id];
205 u32 irqstatus;
206
207 irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
208 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
209 return irqstatus & vp->tranxdone_status;
210}
211
212void omap3_prm_vp_clear_txdone(u8 vp_id)
213{
214 struct omap3_vp *vp = &omap3_vp[vp_id];
215
216 omap2_prm_write_mod_reg(vp->tranxdone_status,
217 OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
218}
219
220u32 omap3_prm_vcvp_read(u8 offset)
221{
222 return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
223}
224
225void omap3_prm_vcvp_write(u32 val, u8 offset)
226{
227 omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
228}
229
230u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
231{
232 return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
233}
234
235/**
236 * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
237 * @events: ptr to a u32, preallocated by caller
238 *
239 * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
240 * MPU IRQs, and store the result into the u32 pointed to by @events.
241 * No return value.
242 */
243void omap3xxx_prm_read_pending_irqs(unsigned long *events)
244{
245 u32 mask, st;
246
247 /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
248 mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
249 st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
250
251 events[0] = mask & st;
252}
253
254/**
255 * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
256 *
257 * Force any buffered writes to the PRM IP block to complete. Needed
258 * by the PRM IRQ handler, which reads and writes directly to the IP
259 * block, to avoid race conditions after acknowledging or clearing IRQ
260 * bits. No return value.
261 */
262void omap3xxx_prm_ocp_barrier(void)
263{
264 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
265}
266
267/**
268 * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
269 * @saved_mask: ptr to a u32 array to save IRQENABLE bits
270 *
271 * Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask
272 * must be allocated by the caller. Intended to be used in the PRM
273 * interrupt handler suspend callback. The OCP barrier is needed to
274 * ensure the write to disable PRM interrupts reaches the PRM before
275 * returning; otherwise, spurious interrupts might occur. No return
276 * value.
277 */
278void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
279{
280 saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
281 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
282 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
283
284 /* OCP barrier */
285 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
286}
287
288/**
289 * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
290 * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
291 *
292 * Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended
293 * to be used in the PRM interrupt handler resume callback to restore
294 * values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP
295 * barrier should be needed here; any pending PRM interrupts will fire
296 * once the writes reach the PRM. No return value.
297 */
298void omap3xxx_prm_restore_irqen(u32 *saved_mask)
299{
300 omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
301 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
302}
303
304/**
305 * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
306 *
307 * Clear any previously-latched I/O wakeup events and ensure that the
308 * I/O wakeup gates are aligned with the current mux settings. Works
309 * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
310 * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No
311 * return value.
312 */
313void omap3xxx_prm_reconfigure_io_chain(void)
314{
315 int i = 0;
316
317 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
318 PM_WKEN);
319
320 omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
321 OMAP3430_ST_IO_CHAIN_MASK,
322 MAX_IOPAD_LATCH_TIME, i);
323 if (i == MAX_IOPAD_LATCH_TIME)
324 pr_warn("PRM: I/O chain clock line assertion timed out\n");
325
326 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
327 PM_WKEN);
328
329 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
330 PM_WKST);
331
332 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
333}
334
335/**
336 * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
337 *
338 * Activates the I/O wakeup event latches and allows events logged by
339 * those latches to signal a wakeup event to the PRCM. For I/O
340 * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
341 * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
342 * No return value.
343 */
344static void __init omap3xxx_prm_enable_io_wakeup(void)
345{
346 if (omap3_has_io_wakeup())
347 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
348 PM_WKEN);
349}
350
351static int __init omap3xxx_prcm_init(void)
352{
353 int ret = 0;
354
355 if (cpu_is_omap34xx()) {
356 omap3xxx_prm_enable_io_wakeup();
357 ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
358 if (!ret)
359 irq_set_status_flags(omap_prcm_event_to_irq("io"),
360 IRQ_NOAUTOEN);
361 }
362
363 return ret;
364}
365subsys_initcall(omap3xxx_prcm_init);
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index c19d249b4816..8d09a1ac9311 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * OMAP2/3 Power/Reset Management (PRM) register definitions 2 * OMAP2xxx/3xxx-common Power/Reset Management (PRM) register definitions
3 * 3 *
4 * Copyright (C) 2007-2009, 2011 Texas Instruments, Inc. 4 * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation 5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Paul Walmsley 6 * Paul Walmsley
7 * 7 *
@@ -19,160 +19,6 @@
19#include "prcm-common.h" 19#include "prcm-common.h"
20#include "prm.h" 20#include "prm.h"
21 21
22#define OMAP2420_PRM_REGADDR(module, reg) \
23 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
24#define OMAP2430_PRM_REGADDR(module, reg) \
25 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
26#define OMAP34XX_PRM_REGADDR(module, reg) \
27 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
28
29
30/*
31 * OMAP2-specific global PRM registers
32 * Use __raw_{read,write}l() with these registers.
33 *
34 * With a few exceptions, these are the register names beginning with
35 * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE
36 * bits.)
37 *
38 */
39
40#define OMAP2_PRCM_REVISION_OFFSET 0x0000
41#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000)
42#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010
43#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010)
44
45#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018
46#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018)
47#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c
48#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c)
49
50#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050
51#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050)
52#define OMAP2_PRCM_VOLTST_OFFSET 0x0054
53#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054)
54#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060
55#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060)
56#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070
57#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070)
58#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078
59#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078)
60#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080
61#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080)
62#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084
63#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084)
64#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090
65#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090)
66#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094
67#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094)
68#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098
69#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098)
70
71#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000)
72#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010)
73
74#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018)
75#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c)
76
77#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050)
78#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054)
79#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060)
80#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070)
81#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078)
82#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080)
83#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084)
84#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090)
85#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094)
86#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098)
87
88/*
89 * OMAP3-specific global PRM registers
90 * Use __raw_{read,write}l() with these registers.
91 *
92 * With a few exceptions, these are the register names beginning with
93 * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE
94 * bits.)
95 */
96
97#define OMAP3_PRM_REVISION_OFFSET 0x0004
98#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
99#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
100#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
101
102#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
103#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
104#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
105#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
106
107
108#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
109#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
110#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
111#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
112#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
113#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
114#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
115#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
116#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
117#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
118#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
119#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
120#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
121#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
122#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
123#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
124#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
125#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
126#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
127#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
128#define OMAP3_PRM_RSTST_OFFSET 0x0058
129#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
130#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
131#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
132#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
133#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
134#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
135#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
136#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
137#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
138#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
139#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
140#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
141#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
142#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
143#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
144#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
145#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
146#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
147#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
148#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
149#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
150#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
151#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
152#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
153#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
154#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
155#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
156#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
157#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
158#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
159#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
160#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
161#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
162#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
163#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
164#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
165#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
166#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
167#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
168#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
169#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
170
171#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
172#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
173#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
174#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
175
176/* 22/*
177 * Module specific PRM register offsets from PRM_BASE + domain offset 23 * Module specific PRM register offsets from PRM_BASE + domain offset
178 * 24 *
@@ -200,67 +46,63 @@
200#define PM_EVGENONTIM 0x00d8 46#define PM_EVGENONTIM 0x00d8
201#define PM_EVGENOFFTIM 0x00dc 47#define PM_EVGENOFFTIM 0x00dc
202 48
203/* OMAP2xxx specific register offsets */
204#define OMAP24XX_PM_WKEN2 0x00a4
205#define OMAP24XX_PM_WKST2 0x00b4
206
207#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */
208#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */
209#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8
210#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc
211
212/* OMAP3 specific register offsets */
213#define OMAP3430ES2_PM_WKEN3 0x00f0
214#define OMAP3430ES2_PM_WKST3 0x00b8
215
216#define OMAP3430_PM_MPUGRPSEL 0x00a4
217#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
218#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
219 49
220#define OMAP3430_PM_IVAGRPSEL 0x00a8 50#ifndef __ASSEMBLER__
221#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
222#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
223
224#define OMAP3430_PM_PREPWSTST 0x00e8
225
226#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
227#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
228 51
52#include <linux/io.h>
229 53
230#ifndef __ASSEMBLER__
231/* Power/reset management domain register get/set */ 54/* Power/reset management domain register get/set */
232extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx); 55static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
233extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx); 56{
234extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); 57 return __raw_readl(prm_base + module + idx);
235extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); 58}
236extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); 59
237extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); 60static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
61{
62 __raw_writel(val, prm_base + module + idx);
63}
64
65/* Read-modify-write a register in a PRM module. Caller must lock */
66static inline u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module,
67 s16 idx)
68{
69 u32 v;
70
71 v = omap2_prm_read_mod_reg(module, idx);
72 v &= ~mask;
73 v |= bits;
74 omap2_prm_write_mod_reg(v, module, idx);
75
76 return v;
77}
78
79/* Read a PRM register, AND it, and shift the result down to bit 0 */
80static inline u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
81{
82 u32 v;
83
84 v = omap2_prm_read_mod_reg(domain, idx);
85 v &= mask;
86 v >>= __ffs(mask);
87
88 return v;
89}
90
91static inline u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
92{
93 return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx);
94}
95
96static inline u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
97{
98 return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
99}
238 100
239/* These omap2_ PRM functions apply to both OMAP2 and 3 */ 101/* These omap2_ PRM functions apply to both OMAP2 and 3 */
240extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); 102extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift);
241extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); 103extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift);
242extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift); 104extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 rst_shift, u8 st_shift);
243 105
244/* OMAP3-specific VP functions */
245u32 omap3_prm_vp_check_txdone(u8 vp_id);
246void omap3_prm_vp_clear_txdone(u8 vp_id);
247
248/*
249 * OMAP3 access functions for voltage controller (VC) and
250 * voltage proccessor (VP) in the PRM.
251 */
252extern u32 omap3_prm_vcvp_read(u8 offset);
253extern void omap3_prm_vcvp_write(u32 val, u8 offset);
254extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
255
256extern void omap3xxx_prm_reconfigure_io_chain(void);
257
258/* PRM interrupt-related functions */
259extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
260extern void omap3xxx_prm_ocp_barrier(void);
261extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
262extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
263
264#endif /* __ASSEMBLER */ 106#endif /* __ASSEMBLER */
265 107
266/* 108/*
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
new file mode 100644
index 000000000000..88f7d8de7da9
--- /dev/null
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -0,0 +1,233 @@
1/*
2 * OMAP3xxx PRM module functions
3 *
4 * Copyright (C) 2010-2012 Texas Instruments, Inc.
5 * Copyright (C) 2010 Nokia Corporation
6 * Benoît Cousson
7 * Paul Walmsley
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19
20#include "common.h"
21#include <plat/cpu.h>
22#include <plat/prcm.h>
23
24#include "vp.h"
25
26#include "prm3xxx.h"
27#include "cm2xxx_3xxx.h"
28#include "prm-regbits-34xx.h"
29
30static const struct omap_prcm_irq omap3_prcm_irqs[] = {
31 OMAP_PRCM_IRQ("wkup", 0, 0),
32 OMAP_PRCM_IRQ("io", 9, 1),
33};
34
35static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
36 .ack = OMAP3_PRM_IRQSTATUS_MPU_OFFSET,
37 .mask = OMAP3_PRM_IRQENABLE_MPU_OFFSET,
38 .nr_regs = 1,
39 .irqs = omap3_prcm_irqs,
40 .nr_irqs = ARRAY_SIZE(omap3_prcm_irqs),
41 .irq = 11 + OMAP_INTC_START,
42 .read_pending_irqs = &omap3xxx_prm_read_pending_irqs,
43 .ocp_barrier = &omap3xxx_prm_ocp_barrier,
44 .save_and_clear_irqen = &omap3xxx_prm_save_and_clear_irqen,
45 .restore_irqen = &omap3xxx_prm_restore_irqen,
46};
47
48/* PRM VP */
49
50/*
51 * struct omap3_vp - OMAP3 VP register access description.
52 * @tranxdone_status: VP_TRANXDONE_ST bitmask in PRM_IRQSTATUS_MPU reg
53 */
54struct omap3_vp {
55 u32 tranxdone_status;
56};
57
58static struct omap3_vp omap3_vp[] = {
59 [OMAP3_VP_VDD_MPU_ID] = {
60 .tranxdone_status = OMAP3430_VP1_TRANXDONE_ST_MASK,
61 },
62 [OMAP3_VP_VDD_CORE_ID] = {
63 .tranxdone_status = OMAP3430_VP2_TRANXDONE_ST_MASK,
64 },
65};
66
67#define MAX_VP_ID ARRAY_SIZE(omap3_vp);
68
69u32 omap3_prm_vp_check_txdone(u8 vp_id)
70{
71 struct omap3_vp *vp = &omap3_vp[vp_id];
72 u32 irqstatus;
73
74 irqstatus = omap2_prm_read_mod_reg(OCP_MOD,
75 OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
76 return irqstatus & vp->tranxdone_status;
77}
78
79void omap3_prm_vp_clear_txdone(u8 vp_id)
80{
81 struct omap3_vp *vp = &omap3_vp[vp_id];
82
83 omap2_prm_write_mod_reg(vp->tranxdone_status,
84 OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
85}
86
87u32 omap3_prm_vcvp_read(u8 offset)
88{
89 return omap2_prm_read_mod_reg(OMAP3430_GR_MOD, offset);
90}
91
92void omap3_prm_vcvp_write(u32 val, u8 offset)
93{
94 omap2_prm_write_mod_reg(val, OMAP3430_GR_MOD, offset);
95}
96
97u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset)
98{
99 return omap2_prm_rmw_mod_reg_bits(mask, bits, OMAP3430_GR_MOD, offset);
100}
101
102/**
103 * omap3xxx_prm_read_pending_irqs - read pending PRM MPU IRQs into @events
104 * @events: ptr to a u32, preallocated by caller
105 *
106 * Read PRM_IRQSTATUS_MPU bits, AND'ed with the currently-enabled PRM
107 * MPU IRQs, and store the result into the u32 pointed to by @events.
108 * No return value.
109 */
110void omap3xxx_prm_read_pending_irqs(unsigned long *events)
111{
112 u32 mask, st;
113
114 /* XXX Can the mask read be avoided (e.g., can it come from RAM?) */
115 mask = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
116 st = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
117
118 events[0] = mask & st;
119}
120
121/**
122 * omap3xxx_prm_ocp_barrier - force buffered MPU writes to the PRM to complete
123 *
124 * Force any buffered writes to the PRM IP block to complete. Needed
125 * by the PRM IRQ handler, which reads and writes directly to the IP
126 * block, to avoid race conditions after acknowledging or clearing IRQ
127 * bits. No return value.
128 */
129void omap3xxx_prm_ocp_barrier(void)
130{
131 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
132}
133
134/**
135 * omap3xxx_prm_save_and_clear_irqen - save/clear PRM_IRQENABLE_MPU reg
136 * @saved_mask: ptr to a u32 array to save IRQENABLE bits
137 *
138 * Save the PRM_IRQENABLE_MPU register to @saved_mask. @saved_mask
139 * must be allocated by the caller. Intended to be used in the PRM
140 * interrupt handler suspend callback. The OCP barrier is needed to
141 * ensure the write to disable PRM interrupts reaches the PRM before
142 * returning; otherwise, spurious interrupts might occur. No return
143 * value.
144 */
145void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask)
146{
147 saved_mask[0] = omap2_prm_read_mod_reg(OCP_MOD,
148 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
149 omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
150
151 /* OCP barrier */
152 omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_REVISION_OFFSET);
153}
154
155/**
156 * omap3xxx_prm_restore_irqen - set PRM_IRQENABLE_MPU register from args
157 * @saved_mask: ptr to a u32 array of IRQENABLE bits saved previously
158 *
159 * Restore the PRM_IRQENABLE_MPU register from @saved_mask. Intended
160 * to be used in the PRM interrupt handler resume callback to restore
161 * values saved by omap3xxx_prm_save_and_clear_irqen(). No OCP
162 * barrier should be needed here; any pending PRM interrupts will fire
163 * once the writes reach the PRM. No return value.
164 */
165void omap3xxx_prm_restore_irqen(u32 *saved_mask)
166{
167 omap2_prm_write_mod_reg(saved_mask[0], OCP_MOD,
168 OMAP3_PRM_IRQENABLE_MPU_OFFSET);
169}
170
171/**
172 * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain
173 *
174 * Clear any previously-latched I/O wakeup events and ensure that the
175 * I/O wakeup gates are aligned with the current mux settings. Works
176 * by asserting WUCLKIN, waiting for WUCLKOUT to be asserted, and then
177 * deasserting WUCLKIN and clearing the ST_IO_CHAIN WKST bit. No
178 * return value.
179 */
180void omap3xxx_prm_reconfigure_io_chain(void)
181{
182 int i = 0;
183
184 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
185 PM_WKEN);
186
187 omap_test_timeout(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST) &
188 OMAP3430_ST_IO_CHAIN_MASK,
189 MAX_IOPAD_LATCH_TIME, i);
190 if (i == MAX_IOPAD_LATCH_TIME)
191 pr_warn("PRM: I/O chain clock line assertion timed out\n");
192
193 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
194 PM_WKEN);
195
196 omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD,
197 PM_WKST);
198
199 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKST);
200}
201
202/**
203 * omap3xxx_prm_enable_io_wakeup - enable wakeup events from I/O wakeup latches
204 *
205 * Activates the I/O wakeup event latches and allows events logged by
206 * those latches to signal a wakeup event to the PRCM. For I/O
207 * wakeups to occur, WAKEUPENABLE bits must be set in the pad mux
208 * registers, and omap3xxx_prm_reconfigure_io_chain() must be called.
209 * No return value.
210 */
211static void __init omap3xxx_prm_enable_io_wakeup(void)
212{
213 if (omap3_has_io_wakeup())
214 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
215 PM_WKEN);
216}
217
218static int __init omap3xxx_prm_init(void)
219{
220 int ret;
221
222 if (!cpu_is_omap34xx())
223 return 0;
224
225 omap3xxx_prm_enable_io_wakeup();
226 ret = omap_prcm_register_chain_handler(&omap3_prcm_irq_setup);
227 if (!ret)
228 irq_set_status_flags(omap_prcm_event_to_irq("io"),
229 IRQ_NOAUTOEN);
230
231 return ret;
232}
233subsys_initcall(omap3xxx_prm_init);
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
new file mode 100644
index 000000000000..6821e8321610
--- /dev/null
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -0,0 +1,158 @@
1/*
2 * OMAP3xxx Power/Reset Management (PRM) register definitions
3 *
4 * Copyright (C) 2007-2009, 2011-2012 Texas Instruments, Inc.
5 * Copyright (C) 2008-2010 Nokia Corporation
6 * Paul Walmsley
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * The PRM hardware modules on the OMAP2/3 are quite similar to each
13 * other. The PRM on OMAP4 has a new register layout, and is handled
14 * in a separate file.
15 */
16#ifndef __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
17#define __ARCH_ARM_MACH_OMAP2_PRM3XXX_H
18
19#include "prcm-common.h"
20#include "prm.h"
21#include "prm2xxx_3xxx.h"
22
23#define OMAP34XX_PRM_REGADDR(module, reg) \
24 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
25
26
27/*
28 * OMAP3-specific global PRM registers
29 * Use __raw_{read,write}l() with these registers.
30 *
31 * With a few exceptions, these are the register names beginning with
32 * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE
33 * bits.)
34 */
35
36#define OMAP3_PRM_REVISION_OFFSET 0x0004
37#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004)
38#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014
39#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014)
40
41#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018
42#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018)
43#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c
44#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c)
45
46
47#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020
48#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020)
49#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024
50#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024)
51#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028
52#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028)
53#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c
54#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c)
55#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030
56#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030)
57#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034
58#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034)
59#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038
60#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038)
61#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c
62#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c)
63#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050
64#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050)
65#define OMAP3_PRM_RSTTIME_OFFSET 0x0054
66#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054)
67#define OMAP3_PRM_RSTST_OFFSET 0x0058
68#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058)
69#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060
70#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060)
71#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064
72#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064)
73#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070
74#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
75#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090
76#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090)
77#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094
78#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094)
79#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098
80#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098)
81#define OMAP3_PRM_POLCTRL_OFFSET 0x009c
82#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c)
83#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0
84#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0)
85#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0
86#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0)
87#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4
88#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4)
89#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8
90#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8)
91#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc
92#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc)
93#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0
94#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0)
95#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4
96#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4)
97#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0
98#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0)
99#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4
100#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4)
101#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8
102#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8)
103#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc
104#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc)
105#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0
106#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0)
107#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4
108#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4)
109
110#define OMAP3_PRM_CLKSEL_OFFSET 0x0040
111#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040)
112#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070
113#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
114
115/* OMAP3 specific register offsets */
116#define OMAP3430ES2_PM_WKEN3 0x00f0
117#define OMAP3430ES2_PM_WKST3 0x00b8
118
119#define OMAP3430_PM_MPUGRPSEL 0x00a4
120#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL
121#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8
122
123#define OMAP3430_PM_IVAGRPSEL 0x00a8
124#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL
125#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4
126
127#define OMAP3430_PM_PREPWSTST 0x00e8
128
129#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8
130#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc
131
132
133#ifndef __ASSEMBLER__
134
135/* OMAP3-specific VP functions */
136u32 omap3_prm_vp_check_txdone(u8 vp_id);
137void omap3_prm_vp_clear_txdone(u8 vp_id);
138
139/*
140 * OMAP3 access functions for voltage controller (VC) and
141 * voltage proccessor (VP) in the PRM.
142 */
143extern u32 omap3_prm_vcvp_read(u8 offset);
144extern void omap3_prm_vcvp_write(u32 val, u8 offset);
145extern u32 omap3_prm_vcvp_rmw(u32 mask, u32 bits, u8 offset);
146
147extern void omap3xxx_prm_reconfigure_io_chain(void);
148
149/* PRM interrupt-related functions */
150extern void omap3xxx_prm_read_pending_irqs(unsigned long *events);
151extern void omap3xxx_prm_ocp_barrier(void);
152extern void omap3xxx_prm_save_and_clear_irqen(u32 *saved_mask);
153extern void omap3xxx_prm_restore_irqen(u32 *saved_mask);
154
155#endif /* __ASSEMBLER */
156
157
158#endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index f0c4d5f4a174..06bb67910a31 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -291,12 +291,13 @@ static void __init omap44xx_prm_enable_io_wakeup(void)
291 OMAP4_PRM_IO_PMCTRL_OFFSET); 291 OMAP4_PRM_IO_PMCTRL_OFFSET);
292} 292}
293 293
294static int __init omap4xxx_prcm_init(void) 294static int __init omap4xxx_prm_init(void)
295{ 295{
296 if (cpu_is_omap44xx()) { 296 if (!cpu_is_omap44xx())
297 omap44xx_prm_enable_io_wakeup(); 297 return 0;
298 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup); 298
299 } 299 omap44xx_prm_enable_io_wakeup();
300 return 0; 300
301 return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
301} 302}
302subsys_initcall(omap4xxx_prcm_init); 303subsys_initcall(omap4xxx_prm_init);
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 73e55e485329..9abd6e266458 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -31,7 +31,7 @@
31#include "soc.h" 31#include "soc.h"
32#include "iomap.h" 32#include "iomap.h"
33#include "common.h" 33#include "common.h"
34#include "prm2xxx_3xxx.h" 34#include "prm2xxx.h"
35#include "clock.h" 35#include "clock.h"
36#include "sdrc.h" 36#include "sdrc.h"
37 37
diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S
index 506987979c1c..d83b91829335 100644
--- a/arch/arm/mach-omap2/sleep34xx.S
+++ b/arch/arm/mach-omap2/sleep34xx.S
@@ -31,7 +31,7 @@
31#include "omap34xx.h" 31#include "omap34xx.h"
32#include "iomap.h" 32#include "iomap.h"
33#include "cm2xxx_3xxx.h" 33#include "cm2xxx_3xxx.h"
34#include "prm2xxx_3xxx.h" 34#include "prm3xxx.h"
35#include "sdrc.h" 35#include "sdrc.h"
36#include "control.h" 36#include "control.h"
37 37
diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S
index 8f7326cd435b..c7204439bdab 100644
--- a/arch/arm/mach-omap2/sram242x.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -34,7 +34,7 @@
34 34
35#include "soc.h" 35#include "soc.h"
36#include "iomap.h" 36#include "iomap.h"
37#include "prm2xxx_3xxx.h" 37#include "prm2xxx.h"
38#include "cm2xxx_3xxx.h" 38#include "cm2xxx_3xxx.h"
39#include "sdrc.h" 39#include "sdrc.h"
40 40
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
index b140d6578529..cfdc0bcfea6d 100644
--- a/arch/arm/mach-omap2/sram243x.S
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -34,7 +34,7 @@
34 34
35#include "soc.h" 35#include "soc.h"
36#include "iomap.h" 36#include "iomap.h"
37#include "prm2xxx_3xxx.h" 37#include "prm2xxx.h"
38#include "cm2xxx_3xxx.h" 38#include "cm2xxx_3xxx.h"
39#include "sdrc.h" 39#include "sdrc.h"
40 40
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-16 17:01:09 -0400