aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorBen Hutchings <bhutchings@solarflare.com>2012-09-18 21:16:05 -0400
committerBen Hutchings <bhutchings@solarflare.com>2013-09-20 14:31:45 -0400
commit137b79220c5a066fe98d4cfb0bde578637534296 (patch)
tree0840f950b26faa291b6f1c9b5fd4a0ca6b8dfad2
parent9fd8095dc1140c45bfc4b7132fb00815a354fb63 (diff)
sfc: Add EF10 registers to register dump
There are very few readable registers, but we may as well report them. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
-rw-r--r--drivers/net/ethernet/sfc/nic.c73
1 files changed, 42 insertions, 31 deletions
diff --git a/drivers/net/ethernet/sfc/nic.c b/drivers/net/ethernet/sfc/nic.c
index e7dbd2dd202e..c75009b8c0d9 100644
--- a/drivers/net/ethernet/sfc/nic.c
+++ b/drivers/net/ethernet/sfc/nic.c
@@ -19,6 +19,7 @@
19#include "bitfield.h" 19#include "bitfield.h"
20#include "efx.h" 20#include "efx.h"
21#include "nic.h" 21#include "nic.h"
22#include "ef10_regs.h"
22#include "farch_regs.h" 23#include "farch_regs.h"
23#include "io.h" 24#include "io.h"
24#include "workarounds.h" 25#include "workarounds.h"
@@ -166,26 +167,30 @@ void efx_nic_fini_interrupt(struct efx_nic *efx)
166 167
167/* Register dump */ 168/* Register dump */
168 169
169#define REGISTER_REVISION_A 1 170#define REGISTER_REVISION_FA 1
170#define REGISTER_REVISION_B 2 171#define REGISTER_REVISION_FB 2
171#define REGISTER_REVISION_C 3 172#define REGISTER_REVISION_FC 3
172#define REGISTER_REVISION_Z 3 /* latest revision */ 173#define REGISTER_REVISION_FZ 3 /* last Falcon arch revision */
174#define REGISTER_REVISION_ED 4
175#define REGISTER_REVISION_EZ 4 /* latest EF10 revision */
173 176
174struct efx_nic_reg { 177struct efx_nic_reg {
175 u32 offset:24; 178 u32 offset:24;
176 u32 min_revision:2, max_revision:2; 179 u32 min_revision:3, max_revision:3;
177}; 180};
178 181
179#define REGISTER(name, min_rev, max_rev) { \ 182#define REGISTER(name, arch, min_rev, max_rev) { \
180 FR_ ## min_rev ## max_rev ## _ ## name, \ 183 arch ## R_ ## min_rev ## max_rev ## _ ## name, \
181 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev \ 184 REGISTER_REVISION_ ## arch ## min_rev, \
185 REGISTER_REVISION_ ## arch ## max_rev \
182} 186}
183#define REGISTER_AA(name) REGISTER(name, A, A) 187#define REGISTER_AA(name) REGISTER(name, F, A, A)
184#define REGISTER_AB(name) REGISTER(name, A, B) 188#define REGISTER_AB(name) REGISTER(name, F, A, B)
185#define REGISTER_AZ(name) REGISTER(name, A, Z) 189#define REGISTER_AZ(name) REGISTER(name, F, A, Z)
186#define REGISTER_BB(name) REGISTER(name, B, B) 190#define REGISTER_BB(name) REGISTER(name, F, B, B)
187#define REGISTER_BZ(name) REGISTER(name, B, Z) 191#define REGISTER_BZ(name) REGISTER(name, F, B, Z)
188#define REGISTER_CZ(name) REGISTER(name, C, Z) 192#define REGISTER_CZ(name) REGISTER(name, F, C, Z)
193#define REGISTER_DZ(name) REGISTER(name, E, D, Z)
189 194
190static const struct efx_nic_reg efx_nic_regs[] = { 195static const struct efx_nic_reg efx_nic_regs[] = {
191 REGISTER_AZ(ADR_REGION), 196 REGISTER_AZ(ADR_REGION),
@@ -292,37 +297,42 @@ static const struct efx_nic_reg efx_nic_regs[] = {
292 REGISTER_AB(XX_TXDRV_CTL), 297 REGISTER_AB(XX_TXDRV_CTL),
293 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */ 298 /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
294 /* XX_CORE_STAT is partly RC */ 299 /* XX_CORE_STAT is partly RC */
300 REGISTER_DZ(BIU_HW_REV_ID),
301 REGISTER_DZ(MC_DB_LWRD),
302 REGISTER_DZ(MC_DB_HWRD),
295}; 303};
296 304
297struct efx_nic_reg_table { 305struct efx_nic_reg_table {
298 u32 offset:24; 306 u32 offset:24;
299 u32 min_revision:2, max_revision:2; 307 u32 min_revision:3, max_revision:3;
300 u32 step:6, rows:21; 308 u32 step:6, rows:21;
301}; 309};
302 310
303#define REGISTER_TABLE_DIMENSIONS(_, offset, min_rev, max_rev, step, rows) { \ 311#define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \
304 offset, \ 312 offset, \
305 REGISTER_REVISION_ ## min_rev, REGISTER_REVISION_ ## max_rev, \ 313 REGISTER_REVISION_ ## arch ## min_rev, \
314 REGISTER_REVISION_ ## arch ## max_rev, \
306 step, rows \ 315 step, rows \
307} 316}
308#define REGISTER_TABLE(name, min_rev, max_rev) \ 317#define REGISTER_TABLE(name, arch, min_rev, max_rev) \
309 REGISTER_TABLE_DIMENSIONS( \ 318 REGISTER_TABLE_DIMENSIONS( \
310 name, FR_ ## min_rev ## max_rev ## _ ## name, \ 319 name, arch ## R_ ## min_rev ## max_rev ## _ ## name, \
311 min_rev, max_rev, \ 320 arch, min_rev, max_rev, \
312 FR_ ## min_rev ## max_rev ## _ ## name ## _STEP, \ 321 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
313 FR_ ## min_rev ## max_rev ## _ ## name ## _ROWS) 322 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
314#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, A, A) 323#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)
315#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, A, Z) 324#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)
316#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, B, B) 325#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)
317#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, B, Z) 326#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)
318#define REGISTER_TABLE_BB_CZ(name) \ 327#define REGISTER_TABLE_BB_CZ(name) \
319 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, B, B, \ 328 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B, \
320 FR_BZ_ ## name ## _STEP, \ 329 FR_BZ_ ## name ## _STEP, \
321 FR_BB_ ## name ## _ROWS), \ 330 FR_BB_ ## name ## _ROWS), \
322 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, C, Z, \ 331 REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z, \
323 FR_BZ_ ## name ## _STEP, \ 332 FR_BZ_ ## name ## _STEP, \
324 FR_CZ_ ## name ## _ROWS) 333 FR_CZ_ ## name ## _ROWS)
325#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, C, Z) 334#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z)
335#define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z)
326 336
327static const struct efx_nic_reg_table efx_nic_reg_tables[] = { 337static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
328 /* DRIVER is not used */ 338 /* DRIVER is not used */
@@ -340,9 +350,9 @@ static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
340 * 1K entries allows for some expansion of queue count and 350 * 1K entries allows for some expansion of queue count and
341 * size before we need to change the version. */ 351 * size before we need to change the version. */
342 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER, 352 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,
343 A, A, 8, 1024), 353 F, A, A, 8, 1024),
344 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL, 354 REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,
345 B, Z, 8, 1024), 355 F, B, Z, 8, 1024),
346 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0), 356 REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),
347 REGISTER_TABLE_BB_CZ(TIMER_TBL), 357 REGISTER_TABLE_BB_CZ(TIMER_TBL),
348 REGISTER_TABLE_BB_CZ(TX_PACE_TBL), 358 REGISTER_TABLE_BB_CZ(TX_PACE_TBL),
@@ -353,6 +363,7 @@ static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
353 /* MSIX_PBA_TABLE is not mapped */ 363 /* MSIX_PBA_TABLE is not mapped */
354 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */ 364 /* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */
355 REGISTER_TABLE_BZ(RX_FILTER_TBL0), 365 REGISTER_TABLE_BZ(RX_FILTER_TBL0),
366 REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS),
356}; 367};
357 368
358size_t efx_nic_get_regs_len(struct efx_nic *efx) 369size_t efx_nic_get_regs_len(struct efx_nic *efx)