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authorBen Hutchings <bhutchings@solarflare.com>2009-10-23 04:30:46 -0400
committerDavid S. Miller <davem@davemloft.net>2009-10-24 07:27:04 -0400
commit12d00cadcc45382fc127712aa35bd0c96cbf81d9 (patch)
tree96239fbc49d4907fd1677b9d9a2558525673c11e
parent3e6c4538542ab2103ab7c01f4458bc2e21b672a1 (diff)
sfc: Rename register I/O header and functions used by both Falcon and Siena
While we're at it, use type suffixes of 'd', 'q' and 'o', consistent with register type names. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/sfc/falcon.c249
-rw-r--r--drivers/net/sfc/falcon_boards.c8
-rw-r--r--drivers/net/sfc/falcon_gmac.c26
-rw-r--r--drivers/net/sfc/falcon_io.h258
-rw-r--r--drivers/net/sfc/falcon_xmac.c48
-rw-r--r--drivers/net/sfc/io.h256
-rw-r--r--drivers/net/sfc/selftest.c2
7 files changed, 426 insertions, 421 deletions
diff --git a/drivers/net/sfc/falcon.c b/drivers/net/sfc/falcon.c
index b35e01031e23..759f55ae4b83 100644
--- a/drivers/net/sfc/falcon.c
+++ b/drivers/net/sfc/falcon.c
@@ -23,7 +23,7 @@
23#include "spi.h" 23#include "spi.h"
24#include "falcon.h" 24#include "falcon.h"
25#include "regs.h" 25#include "regs.h"
26#include "falcon_io.h" 26#include "io.h"
27#include "mdio_10g.h" 27#include "mdio_10g.h"
28#include "phy.h" 28#include "phy.h"
29#include "workarounds.h" 29#include "workarounds.h"
@@ -163,6 +163,13 @@ MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
163 * 163 *
164 **************************************************************************/ 164 **************************************************************************/
165 165
166static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value,
167 unsigned int index)
168{
169 efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base,
170 value, index);
171}
172
166/* Read the current event from the event queue */ 173/* Read the current event from the event queue */
167static inline efx_qword_t *falcon_event(struct efx_channel *channel, 174static inline efx_qword_t *falcon_event(struct efx_channel *channel,
168 unsigned int index) 175 unsigned int index)
@@ -199,9 +206,9 @@ static void falcon_setsda(void *data, int state)
199 struct efx_nic *efx = (struct efx_nic *)data; 206 struct efx_nic *efx = (struct efx_nic *)data;
200 efx_oword_t reg; 207 efx_oword_t reg;
201 208
202 falcon_read(efx, &reg, FR_AB_GPIO_CTL); 209 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
203 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); 210 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
204 falcon_write(efx, &reg, FR_AB_GPIO_CTL); 211 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
205} 212}
206 213
207static void falcon_setscl(void *data, int state) 214static void falcon_setscl(void *data, int state)
@@ -209,9 +216,9 @@ static void falcon_setscl(void *data, int state)
209 struct efx_nic *efx = (struct efx_nic *)data; 216 struct efx_nic *efx = (struct efx_nic *)data;
210 efx_oword_t reg; 217 efx_oword_t reg;
211 218
212 falcon_read(efx, &reg, FR_AB_GPIO_CTL); 219 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
213 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); 220 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
214 falcon_write(efx, &reg, FR_AB_GPIO_CTL); 221 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
215} 222}
216 223
217static int falcon_getsda(void *data) 224static int falcon_getsda(void *data)
@@ -219,7 +226,7 @@ static int falcon_getsda(void *data)
219 struct efx_nic *efx = (struct efx_nic *)data; 226 struct efx_nic *efx = (struct efx_nic *)data;
220 efx_oword_t reg; 227 efx_oword_t reg;
221 228
222 falcon_read(efx, &reg, FR_AB_GPIO_CTL); 229 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
223 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); 230 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
224} 231}
225 232
@@ -228,7 +235,7 @@ static int falcon_getscl(void *data)
228 struct efx_nic *efx = (struct efx_nic *)data; 235 struct efx_nic *efx = (struct efx_nic *)data;
229 efx_oword_t reg; 236 efx_oword_t reg;
230 237
231 falcon_read(efx, &reg, FR_AB_GPIO_CTL); 238 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
232 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); 239 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
233} 240}
234 241
@@ -278,7 +285,7 @@ falcon_init_special_buffer(struct efx_nic *efx,
278 FRF_AZ_BUF_ADR_REGION, 0, 285 FRF_AZ_BUF_ADR_REGION, 0,
279 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12, 286 FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12,
280 FRF_AZ_BUF_OWNER_ID_FBUF, 0); 287 FRF_AZ_BUF_OWNER_ID_FBUF, 0);
281 falcon_write_sram(efx, &buf_desc, index); 288 falcon_write_buf_tbl(efx, &buf_desc, index);
282 } 289 }
283} 290}
284 291
@@ -302,7 +309,7 @@ falcon_fini_special_buffer(struct efx_nic *efx,
302 FRF_AZ_BUF_CLR_CMD, 1, 309 FRF_AZ_BUF_CLR_CMD, 1,
303 FRF_AZ_BUF_CLR_END_ID, end, 310 FRF_AZ_BUF_CLR_END_ID, end,
304 FRF_AZ_BUF_CLR_START_ID, start); 311 FRF_AZ_BUF_CLR_START_ID, start);
305 falcon_write(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD); 312 efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD);
306} 313}
307 314
308/* 315/*
@@ -415,8 +422,8 @@ static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue)
415 422
416 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK; 423 write_ptr = tx_queue->write_count & FALCON_TXD_RING_MASK;
417 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); 424 EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr);
418 falcon_writel_page(tx_queue->efx, &reg, 425 efx_writed_page(tx_queue->efx, &reg,
419 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue); 426 FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue);
420} 427}
421 428
422 429
@@ -491,8 +498,8 @@ void falcon_init_tx(struct efx_tx_queue *tx_queue)
491 !csum); 498 !csum);
492 } 499 }
493 500
494 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, 501 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
495 tx_queue->queue); 502 tx_queue->queue);
496 503
497 if (falcon_rev(efx) < FALCON_REV_B0) { 504 if (falcon_rev(efx) < FALCON_REV_B0) {
498 efx_oword_t reg; 505 efx_oword_t reg;
@@ -500,12 +507,12 @@ void falcon_init_tx(struct efx_tx_queue *tx_queue)
500 /* Only 128 bits in this register */ 507 /* Only 128 bits in this register */
501 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128); 508 BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128);
502 509
503 falcon_read(efx, &reg, FR_AA_TX_CHKSM_CFG); 510 efx_reado(efx, &reg, FR_AA_TX_CHKSM_CFG);
504 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM) 511 if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM)
505 clear_bit_le(tx_queue->queue, (void *)&reg); 512 clear_bit_le(tx_queue->queue, (void *)&reg);
506 else 513 else
507 set_bit_le(tx_queue->queue, (void *)&reg); 514 set_bit_le(tx_queue->queue, (void *)&reg);
508 falcon_write(efx, &reg, FR_AA_TX_CHKSM_CFG); 515 efx_writeo(efx, &reg, FR_AA_TX_CHKSM_CFG);
509 } 516 }
510} 517}
511 518
@@ -518,7 +525,7 @@ static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue)
518 EFX_POPULATE_OWORD_2(tx_flush_descq, 525 EFX_POPULATE_OWORD_2(tx_flush_descq,
519 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, 526 FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
520 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue); 527 FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue);
521 falcon_write(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ); 528 efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ);
522} 529}
523 530
524void falcon_fini_tx(struct efx_tx_queue *tx_queue) 531void falcon_fini_tx(struct efx_tx_queue *tx_queue)
@@ -531,8 +538,8 @@ void falcon_fini_tx(struct efx_tx_queue *tx_queue)
531 538
532 /* Remove TX descriptor ring from card */ 539 /* Remove TX descriptor ring from card */
533 EFX_ZERO_OWORD(tx_desc_ptr); 540 EFX_ZERO_OWORD(tx_desc_ptr);
534 falcon_write_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, 541 efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
535 tx_queue->queue); 542 tx_queue->queue);
536 543
537 /* Unpin TX descriptor ring */ 544 /* Unpin TX descriptor ring */
538 falcon_fini_special_buffer(efx, &tx_queue->txd); 545 falcon_fini_special_buffer(efx, &tx_queue->txd);
@@ -592,8 +599,8 @@ void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue)
592 wmb(); 599 wmb();
593 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK; 600 write_ptr = rx_queue->added_count & FALCON_RXD_RING_MASK;
594 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); 601 EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr);
595 falcon_writel_page(rx_queue->efx, &reg, 602 efx_writed_page(rx_queue->efx, &reg,
596 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue); 603 FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue);
597} 604}
598 605
599int falcon_probe_rx(struct efx_rx_queue *rx_queue) 606int falcon_probe_rx(struct efx_rx_queue *rx_queue)
@@ -634,8 +641,8 @@ void falcon_init_rx(struct efx_rx_queue *rx_queue)
634 /* For >=B0 this is scatter so disable */ 641 /* For >=B0 this is scatter so disable */
635 FRF_AZ_RX_DESCQ_JUMBO, !is_b0, 642 FRF_AZ_RX_DESCQ_JUMBO, !is_b0,
636 FRF_AZ_RX_DESCQ_EN, 1); 643 FRF_AZ_RX_DESCQ_EN, 1);
637 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, 644 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
638 rx_queue->queue); 645 rx_queue->queue);
639} 646}
640 647
641static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue) 648static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
@@ -647,7 +654,7 @@ static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue)
647 EFX_POPULATE_OWORD_2(rx_flush_descq, 654 EFX_POPULATE_OWORD_2(rx_flush_descq,
648 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, 655 FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
649 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue); 656 FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue);
650 falcon_write(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ); 657 efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ);
651} 658}
652 659
653void falcon_fini_rx(struct efx_rx_queue *rx_queue) 660void falcon_fini_rx(struct efx_rx_queue *rx_queue)
@@ -660,8 +667,8 @@ void falcon_fini_rx(struct efx_rx_queue *rx_queue)
660 667
661 /* Remove RX descriptor ring from card */ 668 /* Remove RX descriptor ring from card */
662 EFX_ZERO_OWORD(rx_desc_ptr); 669 EFX_ZERO_OWORD(rx_desc_ptr);
663 falcon_write_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, 670 efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base,
664 rx_queue->queue); 671 rx_queue->queue);
665 672
666 /* Unpin RX descriptor ring */ 673 /* Unpin RX descriptor ring */
667 falcon_fini_special_buffer(efx, &rx_queue->rxd); 674 falcon_fini_special_buffer(efx, &rx_queue->rxd);
@@ -695,7 +702,7 @@ void falcon_eventq_read_ack(struct efx_channel *channel)
695 struct efx_nic *efx = channel->efx; 702 struct efx_nic *efx = channel->efx;
696 703
697 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr); 704 EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr);
698 falcon_writel_table(efx, &reg, efx->type->evq_rptr_tbl_base, 705 efx_writed_table(efx, &reg, efx->type->evq_rptr_tbl_base,
699 channel->channel); 706 channel->channel);
700} 707}
701 708
@@ -711,7 +718,7 @@ void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event)
711 drv_ev_reg.u32[2] = 0; 718 drv_ev_reg.u32[2] = 0;
712 drv_ev_reg.u32[3] = 0; 719 drv_ev_reg.u32[3] = 0;
713 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel); 720 EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel);
714 falcon_write(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV); 721 efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV);
715} 722}
716 723
717/* Handle a transmit completion event 724/* Handle a transmit completion event
@@ -1104,8 +1111,8 @@ void falcon_set_int_moderation(struct efx_channel *channel)
1104 FRF_AB_TC_TIMER_VAL, 0); 1111 FRF_AB_TC_TIMER_VAL, 0);
1105 } 1112 }
1106 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); 1113 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
1107 falcon_writel_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, 1114 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
1108 channel->channel); 1115 channel->channel);
1109 1116
1110} 1117}
1111 1118
@@ -1139,8 +1146,8 @@ void falcon_init_eventq(struct efx_channel *channel)
1139 FRF_AZ_EVQ_EN, 1, 1146 FRF_AZ_EVQ_EN, 1,
1140 FRF_AZ_EVQ_SIZE, FALCON_EVQ_ORDER, 1147 FRF_AZ_EVQ_SIZE, FALCON_EVQ_ORDER,
1141 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index); 1148 FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index);
1142 falcon_write_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base, 1149 efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base,
1143 channel->channel); 1150 channel->channel);
1144 1151
1145 falcon_set_int_moderation(channel); 1152 falcon_set_int_moderation(channel);
1146} 1153}
@@ -1152,8 +1159,8 @@ void falcon_fini_eventq(struct efx_channel *channel)
1152 1159
1153 /* Remove event queue from card */ 1160 /* Remove event queue from card */
1154 EFX_ZERO_OWORD(eventq_ptr); 1161 EFX_ZERO_OWORD(eventq_ptr);
1155 falcon_write_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base, 1162 efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base,
1156 channel->channel); 1163 channel->channel);
1157 1164
1158 /* Unpin event queue */ 1165 /* Unpin event queue */
1159 falcon_fini_special_buffer(efx, &channel->eventq); 1166 falcon_fini_special_buffer(efx, &channel->eventq);
@@ -1325,7 +1332,7 @@ static inline void falcon_interrupts(struct efx_nic *efx, int enabled,
1325 EFX_POPULATE_OWORD_2(int_en_reg_ker, 1332 EFX_POPULATE_OWORD_2(int_en_reg_ker,
1326 FRF_AZ_KER_INT_KER, force, 1333 FRF_AZ_KER_INT_KER, force,
1327 FRF_AZ_DRV_INT_EN_KER, enabled); 1334 FRF_AZ_DRV_INT_EN_KER, enabled);
1328 falcon_write(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); 1335 efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER);
1329} 1336}
1330 1337
1331void falcon_enable_interrupts(struct efx_nic *efx) 1338void falcon_enable_interrupts(struct efx_nic *efx)
@@ -1341,7 +1348,7 @@ void falcon_enable_interrupts(struct efx_nic *efx)
1341 FRF_AZ_NORM_INT_VEC_DIS_KER, 1348 FRF_AZ_NORM_INT_VEC_DIS_KER,
1342 EFX_INT_MODE_USE_MSI(efx), 1349 EFX_INT_MODE_USE_MSI(efx),
1343 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); 1350 FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr);
1344 falcon_write(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER); 1351 efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER);
1345 1352
1346 /* Enable interrupts */ 1353 /* Enable interrupts */
1347 falcon_interrupts(efx, 1, 0); 1354 falcon_interrupts(efx, 1, 0);
@@ -1382,8 +1389,8 @@ static inline void falcon_irq_ack_a1(struct efx_nic *efx)
1382 efx_dword_t reg; 1389 efx_dword_t reg;
1383 1390
1384 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); 1391 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
1385 falcon_writel(efx, &reg, FR_AA_INT_ACK_KER); 1392 efx_writed(efx, &reg, FR_AA_INT_ACK_KER);
1386 falcon_readl(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS); 1393 efx_readd(efx, &reg, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
1387} 1394}
1388 1395
1389/* Process a fatal interrupt 1396/* Process a fatal interrupt
@@ -1396,7 +1403,7 @@ static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1396 efx_oword_t fatal_intr; 1403 efx_oword_t fatal_intr;
1397 int error, mem_perr; 1404 int error, mem_perr;
1398 1405
1399 falcon_read(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER); 1406 efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER);
1400 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR); 1407 error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR);
1401 1408
1402 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status " 1409 EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status "
@@ -1410,7 +1417,7 @@ static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx)
1410 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER); 1417 mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER);
1411 if (mem_perr) { 1418 if (mem_perr) {
1412 efx_oword_t reg; 1419 efx_oword_t reg;
1413 falcon_read(efx, &reg, FR_AZ_MEM_STAT); 1420 efx_reado(efx, &reg, FR_AZ_MEM_STAT);
1414 EFX_ERR(efx, "SYSTEM ERROR: memory parity error " 1421 EFX_ERR(efx, "SYSTEM ERROR: memory parity error "
1415 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg)); 1422 EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg));
1416 } 1423 }
@@ -1454,7 +1461,7 @@ static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id)
1454 int syserr; 1461 int syserr;
1455 1462
1456 /* Read the ISR which also ACKs the interrupts */ 1463 /* Read the ISR which also ACKs the interrupts */
1457 falcon_readl(efx, &reg, FR_BZ_INT_ISR0); 1464 efx_readd(efx, &reg, FR_BZ_INT_ISR0);
1458 queues = EFX_EXTRACT_DWORD(reg, 0, 31); 1465 queues = EFX_EXTRACT_DWORD(reg, 0, 31);
1459 1466
1460 /* Check to see if we have a serious error condition */ 1467 /* Check to see if we have a serious error condition */
@@ -1576,7 +1583,7 @@ static void falcon_setup_rss_indir_table(struct efx_nic *efx)
1576 offset += 0x10) { 1583 offset += 0x10) {
1577 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, 1584 EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE,
1578 i % efx->n_rx_queues); 1585 i % efx->n_rx_queues);
1579 falcon_writel(efx, &dword, offset); 1586 efx_writed(efx, &dword, offset);
1580 i++; 1587 i++;
1581 } 1588 }
1582} 1589}
@@ -1639,7 +1646,7 @@ void falcon_fini_interrupt(struct efx_nic *efx)
1639 1646
1640 /* ACK legacy interrupt */ 1647 /* ACK legacy interrupt */
1641 if (falcon_rev(efx) >= FALCON_REV_B0) 1648 if (falcon_rev(efx) >= FALCON_REV_B0)
1642 falcon_read(efx, &reg, FR_BZ_INT_ISR0); 1649 efx_reado(efx, &reg, FR_BZ_INT_ISR0);
1643 else 1650 else
1644 falcon_irq_ack_a1(efx); 1651 falcon_irq_ack_a1(efx);
1645 1652
@@ -1660,7 +1667,7 @@ void falcon_fini_interrupt(struct efx_nic *efx)
1660static int falcon_spi_poll(struct efx_nic *efx) 1667static int falcon_spi_poll(struct efx_nic *efx)
1661{ 1668{
1662 efx_oword_t reg; 1669 efx_oword_t reg;
1663 falcon_read(efx, &reg, FR_AB_EE_SPI_HCMD); 1670 efx_reado(efx, &reg, FR_AB_EE_SPI_HCMD);
1664 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; 1671 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
1665} 1672}
1666 1673
@@ -1714,13 +1721,13 @@ int falcon_spi_cmd(const struct efx_spi_device *spi,
1714 /* Program address register, if we have an address */ 1721 /* Program address register, if we have an address */
1715 if (addressed) { 1722 if (addressed) {
1716 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); 1723 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
1717 falcon_write(efx, &reg, FR_AB_EE_SPI_HADR); 1724 efx_writeo(efx, &reg, FR_AB_EE_SPI_HADR);
1718 } 1725 }
1719 1726
1720 /* Program data register, if we have data */ 1727 /* Program data register, if we have data */
1721 if (in != NULL) { 1728 if (in != NULL) {
1722 memcpy(&reg, in, len); 1729 memcpy(&reg, in, len);
1723 falcon_write(efx, &reg, FR_AB_EE_SPI_HDATA); 1730 efx_writeo(efx, &reg, FR_AB_EE_SPI_HDATA);
1724 } 1731 }
1725 1732
1726 /* Issue read/write command */ 1733 /* Issue read/write command */
@@ -1733,7 +1740,7 @@ int falcon_spi_cmd(const struct efx_spi_device *spi,
1733 FRF_AB_EE_SPI_HCMD_ADBCNT, 1740 FRF_AB_EE_SPI_HCMD_ADBCNT,
1734 (addressed ? spi->addr_len : 0), 1741 (addressed ? spi->addr_len : 0),
1735 FRF_AB_EE_SPI_HCMD_ENC, command); 1742 FRF_AB_EE_SPI_HCMD_ENC, command);
1736 falcon_write(efx, &reg, FR_AB_EE_SPI_HCMD); 1743 efx_writeo(efx, &reg, FR_AB_EE_SPI_HCMD);
1737 1744
1738 /* Wait for read/write to complete */ 1745 /* Wait for read/write to complete */
1739 rc = falcon_spi_wait(efx); 1746 rc = falcon_spi_wait(efx);
@@ -1742,7 +1749,7 @@ int falcon_spi_cmd(const struct efx_spi_device *spi,
1742 1749
1743 /* Read data */ 1750 /* Read data */
1744 if (out != NULL) { 1751 if (out != NULL) {
1745 falcon_read(efx, &reg, FR_AB_EE_SPI_HDATA); 1752 efx_reado(efx, &reg, FR_AB_EE_SPI_HDATA);
1746 memcpy(out, &reg, len); 1753 memcpy(out, &reg, len);
1747 } 1754 }
1748 1755
@@ -1884,19 +1891,19 @@ static int falcon_reset_macs(struct efx_nic *efx)
1884 */ 1891 */
1885 if (!EFX_IS10G(efx)) { 1892 if (!EFX_IS10G(efx)) {
1886 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1); 1893 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1);
1887 falcon_write(efx, &reg, FR_AB_GM_CFG1); 1894 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1888 udelay(1000); 1895 udelay(1000);
1889 1896
1890 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0); 1897 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0);
1891 falcon_write(efx, &reg, FR_AB_GM_CFG1); 1898 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
1892 udelay(1000); 1899 udelay(1000);
1893 return 0; 1900 return 0;
1894 } else { 1901 } else {
1895 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); 1902 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
1896 falcon_write(efx, &reg, FR_AB_XM_GLB_CFG); 1903 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
1897 1904
1898 for (count = 0; count < 10000; count++) { 1905 for (count = 0; count < 10000; count++) {
1899 falcon_read(efx, &reg, FR_AB_XM_GLB_CFG); 1906 efx_reado(efx, &reg, FR_AB_XM_GLB_CFG);
1900 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == 1907 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
1901 0) 1908 0)
1902 return 0; 1909 return 0;
@@ -1912,19 +1919,19 @@ static int falcon_reset_macs(struct efx_nic *efx)
1912 * the drain sequence with the statistics fetch */ 1919 * the drain sequence with the statistics fetch */
1913 efx_stats_disable(efx); 1920 efx_stats_disable(efx);
1914 1921
1915 falcon_read(efx, &reg, FR_AB_MAC_CTRL); 1922 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1916 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1); 1923 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1);
1917 falcon_write(efx, &reg, FR_AB_MAC_CTRL); 1924 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
1918 1925
1919 falcon_read(efx, &reg, FR_AB_GLB_CTL); 1926 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1920 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); 1927 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
1921 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); 1928 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
1922 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); 1929 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
1923 falcon_write(efx, &reg, FR_AB_GLB_CTL); 1930 efx_writeo(efx, &reg, FR_AB_GLB_CTL);
1924 1931
1925 count = 0; 1932 count = 0;
1926 while (1) { 1933 while (1) {
1927 falcon_read(efx, &reg, FR_AB_GLB_CTL); 1934 efx_reado(efx, &reg, FR_AB_GLB_CTL);
1928 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && 1935 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
1929 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && 1936 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
1930 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { 1937 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
@@ -1958,7 +1965,7 @@ void falcon_drain_tx_fifo(struct efx_nic *efx)
1958 (efx->loopback_mode != LOOPBACK_NONE)) 1965 (efx->loopback_mode != LOOPBACK_NONE))
1959 return; 1966 return;
1960 1967
1961 falcon_read(efx, &reg, FR_AB_MAC_CTRL); 1968 efx_reado(efx, &reg, FR_AB_MAC_CTRL);
1962 /* There is no point in draining more than once */ 1969 /* There is no point in draining more than once */
1963 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) 1970 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
1964 return; 1971 return;
@@ -1974,9 +1981,9 @@ void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
1974 return; 1981 return;
1975 1982
1976 /* Isolate the MAC -> RX */ 1983 /* Isolate the MAC -> RX */
1977 falcon_read(efx, &reg, FR_AZ_RX_CFG); 1984 efx_reado(efx, &reg, FR_AZ_RX_CFG);
1978 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); 1985 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
1979 falcon_write(efx, &reg, FR_AZ_RX_CFG); 1986 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
1980 1987
1981 if (!efx->link_up) 1988 if (!efx->link_up)
1982 falcon_drain_tx_fifo(efx); 1989 falcon_drain_tx_fifo(efx);
@@ -2011,7 +2018,7 @@ void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
2011 !efx->link_up); 2018 !efx->link_up);
2012 } 2019 }
2013 2020
2014 falcon_write(efx, &reg, FR_AB_MAC_CTRL); 2021 efx_writeo(efx, &reg, FR_AB_MAC_CTRL);
2015 2022
2016 /* Restore the multicast hash registers. */ 2023 /* Restore the multicast hash registers. */
2017 falcon_set_multicast_hash(efx); 2024 falcon_set_multicast_hash(efx);
@@ -2020,13 +2027,13 @@ void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
2020 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL. 2027 * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL.
2021 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */ 2028 * Action on receipt of pause frames is controller by XM_DIS_FCNTL */
2022 tx_fc = !!(efx->link_fc & EFX_FC_TX); 2029 tx_fc = !!(efx->link_fc & EFX_FC_TX);
2023 falcon_read(efx, &reg, FR_AZ_RX_CFG); 2030 efx_reado(efx, &reg, FR_AZ_RX_CFG);
2024 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc); 2031 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
2025 2032
2026 /* Unisolate the MAC -> RX */ 2033 /* Unisolate the MAC -> RX */
2027 if (falcon_rev(efx) >= FALCON_REV_B0) 2034 if (falcon_rev(efx) >= FALCON_REV_B0)
2028 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); 2035 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2029 falcon_write(efx, &reg, FR_AZ_RX_CFG); 2036 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2030} 2037}
2031 2038
2032int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset) 2039int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
@@ -2041,7 +2048,7 @@ int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2041 /* Statistics fetch will fail if the MAC is in TX drain */ 2048 /* Statistics fetch will fail if the MAC is in TX drain */
2042 if (falcon_rev(efx) >= FALCON_REV_B0) { 2049 if (falcon_rev(efx) >= FALCON_REV_B0) {
2043 efx_oword_t temp; 2050 efx_oword_t temp;
2044 falcon_read(efx, &temp, FR_AB_MAC_CTRL); 2051 efx_reado(efx, &temp, FR_AB_MAC_CTRL);
2045 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN)) 2052 if (EFX_OWORD_FIELD(temp, FRF_BB_TXFIFO_DRAIN_EN))
2046 return 0; 2053 return 0;
2047 } 2054 }
@@ -2055,7 +2062,7 @@ int falcon_dma_stats(struct efx_nic *efx, unsigned int done_offset)
2055 FRF_AB_MAC_STAT_DMA_CMD, 1, 2062 FRF_AB_MAC_STAT_DMA_CMD, 1,
2056 FRF_AB_MAC_STAT_DMA_ADR, 2063 FRF_AB_MAC_STAT_DMA_ADR,
2057 efx->stats_buffer.dma_addr); 2064 efx->stats_buffer.dma_addr);
2058 falcon_write(efx, &reg, FR_AB_MAC_STAT_DMA); 2065 efx_writeo(efx, &reg, FR_AB_MAC_STAT_DMA);
2059 2066
2060 /* Wait for transfer to complete */ 2067 /* Wait for transfer to complete */
2061 for (i = 0; i < 400; i++) { 2068 for (i = 0; i < 400; i++) {
@@ -2085,7 +2092,7 @@ static int falcon_gmii_wait(struct efx_nic *efx)
2085 2092
2086 /* wait upto 50ms - taken max from datasheet */ 2093 /* wait upto 50ms - taken max from datasheet */
2087 for (count = 0; count < 5000; count++) { 2094 for (count = 0; count < 5000; count++) {
2088 falcon_readl(efx, &md_stat, FR_AB_MD_STAT); 2095 efx_readd(efx, &md_stat, FR_AB_MD_STAT);
2089 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { 2096 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
2090 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || 2097 if (EFX_DWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
2091 EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { 2098 EFX_DWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
@@ -2122,20 +2129,20 @@ static int falcon_mdio_write(struct net_device *net_dev,
2122 2129
2123 /* Write the address/ID register */ 2130 /* Write the address/ID register */
2124 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); 2131 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2125 falcon_write(efx, &reg, FR_AB_MD_PHY_ADR); 2132 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2126 2133
2127 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, 2134 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2128 FRF_AB_MD_DEV_ADR, devad); 2135 FRF_AB_MD_DEV_ADR, devad);
2129 falcon_write(efx, &reg, FR_AB_MD_ID); 2136 efx_writeo(efx, &reg, FR_AB_MD_ID);
2130 2137
2131 /* Write data */ 2138 /* Write data */
2132 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); 2139 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
2133 falcon_write(efx, &reg, FR_AB_MD_TXD); 2140 efx_writeo(efx, &reg, FR_AB_MD_TXD);
2134 2141
2135 EFX_POPULATE_OWORD_2(reg, 2142 EFX_POPULATE_OWORD_2(reg,
2136 FRF_AB_MD_WRC, 1, 2143 FRF_AB_MD_WRC, 1,
2137 FRF_AB_MD_GC, 0); 2144 FRF_AB_MD_GC, 0);
2138 falcon_write(efx, &reg, FR_AB_MD_CS); 2145 efx_writeo(efx, &reg, FR_AB_MD_CS);
2139 2146
2140 /* Wait for data to be written */ 2147 /* Wait for data to be written */
2141 rc = falcon_gmii_wait(efx); 2148 rc = falcon_gmii_wait(efx);
@@ -2144,7 +2151,7 @@ static int falcon_mdio_write(struct net_device *net_dev,
2144 EFX_POPULATE_OWORD_2(reg, 2151 EFX_POPULATE_OWORD_2(reg,
2145 FRF_AB_MD_WRC, 0, 2152 FRF_AB_MD_WRC, 0,
2146 FRF_AB_MD_GC, 1); 2153 FRF_AB_MD_GC, 1);
2147 falcon_write(efx, &reg, FR_AB_MD_CS); 2154 efx_writeo(efx, &reg, FR_AB_MD_CS);
2148 udelay(10); 2155 udelay(10);
2149 } 2156 }
2150 2157
@@ -2169,20 +2176,20 @@ static int falcon_mdio_read(struct net_device *net_dev,
2169 goto out; 2176 goto out;
2170 2177
2171 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); 2178 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
2172 falcon_write(efx, &reg, FR_AB_MD_PHY_ADR); 2179 efx_writeo(efx, &reg, FR_AB_MD_PHY_ADR);
2173 2180
2174 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, 2181 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
2175 FRF_AB_MD_DEV_ADR, devad); 2182 FRF_AB_MD_DEV_ADR, devad);
2176 falcon_write(efx, &reg, FR_AB_MD_ID); 2183 efx_writeo(efx, &reg, FR_AB_MD_ID);
2177 2184
2178 /* Request data to be read */ 2185 /* Request data to be read */
2179 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); 2186 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
2180 falcon_write(efx, &reg, FR_AB_MD_CS); 2187 efx_writeo(efx, &reg, FR_AB_MD_CS);
2181 2188
2182 /* Wait for data to become available */ 2189 /* Wait for data to become available */
2183 rc = falcon_gmii_wait(efx); 2190 rc = falcon_gmii_wait(efx);
2184 if (rc == 0) { 2191 if (rc == 0) {
2185 falcon_read(efx, &reg, FR_AB_MD_RXD); 2192 efx_reado(efx, &reg, FR_AB_MD_RXD);
2186 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); 2193 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
2187 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n", 2194 EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n",
2188 prtad, devad, addr, rc); 2195 prtad, devad, addr, rc);
@@ -2191,7 +2198,7 @@ static int falcon_mdio_read(struct net_device *net_dev,
2191 EFX_POPULATE_OWORD_2(reg, 2198 EFX_POPULATE_OWORD_2(reg,
2192 FRF_AB_MD_RIC, 0, 2199 FRF_AB_MD_RIC, 0,
2193 FRF_AB_MD_GC, 1); 2200 FRF_AB_MD_GC, 1);
2194 falcon_write(efx, &reg, FR_AB_MD_CS); 2201 efx_writeo(efx, &reg, FR_AB_MD_CS);
2195 2202
2196 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n", 2203 EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n",
2197 prtad, devad, addr, rc); 2204 prtad, devad, addr, rc);
@@ -2258,12 +2265,12 @@ int falcon_switch_mac(struct efx_nic *efx)
2258 2265
2259 /* Always push the NIC_STAT_REG setting even if the mac hasn't 2266 /* Always push the NIC_STAT_REG setting even if the mac hasn't
2260 * changed, because this function is run post online reset */ 2267 * changed, because this function is run post online reset */
2261 falcon_read(efx, &nic_stat, FR_AB_NIC_STAT); 2268 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2262 strap_val = EFX_IS10G(efx) ? 5 : 3; 2269 strap_val = EFX_IS10G(efx) ? 5 : 3;
2263 if (falcon_rev(efx) >= FALCON_REV_B0) { 2270 if (falcon_rev(efx) >= FALCON_REV_B0) {
2264 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1); 2271 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
2265 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val); 2272 EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
2266 falcon_write(efx, &nic_stat, FR_AB_NIC_STAT); 2273 efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
2267 } else { 2274 } else {
2268 /* Falcon A1 does not support 1G/10G speed switching 2275 /* Falcon A1 does not support 1G/10G speed switching
2269 * and must not be used with a PHY that does. */ 2276 * and must not be used with a PHY that does. */
@@ -2341,8 +2348,8 @@ void falcon_set_multicast_hash(struct efx_nic *efx)
2341 */ 2348 */
2342 set_bit_le(0xff, mc_hash->byte); 2349 set_bit_le(0xff, mc_hash->byte);
2343 2350
2344 falcon_write(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); 2351 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
2345 falcon_write(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); 2352 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
2346} 2353}
2347 2354
2348 2355
@@ -2478,7 +2485,7 @@ int falcon_test_registers(struct efx_nic *efx)
2478 mask = imask = efx_test_registers[i].mask; 2485 mask = imask = efx_test_registers[i].mask;
2479 EFX_INVERT_OWORD(imask); 2486 EFX_INVERT_OWORD(imask);
2480 2487
2481 falcon_read(efx, &original, address); 2488 efx_reado(efx, &original, address);
2482 2489
2483 /* bit sweep on and off */ 2490 /* bit sweep on and off */
2484 for (j = 0; j < 128; j++) { 2491 for (j = 0; j < 128; j++) {
@@ -2489,8 +2496,8 @@ int falcon_test_registers(struct efx_nic *efx)
2489 EFX_AND_OWORD(reg, original, mask); 2496 EFX_AND_OWORD(reg, original, mask);
2490 EFX_SET_OWORD32(reg, j, j, 1); 2497 EFX_SET_OWORD32(reg, j, j, 1);
2491 2498
2492 falcon_write(efx, &reg, address); 2499 efx_writeo(efx, &reg, address);
2493 falcon_read(efx, &buf, address); 2500 efx_reado(efx, &buf, address);
2494 2501
2495 if (efx_masked_compare_oword(&reg, &buf, &mask)) 2502 if (efx_masked_compare_oword(&reg, &buf, &mask))
2496 goto fail; 2503 goto fail;
@@ -2499,14 +2506,14 @@ int falcon_test_registers(struct efx_nic *efx)
2499 EFX_OR_OWORD(reg, original, mask); 2506 EFX_OR_OWORD(reg, original, mask);
2500 EFX_SET_OWORD32(reg, j, j, 0); 2507 EFX_SET_OWORD32(reg, j, j, 0);
2501 2508
2502 falcon_write(efx, &reg, address); 2509 efx_writeo(efx, &reg, address);
2503 falcon_read(efx, &buf, address); 2510 efx_reado(efx, &buf, address);
2504 2511
2505 if (efx_masked_compare_oword(&reg, &buf, &mask)) 2512 if (efx_masked_compare_oword(&reg, &buf, &mask))
2506 goto fail; 2513 goto fail;
2507 } 2514 }
2508 2515
2509 falcon_write(efx, &original, address); 2516 efx_writeo(efx, &original, address);
2510 } 2517 }
2511 2518
2512 return 0; 2519 return 0;
@@ -2571,7 +2578,7 @@ int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2571 FFE_AB_EXT_PHY_RST_DUR_10240US, 2578 FFE_AB_EXT_PHY_RST_DUR_10240US,
2572 FRF_AB_SWRST, 1); 2579 FRF_AB_SWRST, 1);
2573 } 2580 }
2574 falcon_write(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); 2581 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2575 2582
2576 EFX_LOG(efx, "waiting for hardware reset\n"); 2583 EFX_LOG(efx, "waiting for hardware reset\n");
2577 schedule_timeout_uninterruptible(HZ / 20); 2584 schedule_timeout_uninterruptible(HZ / 20);
@@ -2596,7 +2603,7 @@ int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
2596 } 2603 }
2597 2604
2598 /* Assert that reset complete */ 2605 /* Assert that reset complete */
2599 falcon_read(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); 2606 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
2600 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { 2607 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
2601 rc = -ETIMEDOUT; 2608 rc = -ETIMEDOUT;
2602 EFX_ERR(efx, "timed out waiting for hardware reset\n"); 2609 EFX_ERR(efx, "timed out waiting for hardware reset\n");
@@ -2625,16 +2632,16 @@ static int falcon_reset_sram(struct efx_nic *efx)
2625 int count; 2632 int count;
2626 2633
2627 /* Set the SRAM wake/sleep GPIO appropriately. */ 2634 /* Set the SRAM wake/sleep GPIO appropriately. */
2628 falcon_read(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); 2635 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2629 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); 2636 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
2630 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); 2637 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
2631 falcon_write(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); 2638 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
2632 2639
2633 /* Initiate SRAM reset */ 2640 /* Initiate SRAM reset */
2634 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, 2641 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
2635 FRF_AZ_SRM_INIT_EN, 1, 2642 FRF_AZ_SRM_INIT_EN, 1,
2636 FRF_AZ_SRM_NB_SZ, 0); 2643 FRF_AZ_SRM_NB_SZ, 0);
2637 falcon_write(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); 2644 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2638 2645
2639 /* Wait for SRAM reset to complete */ 2646 /* Wait for SRAM reset to complete */
2640 count = 0; 2647 count = 0;
@@ -2645,7 +2652,7 @@ static int falcon_reset_sram(struct efx_nic *efx)
2645 schedule_timeout_uninterruptible(HZ / 50); 2652 schedule_timeout_uninterruptible(HZ / 50);
2646 2653
2647 /* Check for reset complete */ 2654 /* Check for reset complete */
2648 falcon_read(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); 2655 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
2649 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { 2656 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
2650 EFX_LOG(efx, "SRAM reset complete\n"); 2657 EFX_LOG(efx, "SRAM reset complete\n");
2651 2658
@@ -2771,13 +2778,13 @@ static int falcon_probe_nic_variant(struct efx_nic *efx)
2771 efx_oword_t altera_build; 2778 efx_oword_t altera_build;
2772 efx_oword_t nic_stat; 2779 efx_oword_t nic_stat;
2773 2780
2774 falcon_read(efx, &altera_build, FR_AZ_ALTERA_BUILD); 2781 efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD);
2775 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) { 2782 if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) {
2776 EFX_ERR(efx, "Falcon FPGA not supported\n"); 2783 EFX_ERR(efx, "Falcon FPGA not supported\n");
2777 return -ENODEV; 2784 return -ENODEV;
2778 } 2785 }
2779 2786
2780 falcon_read(efx, &nic_stat, FR_AB_NIC_STAT); 2787 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2781 2788
2782 switch (falcon_rev(efx)) { 2789 switch (falcon_rev(efx)) {
2783 case FALCON_REV_A0: 2790 case FALCON_REV_A0:
@@ -2812,9 +2819,9 @@ static void falcon_probe_spi_devices(struct efx_nic *efx)
2812 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; 2819 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
2813 int boot_dev; 2820 int boot_dev;
2814 2821
2815 falcon_read(efx, &gpio_ctl, FR_AB_GPIO_CTL); 2822 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
2816 falcon_read(efx, &nic_stat, FR_AB_NIC_STAT); 2823 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
2817 falcon_read(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); 2824 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2818 2825
2819 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { 2826 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
2820 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? 2827 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
@@ -2832,7 +2839,7 @@ static void falcon_probe_spi_devices(struct efx_nic *efx)
2832 FRF_AB_EE_SF_CLOCK_DIV, 7, 2839 FRF_AB_EE_SF_CLOCK_DIV, 7,
2833 /* 125 MHz / 63 ~= 2 MHz */ 2840 /* 125 MHz / 63 ~= 2 MHz */
2834 FRF_AB_EE_EE_CLOCK_DIV, 63); 2841 FRF_AB_EE_EE_CLOCK_DIV, 63);
2835 falcon_write(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); 2842 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
2836 } 2843 }
2837 2844
2838 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) 2845 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
@@ -2946,7 +2953,7 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)
2946 int data_xoff_thr = rx_xoff_thresh_bytes >> 8; 2953 int data_xoff_thr = rx_xoff_thresh_bytes >> 8;
2947 efx_oword_t reg; 2954 efx_oword_t reg;
2948 2955
2949 falcon_read(efx, &reg, FR_AZ_RX_CFG); 2956 efx_reado(efx, &reg, FR_AZ_RX_CFG);
2950 if (falcon_rev(efx) <= FALCON_REV_A1) { 2957 if (falcon_rev(efx) <= FALCON_REV_A1) {
2951 /* Data FIFO size is 5.5K */ 2958 /* Data FIFO size is 5.5K */
2952 if (data_xon_thr < 0) 2959 if (data_xon_thr < 0)
@@ -2975,7 +2982,7 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)
2975 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); 2982 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
2976 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); 2983 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
2977 } 2984 }
2978 falcon_write(efx, &reg, FR_AZ_RX_CFG); 2985 efx_writeo(efx, &reg, FR_AZ_RX_CFG);
2979} 2986}
2980 2987
2981/* This call performs hardware-specific global initialisation, such as 2988/* This call performs hardware-specific global initialisation, such as
@@ -2988,15 +2995,15 @@ int falcon_init_nic(struct efx_nic *efx)
2988 int rc; 2995 int rc;
2989 2996
2990 /* Use on-chip SRAM */ 2997 /* Use on-chip SRAM */
2991 falcon_read(efx, &temp, FR_AB_NIC_STAT); 2998 efx_reado(efx, &temp, FR_AB_NIC_STAT);
2992 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); 2999 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
2993 falcon_write(efx, &temp, FR_AB_NIC_STAT); 3000 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
2994 3001
2995 /* Set the source of the GMAC clock */ 3002 /* Set the source of the GMAC clock */
2996 if (falcon_rev(efx) == FALCON_REV_B0) { 3003 if (falcon_rev(efx) == FALCON_REV_B0) {
2997 falcon_read(efx, &temp, FR_AB_GPIO_CTL); 3004 efx_reado(efx, &temp, FR_AB_GPIO_CTL);
2998 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true); 3005 EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
2999 falcon_write(efx, &temp, FR_AB_GPIO_CTL); 3006 efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
3000 } 3007 }
3001 3008
3002 rc = falcon_reset_sram(efx); 3009 rc = falcon_reset_sram(efx);
@@ -3005,31 +3012,31 @@ int falcon_init_nic(struct efx_nic *efx)
3005 3012
3006 /* Set positions of descriptor caches in SRAM. */ 3013 /* Set positions of descriptor caches in SRAM. */
3007 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8); 3014 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8);
3008 falcon_write(efx, &temp, FR_AZ_SRM_TX_DC_CFG); 3015 efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
3009 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8); 3016 EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8);
3010 falcon_write(efx, &temp, FR_AZ_SRM_RX_DC_CFG); 3017 efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
3011 3018
3012 /* Set TX descriptor cache size. */ 3019 /* Set TX descriptor cache size. */
3013 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER)); 3020 BUILD_BUG_ON(TX_DC_ENTRIES != (16 << TX_DC_ENTRIES_ORDER));
3014 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER); 3021 EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER);
3015 falcon_write(efx, &temp, FR_AZ_TX_DC_CFG); 3022 efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG);
3016 3023
3017 /* Set RX descriptor cache size. Set low watermark to size-8, as 3024 /* Set RX descriptor cache size. Set low watermark to size-8, as
3018 * this allows most efficient prefetching. 3025 * this allows most efficient prefetching.
3019 */ 3026 */
3020 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER)); 3027 BUILD_BUG_ON(RX_DC_ENTRIES != (16 << RX_DC_ENTRIES_ORDER));
3021 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER); 3028 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER);
3022 falcon_write(efx, &temp, FR_AZ_RX_DC_CFG); 3029 efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG);
3023 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8); 3030 EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8);
3024 falcon_write(efx, &temp, FR_AZ_RX_DC_PF_WM); 3031 efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM);
3025 3032
3026 /* Clear the parity enables on the TX data fifos as 3033 /* Clear the parity enables on the TX data fifos as
3027 * they produce false parity errors because of timing issues 3034 * they produce false parity errors because of timing issues
3028 */ 3035 */
3029 if (EFX_WORKAROUND_5129(efx)) { 3036 if (EFX_WORKAROUND_5129(efx)) {
3030 falcon_read(efx, &temp, FR_AZ_CSR_SPARE); 3037 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
3031 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); 3038 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
3032 falcon_write(efx, &temp, FR_AZ_CSR_SPARE); 3039 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
3033 } 3040 }
3034 3041
3035 /* Enable all the genuinely fatal interrupts. (They are still 3042 /* Enable all the genuinely fatal interrupts. (They are still
@@ -3043,15 +3050,15 @@ int falcon_init_nic(struct efx_nic *efx)
3043 FRF_AZ_RBUF_OWN_INT_KER_EN, 1, 3050 FRF_AZ_RBUF_OWN_INT_KER_EN, 1,
3044 FRF_AZ_TBUF_OWN_INT_KER_EN, 1); 3051 FRF_AZ_TBUF_OWN_INT_KER_EN, 1);
3045 EFX_INVERT_OWORD(temp); 3052 EFX_INVERT_OWORD(temp);
3046 falcon_write(efx, &temp, FR_AZ_FATAL_INTR_KER); 3053 efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER);
3047 3054
3048 if (EFX_WORKAROUND_7244(efx)) { 3055 if (EFX_WORKAROUND_7244(efx)) {
3049 falcon_read(efx, &temp, FR_BZ_RX_FILTER_CTL); 3056 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
3050 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); 3057 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
3051 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); 3058 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
3052 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); 3059 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
3053 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); 3060 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
3054 falcon_write(efx, &temp, FR_BZ_RX_FILTER_CTL); 3061 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
3055 } 3062 }
3056 3063
3057 falcon_setup_rss_indir_table(efx); 3064 falcon_setup_rss_indir_table(efx);
@@ -3060,17 +3067,17 @@ int falcon_init_nic(struct efx_nic *efx)
3060 /* Setup RX. Wait for descriptor is broken and must 3067 /* Setup RX. Wait for descriptor is broken and must
3061 * be disabled. RXDP recovery shouldn't be needed, but is. 3068 * be disabled. RXDP recovery shouldn't be needed, but is.
3062 */ 3069 */
3063 falcon_read(efx, &temp, FR_AA_RX_SELF_RST); 3070 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
3064 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); 3071 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
3065 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); 3072 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
3066 if (EFX_WORKAROUND_5583(efx)) 3073 if (EFX_WORKAROUND_5583(efx))
3067 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); 3074 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
3068 falcon_write(efx, &temp, FR_AA_RX_SELF_RST); 3075 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
3069 3076
3070 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be 3077 /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be
3071 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. 3078 * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q.
3072 */ 3079 */
3073 falcon_read(efx, &temp, FR_AZ_TX_RESERVED); 3080 efx_reado(efx, &temp, FR_AZ_TX_RESERVED);
3074 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe); 3081 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe);
3075 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1); 3082 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1);
3076 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1); 3083 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
@@ -3083,21 +3090,21 @@ int falcon_init_nic(struct efx_nic *efx)
3083 /* Squash TX of packets of 16 bytes or less */ 3090 /* Squash TX of packets of 16 bytes or less */
3084 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx)) 3091 if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx))
3085 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); 3092 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
3086 falcon_write(efx, &temp, FR_AZ_TX_RESERVED); 3093 efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
3087 3094
3088 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 3095 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
3089 * descriptors (which is bad). 3096 * descriptors (which is bad).
3090 */ 3097 */
3091 falcon_read(efx, &temp, FR_AZ_TX_CFG); 3098 efx_reado(efx, &temp, FR_AZ_TX_CFG);
3092 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); 3099 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
3093 falcon_write(efx, &temp, FR_AZ_TX_CFG); 3100 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
3094 3101
3095 falcon_init_rx_cfg(efx); 3102 falcon_init_rx_cfg(efx);
3096 3103
3097 /* Set destination of both TX and RX Flush events */ 3104 /* Set destination of both TX and RX Flush events */
3098 if (falcon_rev(efx) >= FALCON_REV_B0) { 3105 if (falcon_rev(efx) >= FALCON_REV_B0) {
3099 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); 3106 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
3100 falcon_write(efx, &temp, FR_BZ_DP_CTRL); 3107 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
3101 } 3108 }
3102 3109
3103 return 0; 3110 return 0;
@@ -3133,7 +3140,7 @@ void falcon_update_nic_stats(struct efx_nic *efx)
3133{ 3140{
3134 efx_oword_t cnt; 3141 efx_oword_t cnt;
3135 3142
3136 falcon_read(efx, &cnt, FR_AZ_RX_NODESC_DROP); 3143 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
3137 efx->n_rx_nodesc_drop_cnt += 3144 efx->n_rx_nodesc_drop_cnt +=
3138 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); 3145 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
3139} 3146}
diff --git a/drivers/net/sfc/falcon_boards.c b/drivers/net/sfc/falcon_boards.c
index 68ca45c5d5da..3078c005811f 100644
--- a/drivers/net/sfc/falcon_boards.c
+++ b/drivers/net/sfc/falcon_boards.c
@@ -14,7 +14,7 @@
14#include "efx.h" 14#include "efx.h"
15#include "falcon.h" 15#include "falcon.h"
16#include "regs.h" 16#include "regs.h"
17#include "falcon_io.h" 17#include "io.h"
18#include "workarounds.h" 18#include "workarounds.h"
19 19
20/* Macros for unpacking the board revision */ 20/* Macros for unpacking the board revision */
@@ -332,14 +332,14 @@ static int sfn4111t_reset(struct efx_nic *efx)
332 * FLASH_CFG_1 strap (GPIO 3) appropriately. Only change the 332 * FLASH_CFG_1 strap (GPIO 3) appropriately. Only change the
333 * output enables; the output levels should always be 0 (low) 333 * output enables; the output levels should always be 0 (low)
334 * and we rely on external pull-ups. */ 334 * and we rely on external pull-ups. */
335 falcon_read(efx, &reg, FR_AB_GPIO_CTL); 335 efx_reado(efx, &reg, FR_AB_GPIO_CTL);
336 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, true); 336 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, true);
337 falcon_write(efx, &reg, FR_AB_GPIO_CTL); 337 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
338 msleep(1000); 338 msleep(1000);
339 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, false); 339 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO2_OEN, false);
340 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, 340 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN,
341 !!(efx->phy_mode & PHY_MODE_SPECIAL)); 341 !!(efx->phy_mode & PHY_MODE_SPECIAL));
342 falcon_write(efx, &reg, FR_AB_GPIO_CTL); 342 efx_writeo(efx, &reg, FR_AB_GPIO_CTL);
343 msleep(1); 343 msleep(1);
344 344
345 mutex_unlock(&efx->i2c_adap.bus_lock); 345 mutex_unlock(&efx->i2c_adap.bus_lock);
diff --git a/drivers/net/sfc/falcon_gmac.c b/drivers/net/sfc/falcon_gmac.c
index 0d156c88ca4f..8a1b80d1ff28 100644
--- a/drivers/net/sfc/falcon_gmac.c
+++ b/drivers/net/sfc/falcon_gmac.c
@@ -14,7 +14,7 @@
14#include "falcon.h" 14#include "falcon.h"
15#include "mac.h" 15#include "mac.h"
16#include "regs.h" 16#include "regs.h"
17#include "falcon_io.h" 17#include "io.h"
18 18
19/************************************************************************** 19/**************************************************************************
20 * 20 *
@@ -41,7 +41,7 @@ static void falcon_reconfigure_gmac(struct efx_nic *efx)
41 FRF_AB_GM_TX_FC_EN, tx_fc, 41 FRF_AB_GM_TX_FC_EN, tx_fc,
42 FRF_AB_GM_RX_EN, 1, 42 FRF_AB_GM_RX_EN, 1,
43 FRF_AB_GM_RX_FC_EN, rx_fc); 43 FRF_AB_GM_RX_FC_EN, rx_fc);
44 falcon_write(efx, &reg, FR_AB_GM_CFG1); 44 efx_writeo(efx, &reg, FR_AB_GM_CFG1);
45 udelay(10); 45 udelay(10);
46 46
47 /* Configuration register 2 */ 47 /* Configuration register 2 */
@@ -53,13 +53,13 @@ static void falcon_reconfigure_gmac(struct efx_nic *efx)
53 FRF_AB_GM_FD, efx->link_fd, 53 FRF_AB_GM_FD, efx->link_fd,
54 FRF_AB_GM_PAMBL_LEN, 0x7/*datasheet recommended */); 54 FRF_AB_GM_PAMBL_LEN, 0x7/*datasheet recommended */);
55 55
56 falcon_write(efx, &reg, FR_AB_GM_CFG2); 56 efx_writeo(efx, &reg, FR_AB_GM_CFG2);
57 udelay(10); 57 udelay(10);
58 58
59 /* Max frame len register */ 59 /* Max frame len register */
60 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); 60 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
61 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_MAX_FLEN, max_frame_len); 61 EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_MAX_FLEN, max_frame_len);
62 falcon_write(efx, &reg, FR_AB_GM_MAX_FLEN); 62 efx_writeo(efx, &reg, FR_AB_GM_MAX_FLEN);
63 udelay(10); 63 udelay(10);
64 64
65 /* FIFO configuration register 0 */ 65 /* FIFO configuration register 0 */
@@ -69,42 +69,42 @@ static void falcon_reconfigure_gmac(struct efx_nic *efx)
69 FRF_AB_GMF_FRFENREQ, 1, 69 FRF_AB_GMF_FRFENREQ, 1,
70 FRF_AB_GMF_SRFENREQ, 1, 70 FRF_AB_GMF_SRFENREQ, 1,
71 FRF_AB_GMF_WTMENREQ, 1); 71 FRF_AB_GMF_WTMENREQ, 1);
72 falcon_write(efx, &reg, FR_AB_GMF_CFG0); 72 efx_writeo(efx, &reg, FR_AB_GMF_CFG0);
73 udelay(10); 73 udelay(10);
74 74
75 /* FIFO configuration register 1 */ 75 /* FIFO configuration register 1 */
76 EFX_POPULATE_OWORD_2(reg, 76 EFX_POPULATE_OWORD_2(reg,
77 FRF_AB_GMF_CFGFRTH, 0x12, 77 FRF_AB_GMF_CFGFRTH, 0x12,
78 FRF_AB_GMF_CFGXOFFRTX, 0xffff); 78 FRF_AB_GMF_CFGXOFFRTX, 0xffff);
79 falcon_write(efx, &reg, FR_AB_GMF_CFG1); 79 efx_writeo(efx, &reg, FR_AB_GMF_CFG1);
80 udelay(10); 80 udelay(10);
81 81
82 /* FIFO configuration register 2 */ 82 /* FIFO configuration register 2 */
83 EFX_POPULATE_OWORD_2(reg, 83 EFX_POPULATE_OWORD_2(reg,
84 FRF_AB_GMF_CFGHWM, 0x3f, 84 FRF_AB_GMF_CFGHWM, 0x3f,
85 FRF_AB_GMF_CFGLWM, 0xa); 85 FRF_AB_GMF_CFGLWM, 0xa);
86 falcon_write(efx, &reg, FR_AB_GMF_CFG2); 86 efx_writeo(efx, &reg, FR_AB_GMF_CFG2);
87 udelay(10); 87 udelay(10);
88 88
89 /* FIFO configuration register 3 */ 89 /* FIFO configuration register 3 */
90 EFX_POPULATE_OWORD_2(reg, 90 EFX_POPULATE_OWORD_2(reg,
91 FRF_AB_GMF_CFGHWMFT, 0x1c, 91 FRF_AB_GMF_CFGHWMFT, 0x1c,
92 FRF_AB_GMF_CFGFTTH, 0x08); 92 FRF_AB_GMF_CFGFTTH, 0x08);
93 falcon_write(efx, &reg, FR_AB_GMF_CFG3); 93 efx_writeo(efx, &reg, FR_AB_GMF_CFG3);
94 udelay(10); 94 udelay(10);
95 95
96 /* FIFO configuration register 4 */ 96 /* FIFO configuration register 4 */
97 EFX_POPULATE_OWORD_1(reg, FRF_AB_GMF_HSTFLTRFRM_PAUSE, 1); 97 EFX_POPULATE_OWORD_1(reg, FRF_AB_GMF_HSTFLTRFRM_PAUSE, 1);
98 falcon_write(efx, &reg, FR_AB_GMF_CFG4); 98 efx_writeo(efx, &reg, FR_AB_GMF_CFG4);
99 udelay(10); 99 udelay(10);
100 100
101 /* FIFO configuration register 5 */ 101 /* FIFO configuration register 5 */
102 falcon_read(efx, &reg, FR_AB_GMF_CFG5); 102 efx_reado(efx, &reg, FR_AB_GMF_CFG5);
103 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGBYTMODE, bytemode); 103 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGBYTMODE, bytemode);
104 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGHDPLX, !efx->link_fd); 104 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_CFGHDPLX, !efx->link_fd);
105 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTDRPLT64, !efx->link_fd); 105 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTDRPLT64, !efx->link_fd);
106 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTFLTRFRMDC_PAUSE, 0); 106 EFX_SET_OWORD_FIELD(reg, FRF_AB_GMF_HSTFLTRFRMDC_PAUSE, 0);
107 falcon_write(efx, &reg, FR_AB_GMF_CFG5); 107 efx_writeo(efx, &reg, FR_AB_GMF_CFG5);
108 udelay(10); 108 udelay(10);
109 109
110 /* MAC address */ 110 /* MAC address */
@@ -113,12 +113,12 @@ static void falcon_reconfigure_gmac(struct efx_nic *efx)
113 FRF_AB_GM_ADR_B1, efx->net_dev->dev_addr[4], 113 FRF_AB_GM_ADR_B1, efx->net_dev->dev_addr[4],
114 FRF_AB_GM_ADR_B2, efx->net_dev->dev_addr[3], 114 FRF_AB_GM_ADR_B2, efx->net_dev->dev_addr[3],
115 FRF_AB_GM_ADR_B3, efx->net_dev->dev_addr[2]); 115 FRF_AB_GM_ADR_B3, efx->net_dev->dev_addr[2]);
116 falcon_write(efx, &reg, FR_AB_GM_ADR1); 116 efx_writeo(efx, &reg, FR_AB_GM_ADR1);
117 udelay(10); 117 udelay(10);
118 EFX_POPULATE_OWORD_2(reg, 118 EFX_POPULATE_OWORD_2(reg,
119 FRF_AB_GM_ADR_B4, efx->net_dev->dev_addr[1], 119 FRF_AB_GM_ADR_B4, efx->net_dev->dev_addr[1],
120 FRF_AB_GM_ADR_B5, efx->net_dev->dev_addr[0]); 120 FRF_AB_GM_ADR_B5, efx->net_dev->dev_addr[0]);
121 falcon_write(efx, &reg, FR_AB_GM_ADR2); 121 efx_writeo(efx, &reg, FR_AB_GM_ADR2);
122 udelay(10); 122 udelay(10);
123 123
124 falcon_reconfigure_mac_wrapper(efx); 124 falcon_reconfigure_mac_wrapper(efx);
diff --git a/drivers/net/sfc/falcon_io.h b/drivers/net/sfc/falcon_io.h
deleted file mode 100644
index 8883092dae97..000000000000
--- a/drivers/net/sfc/falcon_io.h
+++ /dev/null
@@ -1,258 +0,0 @@
1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2008 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef EFX_FALCON_IO_H
12#define EFX_FALCON_IO_H
13
14#include <linux/io.h>
15#include <linux/spinlock.h>
16
17/**************************************************************************
18 *
19 * Falcon hardware access
20 *
21 **************************************************************************
22 *
23 * Notes on locking strategy:
24 *
25 * Most Falcon registers require 16-byte (or 8-byte, for SRAM
26 * registers) atomic writes which necessitates locking.
27 * Under normal operation few writes to the Falcon BAR are made and these
28 * registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and TX_DESC_UPD_REG) are special
29 * cased to allow 4-byte (hence lockless) accesses.
30 *
31 * It *is* safe to write to these 4-byte registers in the middle of an
32 * access to an 8-byte or 16-byte register. We therefore use a
33 * spinlock to protect accesses to the larger registers, but no locks
34 * for the 4-byte registers.
35 *
36 * A write barrier is needed to ensure that DW3 is written after DW0/1/2
37 * due to the way the 16byte registers are "collected" in the Falcon BIU
38 *
39 * We also lock when carrying out reads, to ensure consistency of the
40 * data (made possible since the BIU reads all 128 bits into a cache).
41 * Reads are very rare, so this isn't a significant performance
42 * impact. (Most data transferred from NIC to host is DMAed directly
43 * into host memory).
44 *
45 * I/O BAR access uses locks for both reads and writes (but is only provided
46 * for testing purposes).
47 */
48
49/* Special buffer descriptors (Falcon SRAM) */
50#define BUF_TBL_KER_A1 0x18000
51#define BUF_TBL_KER_B0 0x800000
52
53
54#if BITS_PER_LONG == 64
55#define FALCON_USE_QWORD_IO 1
56#endif
57
58#ifdef FALCON_USE_QWORD_IO
59static inline void _falcon_writeq(struct efx_nic *efx, __le64 value,
60 unsigned int reg)
61{
62 __raw_writeq((__force u64)value, efx->membase + reg);
63}
64static inline __le64 _falcon_readq(struct efx_nic *efx, unsigned int reg)
65{
66 return (__force __le64)__raw_readq(efx->membase + reg);
67}
68#endif
69
70static inline void _falcon_writel(struct efx_nic *efx, __le32 value,
71 unsigned int reg)
72{
73 __raw_writel((__force u32)value, efx->membase + reg);
74}
75static inline __le32 _falcon_readl(struct efx_nic *efx, unsigned int reg)
76{
77 return (__force __le32)__raw_readl(efx->membase + reg);
78}
79
80/* Writes to a normal 16-byte Falcon register, locking as appropriate. */
81static inline void falcon_write(struct efx_nic *efx, efx_oword_t *value,
82 unsigned int reg)
83{
84 unsigned long flags;
85
86 EFX_REGDUMP(efx, "writing register %x with " EFX_OWORD_FMT "\n", reg,
87 EFX_OWORD_VAL(*value));
88
89 spin_lock_irqsave(&efx->biu_lock, flags);
90#ifdef FALCON_USE_QWORD_IO
91 _falcon_writeq(efx, value->u64[0], reg + 0);
92 wmb();
93 _falcon_writeq(efx, value->u64[1], reg + 8);
94#else
95 _falcon_writel(efx, value->u32[0], reg + 0);
96 _falcon_writel(efx, value->u32[1], reg + 4);
97 _falcon_writel(efx, value->u32[2], reg + 8);
98 wmb();
99 _falcon_writel(efx, value->u32[3], reg + 12);
100#endif
101 mmiowb();
102 spin_unlock_irqrestore(&efx->biu_lock, flags);
103}
104
105/* Writes to an 8-byte Falcon SRAM register, locking as appropriate. */
106static inline void falcon_write_sram(struct efx_nic *efx, efx_qword_t *value,
107 unsigned int index)
108{
109 unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
110 unsigned long flags;
111
112 EFX_REGDUMP(efx, "writing SRAM register %x with " EFX_QWORD_FMT "\n",
113 reg, EFX_QWORD_VAL(*value));
114
115 spin_lock_irqsave(&efx->biu_lock, flags);
116#ifdef FALCON_USE_QWORD_IO
117 _falcon_writeq(efx, value->u64[0], reg + 0);
118#else
119 _falcon_writel(efx, value->u32[0], reg + 0);
120 wmb();
121 _falcon_writel(efx, value->u32[1], reg + 4);
122#endif
123 mmiowb();
124 spin_unlock_irqrestore(&efx->biu_lock, flags);
125}
126
127/* Write dword to Falcon register that allows partial writes
128 *
129 * Some Falcon registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and
130 * TX_DESC_UPD_REG) can be written to as a single dword. This allows
131 * for lockless writes.
132 */
133static inline void falcon_writel(struct efx_nic *efx, efx_dword_t *value,
134 unsigned int reg)
135{
136 EFX_REGDUMP(efx, "writing partial register %x with "EFX_DWORD_FMT"\n",
137 reg, EFX_DWORD_VAL(*value));
138
139 /* No lock required */
140 _falcon_writel(efx, value->u32[0], reg);
141}
142
143/* Read from a Falcon register
144 *
145 * This reads an entire 16-byte Falcon register in one go, locking as
146 * appropriate. It is essential to read the first dword first, as this
147 * prompts Falcon to load the current value into the shadow register.
148 */
149static inline void falcon_read(struct efx_nic *efx, efx_oword_t *value,
150 unsigned int reg)
151{
152 unsigned long flags;
153
154 spin_lock_irqsave(&efx->biu_lock, flags);
155 value->u32[0] = _falcon_readl(efx, reg + 0);
156 rmb();
157 value->u32[1] = _falcon_readl(efx, reg + 4);
158 value->u32[2] = _falcon_readl(efx, reg + 8);
159 value->u32[3] = _falcon_readl(efx, reg + 12);
160 spin_unlock_irqrestore(&efx->biu_lock, flags);
161
162 EFX_REGDUMP(efx, "read from register %x, got " EFX_OWORD_FMT "\n", reg,
163 EFX_OWORD_VAL(*value));
164}
165
166/* This reads an 8-byte Falcon SRAM entry in one go. */
167static inline void falcon_read_sram(struct efx_nic *efx, efx_qword_t *value,
168 unsigned int index)
169{
170 unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
171 unsigned long flags;
172
173 spin_lock_irqsave(&efx->biu_lock, flags);
174#ifdef FALCON_USE_QWORD_IO
175 value->u64[0] = _falcon_readq(efx, reg + 0);
176#else
177 value->u32[0] = _falcon_readl(efx, reg + 0);
178 rmb();
179 value->u32[1] = _falcon_readl(efx, reg + 4);
180#endif
181 spin_unlock_irqrestore(&efx->biu_lock, flags);
182
183 EFX_REGDUMP(efx, "read from SRAM register %x, got "EFX_QWORD_FMT"\n",
184 reg, EFX_QWORD_VAL(*value));
185}
186
187/* Read dword from Falcon register that allows partial writes (sic) */
188static inline void falcon_readl(struct efx_nic *efx, efx_dword_t *value,
189 unsigned int reg)
190{
191 value->u32[0] = _falcon_readl(efx, reg);
192 EFX_REGDUMP(efx, "read from register %x, got "EFX_DWORD_FMT"\n",
193 reg, EFX_DWORD_VAL(*value));
194}
195
196/* Write to a register forming part of a table */
197static inline void falcon_write_table(struct efx_nic *efx, efx_oword_t *value,
198 unsigned int reg, unsigned int index)
199{
200 falcon_write(efx, value, reg + index * sizeof(efx_oword_t));
201}
202
203/* Read to a register forming part of a table */
204static inline void falcon_read_table(struct efx_nic *efx, efx_oword_t *value,
205 unsigned int reg, unsigned int index)
206{
207 falcon_read(efx, value, reg + index * sizeof(efx_oword_t));
208}
209
210/* Write to a dword register forming part of a table */
211static inline void falcon_writel_table(struct efx_nic *efx, efx_dword_t *value,
212 unsigned int reg, unsigned int index)
213{
214 falcon_writel(efx, value, reg + index * sizeof(efx_oword_t));
215}
216
217/* Page-mapped register block size */
218#define FALCON_PAGE_BLOCK_SIZE 0x2000
219
220/* Calculate offset to page-mapped register block */
221#define FALCON_PAGED_REG(page, reg) \
222 ((page) * FALCON_PAGE_BLOCK_SIZE + (reg))
223
224/* As for falcon_write(), but for a page-mapped register. */
225static inline void falcon_write_page(struct efx_nic *efx, efx_oword_t *value,
226 unsigned int reg, unsigned int page)
227{
228 falcon_write(efx, value, FALCON_PAGED_REG(page, reg));
229}
230
231/* As for falcon_writel(), but for a page-mapped register. */
232static inline void falcon_writel_page(struct efx_nic *efx, efx_dword_t *value,
233 unsigned int reg, unsigned int page)
234{
235 falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
236}
237
238/* Write dword to Falcon page-mapped register with an extra lock.
239 *
240 * As for falcon_writel_page(), but for a register that suffers from
241 * SFC bug 3181. If writing to page 0, take out a lock so the BIU
242 * collector cannot be confused.
243 */
244static inline void falcon_writel_page_locked(struct efx_nic *efx,
245 efx_dword_t *value,
246 unsigned int reg,
247 unsigned int page)
248{
249 unsigned long flags = 0;
250
251 if (page == 0)
252 spin_lock_irqsave(&efx->biu_lock, flags);
253 falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
254 if (page == 0)
255 spin_unlock_irqrestore(&efx->biu_lock, flags);
256}
257
258#endif /* EFX_FALCON_IO_H */
diff --git a/drivers/net/sfc/falcon_xmac.c b/drivers/net/sfc/falcon_xmac.c
index 44e65584ee32..7e57b4a54b37 100644
--- a/drivers/net/sfc/falcon_xmac.c
+++ b/drivers/net/sfc/falcon_xmac.c
@@ -13,7 +13,7 @@
13#include "efx.h" 13#include "efx.h"
14#include "falcon.h" 14#include "falcon.h"
15#include "regs.h" 15#include "regs.h"
16#include "falcon_io.h" 16#include "io.h"
17#include "mac.h" 17#include "mac.h"
18#include "mdio_10g.h" 18#include "mdio_10g.h"
19#include "phy.h" 19#include "phy.h"
@@ -35,7 +35,7 @@ static void falcon_setup_xaui(struct efx_nic *efx)
35 if (efx->phy_type == PHY_TYPE_NONE) 35 if (efx->phy_type == PHY_TYPE_NONE)
36 return; 36 return;
37 37
38 falcon_read(efx, &sdctl, FR_AB_XX_SD_CTL); 38 efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
39 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF); 39 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
40 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF); 40 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
41 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF); 41 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
@@ -44,7 +44,7 @@ static void falcon_setup_xaui(struct efx_nic *efx)
44 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF); 44 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
45 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF); 45 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
46 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF); 46 EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
47 falcon_write(efx, &sdctl, FR_AB_XX_SD_CTL); 47 efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
48 48
49 EFX_POPULATE_OWORD_8(txdrv, 49 EFX_POPULATE_OWORD_8(txdrv,
50 FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF, 50 FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
@@ -55,7 +55,7 @@ static void falcon_setup_xaui(struct efx_nic *efx)
55 FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF, 55 FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
56 FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF, 56 FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
57 FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF); 57 FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
58 falcon_write(efx, &txdrv, FR_AB_XX_TXDRV_CTL); 58 efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
59} 59}
60 60
61int falcon_reset_xaui(struct efx_nic *efx) 61int falcon_reset_xaui(struct efx_nic *efx)
@@ -65,11 +65,11 @@ int falcon_reset_xaui(struct efx_nic *efx)
65 65
66 /* Start reset sequence */ 66 /* Start reset sequence */
67 EFX_POPULATE_DWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1); 67 EFX_POPULATE_DWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
68 falcon_write(efx, &reg, FR_AB_XX_PWR_RST); 68 efx_writeo(efx, &reg, FR_AB_XX_PWR_RST);
69 69
70 /* Wait up to 10 ms for completion, then reinitialise */ 70 /* Wait up to 10 ms for completion, then reinitialise */
71 for (count = 0; count < 1000; count++) { 71 for (count = 0; count < 1000; count++) {
72 falcon_read(efx, &reg, FR_AB_XX_PWR_RST); 72 efx_reado(efx, &reg, FR_AB_XX_PWR_RST);
73 if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 && 73 if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
74 EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) { 74 EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
75 falcon_setup_xaui(efx); 75 falcon_setup_xaui(efx);
@@ -99,12 +99,12 @@ static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
99 99
100 /* Flush the ISR */ 100 /* Flush the ISR */
101 if (enable) 101 if (enable)
102 falcon_read(efx, &reg, FR_AB_XM_MGT_INT_MSK); 102 efx_reado(efx, &reg, FR_AB_XM_MGT_INT_MSK);
103 103
104 EFX_POPULATE_OWORD_2(reg, 104 EFX_POPULATE_OWORD_2(reg,
105 FRF_AB_XM_MSK_RMTFLT, !enable, 105 FRF_AB_XM_MSK_RMTFLT, !enable,
106 FRF_AB_XM_MSK_LCLFLT, !enable); 106 FRF_AB_XM_MSK_LCLFLT, !enable);
107 falcon_write(efx, &reg, FR_AB_XM_MGT_INT_MASK); 107 efx_writeo(efx, &reg, FR_AB_XM_MGT_INT_MASK);
108} 108}
109 109
110/* Get status of XAUI link */ 110/* Get status of XAUI link */
@@ -118,7 +118,7 @@ bool falcon_xaui_link_ok(struct efx_nic *efx)
118 return true; 118 return true;
119 119
120 /* Read link status */ 120 /* Read link status */
121 falcon_read(efx, &reg, FR_AB_XX_CORE_STAT); 121 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
122 122
123 align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE); 123 align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
124 sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT); 124 sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
@@ -129,7 +129,7 @@ bool falcon_xaui_link_ok(struct efx_nic *efx)
129 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES); 129 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
130 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES); 130 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
131 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES); 131 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
132 falcon_write(efx, &reg, FR_AB_XX_CORE_STAT); 132 efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
133 133
134 /* If the link is up, then check the phy side of the xaui link */ 134 /* If the link is up, then check the phy side of the xaui link */
135 if (efx->link_up && link_ok) 135 if (efx->link_up && link_ok)
@@ -150,7 +150,7 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
150 FRF_AB_XM_RX_JUMBO_MODE, 1, 150 FRF_AB_XM_RX_JUMBO_MODE, 1,
151 FRF_AB_XM_TX_STAT_EN, 1, 151 FRF_AB_XM_TX_STAT_EN, 1,
152 FRF_AB_XM_RX_STAT_EN, 1); 152 FRF_AB_XM_RX_STAT_EN, 1);
153 falcon_write(efx, &reg, FR_AB_XM_GLB_CFG); 153 efx_writeo(efx, &reg, FR_AB_XM_GLB_CFG);
154 154
155 /* Configure TX */ 155 /* Configure TX */
156 EFX_POPULATE_DWORD_6(reg, 156 EFX_POPULATE_DWORD_6(reg,
@@ -160,7 +160,7 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
160 FRF_AB_XM_TXCRC, 1, 160 FRF_AB_XM_TXCRC, 1,
161 FRF_AB_XM_FCNTL, 1, 161 FRF_AB_XM_FCNTL, 1,
162 FRF_AB_XM_IPG, 0x3); 162 FRF_AB_XM_IPG, 0x3);
163 falcon_write(efx, &reg, FR_AB_XM_TX_CFG); 163 efx_writeo(efx, &reg, FR_AB_XM_TX_CFG);
164 164
165 /* Configure RX */ 165 /* Configure RX */
166 EFX_POPULATE_DWORD_5(reg, 166 EFX_POPULATE_DWORD_5(reg,
@@ -169,27 +169,27 @@ static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
169 FRF_AB_XM_ACPT_ALL_MCAST, 1, 169 FRF_AB_XM_ACPT_ALL_MCAST, 1,
170 FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous, 170 FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
171 FRF_AB_XM_PASS_CRC_ERR, 1); 171 FRF_AB_XM_PASS_CRC_ERR, 1);
172 falcon_write(efx, &reg, FR_AB_XM_RX_CFG); 172 efx_writeo(efx, &reg, FR_AB_XM_RX_CFG);
173 173
174 /* Set frame length */ 174 /* Set frame length */
175 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu); 175 max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
176 EFX_POPULATE_DWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len); 176 EFX_POPULATE_DWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
177 falcon_write(efx, &reg, FR_AB_XM_RX_PARAM); 177 efx_writeo(efx, &reg, FR_AB_XM_RX_PARAM);
178 EFX_POPULATE_DWORD_2(reg, 178 EFX_POPULATE_DWORD_2(reg,
179 FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len, 179 FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
180 FRF_AB_XM_TX_JUMBO_MODE, 1); 180 FRF_AB_XM_TX_JUMBO_MODE, 1);
181 falcon_write(efx, &reg, FR_AB_XM_TX_PARAM); 181 efx_writeo(efx, &reg, FR_AB_XM_TX_PARAM);
182 182
183 EFX_POPULATE_DWORD_2(reg, 183 EFX_POPULATE_DWORD_2(reg,
184 FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */ 184 FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
185 FRF_AB_XM_DIS_FCNTL, !rx_fc); 185 FRF_AB_XM_DIS_FCNTL, !rx_fc);
186 falcon_write(efx, &reg, FR_AB_XM_FC); 186 efx_writeo(efx, &reg, FR_AB_XM_FC);
187 187
188 /* Set MAC address */ 188 /* Set MAC address */
189 memcpy(&reg, &efx->net_dev->dev_addr[0], 4); 189 memcpy(&reg, &efx->net_dev->dev_addr[0], 4);
190 falcon_write(efx, &reg, FR_AB_XM_ADR_LO); 190 efx_writeo(efx, &reg, FR_AB_XM_ADR_LO);
191 memcpy(&reg, &efx->net_dev->dev_addr[4], 2); 191 memcpy(&reg, &efx->net_dev->dev_addr[4], 2);
192 falcon_write(efx, &reg, FR_AB_XM_ADR_HI); 192 efx_writeo(efx, &reg, FR_AB_XM_ADR_HI);
193} 193}
194 194
195static void falcon_reconfigure_xgxs_core(struct efx_nic *efx) 195static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
@@ -205,12 +205,12 @@ static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
205 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback; 205 bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
206 bool reset_xgxs; 206 bool reset_xgxs;
207 207
208 falcon_read(efx, &reg, FR_AB_XX_CORE_STAT); 208 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
209 old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN); 209 old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
210 old_xgmii_loopback = 210 old_xgmii_loopback =
211 EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN); 211 EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
212 212
213 falcon_read(efx, &reg, FR_AB_XX_SD_CTL); 213 efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
214 old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA); 214 old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
215 215
216 /* The PHY driver may have turned XAUI off */ 216 /* The PHY driver may have turned XAUI off */
@@ -222,20 +222,20 @@ static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
222 falcon_reset_xaui(efx); 222 falcon_reset_xaui(efx);
223 } 223 }
224 224
225 falcon_read(efx, &reg, FR_AB_XX_CORE_STAT); 225 efx_reado(efx, &reg, FR_AB_XX_CORE_STAT);
226 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG, 226 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
227 (xgxs_loopback || xaui_loopback) ? 227 (xgxs_loopback || xaui_loopback) ?
228 FFE_AB_XX_FORCE_SIG_ALL_LANES : 0); 228 FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
229 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback); 229 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
230 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback); 230 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
231 falcon_write(efx, &reg, FR_AB_XX_CORE_STAT); 231 efx_writeo(efx, &reg, FR_AB_XX_CORE_STAT);
232 232
233 falcon_read(efx, &reg, FR_AB_XX_SD_CTL); 233 efx_reado(efx, &reg, FR_AB_XX_SD_CTL);
234 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback); 234 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
235 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback); 235 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
236 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback); 236 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
237 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback); 237 EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
238 falcon_write(efx, &reg, FR_AB_XX_SD_CTL); 238 efx_writeo(efx, &reg, FR_AB_XX_SD_CTL);
239} 239}
240 240
241 241
diff --git a/drivers/net/sfc/io.h b/drivers/net/sfc/io.h
new file mode 100644
index 000000000000..b89177c27f4a
--- /dev/null
+++ b/drivers/net/sfc/io.h
@@ -0,0 +1,256 @@
1/****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef EFX_IO_H
12#define EFX_IO_H
13
14#include <linux/io.h>
15#include <linux/spinlock.h>
16
17/**************************************************************************
18 *
19 * NIC register I/O
20 *
21 **************************************************************************
22 *
23 * Notes on locking strategy:
24 *
25 * Most NIC registers require 16-byte (or 8-byte, for SRAM) atomic writes
26 * which necessitates locking.
27 * Under normal operation few writes to NIC registers are made and these
28 * registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and TX_DESC_UPD_REG) are special
29 * cased to allow 4-byte (hence lockless) accesses.
30 *
31 * It *is* safe to write to these 4-byte registers in the middle of an
32 * access to an 8-byte or 16-byte register. We therefore use a
33 * spinlock to protect accesses to the larger registers, but no locks
34 * for the 4-byte registers.
35 *
36 * A write barrier is needed to ensure that DW3 is written after DW0/1/2
37 * due to the way the 16byte registers are "collected" in the BIU.
38 *
39 * We also lock when carrying out reads, to ensure consistency of the
40 * data (made possible since the BIU reads all 128 bits into a cache).
41 * Reads are very rare, so this isn't a significant performance
42 * impact. (Most data transferred from NIC to host is DMAed directly
43 * into host memory).
44 *
45 * I/O BAR access uses locks for both reads and writes (but is only provided
46 * for testing purposes).
47 */
48
49#if BITS_PER_LONG == 64
50#define EFX_USE_QWORD_IO 1
51#endif
52
53#ifdef EFX_USE_QWORD_IO
54static inline void _efx_writeq(struct efx_nic *efx, __le64 value,
55 unsigned int reg)
56{
57 __raw_writeq((__force u64)value, efx->membase + reg);
58}
59static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg)
60{
61 return (__force __le64)__raw_readq(efx->membase + reg);
62}
63#endif
64
65static inline void _efx_writed(struct efx_nic *efx, __le32 value,
66 unsigned int reg)
67{
68 __raw_writel((__force u32)value, efx->membase + reg);
69}
70static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg)
71{
72 return (__force __le32)__raw_readl(efx->membase + reg);
73}
74
75/* Writes to a normal 16-byte Efx register, locking as appropriate. */
76static inline void efx_writeo(struct efx_nic *efx, efx_oword_t *value,
77 unsigned int reg)
78{
79 unsigned long flags __attribute__ ((unused));
80
81 EFX_REGDUMP(efx, "writing register %x with " EFX_OWORD_FMT "\n", reg,
82 EFX_OWORD_VAL(*value));
83
84 spin_lock_irqsave(&efx->biu_lock, flags);
85#ifdef EFX_USE_QWORD_IO
86 _efx_writeq(efx, value->u64[0], reg + 0);
87 wmb();
88 _efx_writeq(efx, value->u64[1], reg + 8);
89#else
90 _efx_writed(efx, value->u32[0], reg + 0);
91 _efx_writed(efx, value->u32[1], reg + 4);
92 _efx_writed(efx, value->u32[2], reg + 8);
93 wmb();
94 _efx_writed(efx, value->u32[3], reg + 12);
95#endif
96 mmiowb();
97 spin_unlock_irqrestore(&efx->biu_lock, flags);
98}
99
100/* Write an 8-byte NIC SRAM entry through the supplied mapping,
101 * locking as appropriate. */
102static inline void efx_sram_writeq(struct efx_nic *efx, void __iomem *membase,
103 efx_qword_t *value, unsigned int index)
104{
105 unsigned int addr = index * sizeof(*value);
106 unsigned long flags __attribute__ ((unused));
107
108 EFX_REGDUMP(efx, "writing SRAM address %x with " EFX_QWORD_FMT "\n",
109 addr, EFX_QWORD_VAL(*value));
110
111 spin_lock_irqsave(&efx->biu_lock, flags);
112#ifdef EFX_USE_QWORD_IO
113 __raw_writeq((__force u64)value->u64[0], membase + addr);
114#else
115 __raw_writel((__force u32)value->u32[0], membase + addr);
116 wmb();
117 __raw_writel((__force u32)value->u32[1], membase + addr + 4);
118#endif
119 mmiowb();
120 spin_unlock_irqrestore(&efx->biu_lock, flags);
121}
122
123/* Write dword to NIC register that allows partial writes
124 *
125 * Some registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and
126 * TX_DESC_UPD_REG) can be written to as a single dword. This allows
127 * for lockless writes.
128 */
129static inline void efx_writed(struct efx_nic *efx, efx_dword_t *value,
130 unsigned int reg)
131{
132 EFX_REGDUMP(efx, "writing partial register %x with "EFX_DWORD_FMT"\n",
133 reg, EFX_DWORD_VAL(*value));
134
135 /* No lock required */
136 _efx_writed(efx, value->u32[0], reg);
137}
138
139/* Read from a NIC register
140 *
141 * This reads an entire 16-byte register in one go, locking as
142 * appropriate. It is essential to read the first dword first, as this
143 * prompts the NIC to load the current value into the shadow register.
144 */
145static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
146 unsigned int reg)
147{
148 unsigned long flags __attribute__ ((unused));
149
150 spin_lock_irqsave(&efx->biu_lock, flags);
151 value->u32[0] = _efx_readd(efx, reg + 0);
152 rmb();
153 value->u32[1] = _efx_readd(efx, reg + 4);
154 value->u32[2] = _efx_readd(efx, reg + 8);
155 value->u32[3] = _efx_readd(efx, reg + 12);
156 spin_unlock_irqrestore(&efx->biu_lock, flags);
157
158 EFX_REGDUMP(efx, "read from register %x, got " EFX_OWORD_FMT "\n", reg,
159 EFX_OWORD_VAL(*value));
160}
161
162/* Read an 8-byte SRAM entry through supplied mapping,
163 * locking as appropriate. */
164static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
165 efx_qword_t *value, unsigned int index)
166{
167 unsigned int addr = index * sizeof(*value);
168 unsigned long flags __attribute__ ((unused));
169
170 spin_lock_irqsave(&efx->biu_lock, flags);
171#ifdef EFX_USE_QWORD_IO
172 value->u64[0] = (__force __le64)__raw_readq(membase + addr);
173#else
174 value->u32[0] = (__force __le32)__raw_readl(membase + addr);
175 rmb();
176 value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
177#endif
178 spin_unlock_irqrestore(&efx->biu_lock, flags);
179
180 EFX_REGDUMP(efx, "read from SRAM address %x, got "EFX_QWORD_FMT"\n",
181 addr, EFX_QWORD_VAL(*value));
182}
183
184/* Read dword from register that allows partial writes (sic) */
185static inline void efx_readd(struct efx_nic *efx, efx_dword_t *value,
186 unsigned int reg)
187{
188 value->u32[0] = _efx_readd(efx, reg);
189 EFX_REGDUMP(efx, "read from register %x, got "EFX_DWORD_FMT"\n",
190 reg, EFX_DWORD_VAL(*value));
191}
192
193/* Write to a register forming part of a table */
194static inline void efx_writeo_table(struct efx_nic *efx, efx_oword_t *value,
195 unsigned int reg, unsigned int index)
196{
197 efx_writeo(efx, value, reg + index * sizeof(efx_oword_t));
198}
199
200/* Read to a register forming part of a table */
201static inline void efx_reado_table(struct efx_nic *efx, efx_oword_t *value,
202 unsigned int reg, unsigned int index)
203{
204 efx_reado(efx, value, reg + index * sizeof(efx_oword_t));
205}
206
207/* Write to a dword register forming part of a table */
208static inline void efx_writed_table(struct efx_nic *efx, efx_dword_t *value,
209 unsigned int reg, unsigned int index)
210{
211 efx_writed(efx, value, reg + index * sizeof(efx_oword_t));
212}
213
214/* Page-mapped register block size */
215#define EFX_PAGE_BLOCK_SIZE 0x2000
216
217/* Calculate offset to page-mapped register block */
218#define EFX_PAGED_REG(page, reg) \
219 ((page) * EFX_PAGE_BLOCK_SIZE + (reg))
220
221/* As for efx_writeo(), but for a page-mapped register. */
222static inline void efx_writeo_page(struct efx_nic *efx, efx_oword_t *value,
223 unsigned int reg, unsigned int page)
224{
225 efx_writeo(efx, value, EFX_PAGED_REG(page, reg));
226}
227
228/* As for efx_writed(), but for a page-mapped register. */
229static inline void efx_writed_page(struct efx_nic *efx, efx_dword_t *value,
230 unsigned int reg, unsigned int page)
231{
232 efx_writed(efx, value, EFX_PAGED_REG(page, reg));
233}
234
235/* Write dword to page-mapped register with an extra lock.
236 *
237 * As for efx_writed_page(), but for a register that suffers from
238 * SFC bug 3181. Take out a lock so the BIU collector cannot be
239 * confused. */
240static inline void efx_writed_page_locked(struct efx_nic *efx,
241 efx_dword_t *value,
242 unsigned int reg,
243 unsigned int page)
244{
245 unsigned long flags __attribute__ ((unused));
246
247 if (page == 0) {
248 spin_lock_irqsave(&efx->biu_lock, flags);
249 efx_writed(efx, value, EFX_PAGED_REG(page, reg));
250 spin_unlock_irqrestore(&efx->biu_lock, flags);
251 } else {
252 efx_writed(efx, value, EFX_PAGED_REG(page, reg));
253 }
254}
255
256#endif /* EFX_IO_H */
diff --git a/drivers/net/sfc/selftest.c b/drivers/net/sfc/selftest.c
index 4a7be1cc5067..e5c4c9cd4520 100644
--- a/drivers/net/sfc/selftest.c
+++ b/drivers/net/sfc/selftest.c
@@ -26,7 +26,7 @@
26#include "selftest.h" 26#include "selftest.h"
27#include "workarounds.h" 27#include "workarounds.h"
28#include "spi.h" 28#include "spi.h"
29#include "falcon_io.h" 29#include "io.h"
30#include "mdio_10g.h" 30#include "mdio_10g.h"
31 31
32/* 32/*
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 10:26:09 -0500