Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux

Pull clock driver fixes from Mike Turquette:
 "Small number of fixes for clock drivers and a single null pointer
  dereference fix in the framework core code.

  The driver fixes vary from fixing section mismatch warnings to
  preventing machines from hanging (and preventing developers from
  crying)"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
  clk: fix possible null pointer dereference
  Revert "clk: ppc-corenet: Fix Section mismatch warning"
  clk: rockchip: fix deadlock possibility in cpuclk
  clk: berlin: bg2q: remove non-exist "smemc" gate clock
  clk: at91: keep slow clk enabled to prevent system hang
  clk: rockchip: fix rk3288 cpuclk core dividers
  clk: rockchip: fix rk3066 pll lock bit location
  clk: rockchip: Fix clock gate for rk3188 hclk_emem_peri
  clk: rockchip: add CLK_IGNORE_UNUSED flag to fix rk3066/rk3188 USB Host

7 files changed, 69 insertions, 28 deletions

diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c
index 32f7c1b36204..2f13bd5246b5 100644
--- a/drivers/clk/at91/clk-slow.c
+++ b/drivers/clk/at91/clk-slow.c
@@ -70,6 +70,7 @@ struct clk_sam9x5_slow {
 
 #define to_clk_sam9x5_slow(hw) container_of(hw, struct clk_sam9x5_slow, hw)
 
+static struct clk *slow_clk;
 
 static int clk_slow_osc_prepare(struct clk_hw *hw)
 {
@@ -357,6 +358,8 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
         clk = clk_register(NULL, &slowck->hw);
         if (IS_ERR(clk))
                 kfree(slowck);
+        else
+                slow_clk = clk;
 
         return clk;
 }
@@ -433,6 +436,8 @@ at91_clk_register_sam9260_slow(struct at91_pmc *pmc,
         clk = clk_register(NULL, &slowck->hw);
         if (IS_ERR(clk))
                 kfree(slowck);
+        else
+                slow_clk = clk;
 
         return clk;
 }
@@ -465,3 +470,25 @@ void __init of_at91sam9260_clk_slow_setup(struct device_node *np,
 
         of_clk_add_provider(np, of_clk_src_simple_get, clk);
 }
+
+/*
+ * FIXME: All slow clk users are not properly claiming it (get + prepare +
+ * enable) before using it.
+ * If all users properly claiming this clock decide that they don't need it
+ * anymore (or are removed), it is disabled while faulty users are still
+ * requiring it, and the system hangs.
+ * Prevent this clock from being disabled until all users are properly
+ * requesting it.
+ * Once this is done we should remove this function and the slow_clk variable.
+ */
+static int __init of_at91_clk_slow_retain(void)
+{
+        if (!slow_clk)
+                return 0;
+
+        __clk_get(slow_clk);
+        clk_prepare_enable(slow_clk);
+
+        return 0;
+}
+arch_initcall(of_at91_clk_slow_retain);
diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
index 21784e4eb3f0..440ef81ab15c 100644
--- a/drivers/clk/berlin/bg2q.c
+++ b/drivers/clk/berlin/bg2q.c
@@ -285,7 +285,6 @@ static const struct berlin2_gate_data bg2q_gates[] __initconst = {
         { "pbridge",    "perif",        15, CLK_IGNORE_UNUSED },
         { "sdio",       "perif",        16, CLK_IGNORE_UNUSED },
         { "nfc",        "perif",        18 },
-        { "smemc",      "perif",        19 },
         { "pcie",       "perif",        22 },
 };
 
diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-ppc-corenet.c
index b6e6c85507a5..0a47d6f49cd6 100644
--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-ppc-corenet.c
@@ -291,7 +291,7 @@ static const struct of_device_id ppc_clk_ids[] __initconst = {
         {}
 };
 
-static struct platform_driver ppc_corenet_clk_driver __initdata = {
+static struct platform_driver ppc_corenet_clk_driver = {
         .driver = {
                 .name = "ppc_corenet_clock",
                 .of_match_table = ppc_clk_ids,
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index f4963b7d4e17..d48ac71c6c8b 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1366,7 +1366,7 @@ static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
                 new_rate = clk->ops->determine_rate(clk->hw, rate,
                                                     &best_parent_rate,
                                                     &parent_hw);
-                parent = parent_hw->clk;
+                parent = parent_hw ? parent_hw->clk : NULL;
         } else if (clk->ops->round_rate) {
                 new_rate = clk->ops->round_rate(clk->hw, rate,
                                                 &best_parent_rate);
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 75c8c45ef728..8539c4fd34cc 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -124,10 +124,11 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
 {
         const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
         unsigned long alt_prate, alt_div;
+        unsigned long flags;
 
         alt_prate = clk_get_rate(cpuclk->alt_parent);
 
-        spin_lock(cpuclk->lock);
+        spin_lock_irqsave(cpuclk->lock, flags);
 
         /*
          * If the old parent clock speed is less than the clock speed
@@ -164,7 +165,7 @@ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
                         cpuclk->reg_base + reg_data->core_reg);
         }
 
-        spin_unlock(cpuclk->lock);
+        spin_unlock_irqrestore(cpuclk->lock, flags);
         return 0;
 }
 
@@ -173,6 +174,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
 {
         const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data;
         const struct rockchip_cpuclk_rate_table *rate;
+        unsigned long flags;
 
         rate = rockchip_get_cpuclk_settings(cpuclk, ndata->new_rate);
         if (!rate) {
@@ -181,7 +183,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
                 return -EINVAL;
         }
 
-        spin_lock(cpuclk->lock);
+        spin_lock_irqsave(cpuclk->lock, flags);
 
         if (ndata->old_rate < ndata->new_rate)
                 rockchip_cpuclk_set_dividers(cpuclk, rate);
@@ -201,7 +203,7 @@ static int rockchip_cpuclk_post_rate_change(struct rockchip_cpuclk *cpuclk,
         if (ndata->old_rate > ndata->new_rate)
                 rockchip_cpuclk_set_dividers(cpuclk, rate);
 
-        spin_unlock(cpuclk->lock);
+        spin_unlock_irqrestore(cpuclk->lock, flags);
         return 0;
 }
 
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index c54078960847..7eb684c50d42 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -210,6 +210,17 @@ PNAME(mux_sclk_hsadc_p)		= { "hsadc_src", "hsadc_frac", "ext_hsadc" };
 PNAME(mux_mac_p)                = { "gpll", "dpll" };
 PNAME(mux_sclk_macref_p)        = { "mac_src", "ext_rmii" };
 
+static struct rockchip_pll_clock rk3066_pll_clks[] __initdata = {
+        [apll] = PLL(pll_rk3066, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
+                     RK2928_MODE_CON, 0, 5, 0, rk3188_pll_rates),
+        [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
+                     RK2928_MODE_CON, 4, 4, 0, NULL),
+        [cpll] = PLL(pll_rk3066, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(8),