diff options
author | Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | 2014-12-11 11:33:45 -0500 |
---|---|---|
committer | Wolfram Sang <wsa@the-dreams.de> | 2014-12-17 13:25:55 -0500 |
commit | 12598695c26ff8fccea92bd36ee3617a6da9b0d0 (patch) | |
tree | 11d4c0253b57260dba4f176fd66b8d8a5445ea99 | |
parent | 603ba7e41bf5d405aba22294af5d075d8898176d (diff) |
i2c: mv64xxx: use BIT() macro for register value definitions
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
-rw-r--r-- | drivers/i2c/busses/i2c-mv64xxx.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c index 373f6d4e4080..eff108cbcd4c 100644 --- a/drivers/i2c/busses/i2c-mv64xxx.c +++ b/drivers/i2c/busses/i2c-mv64xxx.c | |||
@@ -30,12 +30,12 @@ | |||
30 | #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7) | 30 | #define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7) |
31 | #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3) | 31 | #define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3) |
32 | 32 | ||
33 | #define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004 | 33 | #define MV64XXX_I2C_REG_CONTROL_ACK BIT(2) |
34 | #define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008 | 34 | #define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3) |
35 | #define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010 | 35 | #define MV64XXX_I2C_REG_CONTROL_STOP BIT(4) |
36 | #define MV64XXX_I2C_REG_CONTROL_START 0x00000020 | 36 | #define MV64XXX_I2C_REG_CONTROL_START BIT(5) |
37 | #define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040 | 37 | #define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6) |
38 | #define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080 | 38 | #define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7) |
39 | 39 | ||
40 | /* Ctlr status values */ | 40 | /* Ctlr status values */ |
41 | #define MV64XXX_I2C_STATUS_BUS_ERR 0x00 | 41 | #define MV64XXX_I2C_STATUS_BUS_ERR 0x00 |
@@ -68,16 +68,16 @@ | |||
68 | #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0 | 68 | #define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0 |
69 | 69 | ||
70 | /* Bridge Control values */ | 70 | /* Bridge Control values */ |
71 | #define MV64XXX_I2C_BRIDGE_CONTROL_WR 0x00000001 | 71 | #define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0) |
72 | #define MV64XXX_I2C_BRIDGE_CONTROL_RD 0x00000002 | 72 | #define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1) |
73 | #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2 | 73 | #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2 |
74 | #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT 0x00001000 | 74 | #define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12) |
75 | #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13 | 75 | #define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13 |
76 | #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16 | 76 | #define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16 |
77 | #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE 0x00080000 | 77 | #define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19) |
78 | 78 | ||
79 | /* Bridge Status values */ | 79 | /* Bridge Status values */ |
80 | #define MV64XXX_I2C_BRIDGE_STATUS_ERROR 0x00000001 | 80 | #define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0) |
81 | #define MV64XXX_I2C_STATUS_OFFLOAD_ERROR 0xf0000001 | 81 | #define MV64XXX_I2C_STATUS_OFFLOAD_ERROR 0xf0000001 |
82 | #define MV64XXX_I2C_STATUS_OFFLOAD_OK 0xf0000000 | 82 | #define MV64XXX_I2C_STATUS_OFFLOAD_OK 0xf0000000 |
83 | 83 | ||