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authorSuman Anna <s-anna@ti.com>2014-10-22 18:22:26 -0400
committerJoerg Roedel <jroedel@suse.de>2014-10-23 08:32:25 -0400
commit124262a2eecc4c3e6e96e083e50ce4909b2d69d9 (patch)
tree92cb65cb0d754750c4c1707d76cd10f20c55818b
parentc2372aafbc4ff59bb6a6bda7ed73364d7f7c53bb (diff)
iommu/omap: Simplify omap2_iommu_fault_isr()
The function omap2_iommu_fault_isr() does an unnecessary recomputation of the return value. The logic relies on setting the same bit fields as the MMU fault error status bits, so simplify this function and remove the unneeded macros. These macros were originally exported to notify MMU faults to users prior to the IOMMU framework adaptation, but are now redundant. Signed-off-by: Suman Anna <s-anna@ti.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
-rw-r--r--drivers/iommu/omap-iommu2.c20
1 files changed, 1 insertions, 19 deletions
diff --git a/drivers/iommu/omap-iommu2.c b/drivers/iommu/omap-iommu2.c
index 372141b2267d..ce2fff37aa61 100644
--- a/drivers/iommu/omap-iommu2.c
+++ b/drivers/iommu/omap-iommu2.c
@@ -53,13 +53,6 @@
53 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \ 53 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 : \
54 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0) 54 ((pgsz) == MMU_CAM_PGSZ_4K) ? 0xfffff000 : 0)
55 55
56/* IOMMU errors */
57#define OMAP_IOMMU_ERR_TLB_MISS (1 << 0)
58#define OMAP_IOMMU_ERR_TRANS_FAULT (1 << 1)
59#define OMAP_IOMMU_ERR_EMU_MISS (1 << 2)
60#define OMAP_IOMMU_ERR_TBLWALK_FAULT (1 << 3)
61#define OMAP_IOMMU_ERR_MULTIHIT_FAULT (1 << 4)
62
63static void __iommu_set_twl(struct omap_iommu *obj, bool on) 56static void __iommu_set_twl(struct omap_iommu *obj, bool on)
64{ 57{
65 u32 l = iommu_read_reg(obj, MMU_CNTL); 58 u32 l = iommu_read_reg(obj, MMU_CNTL);
@@ -122,7 +115,6 @@ static void omap2_iommu_set_twl(struct omap_iommu *obj, bool on)
122static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra) 115static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
123{ 116{
124 u32 stat, da; 117 u32 stat, da;
125 u32 errs = 0;
126 118
127 stat = iommu_read_reg(obj, MMU_IRQSTATUS); 119 stat = iommu_read_reg(obj, MMU_IRQSTATUS);
128 stat &= MMU_IRQ_MASK; 120 stat &= MMU_IRQ_MASK;
@@ -134,19 +126,9 @@ static u32 omap2_iommu_fault_isr(struct omap_iommu *obj, u32 *ra)
134 da = iommu_read_reg(obj, MMU_FAULT_AD); 126 da = iommu_read_reg(obj, MMU_FAULT_AD);
135 *ra = da; 127 *ra = da;
136 128
137 if (stat & MMU_IRQ_TLBMISS)
138 errs |= OMAP_IOMMU_ERR_TLB_MISS;
139 if (stat & MMU_IRQ_TRANSLATIONFAULT)
140 errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
141 if (stat & MMU_IRQ_EMUMISS)
142 errs |= OMAP_IOMMU_ERR_EMU_MISS;
143 if (stat & MMU_IRQ_TABLEWALKFAULT)
144 errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
145 if (stat & MMU_IRQ_MULTIHITFAULT)
146 errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
147 iommu_write_reg(obj, stat, MMU_IRQSTATUS); 129 iommu_write_reg(obj, stat, MMU_IRQSTATUS);
148 130
149 return errs; 131 return stat;
150} 132}
151 133
152static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr) 134static void omap2_tlb_read_cr(struct omap_iommu *obj, struct cr_regs *cr)