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authorMaxim Levitsky <maximlevitsky@gmail.com>2010-09-06 17:26:11 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2010-10-21 05:54:15 -0400
commit11b64d31c00359e2e6fa73b0ae4688663e848765 (patch)
treed1f879927c661da0cb7d780f996e7ffb676cb0a5
parent991369e33f0182903d2c64e4b1c6c74ed6f83089 (diff)
[media] IR: ene_ir: updates
* Add support for newer firmware version that uses different buffer format. Makes hardware work for many users. * Register name updates * Lot of refactoring * Lots of fixes as a result of full testing * Idle mode is done now by resetting the device, and this eliminates the ugly sample_period = 75 hack. Every feature of the driver is now well tested. Signed-off-by: Maxim Levitsky <maximlevitsky@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat
-rw-r--r--drivers/media/IR/Kconfig6
-rw-r--r--drivers/media/IR/ene_ir.c978
-rw-r--r--drivers/media/IR/ene_ir.h273
3 files changed, 719 insertions, 538 deletions
diff --git a/drivers/media/IR/Kconfig b/drivers/media/IR/Kconfig
index d67fff398f74..aa4163eb7a83 100644
--- a/drivers/media/IR/Kconfig
+++ b/drivers/media/IR/Kconfig
@@ -102,15 +102,15 @@ config IR_LIRC_CODEC
102 the LIRC interface. 102 the LIRC interface.
103 103
104config IR_ENE 104config IR_ENE
105 tristate "ENE eHome Receiver/Transciever (pnp id: ENE0100/ENE02xxx)" 105 tristate "ENE eHome Receiver/Transceiver (pnp id: ENE0100/ENE02xxx)"
106 depends on PNP 106 depends on PNP
107 depends on IR_CORE 107 depends on IR_CORE
108 ---help--- 108 ---help---
109 Say Y here to enable support for integrated infrared receiver 109 Say Y here to enable support for integrated infrared receiver
110 /transciever made by ENE. 110 /transceiver made by ENE.
111 111
112 You can see if you have it by looking at lspnp output. 112 You can see if you have it by looking at lspnp output.
113 Output should include ENE0100 ENE0200 or something similiar. 113 Output should include ENE0100 ENE0200 or something similar.
114 114
115 To compile this driver as a module, choose M here: the 115 To compile this driver as a module, choose M here: the
116 module will be called ene_ir. 116 module will be called ene_ir.
diff --git a/drivers/media/IR/ene_ir.c b/drivers/media/IR/ene_ir.c
index 5447750f5e38..7880d9c72d47 100644
--- a/drivers/media/IR/ene_ir.c
+++ b/drivers/media/IR/ene_ir.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * driver for ENE KB3926 B/C/D CIR (pnp id: ENE0XXX) 2 * driver for ENE KB3926 B/C/D/E/F CIR (pnp id: ENE0XXX)
3 * 3 *
4 * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com> 4 * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
5 * 5 *
@@ -17,6 +17,17 @@
17 * along with this program; if not, write to the Free Software 17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
19 * USA 19 * USA
20 *
21 * Special thanks to:
22 * Sami R. <maesesami@gmail.com> for lot of help in debugging and therefore
23 * bringing to life support for transmission & learning mode.
24 *
25 * Charlie Andrews <charliethepilot@googlemail.com> for lots of help in
26 * bringing up the support of new firmware buffer that is popular
27 * on latest notebooks
28 *
29 * ENE for partial device documentation
30 *
20 */ 31 */
21 32
22#include <linux/kernel.h> 33#include <linux/kernel.h>
@@ -31,51 +42,59 @@
31#include <media/ir-common.h> 42#include <media/ir-common.h>
32#include "ene_ir.h" 43#include "ene_ir.h"
33 44
34 45static int sample_period;
35static int sample_period = -1; 46static bool learning_mode;
36static int enable_idle = 1;
37static int input = 1;
38static int debug; 47static int debug;
39static int txsim; 48static bool txsim;
40 49
41static int ene_irq_status(struct ene_device *dev); 50static void ene_set_reg_addr(struct ene_device *dev, u16 reg)
51{
52 outb(reg >> 8, dev->hw_io + ENE_ADDR_HI);
53 outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
54}
42 55
43/* read a hardware register */ 56/* read a hardware register */
44static u8 ene_hw_read_reg(struct ene_device *dev, u16 reg) 57static u8 ene_read_reg(struct ene_device *dev, u16 reg)
45{ 58{
46 u8 retval; 59 u8 retval;
47 outb(reg >> 8, dev->hw_io + ENE_ADDR_HI); 60 ene_set_reg_addr(dev, reg);
48 outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO);
49 retval = inb(dev->hw_io + ENE_IO); 61 retval = inb(dev->hw_io + ENE_IO);
50 62 dbg_regs("reg %04x == %02x", reg, retval);
51 ene_dbg_verbose("reg %04x == %02x", reg, retval);
52 return retval; 63 return retval;
53} 64}
54 65
55/* write a hardware register */ 66/* write a hardware register */
56static void ene_hw_write_reg(struct ene_device *dev, u16 reg, u8 value) 67static void ene_write_reg(struct ene_device *dev, u16 reg, u8 value)
57{ 68{
58 outb(reg >> 8, dev->hw_io + ENE_ADDR_HI); 69 dbg_regs("reg %04x <- %02x", reg, value);
59 outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO); 70 ene_set_reg_addr(dev, reg);
60 outb(value, dev->hw_io + ENE_IO); 71 outb(value, dev->hw_io + ENE_IO);
61
62 ene_dbg_verbose("reg %04x <- %02x", reg, value);
63} 72}
64 73
65/* change specific bits in hardware register */ 74/* Set bits in hardware register */
66static void ene_hw_write_reg_mask(struct ene_device *dev, 75static void ene_set_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
67 u16 reg, u8 value, u8 mask)
68{ 76{
69 u8 regvalue; 77 dbg_regs("reg %04x |= %02x", reg, mask);
70 78 ene_set_reg_addr(dev, reg);
71 outb(reg >> 8, dev->hw_io + ENE_ADDR_HI); 79 outb(inb(dev->hw_io + ENE_IO) | mask, dev->hw_io + ENE_IO);
72 outb(reg & 0xFF, dev->hw_io + ENE_ADDR_LO); 80}
73 81
74 regvalue = inb(dev->hw_io + ENE_IO) & ~mask; 82/* Clear bits in hardware register */
75 regvalue |= (value & mask); 83static void ene_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask)
76 outb(regvalue, dev->hw_io + ENE_IO); 84{
85 dbg_regs("reg %04x &= ~%02x ", reg, mask);
86 ene_set_reg_addr(dev, reg);
87 outb(inb(dev->hw_io + ENE_IO) & ~mask, dev->hw_io + ENE_IO);
88}
77 89
78 ene_dbg_verbose("reg %04x <- %02x (mask=%02x)", reg, value, mask); 90/* A helper to set/clear a bit in register according to boolean variable */
91static void ene_set_clear_reg_mask(struct ene_device *dev, u16 reg, u8 mask,
92 bool set)
93{
94 if (set)
95 ene_set_reg_mask(dev, reg, mask);
96 else
97 ene_clear_reg_mask(dev, reg, mask);
79} 98}
80 99
81/* detect hardware features */ 100/* detect hardware features */
@@ -83,339 +102,369 @@ static int ene_hw_detect(struct ene_device *dev)
83{ 102{
84 u8 chip_major, chip_minor; 103 u8 chip_major, chip_minor;
85 u8 hw_revision, old_ver; 104 u8 hw_revision, old_ver;
86 u8 tmp; 105 u8 fw_reg2, fw_reg1;
87 u8 fw_capabilities;
88 int pll_freq;
89
90 tmp = ene_hw_read_reg(dev, ENE_HW_UNK);
91 ene_hw_write_reg(dev, ENE_HW_UNK, tmp & ~ENE_HW_UNK_CLR);
92 106
93 chip_major = ene_hw_read_reg(dev, ENE_HW_VER_MAJOR); 107 ene_clear_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
94 chip_minor = ene_hw_read_reg(dev, ENE_HW_VER_MINOR); 108 chip_major = ene_read_reg(dev, ENE_ECVER_MAJOR);
109 chip_minor = ene_read_reg(dev, ENE_ECVER_MINOR);
110 ene_set_reg_mask(dev, ENE_ECSTS, ENE_ECSTS_RSRVD);
95 111
96 ene_hw_write_reg(dev, ENE_HW_UNK, tmp); 112 hw_revision = ene_read_reg(dev, ENE_ECHV);
97 hw_revision = ene_hw_read_reg(dev, ENE_HW_VERSION); 113 old_ver = ene_read_reg(dev, ENE_HW_VER_OLD);
98 old_ver = ene_hw_read_reg(dev, ENE_HW_VER_OLD);
99 114
100 pll_freq = (ene_hw_read_reg(dev, ENE_PLLFRH) << 4) + 115 dev->pll_freq = (ene_read_reg(dev, ENE_PLLFRH) << 4) +
101 (ene_hw_read_reg(dev, ENE_PLLFRL) >> 4); 116 (ene_read_reg(dev, ENE_PLLFRL) >> 4);
102
103 if (pll_freq != 1000)
104 dev->rx_period_adjust = 4;
105 else
106 dev->rx_period_adjust = 2;
107 117
108 118 if (sample_period != ENE_DEFAULT_SAMPLE_PERIOD)
109 ene_printk(KERN_NOTICE, "PLL freq = %d\n", pll_freq); 119 dev->rx_period_adjust =
120 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 2 : 4;
110 121
111 if (hw_revision == 0xFF) { 122 if (hw_revision == 0xFF) {
112 123 ene_warn("device seems to be disabled");
113 ene_printk(KERN_WARNING, "device seems to be disabled\n"); 124 ene_warn("send a mail to lirc-list@lists.sourceforge.net");
114 ene_printk(KERN_WARNING, 125 ene_warn("please attach output of acpidump and dmidecode");
115 "send a mail to lirc-list@lists.sourceforge.net\n");
116 ene_printk(KERN_WARNING, "please attach output of acpidump\n");
117 return -ENODEV; 126 return -ENODEV;
118 } 127 }
119 128
129 ene_notice("chip is 0x%02x%02x - kbver = 0x%02x, rev = 0x%02x",
130 chip_major, chip_minor, old_ver, hw_revision);
131
132 ene_notice("PLL freq = %d", dev->pll_freq);
133
120 if (chip_major == 0x33) { 134 if (chip_major == 0x33) {
121 ene_printk(KERN_WARNING, "chips 0x33xx aren't supported\n"); 135 ene_warn("chips 0x33xx aren't supported");
122 return -ENODEV; 136 return -ENODEV;
123 } 137 }
124 138
125 if (chip_major == 0x39 && chip_minor == 0x26 && hw_revision == 0xC0) { 139 if (chip_major == 0x39 && chip_minor == 0x26 && hw_revision == 0xC0) {
126 dev->hw_revision = ENE_HW_C; 140 dev->hw_revision = ENE_HW_C;
141 ene_notice("KB3926C detected");
127 } else if (old_ver == 0x24 && hw_revision == 0xC0) { 142 } else if (old_ver == 0x24 && hw_revision == 0xC0) {
128 dev->hw_revision = ENE_HW_B; 143 dev->hw_revision = ENE_HW_B;
129 ene_printk(KERN_NOTICE, "KB3926B detected\n"); 144 ene_notice("KB3926B detected");
130 } else { 145 } else {
131 dev->hw_revision = ENE_HW_D; 146 dev->hw_revision = ENE_HW_D;
132 ene_printk(KERN_WARNING, 147 ene_notice("KB3926D or higher detected");
133 "unknown ENE chip detected, assuming KB3926D\n");
134 ene_printk(KERN_WARNING,
135 "driver support might be not complete");
136
137 } 148 }
138 149
139 ene_printk(KERN_DEBUG,
140 "chip is 0x%02x%02x - kbver = 0x%02x, rev = 0x%02x\n",
141 chip_major, chip_minor, old_ver, hw_revision);
142
143 /* detect features hardware supports */ 150 /* detect features hardware supports */
144 if (dev->hw_revision < ENE_HW_C) 151 if (dev->hw_revision < ENE_HW_C)
145 return 0; 152 return 0;
146 153
147 fw_capabilities = ene_hw_read_reg(dev, ENE_FW2); 154 fw_reg1 = ene_read_reg(dev, ENE_FW1);
148 ene_dbg("Firmware capabilities: %02x", fw_capabilities); 155 fw_reg2 = ene_read_reg(dev, ENE_FW2);
149 156
150 dev->hw_gpio40_learning = fw_capabilities & ENE_FW2_GP40_AS_LEARN; 157 ene_notice("Firmware regs: %02x %02x", fw_reg1, fw_reg2);
151 dev->hw_learning_and_tx_capable = fw_capabilities & ENE_FW2_LEARNING;
152 158
153 dev->hw_fan_as_normal_input = dev->hw_learning_and_tx_capable && 159 dev->hw_use_gpio_0a = fw_reg2 & ENE_FW2_GP0A;
154 (fw_capabilities & ENE_FW2_FAN_AS_NRML_IN); 160 dev->hw_learning_and_tx_capable = fw_reg2 & ENE_FW2_LEARNING;
161 dev->hw_extra_buffer = fw_reg1 & ENE_FW1_HAS_EXTRA_BUF;
162 dev->hw_fan_input = dev->hw_learning_and_tx_capable &&
163 (fw_reg2 & ENE_FW2_FAN_INPUT);
155 164
156 ene_printk(KERN_NOTICE, "hardware features:\n"); 165 ene_notice("Hardware features:");
157 ene_printk(KERN_NOTICE,
158 "learning and transmit %s, gpio40_learn %s, fan_in %s\n",
159 dev->hw_learning_and_tx_capable ? "on" : "off",
160 dev->hw_gpio40_learning ? "on" : "off",
161 dev->hw_fan_as_normal_input ? "on" : "off");
162 166
163 if (dev->hw_learning_and_tx_capable) { 167 if (dev->hw_learning_and_tx_capable) {
164 ene_printk(KERN_WARNING, 168 ene_notice("* Supports transmitting & learning mode");
165 "Device supports transmitting, but that support is\n"); 169 ene_notice(" This feature is rare and therefore,");
166 ene_printk(KERN_WARNING, 170 ene_notice(" you are welcome to test it,");
167 "lightly tested. Please test it and mail\n"); 171 ene_notice(" and/or contact the author via:");
168 ene_printk(KERN_WARNING, 172 ene_notice(" lirc-list@lists.sourceforge.net");
169 "lirc-list@lists.sourceforge.net\n"); 173 ene_notice(" or maximlevitsky@gmail.com");
174
175 ene_notice("* Uses GPIO %s for IR raw input",
176 dev->hw_use_gpio_0a ? "40" : "0A");
177
178 if (dev->hw_fan_input)
179 ene_notice("* Uses unused fan feedback input as source"
180 " of demodulated IR data");
170 } 181 }
182
183 if (!dev->hw_fan_input)
184 ene_notice("* Uses GPIO %s for IR demodulated input",
185 dev->hw_use_gpio_0a ? "0A" : "40");
186
187 if (dev->hw_extra_buffer)
188 ene_notice("* Uses new style input buffer");
171 return 0; 189 return 0;
172} 190}
173 191
174/* this enables/disables IR input via gpio40*/ 192/* Sense current received carrier */
175static void ene_enable_gpio40_receive(struct ene_device *dev, int enable) 193void ene_rx_sense_carrier(struct ene_device *dev)
176{ 194{
177 ene_hw_write_reg_mask(dev, ENE_CIR_CONF2, enable ? 195 int period = ene_read_reg(dev, ENE_CIRCAR_PRD);
178 0 : ENE_CIR_CONF2_GPIO40DIS, 196 int hperiod = ene_read_reg(dev, ENE_CIRCAR_HPRD);
179 ENE_CIR_CONF2_GPIO40DIS); 197 int carrier, duty_cycle;
198
199
200 if (!(period & ENE_CIRCAR_PRD_VALID))
201 return;
202
203 period &= ~ENE_CIRCAR_PRD_VALID;
204
205 if (!period)
206 return;
207
208 dbg("RX: hardware carrier period = %02x", period);
209 dbg("RX: hardware carrier pulse period = %02x", hperiod);
210
211
212 carrier = 2000000 / period;
213 duty_cycle = (hperiod * 100) / period;
214 dbg("RX: sensed carrier = %d Hz, duty cycle %d%%",
215 carrier, duty_cycle);
216
217 /* TODO: Send carrier & duty cycle to IR layer */
180} 218}
181 219
182/* this enables/disables IR via standard input */ 220/* this enables/disables the CIR RX engine */
183static void ene_enable_normal_receive(struct ene_device *dev, int enable) 221static void ene_enable_cir_engine(struct ene_device *dev, bool enable)
184{ 222{
185 ene_hw_write_reg(dev, ENE_CIR_CONF1, enable ? ENE_CIR_CONF1_RX_ON : 0); 223 ene_set_clear_reg_mask(dev, ENE_CIRCFG,
224 ENE_CIRCFG_RX_EN | ENE_CIRCFG_RX_IRQ, enable);
186} 225}
187 226
188/* this enables/disables IR input via unused fan tachtometer input */ 227/* this selects input for CIR engine. Ether GPIO 0A or GPIO40*/
189static void ene_enable_fan_receive(struct ene_device *dev, int enable) 228static void ene_select_rx_input(struct ene_device *dev, bool gpio_0a)
190{ 229{
191 if (!enable) 230 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_GPIO0A, gpio_0a);
192 ene_hw_write_reg(dev, ENE_FAN_AS_IN1, 0);
193 else {
194 ene_hw_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);
195 ene_hw_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);
196 }
197 dev->rx_fan_input_inuse = enable;
198} 231}
199 232
200 233/*
201/* Sense current received carrier */ 234 * this enables alternative input via fan tachometer sensor and bypasses
202static int ene_rx_sense_carrier(struct ene_device *dev) 235 * the hw CIR engine
236 */
237static void ene_enable_fan_input(struct ene_device *dev, bool enable)
203{ 238{
204 int period = ene_hw_read_reg(dev, ENE_RX_CARRIER); 239 if (!dev->hw_fan_input)
205 int carrier; 240 return;
206 ene_dbg("RX: hardware carrier period = %02x", period);
207
208 if (!(period & ENE_RX_CARRIER_VALID))
209 return 0;
210
211 period &= ~ENE_RX_CARRIER_VALID;
212
213 if (!period)
214 return 0;
215 241
216 carrier = 2000000 / period; 242 if (!enable)
217 ene_dbg("RX: sensed carrier = %d Hz", carrier); 243 ene_write_reg(dev, ENE_FAN_AS_IN1, 0);
218 return carrier; 244 else {
245 ene_write_reg(dev, ENE_FAN_AS_IN1, ENE_FAN_AS_IN1_EN);
246 ene_write_reg(dev, ENE_FAN_AS_IN2, ENE_FAN_AS_IN2_EN);
247 }
248 dev->rx_fan_input_inuse = enable;
219} 249}
220 250
221/* determine which input to use*/ 251/* setup the receiver for RX*/
222static void ene_rx_set_inputs(struct ene_device *dev) 252static void ene_rx_setup(struct ene_device *dev)
223{ 253{
224 int learning_mode = dev->learning_enabled; 254 bool learning_mode = dev->learning_enabled ||
255 dev->carrier_detect_enabled;
256 int sample_period_adjust = 0;
225 257
226 ene_dbg("RX: setup receiver, learning mode = %d", learning_mode);
227 258
228 ene_enable_normal_receive(dev, 1); 259 /* set sample period*/
260 if (sample_period == ENE_DEFAULT_SAMPLE_PERIOD)
261 sample_period_adjust =
262 dev->pll_freq == ENE_DEFAULT_PLL_FREQ ? 1 : 2;
229 263
230 /* old hardware doesn't support learning mode for sure */ 264 ene_write_reg(dev, ENE_CIRRLC_CFG,
231 if (dev->hw_revision <= ENE_HW_B) 265 (sample_period + sample_period_adjust) |
232 return; 266 ENE_CIRRLC_CFG_OVERFLOW);
267 /* revB doesn't support inputs */
268 if (dev->hw_revision < ENE_HW_C)
269 goto select_timeout;
233 270
234 /* receiver not learning capable, still set gpio40 correctly */ 271 if (learning_mode && dev->hw_learning_and_tx_capable) {
235 if (!dev->hw_learning_and_tx_capable) {
236 ene_enable_gpio40_receive(dev, !dev->hw_gpio40_learning);
237 return;
238 }
239 272
240 /* enable learning mode */ 273 /* Enable the opposite of the normal input
241 if (learning_mode) { 274 That means that if GPIO40 is normally used, use GPIO0A
242 ene_enable_gpio40_receive(dev, dev->hw_gpio40_learning); 275 and vice versa.
276 This input will carry non demodulated
277 signal, and we will tell the hw to demodulate it itself */
278 ene_select_rx_input(dev, !dev->hw_use_gpio_0a);
279 dev->rx_fan_input_inuse = false;
243 280
244 /* fan input is not used for learning */ 281 /* Enable carrier demodulation */
245 if (dev->hw_fan_as_normal_input) 282 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
246 ene_enable_fan_receive(dev, 0);
247 283
248 /* disable learning mode */ 284 /* Enable carrier detection */
285 ene_set_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT,
286 dev->carrier_detect_enabled || debug);
249 } else { 287 } else {
250 if (dev->hw_fan_as_normal_input) { 288 if (dev->hw_fan_input)
251 ene_enable_fan_receive(dev, 1); 289 dev->rx_fan_input_inuse = true;
252 ene_enable_normal_receive(dev, 0); 290 else
253 } else 291 ene_select_rx_input(dev, dev->hw_use_gpio_0a);
254 ene_enable_gpio40_receive(dev, 292
255 !dev->hw_gpio40_learning); 293 /* Disable carrier detection & demodulation */
294 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_CARR_DEMOD);
295 ene_clear_reg_mask(dev, ENE_CIRCFG2, ENE_CIRCFG2_CARR_DETECT);
256 } 296 }
257 297
258 /* set few additional settings for this mode */ 298select_timeout:
259 ene_hw_write_reg_mask(dev, ENE_CIR_CONF1, learning_mode ?
260 ENE_CIR_CONF1_LEARN1 : 0, ENE_CIR_CONF1_LEARN1);
261
262 ene_hw_write_reg_mask(dev, ENE_CIR_CONF2, learning_mode ?
263 ENE_CIR_CONF2_LEARN2 : 0, ENE_CIR_CONF2_LEARN2);
264
265 if (dev->rx_fan_input_inuse) { 299 if (dev->rx_fan_input_inuse) {
266 dev->props->rx_resolution = ENE_SAMPLE_PERIOD_FAN * 1000; 300 dev->props->rx_resolution = MS_TO_NS(ENE_FW_SAMPLE_PERIOD_FAN);
267 301
268 dev->props->timeout = 302 /* Fan input doesn't support timeouts, it just ends the
269 ENE_FAN_VALUE_MASK * ENE_SAMPLE_PERIOD_FAN * 1000; 303 input with a maximum sample */
304 dev->props->min_timeout = dev->props->max_timeout =
305 MS_TO_NS(ENE_FW_SMPL_BUF_FAN_MSK *
306 ENE_FW_SAMPLE_PERIOD_FAN);
270 } else { 307 } else {
271 dev->props->rx_resolution = sample_period * 1000; 308 dev->props->rx_resolution = MS_TO_NS(sample_period);
272 dev->props->timeout = ENE_MAXGAP * 1000; 309
310 /* Theoreticly timeout is unlimited, but we cap it
311 * because it was seen that on one device, it
312 * would stop sending spaces after around 250 msec.
313 * Besides, this is close to 2^32 anyway and timeout is u32.
314 */
315 dev->props->min_timeout = MS_TO_NS(127 * sample_period);
316 dev->props->max_timeout = MS_TO_NS(200000);
273 } 317 }
318
319 if (dev->hw_learning_and_tx_capable)
320 dev->props->tx_resolution = MS_TO_NS(sample_period);
321
322 if (dev->props->timeout > dev->props->max_timeout)
323 dev->props->timeout = dev->props->max_timeout;
324 if (dev->props->timeout < dev->props->min_timeout)
325 dev->props->timeout = dev->props->min_timeout;
274} 326}
275 327
276/* Enable the device for receive */ 328/* Enable the device for receive */
277static void ene_rx_enable(struct ene_device *dev) 329static void ene_rx_enable(struct ene_device *dev)
278{ 330{
279 u8 reg_value; 331 u8 reg_value;
332 dbg("RX: setup receiver, learning mode = %d", learning_mode);
280 333
334 /* Enable system interrupt */
281 if (dev->hw_revision < ENE_HW_C) { 335 if (dev->hw_revision < ENE_HW_C) {
282 ene_hw_write_reg(dev, ENEB_IRQ, dev->irq << 1); 336 ene_write_reg(dev, ENEB_IRQ, dev->irq << 1);
283 ene_hw_write_reg(dev, ENEB_IRQ_UNK1, 0x01); 337 ene_write_reg(dev, ENEB_IRQ_UNK1, 0x01);
284 } else { 338 } else {
285 reg_value = ene_hw_read_reg(dev, ENEC_IRQ) & 0xF0; 339 reg_value = ene_read_reg(dev, ENE_IRQ) & 0xF0;
286 reg_value |= ENEC_IRQ_UNK_EN; 340 reg_value |= ENE_IRQ_UNK_EN;
287 reg_value &= ~ENEC_IRQ_STATUS; 341 reg_value &= ~ENE_IRQ_STATUS;
288 reg_value |= (dev->irq & ENEC_IRQ_MASK); 342 reg_value |= (dev->irq & ENE_IRQ_MASK);
289 ene_hw_write_reg(dev, ENEC_IRQ, reg_value); 343 ene_write_reg(dev, ENE_IRQ, reg_value);
290 ene_hw_write_reg(dev, ENE_TX_UNK1, 0x63);
291 } 344 }
292 345
293 ene_hw_write_reg(dev, ENE_CIR_CONF2, 0x00); 346 if (dev->hw_revision >= ENE_HW_C)
294 ene_rx_set_inputs(dev); 347 ene_write_reg(dev, ENE_CIRCAR_PULS, 0x63);
348
349 /* Enable the inputs */
350 ene_write_reg(dev, ENE_CIRCFG2, 0x00);
295 351
296 /* set sampling period */ 352 if (dev->rx_fan_input_inuse) {
297 ene_hw_write_reg(dev, ENE_CIR_SAMPLE_PERIOD, sample_period); 353 ene_enable_cir_engine(dev, false);
354 ene_enable_fan_input(dev, true);
355 } else {
356 ene_enable_cir_engine(dev, true);
357 ene_enable_fan_input(dev, false);
358 }
298 359
299 /* ack any pending irqs - just in case */ 360 /* ack any pending irqs - just in case */
300 ene_irq_status(dev); 361 ene_irq_status(dev);
301 362
302 /* enable firmware bits */ 363 /* enable firmware bits */
303 ene_hw_write_reg_mask(dev, ENE_FW1, 364 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
304 ENE_FW1_ENABLE | ENE_FW1_IRQ,
305 ENE_FW1_ENABLE | ENE_FW1_IRQ);
306 365
307 /* enter idle mode */ 366 /* enter idle mode */
308 ir_raw_event_set_idle(dev->idev, 1); 367 ir_raw_event_set_idle(dev->idev, true);
309 ir_raw_event_reset(dev->idev); 368 dev->rx_enabled = true;
310
311} 369}
312 370
313/* Disable the device receiver */ 371/* Disable the device receiver */
314static void ene_rx_disable(struct ene_device *dev) 372static void ene_rx_disable(struct ene_device *dev)
315{ 373{
316 /* disable inputs */ 374 /* disable inputs */
317 ene_enable_normal_receive(dev, 0); 375 ene_enable_cir_engine(dev, false);
318 376 ene_enable_fan_input(dev, false);
319 if (dev->hw_fan_as_normal_input)
320 ene_enable_fan_receive(dev, 0);
321 377
322 /* disable hardware IRQ and firmware flag */ 378 /* disable hardware IRQ and firmware flag */
323 ene_hw_write_reg_mask(dev, ENE_FW1, 0, ENE_FW1_ENABLE | ENE_FW1_IRQ); 379 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_ENABLE | ENE_FW1_IRQ);
324 380
325 ir_raw_event_set_idle(dev->idev, 1); 381 ir_raw_event_set_idle(dev->idev, true);
326 ir_raw_event_reset(dev->idev); 382 dev->rx_enabled = false;
327} 383}
328 384
329
330/* prepare transmission */ 385/* prepare transmission */
331static void ene_tx_prepare(struct ene_device *dev) 386static void ene_tx_prepare(struct ene_device *dev)
332{ 387{
333 u8 conf1; 388 u8 conf1 = ene_read_reg(dev, ENE_CIRCFG);
389 u8 fwreg2 = ene_read_reg(dev, ENE_FW2);
334 390
335 conf1 = ene_hw_read_reg(dev, ENE_CIR_CONF1);
336 dev->saved_conf1 = conf1; 391 dev->saved_conf1 = conf1;
337 392
338 if (dev->hw_revision == ENE_HW_C) 393 /* Show information about currently connected transmitter jacks */
339 conf1 &= ~ENE_CIR_CONF1_TX_CLEAR; 394 if (fwreg2 & ENE_FW2_EMMITER1_CONN)
395 dbg("TX: Transmitter #1 is connected");
340 396
341 /* Enable TX engine */ 397 if (fwreg2 & ENE_FW2_EMMITER2_CONN)
342 conf1 |= ENE_CIR_CONF1_TX_ON; 398 dbg("TX: Transmitter #2 is connected");
343 399
344 /* Set carrier */ 400 if (!(fwreg2 & (ENE_FW2_EMMITER1_CONN | ENE_FW2_EMMITER2_CONN)))
345 if (dev->tx_period) { 401 ene_warn("TX: transmitter cable isn't connected!");
402
403 /* Set transmitter mask */
404 ene_set_clear_reg_mask(dev, ENE_GPIOFS8, ENE_GPIOFS8_GPIO41,
405 !!(dev->transmitter_mask & 0x01));
406 ene_set_clear_reg_mask(dev, ENE_GPIOFS1, ENE_GPIOFS1_GPIO0D,
407 !!(dev->transmitter_mask & 0x02));
346 408
347 /* NOTE: duty cycle handling is just a guess, it might 409 /* Set the carrier period && duty cycle */
348 not be aviable. Default values were tested */ 410 if (dev->tx_period) {
349 int tx_period_in500ns = dev->tx_period * 2;
350 411
351 int tx_pulse_width_in_500ns = 412 int tx_puls_width = dev->tx_period / (100 / dev->tx_duty_cycle);
352 tx_period_in500ns / (100 / dev->tx_duty_cycle);
353 413
354 if (!tx_pulse_width_in_500ns) 414 if (!tx_puls_width)
355 tx_pulse_width_in_500ns = 1; 415 tx_puls_width = 1;
356 416
357 ene_dbg("TX: pulse distance = %d * 500 ns", tx_period_in500ns); 417 dbg("TX: pulse distance = %d * 500 ns", dev->tx_period);
358 ene_dbg("TX: pulse width = %d * 500 ns", 418 dbg("TX: pulse width = %d * 500 ns", tx_puls_width);
359 tx_pulse_width_in_500ns);
360 419
361 ene_hw_write_reg(dev, ENE_TX_PERIOD, ENE_TX_PERIOD_UNKBIT | 420 ene_write_reg(dev, ENE_CIRMOD_PRD, ENE_CIRMOD_PRD_POL |
362 tx_period_in500ns); 421 dev->tx_period);
363 422
364 ene_hw_write_reg(dev, ENE_TX_PERIOD_PULSE, 423 ene_write_reg(dev, ENE_CIRMOD_HPRD, tx_puls_width);
365 tx_pulse_width_in_500ns);
366 424
367 conf1 |= ENE_CIR_CONF1_TX_CARR; 425 conf1 |= ENE_CIRCFG_TX_CARR;
368 } else 426 } else
369 conf1 &= ~ENE_CIR_CONF1_TX_CARR; 427 conf1 &= ~ENE_CIRCFG_TX_CARR;
370 428
371 ene_hw_write_reg(dev, ENE_CIR_CONF1, conf1); 429 /* disable receive on revc */
430 if (dev->hw_revision == ENE_HW_C)
431 conf1 &= ~ENE_CIRCFG_RX_EN;
372 432
433 /* Enable TX engine */
434 conf1 |= ENE_CIRCFG_TX_EN | ENE_CIRCFG_TX_IRQ;
435 ene_write_reg(dev, ENE_CIRCFG, conf1);
373} 436}
374 437
375/* end transmission */ 438/* end transmission */
376static void ene_tx_complete(struct ene_device *dev) 439static void ene_tx_complete(struct ene_device *dev)
377{ 440{
378 ene_hw_write_reg(dev, ENE_CIR_CONF1, dev->saved_conf1); 441 ene_write_reg(dev, ENE_CIRCFG, dev->saved_conf1);
379 dev->tx_buffer = NULL; 442 dev->tx_buffer = NULL;
380} 443}
381 444
382/* set transmit mask */
383static void ene_tx_hw_set_transmiter_mask(struct ene_device *dev)
384{
385 u8 txport1 = ene_hw_read_reg(dev, ENE_TX_PORT1) & ~ENE_TX_PORT1_EN;
386 u8 txport2 = ene_hw_read_reg(dev, ENE_TX_PORT2) & ~ENE_TX_PORT2_EN;
387
388 if (dev->transmitter_mask & 0x01)
389 txport1 |= ENE_TX_PORT1_EN;
390
391 if (dev->transmitter_mask & 0x02)
392 txport2 |= ENE_TX_PORT2_EN;
393
394 ene_hw_write_reg(dev, ENE_TX_PORT1, txport1);
395 ene_hw_write_reg(dev, ENE_TX_PORT2, txport2);
396}
397 445
398/* TX one sample - must be called with dev->hw_lock*/ 446/* TX one sample - must be called with dev->hw_lock*/
399static void ene_tx_sample(struct ene_device *dev) 447static void ene_tx_sample(struct ene_device *dev)
400{ 448{
401 u8 raw_tx; 449 u8 raw_tx;
402 u32 sample; 450 u32 sample;
451 bool pulse = dev->tx_sample_pulse;
403 452
404 if (!dev->tx_buffer) { 453 if (!dev->tx_buffer) {
405 ene_dbg("TX: attempt to transmit NULL buffer"); 454 ene_warn("TX: BUG: attempt to transmit NULL buffer");
406 return; 455 return;
407 } 456 }
408 457
409 /* Grab next TX sample */ 458 /* Grab next TX sample */
410 if (!dev->tx_sample) { 459 if (!dev->tx_sample) {
411again: 460
412 if (dev->tx_pos == dev->tx_len + 1) { 461 if (dev->tx_pos == dev->tx_len) {
413 if (!dev->tx_done) { 462 if (!dev->tx_done) {
414 ene_dbg("TX: no more data to send"); 463 dbg("TX: no more data to send");
415 dev->tx_done = 1; 464 dev->tx_done = true;
416 goto exit; 465 goto exit;
417 } else { 466 } else {
418 ene_dbg("TX: last sample sent by hardware"); 467 dbg("TX: last sample sent by hardware");
419 ene_tx_complete(dev); 468 ene_tx_complete(dev);
420 complete(&dev->tx_complete); 469 complete(&dev->tx_complete);
421 return; 470 return;
@@ -425,23 +474,23 @@ again:
425 sample = dev->tx_buffer[dev->tx_pos++]; 474 sample = dev->tx_buffer[dev->tx_pos++];
426 dev->tx_sample_pulse = !dev->tx_sample_pulse; 475 dev->tx_sample_pulse = !dev->tx_sample_pulse;
427 476
428 ene_dbg("TX: sample %8d (%s)", sample, dev->tx_sample_pulse ? 477 dev->tx_sample = DIV_ROUND_CLOSEST(sample, sample_period);
429 "pulse" : "space");
430 478
431 dev->tx_sample = DIV_ROUND_CLOSEST(sample, ENE_TX_SMPL_PERIOD);
432
433 /* guard against too short samples */
434 if (!dev->tx_sample) 479 if (!dev->tx_sample)
435 goto again; 480 dev->tx_sample = 1;
436 } 481 }
437 482
438 raw_tx = min(dev->tx_sample , (unsigned int)ENE_TX_SMLP_MASK); 483 raw_tx = min(dev->tx_sample , (unsigned int)ENE_CIRRLC_OUT_MASK);
439 dev->tx_sample -= raw_tx; 484 dev->tx_sample -= raw_tx;
440 485
441 if (dev->tx_sample_pulse) 486 dbg("TX: sample %8d (%s)", raw_tx * sample_period,
442 raw_tx |= ENE_TX_PULSE_MASK; 487 pulse ? "pulse" : "space");
488 if (pulse)
489 raw_tx |= ENE_CIRRLC_OUT_PULSE;
490
491 ene_write_reg(dev,
492 dev->tx_reg ? ENE_CIRRLC_OUT1 : ENE_CIRRLC_OUT0, raw_tx);
443 493
444 ene_hw_write_reg(dev, ENE_TX_INPUT1 + dev->tx_reg, raw_tx);
445 dev->tx_reg = !dev->tx_reg; 494 dev->tx_reg = !dev->tx_reg;
446exit: 495exit:
447 /* simulate TX done interrupt */ 496 /* simulate TX done interrupt */
@@ -460,82 +509,204 @@ static void ene_tx_irqsim(unsigned long data)
460 spin_unlock_irqrestore(&dev->hw_lock, flags); 509 spin_unlock_irqrestore(&dev->hw_lock, flags);
461} 510}
462 511
512/* Read properities of hw sample buffer */
513static void ene_setup_hw_buffer(struct ene_device *dev)
514{
515 u16 tmp;
516
517 ene_read_hw_pointer(dev);
518 dev->r_pointer = dev->w_pointer;
519
520 if (!dev->hw_extra_buffer) {
521 dev->buffer_len = ENE_FW_PACKET_SIZE * 2;
522 return;
523 }
524
525 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER);
526 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER+1) << 8;
527 dev->extra_buf1_address = tmp;
528
529 dev->extra_buf1_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 2);
530
531 tmp = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 3);
532 tmp |= ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 4) << 8;
533 dev->extra_buf2_address = tmp;
534
535 dev->extra_buf2_len = ene_read_reg(dev, ENE_FW_SAMPLE_BUFFER + 5);
536
537 dev->buffer_len = dev->extra_buf1_len + dev->extra_buf2_len + 8;
538
539 ene_notice("Hardware uses 2 extended buffers:");
540 ene_notice(" 0x%04x - len : %d", dev->extra_buf1_address,
541 dev->extra_buf1_len);
542 ene_notice(" 0x%04x - len : %d", dev->extra_buf2_address,
543 dev->extra_buf2_len);
544
545 ene_notice("Total buffer len = %d", dev->buffer_len);
546
547 if (dev->buffer_len > 64 || dev->buffer_len < 16)
548 goto error;
549
550 if (dev->extra_buf1_address > 0xFBFC ||
551 dev->extra_buf1_address < 0xEC00)
552 goto error;
553
554 if (dev->extra_buf2_address > 0xFBFC ||
555 dev->extra_buf2_address < 0xEC00)
556 goto error;
557
558 if (dev->r_pointer > dev->buffer_len)
559 goto error;
560
561 ene_set_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
562 return;
563error:
564 ene_warn("Error validating extra buffers, device probably won't work");
565 dev->hw_extra_buffer = false;
566 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
567}
568
569
570/* Restore the pointers to extra buffers - to make module reload work*/
571static void ene_restore_extra_buffer(struct ene_device *dev)
572{
573 if (!dev->hw_extra_buffer)
574 return;
575
576 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 0,
577 dev->extra_buf1_address & 0xFF);
578 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 1,
579 dev->extra_buf1_address >> 8);
580 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 2, dev->extra_buf1_len);
581
582 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 3,
583 dev->extra_buf2_address & 0xFF);
584 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 4,
585 dev->extra_buf2_address >> 8);
586 ene_write_reg(dev, ENE_FW_SAMPLE_BUFFER + 5,
587 dev->extra_buf2_len);
588 ene_clear_reg_mask(dev, ENE_FW1, ENE_FW1_EXTRA_BUF_HND);
589}
590
463 591
464/* read irq status and ack it */ 592/* read irq status and ack it */
465static int ene_irq_status(struct ene_device *dev) 593static int ene_irq_status(struct ene_device *dev)
466{ 594{
467 u8 irq_status; 595 u8 irq_status;
468 u8 fw_flags1, fw_flags2; 596 u8 fw_flags1, fw_flags2;
469 int cur_rx_pointer;
470 int retval = 0; 597 int retval = 0;
471 598
472 fw_flags2 = ene_hw_read_reg(dev, ENE_FW2); 599 fw_flags2 = ene_read_reg(dev, ENE_FW2);
473 cur_rx_pointer = !!(fw_flags2 & ENE_FW2_BUF_HIGH);
474 600
475 if (dev->hw_revision < ENE_HW_C) { 601 if (dev->hw_revision < ENE_HW_C) {
476 irq_status = ene_hw_read_reg(dev, ENEB_IRQ_STATUS); 602 irq_status = ene_read_reg(dev, ENEB_IRQ_STATUS);
477 603
478 if (!(irq_status & ENEB_IRQ_STATUS_IR)) 604 if (!(irq_status & ENEB_IRQ_STATUS_IR))
479 return 0; 605 return 0;
480 606
481 ene_hw_write_reg(dev, ENEB_IRQ_STATUS, 607 ene_clear_reg_mask(dev, ENEB_IRQ_STATUS, ENEB_IRQ_STATUS_IR);
482 irq_status & ~ENEB_IRQ_STATUS_IR);
483 dev->rx_pointer = cur_rx_pointer;
484 return ENE_IRQ_RX; 608 return ENE_IRQ_RX;
485 } 609 }
486 610
487 irq_status = ene_hw_read_reg(dev, ENEC_IRQ); 611 irq_status = ene_read_reg(dev, ENE_IRQ);
488 612 if (!(irq_status & ENE_IRQ_STATUS))
489 if (!(irq_status & ENEC_IRQ_STATUS))
490 return 0; 613 return 0;
491 614
492 /* original driver does that twice - a workaround ? */ 615 /* original driver does that twice - a workaround ? */
493 ene_hw_write_reg(dev, ENEC_IRQ, irq_status & ~ENEC_IRQ_STATUS); 616 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
494 ene_hw_write_reg(dev, ENEC_IRQ, irq_status & ~ENEC_IRQ_STATUS); 617 ene_write_reg(dev, ENE_IRQ, irq_status & ~ENE_IRQ_STATUS);
495 618
496 /* clear unknown flag in F8F9 */ 619 /* check RX interrupt */
497 if (fw_flags2 & ENE_FW2_IRQ_CLR) 620 if (fw_flags2 & ENE_FW2_RXIRQ) {
498 ene_hw_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_IRQ_CLR); 621 retval |= ENE_IRQ_RX;
622 ene_write_reg(dev, ENE_FW2, fw_flags2 & ~ENE_FW2_RXIRQ);
623 }
499 624
500 /* check if this is a TX interrupt */ 625 /* check TX interrupt */
501 fw_flags1 = ene_hw_read_reg(dev, ENE_FW1); 626 fw_flags1 = ene_read_reg(dev, ENE_FW1);
502 if (fw_flags1 & ENE_FW1_TXIRQ) { 627 if (fw_flags1 & ENE_FW1_TXIRQ) {
503 ene_hw_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ); 628 ene_write_reg(dev, ENE_FW1, fw_flags1 & ~ENE_FW1_TXIRQ);
504 retval |= ENE_IRQ_TX; 629 retval |= ENE_IRQ_TX;
505 } 630 }
506 631
507 /* Check if this is RX interrupt */ 632 return retval;
508 if (dev->rx_pointer != cur_rx_pointer) { 633}
509 retval |= ENE_IRQ_RX;
510 dev->rx_pointer = cur_rx_pointer;
511 634
512 } else if (!(retval & ENE_IRQ_TX)) { 635/* Read hardware write pointer */
513 ene_dbg("RX: interrupt without change in RX pointer(%d)", 636static void ene_read_hw_pointer(struct ene_device *dev)
514 dev->rx_pointer); 637{
515 retval |= ENE_IRQ_RX; 638 if (dev->hw_extra_buffer)
639 dev->w_pointer = ene_read_reg(dev, ENE_FW_RX_POINTER);
640 else
641 dev->w_pointer = ene_read_reg(dev, ENE_FW2)
642 & ENE_FW2_BUF_WPTR ? 0 : ENE_FW_PACKET_SIZE;
643
644 dbg_verbose("RB: HW write pointer: %02x, driver read pointer: %02x",
645 dev->w_pointer, dev->r_pointer);
646}
647
648/* Gets address of next sample from HW ring buffer */
649static int ene_get_sample_reg(struct ene_device *dev)
650{
651 int r_pointer;
652
653 if (dev->r_pointer == dev->w_pointer) {
654 dbg_verbose("RB: hit end, try update w_pointer");
655 ene_read_hw_pointer(dev);
516 } 656 }
517 657
518 if ((retval & ENE_IRQ_RX) && (retval & ENE_IRQ_TX)) 658 if (dev->r_pointer == dev->w_pointer) {
519 ene_dbg("both RX and TX interrupt at same time"); 659 dbg_verbose("RB: end of data at %d", dev->r_pointer);
660 return 0;
661 }
520 662
521 return retval; 663 dbg_verbose("RB: reading at offset %d", dev->r_pointer);
664 r_pointer = dev->r_pointer;
665
666 dev->r_pointer++;
667 if (dev->r_pointer == dev->buffer_len)
668 dev->r_pointer = 0;
669
670 dbg_verbose("RB: next read will be from offset %d", dev->r_pointer);
671
672 if (r_pointer < 8) {
673 dbg_verbose("RB: read at main buffer at %d", r_pointer);
674 return ENE_FW_SAMPLE_BUFFER + r_pointer;
675 }
676
677 r_pointer -= 8;
678
679 if (r_pointer < dev->extra_buf1_len) {
680 dbg_verbose("RB: read at 1st extra buffer at %d", r_pointer);
681 return dev->extra_buf1_address + r_pointer;
682 }
683
684 r_pointer -= dev->extra_buf1_len;
685
686 if (r_pointer < dev->extra_buf2_len) {
687 dbg_verbose("RB: read at 2nd extra buffer at %d", r_pointer);
688 return dev->extra_buf2_address + r_pointer;
689 }
690
691 dbg("attempt to read beyong ring bufer end");
692 return 0;
522} 693}
523 694
524/* interrupt handler */ 695/* interrupt handler */
525static irqreturn_t ene_isr(int irq, void *data) 696static irqreturn_t ene_isr(int irq, void *data)
526{ 697{
527 u16 hw_value; 698 u16 hw_value, reg;
528 int i, hw_sample; 699 int hw_sample, irq_status;
529 int pulse; 700 bool pulse;
530 int irq_status;
531 unsigned long flags; 701 unsigned long flags;
532 int carrier = 0;
533 irqreturn_t retval = IRQ_NONE; 702 irqreturn_t retval = IRQ_NONE;
534 struct ene_device *dev = (struct ene_device *)data; 703 struct ene_device *dev = (struct ene_device *)data;
535 struct ir_raw_event ev; 704 struct ir_raw_event ev;
536 705
537
538 spin_lock_irqsave(&dev->hw_lock, flags); 706 spin_lock_irqsave(&dev->hw_lock, flags);
707
708 dbg_verbose("ISR called");
709 ene_read_hw_pointer(dev);
539 irq_status = ene_irq_status(dev); 710 irq_status = ene_irq_status(dev);
540 711
541 if (!irq_status) 712 if (!irq_status)
@@ -544,9 +715,9 @@ static irqreturn_t ene_isr(int irq, void *data)
544 retval = IRQ_HANDLED; 715 retval = IRQ_HANDLED;
545 716
546 if (irq_status & ENE_IRQ_TX) { 717 if (irq_status & ENE_IRQ_TX) {
547 718 dbg_verbose("TX interrupt");
548 if (!dev->hw_learning_and_tx_capable) { 719 if (!dev->hw_learning_and_tx_capable) {
549 ene_dbg("TX interrupt on unsupported device!"); 720 dbg("TX interrupt on unsupported device!");
550 goto unlock; 721 goto unlock;
551 } 722 }
552 ene_tx_sample(dev); 723 ene_tx_sample(dev);
@@ -555,48 +726,57 @@ static irqreturn_t ene_isr(int irq, void *data)
555 if (!(irq_status & ENE_IRQ_RX)) 726 if (!(irq_status & ENE_IRQ_RX))
556 goto unlock; 727 goto unlock;
557 728
729 dbg_verbose("RX interrupt");
558 730
559 if (dev->carrier_detect_enabled || debug) 731 if (dev->carrier_detect_enabled || debug)
560 carrier = ene_rx_sense_carrier(dev); 732 ene_rx_sense_carrier(dev);
561#if 0 733
562 /* TODO */ 734 /* On hardware that don't support extra buffer we need to trust
563 if (dev->carrier_detect_enabled && carrier) 735 the interrupt and not track the read pointer */
564 ir_raw_event_report_frequency(dev->idev, carrier); 736 if (!dev->hw_extra_buffer)
565#endif 737 dev->r_pointer = dev->w_pointer == 0 ? ENE_FW_PACKET_SIZE : 0;
738
739 while (1) {
566 740
567 for (i = 0; i < ENE_SAMPLES_SIZE; i++) { 741 reg = ene_get_sample_reg(dev);
568 hw_value = ene_hw_read_reg(dev, 742
569 ENE_SAMPLE_BUFFER + dev->rx_pointer * 4 + i); 743 dbg_verbose("next sample to read at: %04x", reg);
744 if (!reg)
745 break;
746
747 hw_value = ene_read_reg(dev, reg);
570 748
571 if (dev->rx_fan_input_inuse) { 749 if (dev->rx_fan_input_inuse) {
750
751 int offset = ENE_FW_SMPL_BUF_FAN - ENE_FW_SAMPLE_BUFFER;
752
572 /* read high part of the sample */ 753 /* read high part of the sample */
573 hw_value |= ene_hw_read_reg(dev, 754 hw_value |= ene_read_reg(dev, reg + offset) << 8;
574 ENE_SAMPLE_BUFFER_FAN + 755 pulse = hw_value & ENE_FW_SMPL_BUF_FAN_PLS;
575 dev->rx_pointer * 4 + i) << 8;
576 pulse = hw_value & ENE_FAN_SMPL_PULS_MSK;
577 756
578 /* clear space bit, and other unused bits */ 757 /* clear space bit, and other unused bits */
579 hw_value &= ENE_FAN_VALUE_MASK; 758 hw_value &= ENE_FW_SMPL_BUF_FAN_MSK;
580 hw_sample = hw_value * ENE_SAMPLE_PERIOD_FAN; 759 hw_sample = hw_value * ENE_FW_SAMPLE_PERIOD_FAN;
581 760
582 } else { 761 } else {
583 pulse = !(hw_value & ENE_SAMPLE_SPC_MASK); 762 pulse = !(hw_value & ENE_FW_SAMPLE_SPACE);
584 hw_value &= ENE_SAMPLE_VALUE_MASK; 763 hw_value &= ~ENE_FW_SAMPLE_SPACE;
585 hw_sample = hw_value * sample_period; 764 hw_sample = hw_value * sample_period;
586 765
587 if (dev->rx_period_adjust) { 766 if (dev->rx_period_adjust) {
588 hw_sample *= (100 - dev->rx_period_adjust); 767 hw_sample *= 100;
589 hw_sample /= 100; 768 hw_sample /= (100 + dev->rx_period_adjust);
590 } 769 }
591 } 770 }
592 /* no more data */
593 if (!(hw_value))
594 break;
595 771
596 ene_dbg("RX: %d (%s)", hw_sample, pulse ? "pulse" : "space"); 772 if (!dev->hw_extra_buffer && !hw_sample) {
773 dev->r_pointer = dev->w_pointer;
774 continue;
775 }
597 776
777 dbg("RX: %d (%s)", hw_sample, pulse ? "pulse" : "space");
598 778
599 ev.duration = hw_sample * 1000; 779 ev.duration = MS_TO_NS(hw_sample);
600 ev.pulse = pulse; 780 ev.pulse = pulse;
601 ir_raw_event_store_with_filter(dev->idev, &ev); 781 ir_raw_event_store_with_filter(dev->idev, &ev);
602 } 782 }
@@ -611,16 +791,14 @@ unlock:
611static void ene_setup_settings(struct ene_device *dev) 791static void ene_setup_settings(struct ene_device *dev)
612{ 792{
613 dev->tx_period = 32; 793 dev->tx_period = 32;
614 dev->tx_duty_cycle = 25; /*%*/ 794 dev->tx_duty_cycle = 50; /*%*/
615 dev->transmitter_mask = 3; 795 dev->transmitter_mask = 0x03;
616 796
617 /* Force learning mode if (input == 2), otherwise
618 let user set it with LIRC_SET_REC_CARRIER */
619 dev->learning_enabled = 797 dev->learning_enabled =
620 (input == 2 && dev->hw_learning_and_tx_capable); 798 (learning_mode && dev->hw_learning_and_tx_capable);
621
622 dev->rx_pointer = -1;
623 799
800 /* Set reasonable default timeout */
801 dev->props->timeout = MS_TO_NS(15000);
624} 802}
625 803
626/* outside interface: called on first open*/ 804/* outside interface: called on first open*/
@@ -630,8 +808,6 @@ static int ene_open(void *data)
630 unsigned long flags; 808 unsigned long flags;
631 809
632 spin_lock_irqsave(&dev->hw_lock, flags); 810 spin_lock_irqsave(&dev->hw_lock, flags);
633 dev->in_use = 1;
634 ene_setup_settings(dev);
635 ene_rx_enable(dev); 811 ene_rx_enable(dev);
636 spin_unlock_irqrestore(&dev->hw_lock, flags); 812 spin_unlock_irqrestore(&dev->hw_lock, flags);
637 return 0; 813 return 0;
@@ -645,7 +821,6 @@ static void ene_close(void *data)
645 spin_lock_irqsave(&dev->hw_lock, flags); 821 spin_lock_irqsave(&dev->hw_lock, flags);
646 822
647 ene_rx_disable(dev); 823 ene_rx_disable(dev);
648 dev->in_use = 0;
649 spin_unlock_irqrestore(&dev->hw_lock, flags); 824 spin_unlock_irqrestore(&dev->hw_lock, flags);
650} 825}
651 826
@@ -654,11 +829,11 @@ static int ene_set_tx_mask(void *data, u32 tx_mask)
654{ 829{
655 struct ene_device *dev = (struct ene_device *)data; 830 struct ene_device *dev = (struct ene_device *)data;
656 unsigned long flags; 831 unsigned long flags;
657 ene_dbg("TX: attempt to set transmitter mask %02x", tx_mask); 832 dbg("TX: attempt to set transmitter mask %02x", tx_mask);
658 833
659 /* invalid txmask */ 834 /* invalid txmask */
660 if (!tx_mask || tx_mask & ~0x3) { 835 if (!tx_mask || tx_mask & ~0x03) {
661 ene_dbg("TX: invalid mask"); 836 dbg("TX: invalid mask");
662 /* return count of transmitters */ 837 /* return count of transmitters */
663 return 2; 838 return 2;
664 } 839 }
@@ -674,28 +849,42 @@ static int ene_set_tx_carrier(void *data, u32 carrier)
674{ 849{
675 struct ene_device *dev = (struct ene_device *)data; 850 struct ene_device *dev = (struct ene_device *)data;
676 unsigned long flags; 851 unsigned long flags;
677 u32 period = 1000000 / carrier; /* (1 / freq) (* # usec in 1 sec) */ 852 u32 period = 2000000 / carrier;
678 853
679 ene_dbg("TX: attempt to set tx carrier to %d kHz", carrier); 854 dbg("TX: attempt to set tx carrier to %d kHz", carrier);
680 855
681 if (period && (period > ENE_TX_PERIOD_MAX || 856 if (period && (period > ENE_CIRMOD_PRD_MAX ||
682 period < ENE_TX_PERIOD_MIN)) { 857 period < ENE_CIRMOD_PRD_MIN)) {
683 858
684 ene_dbg("TX: out of range %d-%d carrier, " 859 dbg("TX: out of range %d-%d kHz carrier",
685 "falling back to 32 kHz", 860 2000 / ENE_CIRMOD_PRD_MIN,
686 1000 / ENE_TX_PERIOD_MIN, 861 2000 / ENE_CIRMOD_PRD_MAX);
687 1000 / ENE_TX_PERIOD_MAX);
688 862
689 period = 32; /* this is just a coincidence!!! */ 863 return -1;
690 } 864 }
691 ene_dbg("TX: set carrier to %d kHz", carrier);
692 865
866 dbg("TX: set carrier to %d kHz", carrier);
693 spin_lock_irqsave(&dev->hw_lock, flags); 867 spin_lock_irqsave(&dev->hw_lock, flags);
694 dev->tx_period = period; 868 dev->tx_period = period;
695 spin_unlock_irqrestore(&dev->hw_lock, flags); 869 spin_unlock_irqrestore(&dev->hw_lock, flags);
696 return 0; 870 return 0;
697} 871}
698 872
873/*outside interface : set tx duty cycle */
874static int ene_set_tx_duty_cycle(void *data, u32 duty_cycle)
875{
876 struct ene_device *dev = (struct ene_device *)data;
877 unsigned long flags;
878
879 dbg("TX: setting duty cycle to %d%%", duty_cycle);
880
881 BUG_ON(!duty_cycle || duty_cycle >= 100);
882
883 spin_lock_irqsave(&dev->hw_lock, flags);
884 dev->tx_duty_cycle = duty_cycle;
885 spin_unlock_irqrestore(&dev->hw_lock, flags);
886 return 0;
887}
699 888
700/* outside interface: enable learning mode */ 889/* outside interface: enable learning mode */
701static int ene_set_learning_mode(void *data, int enable) 890static int ene_set_learning_mode(void *data, int enable)
@@ -707,31 +896,25 @@ static int ene_set_learning_mode(void *data, int enable)
707 896
708 spin_lock_irqsave(&dev->hw_lock, flags); 897 spin_lock_irqsave(&dev->hw_lock, flags);
709 dev->learning_enabled = enable; 898 dev->learning_enabled = enable;
710 ene_rx_set_inputs(dev); 899 ene_rx_disable(dev);
900 ene_rx_setup(dev);
901 ene_rx_enable(dev);
711 spin_unlock_irqrestore(&dev->hw_lock, flags); 902 spin_unlock_irqrestore(&dev->hw_lock, flags);
712 return 0; 903 return 0;
713} 904}
714 905
715/* outside interface: set rec carrier */
716static int ene_set_rec_carrier(void *data, u32 min, u32 max)
717{
718 struct ene_device *dev = (struct ene_device *)data;
719 ene_set_learning_mode(dev,
720 max > ENE_NORMAL_RX_HI || min < ENE_NORMAL_RX_LOW);
721 return 0;
722}
723
724/* outside interface: enable or disable idle mode */ 906/* outside interface: enable or disable idle mode */
725static void ene_rx_set_idle(void *data, int idle) 907static void ene_rx_set_idle(void *data, int idle)
726{ 908{
727 struct ene_device *dev = (struct ene_device *)data; 909 struct ene_device *dev = (struct ene_device *)data;
728 ene_dbg("%sabling idle mode", idle ? "en" : "dis");
729 910
730 ene_hw_write_reg_mask(dev, ENE_CIR_SAMPLE_PERIOD, 911 if (!idle)
731 (enable_idle && idle) ? 0 : ENE_CIR_SAMPLE_OVERFLOW, 912 return;
732 ENE_CIR_SAMPLE_OVERFLOW);
733}
734 913
914 dbg("RX: stopping the receiver");
915 ene_clear_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
916 ene_set_reg_mask(dev, ENE_CIRCFG, ENE_CIRCFG_RX_EN);
917}
735 918
736/* outside interface: transmit */ 919/* outside interface: transmit */
737static int ene_transmit(void *data, int *buf, u32 n) 920static int ene_transmit(void *data, int *buf, u32 n)
@@ -747,11 +930,10 @@ static int ene_transmit(void *data, int *buf, u32 n)
747 dev->tx_sample = 0; 930 dev->tx_sample = 0;
748 dev->tx_sample_pulse = 0; 931 dev->tx_sample_pulse = 0;
749 932
750 ene_dbg("TX: %d samples", dev->tx_len); 933 dbg("TX: %d samples", dev->tx_len);
751 934
752 spin_lock_irqsave(&dev->hw_lock, flags); 935 spin_lock_irqsave(&dev->hw_lock, flags);
753 936
754 ene_tx_hw_set_transmiter_mask(dev);
755 ene_tx_prepare(dev); 937 ene_tx_prepare(dev);
756 938
757 /* Transmit first two samples */ 939 /* Transmit first two samples */
@@ -761,16 +943,15 @@ static int ene_transmit(void *data, int *buf, u32 n)
761 spin_unlock_irqrestore(&dev->hw_lock, flags); 943 spin_unlock_irqrestore(&dev->hw_lock, flags);
762 944
763 if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) { 945 if (wait_for_completion_timeout(&dev->tx_complete, 2 * HZ) == 0) {
764 ene_dbg("TX: timeout"); 946 dbg("TX: timeout");
765 spin_lock_irqsave(&dev->hw_lock, flags); 947 spin_lock_irqsave(&dev->hw_lock, flags);
766 ene_tx_complete(dev); 948 ene_tx_complete(dev);
767 spin_unlock_irqrestore(&dev->hw_lock, flags); 949 spin_unlock_irqrestore(&dev->hw_lock, flags);
768 } else 950 } else
769 ene_dbg("TX: done"); 951 dbg("TX: done");
770 return n; 952 return n;
771} 953}
772 954
773
774/* probe entry */ 955/* probe entry */
775static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id) 956static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id)
776{ 957{
@@ -791,41 +972,47 @@ static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id)
791 error = -ENODEV; 972 error = -ENODEV;
792 973
793 if (!pnp_port_valid(pnp_dev, 0) || 974 if (!pnp_port_valid(pnp_dev, 0) ||
794 pnp_port_len(pnp_dev, 0) < ENE_MAX_IO) 975 pnp_port_len(pnp_dev, 0) < ENE_IO_SIZE)
795 goto error; 976 goto error;
796 977
797 if (!pnp_irq_valid(pnp_dev, 0)) 978 if (!pnp_irq_valid(pnp_dev, 0))
798 goto error; 979 goto error;
799 980
800 dev->hw_io = pnp_port_start(pnp_dev, 0);
801 dev->irq = pnp_irq(pnp_dev, 0);
802 spin_lock_init(&dev->hw_lock); 981 spin_lock_init(&dev->hw_lock);
803 982
804 /* claim the resources */ 983 /* claim the resources */
805 error = -EBUSY; 984 error = -EBUSY;
806 if (!request_region(dev->hw_io, ENE_MAX_IO, ENE_DRIVER_NAME)) 985 dev->hw_io = pnp_port_start(pnp_dev, 0);
986 if (!request_region(dev->hw_io, ENE_IO_SIZE, ENE_DRIVER_NAME)) {
987 dev->hw_io = -1;
988 dev->irq = -1;
807 goto error; 989 goto error;
990 }
808 991
992 dev->irq = pnp_irq(pnp_dev, 0);
809 if (request_irq(dev->irq, ene_isr, 993 if (request_irq(dev->irq, ene_isr,
810 IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev)) 994 IRQF_SHARED, ENE_DRIVER_NAME, (void *)dev)) {
995 dev->irq = -1;
811 goto error; 996 goto error;
997 }
812 998
813 pnp_set_drvdata(pnp_dev, dev); 999 pnp_set_drvdata(pnp_dev, dev);
814 dev->pnp_dev = pnp_dev; 1000 dev->pnp_dev = pnp_dev;
815 1001
1002 /* don't allow too short/long sample periods */
1003 if (sample_period < 5 || sample_period > 0x7F)
1004 sample_period = ENE_DEFAULT_SAMPLE_PERIOD;
1005
816 /* detect hardware version and features */ 1006 /* detect hardware version and features */
817 error = ene_hw_detect(dev); 1007 error = ene_hw_detect(dev);
818 if (error) 1008 if (error)
819 goto error; 1009 goto error;
820 1010
821 ene_setup_settings(dev);
822
823 if (!dev->hw_learning_and_tx_capable && txsim) { 1011 if (!dev->hw_learning_and_tx_capable && txsim) {
824 dev->hw_learning_and_tx_capable = 1; 1012 dev->hw_learning_and_tx_capable = true;
825 setup_timer(&dev->tx_sim_timer, ene_tx_irqsim, 1013 setup_timer(&dev->tx_sim_timer, ene_tx_irqsim,
826 (long unsigned int)dev); 1014 (long unsigned int)dev);
827 ene_printk(KERN_WARNING, 1015 ene_warn("Simulation of TX activated");
828 "Simulation of TX activated\n");
829 } 1016 }
830 1017
831 ir_props->driver_type = RC_DRIVER_IR_RAW; 1018 ir_props->driver_type = RC_DRIVER_IR_RAW;
@@ -833,72 +1020,45 @@ static int ene_probe(struct pnp_dev *pnp_dev, const struct pnp_device_id *id)
833 ir_props->priv = dev; 1020 ir_props->priv = dev;
834 ir_props->open = ene_open; 1021 ir_props->open = ene_open;
835 ir_props->close = ene_close; 1022 ir_props->close = ene_close;
836 ir_props->min_timeout = ENE_MINGAP * 1000; 1023 ir_props->s_idle = ene_rx_set_idle;
837 ir_props->max_timeout = ENE_MAXGAP * 1000;
838 ir_props->timeout = ENE_MAXGAP * 1000;
839
840 if (dev->hw_revision == ENE_HW_B)
841 ir_props->s_idle = ene_rx_set_idle;
842
843 1024
844 dev->props = ir_props; 1025 dev->props = ir_props;
845 dev->idev = input_dev; 1026 dev->idev = input_dev;
846 1027
847 /* don't allow too short/long sample periods */
848 if (sample_period < 5 || sample_period > 0x7F)
849 sample_period = -1;
850
851 /* choose default sample period */
852 if (sample_period == -1) {
853
854 sample_period = 50;
855
856 /* on revB, hardware idle mode eats first sample
857 if we set too low sample period */
858 if (dev->hw_revision == ENE_HW_B && enable_idle)
859 sample_period = 75;
860 }
861
862 ir_props->rx_resolution = sample_period * 1000;
863
864 if (dev->hw_learning_and_tx_capable) { 1028 if (dev->hw_learning_and_tx_capable) {
865
866 ir_props->s_learning_mode = ene_set_learning_mode; 1029 ir_props->s_learning_mode = ene_set_learning_mode;
867
868 if (input == 0)
869 ir_props->s_rx_carrier_range = ene_set_rec_carrier;
870
871 init_completion(&dev->tx_complete); 1030 init_completion(&dev->tx_complete);
872 ir_props->tx_ir = ene_transmit; 1031 ir_props->tx_ir = ene_transmit;
873 ir_props->s_tx_mask = ene_set_tx_mask; 1032 ir_props->s_tx_mask = ene_set_tx_mask;
874 ir_props->s_tx_carrier = ene_set_tx_carrier; 1033 ir_props->s_tx_carrier = ene_set_tx_carrier;
875 ir_props->tx_resolution = ENE_TX_SMPL_PERIOD * 1000; 1034 ir_props->s_tx_duty_cycle = ene_set_tx_duty_cycle;
876 /* ir_props->s_carrier_report = ene_set_carrier_report; */ 1035 /* ir_props->s_carrier_report = ene_set_carrier_report; */
877 } 1036 }
878 1037
1038 ene_setup_hw_buffer(dev);
1039 ene_setup_settings(dev);
1040 ene_rx_setup(dev);
879 1041
880 device_set_wakeup_capable(&pnp_dev->dev, 1); 1042 device_set_wakeup_capable(&pnp_dev->dev, true);
881 device_set_wakeup_enable(&pnp_dev->dev, 1); 1043 device_set_wakeup_enable(&pnp_dev->dev, true);
882 1044
883 if (dev->hw_learning_and_tx_capable) 1045 if (dev->hw_learning_and_tx_capable)
884 input_dev->name = "ENE eHome Infrared Remote Transceiver"; 1046 input_dev->name = "ENE eHome Infrared Remote Transceiver";
885 else 1047 else
886 input_dev->name = "ENE eHome Infrared Remote Receiver"; 1048 input_dev->name = "ENE eHome Infrared Remote Receiver";
887 1049
888
889 error = -ENODEV; 1050 error = -ENODEV;
890 if (ir_input_register(input_dev, RC_MAP_RC6_MCE, ir_props, 1051 if (ir_input_register(input_dev, RC_MAP_RC6_MCE, ir_props,
891 ENE_DRIVER_NAME)) 1052 ENE_DRIVER_NAME))
892 goto error; 1053 goto error;
893 1054
894 1055 ene_notice("driver has been succesfully loaded");
895 ene_printk(KERN_NOTICE, "driver has been succesfully loaded\n");
896 return 0; 1056 return 0;
897error: 1057error:
898 if (dev->irq) 1058 if (dev && dev->irq >= 0)
899 free_irq(dev->irq, dev); 1059 free_irq(dev->irq, dev);
900 if (dev->hw_io) 1060 if (dev && dev->hw_io >= 0)
901 release_region(dev->hw_io, ENE_MAX_IO); 1061 release_region(dev->hw_io, ENE_IO_SIZE);
902 1062
903 input_free_device(input_dev); 1063 input_free_device(input_dev);
904 kfree(ir_props); 1064 kfree(ir_props);
@@ -914,10 +1074,11 @@ static void ene_remove(struct pnp_dev *pnp_dev)
914 1074
915 spin_lock_irqsave(&dev->hw_lock, flags); 1075 spin_lock_irqsave(&dev->hw_lock, flags);
916 ene_rx_disable(dev); 1076 ene_rx_disable(dev);
1077 ene_restore_extra_buffer(dev);
917 spin_unlock_irqrestore(&dev->hw_lock, flags); 1078 spin_unlock_irqrestore(&dev->hw_lock, flags);
918 1079
919 free_irq(dev->irq, dev); 1080 free_irq(dev->irq, dev);
920 release_region(dev->hw_io, ENE_MAX_IO); 1081 release_region(dev->hw_io, ENE_IO_SIZE);
921 ir_input_unregister(dev->idev); 1082 ir_input_unregister(dev->idev);
922 kfree(dev->props); 1083 kfree(dev->props);
923 kfree(dev); 1084 kfree(dev);
@@ -927,28 +1088,28 @@ static void ene_remove(struct pnp_dev *pnp_dev)
927static void ene_enable_wake(struct ene_device *dev, int enable) 1088static void ene_enable_wake(struct ene_device *dev, int enable)
928{ 1089{
929 enable = enable && device_may_wakeup(&dev->pnp_dev->dev); 1090 enable = enable && device_may_wakeup(&dev->pnp_dev->dev);
930 1091 dbg("wake on IR %s", enable ? "enabled" : "disabled");
931 ene_dbg("wake on IR %s", enable ? "enabled" : "disabled"); 1092 ene_set_clear_reg_mask(dev, ENE_FW1, ENE_FW1_WAKE, enable);
932
933 ene_hw_write_reg_mask(dev, ENE_FW1, enable ?
934 ENE_FW1_WAKE : 0, ENE_FW1_WAKE);
935} 1093}
936 1094
937#ifdef CONFIG_PM 1095#ifdef CONFIG_PM
938static int ene_suspend(struct pnp_dev *pnp_dev, pm_message_t state) 1096static int ene_suspend(struct pnp_dev *pnp_dev, pm_message_t state)
939{ 1097{
940 struct ene_device *dev = pnp_get_drvdata(pnp_dev); 1098 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
941 ene_enable_wake(dev, 1); 1099 ene_enable_wake(dev, true);
1100
1101 /* TODO: add support for wake pattern */
942 return 0; 1102 return 0;
943} 1103}
944 1104
945static int ene_resume(struct pnp_dev *pnp_dev) 1105static int ene_resume(struct pnp_dev *pnp_dev)
946{ 1106{
947 struct ene_device *dev = pnp_get_drvdata(pnp_dev); 1107 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
948 if (dev->in_use) 1108 if (dev->rx_enabled) {
1109 ene_rx_setup(dev);
949 ene_rx_enable(dev); 1110 ene_rx_enable(dev);
950 1111 }
951 ene_enable_wake(dev, 0); 1112 ene_enable_wake(dev, false);
952 return 0; 1113 return 0;
953} 1114}
954#endif 1115#endif
@@ -956,7 +1117,7 @@ static int ene_resume(struct pnp_dev *pnp_dev)
956static void ene_shutdown(struct pnp_dev *pnp_dev) 1117static void ene_shutdown(struct pnp_dev *pnp_dev)
957{ 1118{
958 struct ene_device *dev = pnp_get_drvdata(pnp_dev); 1119 struct ene_device *dev = pnp_get_drvdata(pnp_dev);
959 ene_enable_wake(dev, 1); 1120 ene_enable_wake(dev, true);
960} 1121}
961 1122
962static const struct pnp_device_id ene_ids[] = { 1123static const struct pnp_device_id ene_ids[] = {
@@ -994,18 +1155,11 @@ static void ene_exit(void)
994module_param(sample_period, int, S_IRUGO); 1155module_param(sample_period, int, S_IRUGO);
995MODULE_PARM_DESC(sample_period, "Hardware sample period (50 us default)"); 1156MODULE_PARM_DESC(sample_period, "Hardware sample period (50 us default)");
996 1157
997module_param(enable_idle, bool, S_IRUGO | S_IWUSR); 1158module_param(learning_mode, bool, S_IRUGO);
998MODULE_PARM_DESC(enable_idle, 1159MODULE_PARM_DESC(learning_mode, "Enable learning mode by default");
999 "Enables turning off signal sampling after long inactivity time; "
1000 "if disabled might help detecting input signal (default: enabled)"
1001 " (KB3926B only)");
1002
1003module_param(input, bool, S_IRUGO);
1004MODULE_PARM_DESC(input, "select which input to use "
1005 "0 - auto, 1 - standard, 2 - wideband(KB3926C+)");
1006 1160
1007module_param(debug, int, S_IRUGO | S_IWUSR); 1161module_param(debug, int, S_IRUGO | S_IWUSR);
1008MODULE_PARM_DESC(debug, "Enable debug (debug=2 verbose debug output)"); 1162MODULE_PARM_DESC(debug, "Debug level");
1009 1163
1010module_param(txsim, bool, S_IRUGO); 1164module_param(txsim, bool, S_IRUGO);
1011MODULE_PARM_DESC(txsim, 1165MODULE_PARM_DESC(txsim,
@@ -1013,8 +1167,8 @@ MODULE_PARM_DESC(txsim,
1013 1167
1014MODULE_DEVICE_TABLE(pnp, ene_ids); 1168MODULE_DEVICE_TABLE(pnp, ene_ids);
1015MODULE_DESCRIPTION 1169MODULE_DESCRIPTION
1016 ("Infrared input driver for KB3926B/KB3926C/KB3926D " 1170 ("Infrared input driver for KB3926B/C/D/E/F "
1017 "(aka ENE0100/ENE0200/ENE0201) CIR port"); 1171 "(aka ENE0100/ENE0200/ENE0201/ENE0202) CIR port");
1018 1172
1019MODULE_AUTHOR("Maxim Levitsky"); 1173MODULE_AUTHOR("Maxim Levitsky");
1020MODULE_LICENSE("GPL"); 1174MODULE_LICENSE("GPL");
diff --git a/drivers/media/IR/ene_ir.h b/drivers/media/IR/ene_ir.h
index 54c76af0d033..39c707b42412 100644
--- a/drivers/media/IR/ene_ir.h
+++ b/drivers/media/IR/ene_ir.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * driver for ENE KB3926 B/C/D CIR (also known as ENE0XXX) 2 * driver for ENE KB3926 B/C/D/E/F CIR (also known as ENE0XXX)
3 * 3 *
4 * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com> 4 * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
5 * 5 *
@@ -26,43 +26,50 @@
26#define ENE_ADDR_HI 1 /* hi byte of register address */ 26#define ENE_ADDR_HI 1 /* hi byte of register address */
27#define ENE_ADDR_LO 2 /* low byte of register address */ 27#define ENE_ADDR_LO 2 /* low byte of register address */
28#define ENE_IO 3 /* read/write window */ 28#define ENE_IO 3 /* read/write window */
29#define ENE_MAX_IO 4 29#define ENE_IO_SIZE 4
30 30
31/* 8 bytes of samples, divided in 2 halfs*/ 31/* 8 bytes of samples, divided in 2 packets*/
32#define ENE_SAMPLE_BUFFER 0xF8F0 /* regular sample buffer */ 32#define ENE_FW_SAMPLE_BUFFER 0xF8F0 /* sample buffer */
33#define ENE_SAMPLE_SPC_MASK 0x80 /* sample is space */ 33#define ENE_FW_SAMPLE_SPACE 0x80 /* sample is space */
34#define ENE_SAMPLE_VALUE_MASK 0x7F 34#define ENE_FW_PACKET_SIZE 4
35#define ENE_SAMPLE_OVERFLOW 0x7F 35
36#define ENE_SAMPLES_SIZE 4 36/* first firmware flag register */
37 37#define ENE_FW1 0xF8F8 /* flagr */
38/* fan input sample buffer */
39#define ENE_SAMPLE_BUFFER_FAN 0xF8FB /* this buffer holds high byte of */
40 /* each sample of normal buffer */
41#define ENE_FAN_SMPL_PULS_MSK 0x8000 /* this bit of combined sample */
42 /* if set, says that sample is pulse */
43#define ENE_FAN_VALUE_MASK 0x0FFF /* mask for valid bits of the value */
44
45/* first firmware register */
46#define ENE_FW1 0xF8F8
47#define ENE_FW1_ENABLE 0x01 /* enable fw processing */ 38#define ENE_FW1_ENABLE 0x01 /* enable fw processing */
48#define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */ 39#define ENE_FW1_TXIRQ 0x02 /* TX interrupt pending */
40#define ENE_FW1_HAS_EXTRA_BUF 0x04 /* fw uses extra buffer*/
41#define ENE_FW1_EXTRA_BUF_HND 0x08 /* extra buffer handshake bit*/
42#define ENE_FW1_LED_ON 0x10 /* turn on a led */
43
44#define ENE_FW1_WPATTERN 0x20 /* enable wake pattern */
49#define ENE_FW1_WAKE 0x40 /* enable wake from S3 */ 45#define ENE_FW1_WAKE 0x40 /* enable wake from S3 */
50#define ENE_FW1_IRQ 0x80 /* enable interrupt */ 46#define ENE_FW1_IRQ 0x80 /* enable interrupt */
51 47
52/* second firmware register */ 48/* second firmware flag register */
53#define ENE_FW2 0xF8F9 49#define ENE_FW2 0xF8F9 /* flagw */
54#define ENE_FW2_BUF_HIGH 0x01 /* which half of the buffer to read */ 50#define ENE_FW2_BUF_WPTR 0x01 /* which half of the buffer to read */
55#define ENE_FW2_IRQ_CLR 0x04 /* clear this on IRQ */ 51#define ENE_FW2_RXIRQ 0x04 /* RX IRQ pending*/
56#define ENE_FW2_GP40_AS_LEARN 0x08 /* normal input is used as */ 52#define ENE_FW2_GP0A 0x08 /* Use GPIO0A for demodulated input */
57 /* learning input */ 53#define ENE_FW2_EMMITER1_CONN 0x10 /* TX emmiter 1 connected */
58#define ENE_FW2_FAN_AS_NRML_IN 0x40 /* fan is used as normal input */ 54#define ENE_FW2_EMMITER2_CONN 0x20 /* TX emmiter 2 connected */
55
56#define ENE_FW2_FAN_INPUT 0x40 /* fan input used for demodulated data*/
59#define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */ 57#define ENE_FW2_LEARNING 0x80 /* hardware supports learning and TX */
60 58
59/* firmware RX pointer for new style buffer */
60#define ENE_FW_RX_POINTER 0xF8FA
61
62/* high parts of samples for fan input (8 samples)*/
63#define ENE_FW_SMPL_BUF_FAN 0xF8FB
64#define ENE_FW_SMPL_BUF_FAN_PLS 0x8000 /* combined sample is pulse */
65#define ENE_FW_SMPL_BUF_FAN_MSK 0x0FFF /* combined sample maximum value */
66#define ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
67
61/* transmitter ports */ 68/* transmitter ports */
62#define ENE_TX_PORT2 0xFC01 /* this enables one or both */ 69#define ENE_GPIOFS1 0xFC01
63#define ENE_TX_PORT2_EN 0x20 /* TX ports */ 70#define ENE_GPIOFS1_GPIO0D 0x20 /* enable tx output on GPIO0D */
64#define ENE_TX_PORT1 0xFC08 71#define ENE_GPIOFS8 0xFC08
65#define ENE_TX_PORT1_EN 0x02 72#define ENE_GPIOFS8_GPIO41 0x02 /* enable tx output on GPIO40 */
66 73
67/* IRQ registers block (for revision B) */ 74/* IRQ registers block (for revision B) */
68#define ENEB_IRQ 0xFD09 /* IRQ number */ 75#define ENEB_IRQ 0xFD09 /* IRQ number */
@@ -70,97 +77,99 @@
70#define ENEB_IRQ_STATUS 0xFD80 /* irq status */ 77#define ENEB_IRQ_STATUS 0xFD80 /* irq status */
71#define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */ 78#define ENEB_IRQ_STATUS_IR 0x20 /* IR irq */
72 79
73/* fan as input settings - only if learning capable */ 80/* fan as input settings */
74#define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */ 81#define ENE_FAN_AS_IN1 0xFE30 /* fan init reg 1 */
75#define ENE_FAN_AS_IN1_EN 0xCD 82#define ENE_FAN_AS_IN1_EN 0xCD
76#define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */ 83#define ENE_FAN_AS_IN2 0xFE31 /* fan init reg 2 */
77#define ENE_FAN_AS_IN2_EN 0x03 84#define ENE_FAN_AS_IN2_EN 0x03
78#define ENE_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
79 85
80/* IRQ registers block (for revision C,D) */ 86/* IRQ registers block (for revision C,D) */
81#define ENEC_IRQ 0xFE9B /* new irq settings register */ 87#define ENE_IRQ 0xFE9B /* new irq settings register */
82#define ENEC_IRQ_MASK 0x0F /* irq number mask */ 88#define ENE_IRQ_MASK 0x0F /* irq number mask */
83#define ENEC_IRQ_UNK_EN 0x10 /* always enabled */ 89#define ENE_IRQ_UNK_EN 0x10 /* always enabled */
84#define ENEC_IRQ_STATUS 0x20 /* irq status and ACK */ 90#define ENE_IRQ_STATUS 0x20 /* irq status and ACK */
85 91
86/* CIR block settings */ 92/* CIR Config register #1 */
87#define ENE_CIR_CONF1 0xFEC0 93#define ENE_CIRCFG 0xFEC0
88#define ENE_CIR_CONF1_TX_CLEAR 0x01 /* clear that on revC */ 94#define ENE_CIRCFG_RX_EN 0x01 /* RX enable */
89 /* while transmitting */ 95#define ENE_CIRCFG_RX_IRQ 0x02 /* Enable hardware interrupt */
90#define ENE_CIR_CONF1_RX_ON 0x07 /* normal receiver enabled */ 96#define ENE_CIRCFG_REV_POL 0x04 /* Input polarity reversed */
91#define ENE_CIR_CONF1_LEARN1 0x08 /* enabled on learning mode */ 97#define ENE_CIRCFG_CARR_DEMOD 0x08 /* Enable carrier demodulator */
92#define ENE_CIR_CONF1_TX_ON 0x30 /* enabled on transmit */ 98
93#define ENE_CIR_CONF1_TX_CARR 0x80 /* send TX carrier or not */ 99#define ENE_CIRCFG_TX_EN 0x10 /* TX enable */
94 100#define ENE_CIRCFG_TX_IRQ 0x20 /* Send interrupt on TX done */
95#define ENE_CIR_CONF2 0xFEC1 /* unknown setting = 0 */ 101#define ENE_CIRCFG_TX_POL_REV 0x40 /* TX polarity reversed */
96#define ENE_CIR_CONF2_LEARN2 0x10 /* set on enable learning */ 102#define ENE_CIRCFG_TX_CARR 0x80 /* send TX carrier or not */
97#define ENE_CIR_CONF2_GPIO40DIS 0x20 /* disable input via gpio40 */ 103
98 104/* CIR config register #2 */
99#define ENE_CIR_SAMPLE_PERIOD 0xFEC8 /* sample period in us */ 105#define ENE_CIRCFG2 0xFEC1
100#define ENE_CIR_SAMPLE_OVERFLOW 0x80 /* interrupt on overflows if set */ 106#define ENE_CIRCFG2_RLC 0x00
101 107#define ENE_CIRCFG2_RC5 0x01
102 108#define ENE_CIRCFG2_RC6 0x02
103/* Two byte tx buffer */ 109#define ENE_CIRCFG2_NEC 0x03
104#define ENE_TX_INPUT1 0xFEC9 110#define ENE_CIRCFG2_CARR_DETECT 0x10 /* Enable carrier detection */
105#define ENE_TX_INPUT2 0xFECA 111#define ENE_CIRCFG2_GPIO0A 0x20 /* Use GPIO0A instead of GPIO40 for input */
106#define ENE_TX_PULSE_MASK 0x80 /* Transmitted sample is pulse */ 112#define ENE_CIRCFG2_FAST_SAMPL1 0x40 /* Fast leading pulse detection for RC6 */
107#define ENE_TX_SMLP_MASK 0x7F 113#define ENE_CIRCFG2_FAST_SAMPL2 0x80 /* Fast data detection for RC6 */
108#define ENE_TX_SMPL_PERIOD 50 /* transmit sample period - fixed */ 114
115/* Knobs for protocol decoding - will document when/if will use them */
116#define ENE_CIRPF 0xFEC2
117#define ENE_CIRHIGH 0xFEC3
118#define ENE_CIRBIT 0xFEC4
119#define ENE_CIRSTART 0xFEC5
120#define ENE_CIRSTART2 0xFEC6
121
122/* Actual register which contains RLC RX data - read by firmware */
123#define ENE_CIRDAT_IN 0xFEC7
124
125
126/* RLC configuration - sample period (1us resulution) + idle mode */
127#define ENE_CIRRLC_CFG 0xFEC8
128#define ENE_CIRRLC_CFG_OVERFLOW 0x80 /* interrupt on overflows if set */
129#define ENE_DEFAULT_SAMPLE_PERIOD 50
130
131/* Two byte RLC TX buffer */
132#define ENE_CIRRLC_OUT0 0xFEC9
133#define ENE_CIRRLC_OUT1 0xFECA
134#define ENE_CIRRLC_OUT_PULSE 0x80 /* Transmitted sample is pulse */
135#define ENE_CIRRLC_OUT_MASK 0x7F
136
137
138/* Carrier detect setting
139 * Low nibble - number of carrier pulses to average
140 * High nibble - number of initial carrier pulses to discard
141 */
142#define ENE_CIRCAR_PULS 0xFECB
109 143
144/* detected RX carrier period (resolution: 500 ns) */
145#define ENE_CIRCAR_PRD 0xFECC
146#define ENE_CIRCAR_PRD_VALID 0x80 /* data valid content valid */
110 147
111/* Unknown TX setting - TX sample period ??? */ 148/* detected RX carrier pulse width (resolution: 500 ns) */
112#define ENE_TX_UNK1 0xFECB /* set to 0x63 */ 149#define ENE_CIRCAR_HPRD 0xFECD
113 150
114/* Current received carrier period */ 151/* TX period (resolution: 500 ns, minimum 2)*/
115#define ENE_RX_CARRIER 0xFECC /* RX period (500 ns) */ 152#define ENE_CIRMOD_PRD 0xFECE
116#define ENE_RX_CARRIER_VALID 0x80 /* Register content valid */ 153#define ENE_CIRMOD_PRD_POL 0x80 /* TX carrier polarity*/
117 154
155#define ENE_CIRMOD_PRD_MAX 0x7F /* 15.87 kHz */
156#define ENE_CIRMOD_PRD_MIN 0x02 /* 1 Mhz */
118 157
119/* TX period (1/carrier) */ 158/* TX pulse width (resolution: 500 ns)*/
120#define ENE_TX_PERIOD 0xFECE /* TX period (500 ns) */ 159#define ENE_CIRMOD_HPRD 0xFECF
121#define ENE_TX_PERIOD_UNKBIT 0x80 /* This bit set on transmit*/
122#define ENE_TX_PERIOD_PULSE 0xFECF /* TX pulse period (500 ns)*/
123 160
124/* Hardware versions */ 161/* Hardware versions */
125#define ENE_HW_VERSION 0xFF00 /* hardware revision */ 162#define ENE_ECHV 0xFF00 /* hardware revision */
126#define ENE_PLLFRH 0xFF16 163#define ENE_PLLFRH 0xFF16
127#define ENE_PLLFRL 0xFF17 164#define ENE_PLLFRL 0xFF17
165#define ENE_DEFAULT_PLL_FREQ 1000
128 166
129#define ENE_HW_UNK 0xFF1D 167#define ENE_ECSTS 0xFF1D
130#define ENE_HW_UNK_CLR 0x04 168#define ENE_ECSTS_RSRVD 0x04
131#define ENE_HW_VER_MAJOR 0xFF1E /* chip version */
132#define ENE_HW_VER_MINOR 0xFF1F
133#define ENE_HW_VER_OLD 0xFD00
134
135/* Normal/Learning carrier ranges - only valid if we have learning input*/
136/* TODO: test */
137#define ENE_NORMAL_RX_LOW 34
138#define ENE_NORMAL_RX_HI 38
139 169
140/* Tx carrier range */ 170#define ENE_ECVER_MAJOR 0xFF1E /* chip version */
141/* Hardware might be able to do more, but this range is enough for 171#define ENE_ECVER_MINOR 0xFF1F
142 all purposes */ 172#define ENE_HW_VER_OLD 0xFD00
143#define ENE_TX_PERIOD_MAX 32 /* corresponds to 29.4 kHz */
144#define ENE_TX_PERIOD_MIN 16 /* corrsponds to 62.5 kHz */
145
146
147
148/* Minimal and maximal gaps */
149
150/* Normal case:
151 Minimal gap is 0x7F * sample period
152 Maximum gap depends on hardware.
153 For KB3926B, it is unlimited, for newer models its around
154 250000, after which HW stops sending samples, and that is
155 not possible to change */
156
157/* Fan case:
158 Both minimal and maximal gaps are same, and equal to 0xFFF * 0x61
159 And there is nothing to change this setting
160*/
161
162#define ENE_MAXGAP 250000
163#define ENE_MINGAP (127 * sample_period)
164 173
165/******************************************************************************/ 174/******************************************************************************/
166 175
@@ -171,46 +180,60 @@
171 180
172#define ENE_HW_B 1 /* 3926B */ 181#define ENE_HW_B 1 /* 3926B */
173#define ENE_HW_C 2 /* 3926C */ 182#define ENE_HW_C 2 /* 3926C */
174#define ENE_HW_D 3 /* 3926D */ 183#define ENE_HW_D 3 /* 3926D or later */
175 184
176#define ene_printk(level, text, ...) \ 185#define ene_printk(level, text, ...) \
177 printk(level ENE_DRIVER_NAME ": " text, ## __VA_ARGS__) 186 printk(level ENE_DRIVER_NAME ": " text "\n", ## __VA_ARGS__)
178 187
179#define ene_dbg(text, ...) \ 188#define ene_notice(text, ...) ene_printk(KERN_NOTICE, text, ## __VA_ARGS__)
180 if (debug) \ 189#define ene_warn(text, ...) ene_printk(KERN_WARNING, text, ## __VA_ARGS__)
181 printk(KERN_DEBUG \
182 ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)
183 190
184#define ene_dbg_verbose(text, ...) \
185 if (debug > 1) \
186 printk(KERN_DEBUG \
187 ENE_DRIVER_NAME ": " text "\n" , ## __VA_ARGS__)
188 191
192#define __dbg(level, format, ...) \
193 do { \
194 if (debug >= level) \
195 printk(KERN_DEBUG ENE_DRIVER_NAME \
196 ": " format "\n", ## __VA_ARGS__); \
197 } while (0)
198
199
200#define dbg(format, ...) __dbg(1, format, ## __VA_ARGS__)
201#define dbg_verbose(format, ...) __dbg(2, format, ## __VA_ARGS__)
202#define dbg_regs(format, ...) __dbg(3, format, ## __VA_ARGS__)
203
204#define MS_TO_NS(msec) ((msec) * 1000)
189 205
190struct ene_device { 206struct ene_device {
191 struct pnp_dev *pnp_dev; 207 struct pnp_dev *pnp_dev;
192 struct input_dev *idev; 208 struct input_dev *idev;
193 struct ir_dev_props *props; 209 struct ir_dev_props *props;
194 int in_use;
195 210
196 /* hw IO settings */ 211 /* hw IO settings */
197 unsigned long hw_io; 212 long hw_io;
198 int irq; 213 int irq;
199 spinlock_t hw_lock; 214 spinlock_t hw_lock;
200 215
201 /* HW features */ 216 /* HW features */
202 int hw_revision; /* hardware revision */ 217 int hw_revision; /* hardware revision */
203 bool hw_learning_and_tx_capable; /* learning capable */ 218 bool hw_use_gpio_0a; /* gpio40 is demodulated input*/
204 bool hw_gpio40_learning; /* gpio40 is learning */ 219 bool hw_extra_buffer; /* hardware has 'extra buffer' */
205 bool hw_fan_as_normal_input; /* fan input is used as */ 220 bool hw_fan_input; /* fan input is IR data source */
206 /* regular input */ 221 bool hw_learning_and_tx_capable; /* learning & tx capable */
222 int pll_freq;
223 int buffer_len;
224
225 /* Extra RX buffer location */
226 int extra_buf1_address;
227 int extra_buf1_len;
228 int extra_buf2_address;
229 int extra_buf2_len;
230
207 /* HW state*/ 231 /* HW state*/
208 int rx_pointer; /* hw pointer to rx buffer */ 232 int r_pointer; /* pointer to next sample to read */
233 int w_pointer; /* pointer to next sample hw will write */
209 bool rx_fan_input_inuse; /* is fan input in use for rx*/ 234 bool rx_fan_input_inuse; /* is fan input in use for rx*/
210 int tx_reg; /* current reg used for TX */ 235 int tx_reg; /* current reg used for TX */
211 u8 saved_conf1; /* saved FEC0 reg */ 236 u8 saved_conf1; /* saved FEC0 reg */
212
213 /* TX sample handling */
214 unsigned int tx_sample; /* current sample for TX */ 237 unsigned int tx_sample; /* current sample for TX */
215 bool tx_sample_pulse; /* current sample is pulse */ 238 bool tx_sample_pulse; /* current sample is pulse */
216 239
@@ -232,4 +255,8 @@ struct ene_device {
232 bool learning_enabled; /* learning input enabled */ 255 bool learning_enabled; /* learning input enabled */
233 bool carrier_detect_enabled; /* carrier detect enabled */ 256 bool carrier_detect_enabled; /* carrier detect enabled */
234 int rx_period_adjust; 257 int rx_period_adjust;
258 bool rx_enabled;
235}; 259};
260
261static int ene_irq_status(struct ene_device *dev);
262static void ene_read_hw_pointer(struct ene_device *dev);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 14:53:39 -0500