diff options
| author | Steffen Trumtrar <s.trumtrar@pengutronix.de> | 2013-01-09 08:44:23 -0500 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@linaro.org> | 2013-02-10 10:25:44 -0500 |
| commit | 11ab21e90a4aa3e9bb33b345a12e63ceff742655 (patch) | |
| tree | 4fb74ae822649a5f84ae0ff173276caf844dba3f | |
| parent | 67eb7c0bc8ee66aa74ed891b9c97f8da9c44a9c9 (diff) | |
ARM: dts: imx53: pinctrl update
Add pinctrl for cspi, csi.
Add new pingroups for can1 and uart3.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| -rw-r--r-- | arch/arm/boot/dts/imx53.dtsi | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index edc3f1eb6699..a9a3adde4e5a 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi | |||
| @@ -274,6 +274,44 @@ | |||
| 274 | }; | 274 | }; |
| 275 | }; | 275 | }; |
| 276 | 276 | ||
| 277 | csi { | ||
| 278 | pinctrl_csi_1: csigrp-1 { | ||
| 279 | fsl,pins = < | ||
| 280 | 286 0x1d5 /* MX53_PAD_CSI0_DATA_EN__IPU_CSI0_DATA_EN */ | ||
| 281 | 291 0x1d5 /* MX53_PAD_CSI0_VSYNC__IPU_CSI0_VSYNC */ | ||
| 282 | 280 0x1d5 /* MX53_PAD_CSI0_MCLK__IPU_CSI0_HSYNC */ | ||
| 283 | 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */ | ||
| 284 | 409 0x1d5 /* MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 */ | ||
| 285 | 402 0x1d5 /* MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 */ | ||
| 286 | 395 0x1d5 /* MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 */ | ||
| 287 | 388 0x1d5 /* MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 */ | ||
| 288 | 381 0x1d5 /* MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 */ | ||
| 289 | 374 0x1d5 /* MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 */ | ||
| 290 | 367 0x1d5 /* MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 */ | ||
| 291 | 360 0x1d5 /* MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 */ | ||
| 292 | 352 0x1d5 /* MX53_PAD_CSI0_DAT11__IPU_CSI0_D_11 */ | ||
| 293 | 344 0x1d5 /* MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 */ | ||
| 294 | 336 0x1d5 /* MX53_PAD_CSI0_DAT9__IPU_CSI0_D_9 */ | ||
| 295 | 328 0x1d5 /* MX53_PAD_CSI0_DAT8__IPU_CSI0_D_8 */ | ||
| 296 | 320 0x1d5 /* MX53_PAD_CSI0_DAT7__IPU_CSI0_D_7 */ | ||
| 297 | 312 0x1d5 /* MX53_PAD_CSI0_DAT6__IPU_CSI0_D_6 */ | ||
| 298 | 304 0x1d5 /* MX53_PAD_CSI0_DAT5__IPU_CSI0_D_5 */ | ||
| 299 | 296 0x1d5 /* MX53_PAD_CSI0_DAT4__IPU_CSI0_D_4 */ | ||
| 300 | 276 0x1d5 /* MX53_PAD_CSI0_PIXCLK__IPU_CSI0_PIXCLK */ | ||
| 301 | >; | ||
| 302 | }; | ||
| 303 | }; | ||
| 304 | |||
| 305 | cspi { | ||
| 306 | pinctrl_cspi_1: cspigrp-1 { | ||
| 307 | fsl,pins = < | ||
| 308 | 998 0x1d5 /* MX53_PAD_SD1_DATA0__CSPI_MISO */ | ||
| 309 | 1008 0x1d5 /* MX53_PAD_SD1_CMD__CSPI_MOSI */ | ||
| 310 | 1022 0x1d5 /* MX53_PAD_SD1_CLK__CSPI_SCLK */ | ||
| 311 | >; | ||
| 312 | }; | ||
| 313 | }; | ||
| 314 | |||
| 277 | ecspi1 { | 315 | ecspi1 { |
| 278 | pinctrl_ecspi1_1: ecspi1grp-1 { | 316 | pinctrl_ecspi1_1: ecspi1grp-1 { |
| 279 | fsl,pins = < | 317 | fsl,pins = < |
| @@ -349,6 +387,13 @@ | |||
| 349 | 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */ | 387 | 853 0x80000000 /* MX53_PAD_PATA_DIOR__CAN1_RXCAN */ |
| 350 | >; | 388 | >; |
| 351 | }; | 389 | }; |
| 390 | |||
| 391 | pinctrl_can1_2: can1grp-2 { | ||
| 392 | fsl,pins = < | ||
| 393 | 37 0x80000000 /* MX53_PAD_KEY_COL2__CAN1_TXCAN */ | ||
| 394 | 44 0x80000000 /* MX53_PAD_KEY_ROW2__CAN1_RXCAN */ | ||
| 395 | >; | ||
| 396 | }; | ||
| 352 | }; | 397 | }; |
| 353 | 398 | ||
| 354 | can2 { | 399 | can2 { |
| @@ -421,6 +466,14 @@ | |||
| 421 | 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ | 466 | 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ |
| 422 | >; | 467 | >; |
| 423 | }; | 468 | }; |
| 469 | |||
| 470 | pinctrl_uart3_2: uart3grp-2 { | ||
| 471 | fsl,pins = < | ||
| 472 | 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ | ||
| 473 | 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ | ||
| 474 | >; | ||
| 475 | }; | ||
| 476 | |||
| 424 | }; | 477 | }; |
| 425 | 478 | ||
| 426 | uart4 { | 479 | uart4 { |