diff options
author | Gary Hade <garyhade@us.ibm.com> | 2007-10-08 19:24:16 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2007-10-12 18:03:18 -0400 |
commit | 11949255d9433ea6c0908b7390ec4faecd1d4cf0 (patch) | |
tree | bfbec17f06906f9fbbc65263af010b4cb170c80a | |
parent | 62f420f828249f686aaae949ac3439d1304a759a (diff) |
PCI: modify PCI bridge control ISA flag for clarity
Modify PCI Bridge Control ISA flag for clarity
This patch changes PCI_BRIDGE_CTL_NO_ISA to PCI_BRIDGE_CTL_ISA
and modifies it's clarifying comment and locations where used.
The change reduces the chance of future confusion since it makes
the set/unset meaning of the bit the same in both the bridge
control register and bridge_ctl field of the pci_bus struct.
Signed-off-by: Gary Hade <garyhade@us.ibm.com>
Acked-by: Linas Vepstas <linas@austin.ibm.com>
Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r-- | arch/x86/pci/i386.c | 2 | ||||
-rw-r--r-- | drivers/pci/probe.c | 4 | ||||
-rw-r--r-- | include/linux/pci_regs.h | 2 |
3 files changed, 4 insertions, 4 deletions
diff --git a/arch/x86/pci/i386.c b/arch/x86/pci/i386.c index 055187bc255a..42ba0e2da1a0 100644 --- a/arch/x86/pci/i386.c +++ b/arch/x86/pci/i386.c | |||
@@ -37,7 +37,7 @@ static int | |||
37 | skip_isa_ioresource_align(struct pci_dev *dev) { | 37 | skip_isa_ioresource_align(struct pci_dev *dev) { |
38 | 38 | ||
39 | if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) && | 39 | if ((pci_probe & PCI_CAN_SKIP_ISA_ALIGN) && |
40 | (dev->bus->bridge_ctl & PCI_BRIDGE_CTL_NO_ISA)) | 40 | !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA)) |
41 | return 1; | 41 | return 1; |
42 | return 0; | 42 | return 0; |
43 | } | 43 | } |
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 3112024bdc2a..5db6b6690b59 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c | |||
@@ -543,7 +543,7 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass | |||
543 | goto out; | 543 | goto out; |
544 | child->primary = buses & 0xFF; | 544 | child->primary = buses & 0xFF; |
545 | child->subordinate = (buses >> 16) & 0xFF; | 545 | child->subordinate = (buses >> 16) & 0xFF; |
546 | child->bridge_ctl = bctl ^ PCI_BRIDGE_CTL_NO_ISA; | 546 | child->bridge_ctl = bctl; |
547 | 547 | ||
548 | cmax = pci_scan_child_bus(child); | 548 | cmax = pci_scan_child_bus(child); |
549 | if (cmax > max) | 549 | if (cmax > max) |
@@ -596,7 +596,7 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass | |||
596 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); | 596 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); |
597 | 597 | ||
598 | if (!is_cardbus) { | 598 | if (!is_cardbus) { |
599 | child->bridge_ctl = bctl ^ PCI_BRIDGE_CTL_NO_ISA; | 599 | child->bridge_ctl = bctl; |
600 | /* | 600 | /* |
601 | * Adjust subordinate busnr in parent buses. | 601 | * Adjust subordinate busnr in parent buses. |
602 | * We do this before scanning for children because | 602 | * We do this before scanning for children because |
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h index 4a24ee368a11..c1914a8b94a9 100644 --- a/include/linux/pci_regs.h +++ b/include/linux/pci_regs.h | |||
@@ -147,7 +147,7 @@ | |||
147 | #define PCI_BRIDGE_CONTROL 0x3e | 147 | #define PCI_BRIDGE_CONTROL 0x3e |
148 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ | 148 | #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */ |
149 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ | 149 | #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */ |
150 | #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */ | 150 | #define PCI_BRIDGE_CTL_ISA 0x04 /* Enable ISA mode */ |
151 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ | 151 | #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */ |
152 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ | 152 | #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */ |
153 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ | 153 | #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */ |