diff options
author | Arend van Spriel <arend@broadcom.com> | 2013-08-20 10:00:44 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2013-08-22 14:30:34 -0400 |
commit | 118e545a2cf34c8a660d050a72d8e711850f8f93 (patch) | |
tree | 85e3546c01aaf5e9fca17ac3c2df1b6a7845d0ee | |
parent | 02fcc7535e92031695c50eb518e56ea09fd3c6e2 (diff) |
brcmsmac: correct phy registers for TSSI-based power control
A number of additional phy registers needs to be programmed when
using TSSI-based power control.
Tested-by: David Herrmann <dh.herrmann@gmail.com>
Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com>
Signed-off-by: Arend van Spriel <arend@broadcom.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r-- | drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c index 08bcae4b8c28..2917f5c9fc1e 100644 --- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c +++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_lcn.c | |||
@@ -2020,6 +2020,16 @@ wlc_lcnphy_set_tssi_mux(struct brcms_phy *pi, enum lcnphy_tssi_mode pos) | |||
2020 | } else { | 2020 | } else { |
2021 | mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0x1); | 2021 | mod_radio_reg(pi, RADIO_2064_REG03A, 1, 0x1); |
2022 | mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8); | 2022 | mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8); |
2023 | mod_radio_reg(pi, RADIO_2064_REG028, 0x1, 0x0); | ||
2024 | mod_radio_reg(pi, RADIO_2064_REG11A, 0x4, 1<<2); | ||
2025 | mod_radio_reg(pi, RADIO_2064_REG036, 0x10, 0x0); | ||
2026 | mod_radio_reg(pi, RADIO_2064_REG11A, 0x10, 1<<4); | ||
2027 | mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0); | ||
2028 | mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x77); | ||
2029 | mod_radio_reg(pi, RADIO_2064_REG028, 0x1e, 0xe<<1); | ||
2030 | mod_radio_reg(pi, RADIO_2064_REG112, 0x80, 1<<7); | ||
2031 | mod_radio_reg(pi, RADIO_2064_REG005, 0x7, 1<<1); | ||
2032 | mod_radio_reg(pi, RADIO_2064_REG029, 0xf0, 0<<4); | ||
2023 | } | 2033 | } |
2024 | } else { | 2034 | } else { |
2025 | mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0x1) << 2); | 2035 | mod_phy_reg(pi, 0x4d9, (0x1 << 2), (0x1) << 2); |
@@ -2106,6 +2116,7 @@ static void wlc_lcnphy_pwrctrl_rssiparams(struct brcms_phy *pi) | |||
2106 | (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12)); | 2116 | (auxpga_vmid_temp << 0) | (auxpga_gain_temp << 12)); |
2107 | 2117 | ||
2108 | mod_radio_reg(pi, RADIO_2064_REG082, (1 << 5), (1 << 5)); | 2118 | mod_radio_reg(pi, RADIO_2064_REG082, (1 << 5), (1 << 5)); |
2119 | mod_radio_reg(pi, RADIO_2064_REG07C, (1 << 0), (1 << 0)); | ||
2109 | } | 2120 | } |
2110 | 2121 | ||
2111 | static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi) | 2122 | static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi) |
@@ -2218,6 +2229,10 @@ static void wlc_lcnphy_tssi_setup(struct brcms_phy *pi) | |||
2218 | 2229 | ||
2219 | mod_phy_reg(pi, 0x4d7, (0xf << 8), (0) << 8); | 2230 | mod_phy_reg(pi, 0x4d7, (0xf << 8), (0) << 8); |
2220 | 2231 | ||
2232 | mod_radio_reg(pi, RADIO_2064_REG035, 0xff, 0x0); | ||
2233 | mod_radio_reg(pi, RADIO_2064_REG036, 0x3, 0x0); | ||
2234 | mod_radio_reg(pi, RADIO_2064_REG11A, 0x8, 0x8); | ||
2235 | |||
2221 | wlc_lcnphy_pwrctrl_rssiparams(pi); | 2236 | wlc_lcnphy_pwrctrl_rssiparams(pi); |
2222 | } | 2237 | } |
2223 | 2238 | ||
@@ -3096,6 +3111,11 @@ static void wlc_lcnphy_tx_pwr_ctrl_init(struct brcms_phy_pub *ppi) | |||
3096 | wlc_lcnphy_write_table(pi, &tab); | 3111 | wlc_lcnphy_write_table(pi, &tab); |
3097 | tab.tbl_offset++; | 3112 | tab.tbl_offset++; |
3098 | } | 3113 | } |
3114 | mod_phy_reg(pi, 0x4d0, (0x1 << 0), (0) << 0); | ||
3115 | mod_phy_reg(pi, 0x4d3, (0xff << 0), (0) << 0); | ||
3116 | mod_phy_reg(pi, 0x4d3, (0xff << 8), (0) << 8); | ||
3117 | mod_phy_reg(pi, 0x4d0, (0x1 << 4), (0) << 4); | ||
3118 | mod_phy_reg(pi, 0x4d0, (0x1 << 2), (0) << 2); | ||
3099 | 3119 | ||
3100 | mod_phy_reg(pi, 0x410, (0x1 << 7), (0) << 7); | 3120 | mod_phy_reg(pi, 0x410, (0x1 << 7), (0) << 7); |
3101 | 3121 | ||