Merge tag 'for-v3.20-exynos7-clk' of git://linuxtv.org/snawrocki/samsung into clk-next

- Clock definitions for Exynos7 SoC peripheral devices:
  video scaler, USB, DMA, SPI and the audio subsystem.

3 files changed, 505 insertions, 6 deletions

diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
index 6d3d5f80c1c3..6bf1e7493f61 100644
--- a/Documentation/devicetree/bindings/clock/exynos7-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -34,6 +34,8 @@ Required Properties for Clock Controller:
         - "samsung,exynos7-clock-peris"
         - "samsung,exynos7-clock-fsys0"
         - "samsung,exynos7-clock-fsys1"
+        - "samsung,exynos7-clock-mscl"
+        - "samsung,exynos7-clock-aud"
 
  - reg: physical base address of the controller and the length of
         memory mapped region.
@@ -53,6 +55,7 @@ Input clocks for top0 clock controller:
         - dout_sclk_bus1_pll
         - dout_sclk_cc_pll
         - dout_sclk_mfc_pll
+        - dout_sclk_aud_pll
 
 Input clocks for top1 clock controller:
         - fin_pll
@@ -76,6 +79,14 @@ Input clocks for peric1 clock controller:
         - sclk_uart1
         - sclk_uart2
         - sclk_uart3
+        - sclk_spi0
+        - sclk_spi1
+        - sclk_spi2
+        - sclk_spi3
+        - sclk_spi4
+        - sclk_i2s1
+        - sclk_pcm1
+        - sclk_spdif
 
 Input clocks for peris clock controller:
         - fin_pll
@@ -91,3 +102,7 @@ Input clocks for fsys1 clock controller:
         - dout_aclk_fsys1_200
         - dout_sclk_mmc0
         - dout_sclk_mmc1
+
+Input clocks for aud clock controller:
+        - fin_pll
+        - fout_aud_pll
diff --git a/drivers/clk/samsung/clk-exynos7.c b/drivers/clk/samsung/clk-exynos7.c
index ea4483b8d62e..03d36e847b78 100644
--- a/drivers/clk/samsung/clk-exynos7.c
+++ b/drivers/clk/samsung/clk-exynos7.c
@@ -34,6 +34,7 @@
 #define DIV_TOPC0               0x0600
 #define DIV_TOPC1               0x0604
 #define DIV_TOPC3               0x060C
+#define ENABLE_ACLK_TOPC1       0x0804
 
 static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
         FFACTOR(0, "ffac_topc_bus0_pll_div2", "mout_bus0_pll_ctrl", 1, 2, 0),
@@ -45,6 +46,7 @@ static struct samsung_fixed_factor_clock topc_fixed_factor_clks[] __initdata = {
 };
 
 /* List of parent clocks for Muxes in CMU_TOPC */
+PNAME(mout_aud_pll_ctrl_p)      = { "fin_pll", "fout_aud_pll" };
 PNAME(mout_bus0_pll_ctrl_p)     = { "fin_pll", "fout_bus0_pll" };
 PNAME(mout_bus1_pll_ctrl_p)     = { "fin_pll", "fout_bus1_pll" };
 PNAME(mout_cc_pll_ctrl_p)       = { "fin_pll", "fout_cc_pll" };
@@ -104,9 +106,11 @@ static struct samsung_mux_clock topc_mux_clks[] __initdata = {
 
         MUX(0, "mout_sclk_bus0_pll_out", mout_sclk_bus0_pll_out_p,
                 MUX_SEL_TOPC1, 16, 1),
+        MUX(0, "mout_aud_pll_ctrl", mout_aud_pll_ctrl_p, MUX_SEL_TOPC1, 0, 1),
 
         MUX(0, "mout_aclk_ccore_133", mout_topc_group2, MUX_SEL_TOPC2, 4, 2),
 
+        MUX(0, "mout_aclk_mscl_532", mout_topc_group2, MUX_SEL_TOPC3, 20, 2),
         MUX(0, "mout_aclk_peris_66", mout_topc_group2, MUX_SEL_TOPC3, 24, 2),
 };
 
@@ -114,6 +118,8 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
         DIV(DOUT_ACLK_CCORE_133, "dout_aclk_ccore_133", "mout_aclk_ccore_133",
                 DIV_TOPC0, 4, 4),
 
+        DIV(DOUT_ACLK_MSCL_532, "dout_aclk_mscl_532", "mout_aclk_mscl_532",
+                DIV_TOPC1, 20, 4),
         DIV(DOUT_ACLK_PERIS, "dout_aclk_peris_66", "mout_aclk_peris_66",
                 DIV_TOPC1, 24, 4),
 
@@ -125,6 +131,18 @@ static struct samsung_div_clock topc_div_clks[] __initdata = {
                 DIV_TOPC3, 12, 3),
         DIV(DOUT_SCLK_MFC_PLL, "dout_sclk_mfc_pll", "mout_mfc_pll_ctrl",
                 DIV_TOPC3, 16, 3),
+        DIV(DOUT_SCLK_AUD_PLL, "dout_sclk_aud_pll", "mout_aud_pll_ctrl",
+                DIV_TOPC3, 28, 3),
+};
+
+static struct samsung_pll_rate_table pll1460x_24mhz_tbl[] __initdata = {
+        PLL_36XX_RATE(491520000, 20, 1, 0, 31457),
+        {},
+};
+
+static struct samsung_gate_clock topc_gate_clks[] __initdata = {
+        GATE(ACLK_MSCL_532, "aclk_mscl_532", "dout_aclk_mscl_532",
+                ENABLE_ACLK_TOPC1, 20, 0, 0),
 };
 
 static struct samsung_pll_clock topc_pll_clks[] __initdata = {
@@ -136,8 +154,8 @@ static struct samsung_pll_clock topc_pll_clks[] __initdata = {
                 BUS1_DPLL_CON0, NULL),
         PLL(pll_1452x, 0, "fout_mfc_pll", "fin_pll", MFC_PLL_LOCK,
                 MFC_PLL_CON0, NULL),
-        PLL(pll_1460x, 0, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
-                AUD_PLL_CON0, NULL),
+        PLL(pll_1460x, FOUT_AUD_PLL, "fout_aud_pll", "fin_pll", AUD_PLL_LOCK,
+                AUD_PLL_CON0, pll1460x_24mhz_tbl),
 };
 
 static struct samsung_cmu_info topc_cmu_info __initdata = {
@@ -147,6 +165,8 @@ static struct samsung_cmu_info topc_cmu_info __initdata = {
         .nr_mux_clks            = ARRAY_SIZE(topc_mux_clks),
         .div_clks               = topc_div_clks,
         .nr_div_clks            = ARRAY_SIZE(topc_div_clks),
+        .gate_clks              = topc_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(topc_gate_clks),
         .fixed_factor_clks      = topc_fixed_factor_clks,
         .nr_fixed_factor_clks   = ARRAY_SIZE(topc_fixed_factor_clks),
         .nr_clk_ids             = TOPC_NR_CLK,
@@ -166,9 +186,18 @@ CLK_OF_DECLARE(exynos7_clk_topc, "samsung,exynos7-clock-topc",
 #define MUX_SEL_TOP00                   0x0200
 #define MUX_SEL_TOP01                   0x0204
 #define MUX_SEL_TOP03                   0x020C
+#define MUX_SEL_TOP0_PERIC0             0x0230
+#define MUX_SEL_TOP0_PERIC1             0x0234
+#define MUX_SEL_TOP0_PERIC2             0x0238
 #define MUX_SEL_TOP0_PERIC3             0x023C
 #define DIV_TOP03                       0x060C
+#define DIV_TOP0_PERIC0                 0x0630
+#define DIV_TOP0_PERIC1                 0x0634
+#define DIV_TOP0_PERIC2                 0x0638
 #define DIV_TOP0_PERIC3                 0x063C
+#define ENABLE_SCLK_TOP0_PERIC0         0x0A30
+#define ENABLE_SCLK_TOP0_PERIC1         0x0A34
+#define ENABLE_SCLK_TOP0_PERIC2         0x0A38
 #define ENABLE_SCLK_TOP0_PERIC3         0x0A3C
 
 /* List of parent clocks for Muxes in CMU_TOP0 */
@@ -176,6 +205,7 @@ PNAME(mout_bus0_pll_p)	= { "fin_pll", "dout_sclk_bus0_pll" };
 PNAME(mout_bus1_pll_p)  = { "fin_pll", "dout_sclk_bus1_pll" };
 PNAME(mout_cc_pll_p)    = { "fin_pll", "dout_sclk_cc_pll" };
 PNAME(mout_mfc_pll_p)   = { "fin_pll", "dout_sclk_mfc_pll" };
+PNAME(mout_aud_pll_p)   = { "fin_pll", "dout_sclk_aud_pll" };
 
 PNAME(mout_top0_half_bus0_pll_p) = {"mout_top0_bus0_pll",
         "ffac_top0_bus0_pll_div2"};
@@ -189,18 +219,34 @@ PNAME(mout_top0_half_mfc_pll_p) = {"mout_top0_mfc_pll",
 PNAME(mout_top0_group1) = {"mout_top0_half_bus0_pll",
         "mout_top0_half_bus1_pll", "mout_top0_half_cc_pll",
         "mout_top0_half_mfc_pll"};
+PNAME(mout_top0_group3) = {"ioclk_audiocdclk0",
+        "ioclk_audiocdclk1", "ioclk_spdif_extclk",
+        "mout_top0_aud_pll", "mout_top0_half_bus0_pll",
+        "mout_top0_half_bus1_pll"};
+PNAME(mout_top0_group4) = {"ioclk_audiocdclk1", "mout_top0_aud_pll",
+        "mout_top0_half_bus0_pll", "mout_top0_half_bus1_pll"};
 
 static unsigned long top0_clk_regs[] __initdata = {
         MUX_SEL_TOP00,
         MUX_SEL_TOP01,
         MUX_SEL_TOP03,
+        MUX_SEL_TOP0_PERIC0,
+        MUX_SEL_TOP0_PERIC1,
+        MUX_SEL_TOP0_PERIC2,
         MUX_SEL_TOP0_PERIC3,
         DIV_TOP03,
+        DIV_TOP0_PERIC0,
+        DIV_TOP0_PERIC1,
+        DIV_TOP0_PERIC2,
         DIV_TOP0_PERIC3,
+        ENABLE_SCLK_TOP0_PERIC0,
+        ENABLE_SCLK_TOP0_PERIC1,
+        ENABLE_SCLK_TOP0_PERIC2,
         ENABLE_SCLK_TOP0_PERIC3,
 };
 
 static struct samsung_mux_clock top0_mux_clks[] __initdata = {
+        MUX(0, "mout_top0_aud_pll", mout_aud_pll_p, MUX_SEL_TOP00, 0, 1),
         MUX(0, "mout_top0_mfc_pll", mout_mfc_pll_p, MUX_SEL_TOP00, 4, 1),
         MUX(0, "mout_top0_cc_pll", mout_cc_pll_p, MUX_SEL_TOP00, 8, 1),
         MUX(0, "mout_top0_bus1_pll", mout_bus1_pll_p, MUX_SEL_TOP00, 12, 1),
@@ -218,10 +264,20 @@ static struct samsung_mux_clock top0_mux_clks[] __initdata = {
         MUX(0, "mout_aclk_peric1_66", mout_top0_group1, MUX_SEL_TOP03, 12, 2),
         MUX(0, "mout_aclk_peric0_66", mout_top0_group1, MUX_SEL_TOP03, 20, 2),
 
+        MUX(0, "mout_sclk_spdif", mout_top0_group3, MUX_SEL_TOP0_PERIC0, 4, 3),
+        MUX(0, "mout_sclk_pcm1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 8, 2),
+        MUX(0, "mout_sclk_i2s1", mout_top0_group4, MUX_SEL_TOP0_PERIC0, 20, 2),
+
+        MUX(0, "mout_sclk_spi1", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 8, 2),
+        MUX(0, "mout_sclk_spi0", mout_top0_group1, MUX_SEL_TOP0_PERIC1, 20, 2),
+
+        MUX(0, "mout_sclk_spi3", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 8, 2),
+        MUX(0, "mout_sclk_spi2", mout_top0_group1, MUX_SEL_TOP0_PERIC2, 20, 2),
         MUX(0, "mout_sclk_uart3", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 4, 2),
         MUX(0, "mout_sclk_uart2", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 8, 2),
         MUX(0, "mout_sclk_uart1", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 12, 2),
         MUX(0, "mout_sclk_uart0", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 16, 2),
+        MUX(0, "mout_sclk_spi4", mout_top0_group1, MUX_SEL_TOP0_PERIC3, 20, 2),
 };
 
 static struct samsung_div_clock top0_div_clks[] __initdata = {
@@ -230,13 +286,40 @@ static struct samsung_div_clock top0_div_clks[] __initdata = {
         DIV(DOUT_ACLK_PERIC0, "dout_aclk_peric0_66", "mout_aclk_peric0_66",
                 DIV_TOP03, 20, 6),
 
+        DIV(0, "dout_sclk_spdif", "mout_sclk_spdif", DIV_TOP0_PERIC0, 4, 4),
+        DIV(0, "dout_sclk_pcm1", "mout_sclk_pcm1", DIV_TOP0_PERIC0, 8, 12),
+        DIV(0, "dout_sclk_i2s1", "mout_sclk_i2s1", DIV_TOP0_PERIC0, 20, 10),
+
+        DIV(0, "dout_sclk_spi1", "mout_sclk_spi1", DIV_TOP0_PERIC1, 8, 12),
+        DIV(0, "dout_sclk_spi0", "mout_sclk_spi0", DIV_TOP0_PERIC1, 20, 12),
+
+        DIV(0, "dout_sclk_spi3", "mout_sclk_spi3", DIV_TOP0_PERIC2, 8, 12),
+        DIV(0, "dout_sclk_spi2", "mout_sclk_spi2", DIV_TOP0_PERIC2, 20, 12),
+
         DIV(0, "dout_sclk_uart3", "mout_sclk_uart3", DIV_TOP0_PERIC3, 4, 4),
         DIV(0, "dout_sclk_uart2", "mout_sclk_uart2", DIV_TOP0_PERIC3, 8, 4),
         DIV(0, "dout_sclk_uart1", "mout_sclk_uart1", DIV_TOP0_PERIC3, 12, 4),
         DIV(0, "dout_sclk_uart0", "mout_sclk_uart0", DIV_TOP0_PERIC3, 16, 4),
+        DIV(0, "dout_sclk_spi4", "mout_sclk_spi4", DIV_TOP0_PERIC3, 20, 12),
 };
 
 static struct samsung_gate_clock top0_gate_clks[] __initdata = {
+        GATE(CLK_SCLK_SPDIF, "sclk_spdif", "dout_sclk_spdif",
+                ENABLE_SCLK_TOP0_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_sclk_pcm1",
+                ENABLE_SCLK_TOP0_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_sclk_i2s1",
+                ENABLE_SCLK_TOP0_PERIC0, 20, CLK_SET_RATE_PARENT, 0),
+
+        GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_sclk_spi1",
+                ENABLE_SCLK_TOP0_PERIC1, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_sclk_spi0",
+                ENABLE_SCLK_TOP0_PERIC1, 20, CLK_SET_RATE_PARENT, 0),
+
+        GATE(CLK_SCLK_SPI3, "sclk_spi3", "dout_sclk_spi3",
+                ENABLE_SCLK_TOP0_PERIC2, 8, CLK_SET_RATE_PARENT, 0),
+        GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_sclk_spi2",
+                ENABLE_SCLK_TOP0_PERIC2, 20, CLK_SET_RATE_PARENT, 0),
         GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_sclk_uart3",
                 ENABLE_SCLK_TOP0_PERIC3, 4, 0, 0),
         GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_sclk_uart2",
@@ -245,6 +328,8 @@ static struct samsung_gate_clock top0_gate_clks[] __initdata = {
                 ENABLE_SCLK_TOP0_PERIC3, 12, 0, 0),
         GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_sclk_uart0",
                 ENABLE_SCLK_TOP0_PERIC3, 16, 0, 0),
+        GATE(CLK_SCLK_SPI4, "sclk_spi4", "dout_sclk_spi4",
+                ENABLE_SCLK_TOP0_PERIC3, 20, CLK_SET_RATE_PARENT, 0),
 };
 
 static struct samsung_fixed_factor_clock top0_fixed_factor_clks[] __initdata = {
@@ -343,6 +428,8 @@ static struct samsung_mux_clock top1_mux_clks[] __initdata = {
         MUX(0, "mout_aclk_fsys0_200", mout_top1_group1, MUX_SEL_TOP13, 28, 2),
 
         MUX(0, "mout_sclk_mmc2", mout_top1_group1, MUX_SEL_TOP1_FSYS0, 24, 2),
+        MUX(0, "mout_sclk_usbdrd300", mout_top1_group1,
+                MUX_SEL_TOP1_FSYS0, 28, 2),
 
         MUX(0, "mout_sclk_mmc1", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 24, 2),
         MUX(0, "mout_sclk_mmc0", mout_top1_group1, MUX_SEL_TOP1_FSYS1, 28, 2),
@@ -356,6 +443,8 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
 
         DIV(DOUT_SCLK_MMC2, "dout_sclk_mmc2", "mout_sclk_mmc2",
                 DIV_TOP1_FSYS0, 24, 4),
+        DIV(0, "dout_sclk_usbdrd300", "mout_sclk_usbdrd300",
+                DIV_TOP1_FSYS0, 28, 4),
 
         DIV(DOUT_SCLK_MMC1, "dout_sclk_mmc1", "mout_sclk_mmc1",
                 DIV_TOP1_FSYS1, 24, 4),
@@ -366,6 +455,8 @@ static struct samsung_div_clock top1_div_clks[] __initdata = {
 static struct samsung_gate_clock top1_gate_clks[] __initdata = {
         GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_sclk_mmc2",
                 ENABLE_SCLK_TOP1_FSYS0, 24, CLK_SET_RATE_PARENT, 0),
+        GATE(0, "sclk_usbdrd300", "dout_sclk_usbdrd300",
+                ENABLE_SCLK_TOP1_FSYS0, 28, 0, 0),
 
         GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_sclk_mmc1",
                 ENABLE_SCLK_TOP1_FSYS1, 24, CLK_SET_RATE_PARENT, 0),
@@ -514,6 +605,7 @@ static void __init exynos7_clk_peric0_init(struct device_node *np)
 /* Register Offset definitions for CMU_PERIC1 (0x14C80000) */
 #define MUX_SEL_PERIC10                 0x0200
 #define MUX_SEL_PERIC11                 0x0204
+#define MUX_SEL_PERIC12                 0x0208
 #define ENABLE_PCLK_PERIC1              0x0900
 #define ENABLE_SCLK_PERIC10             0x0A00
 
@@ -525,10 +617,16 @@ PNAME(mout_aclk_peric1_66_p)	= { "fin_pll", "dout_aclk_peric1_66" };
 PNAME(mout_sclk_uart1_p)        = { "fin_pll", "sclk_uart1" };
 PNAME(mout_sclk_uart2_p)        = { "fin_pll", "sclk_uart2" };
 PNAME(mout_sclk_uart3_p)        = { "fin_pll", "sclk_uart3" };
+PNAME(mout_sclk_spi0_p)         = { "fin_pll", "sclk_spi0" };
+PNAME(mout_sclk_spi1_p)         = { "fin_pll", "sclk_spi1" };
+PNAME(mout_sclk_spi2_p)         = { "fin_pll", "sclk_spi2" };
+PNAME(mout_sclk_spi3_p)         = { "fin_pll", "sclk_spi3" };
+PNAME(mout_sclk_spi4_p)         = { "fin_pll", "sclk_spi4" };
 
 static unsigned long peric1_clk_regs[] __initdata = {
         MUX_SEL_PERIC10,
         MUX_SEL_PERIC11,
+        MUX_SEL_PERIC12,
         ENABLE_PCLK_PERIC1,
         ENABLE_SCLK_PERIC10,
 };
@@ -537,6 +635,16 @@ static struct samsung_mux_clock peric1_mux_clks[] __initdata = {
         MUX(0, "mout_aclk_peric1_66_user", mout_aclk_peric1_66_p,
                 MUX_SEL_PERIC10, 0, 1),
 
+        MUX_F(0, "mout_sclk_spi0_user", mout_sclk_spi0_p,
+                MUX_SEL_PERIC11, 0, 1, CLK_SET_RATE_PARENT, 0),
+        MUX_F(0, "mout_sclk_spi1_user", mout_sclk_spi1_p,
+                MUX_SEL_PERIC11, 4, 1, CLK_SET_RATE_PARENT, 0),
+        MUX_F(0, "mout_sclk_spi2_user", mout_sclk_spi2_p,
+                MUX_SEL_PERIC11, 8, 1, CLK_SET_RATE_PARENT, 0),
+        MUX_F(0, "mout_sclk_spi3_user", mout_sclk_spi3_p,
+                MUX_SEL_PERIC11, 12, 1, CLK_SET_RATE_PARENT, 0),
+        MUX_F(0, "mout_sclk_spi4_user", mout_sclk_spi4_p,
+                MUX_SEL_PERIC11, 16, 1, CLK_SET_RATE_PARENT, 0),
         MUX(0, "mout_sclk_uart1_user", mout_sclk_uart1_p,
                 MUX_SEL_PERIC11, 20, 1),
         MUX(0, "mout_sclk_uart2_user", mout_sclk_uart2_p,
@@ -562,6 +670,22 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
                 ENABLE_PCLK_PERIC1, 10, 0, 0),
         GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
                 ENABLE_PCLK_PERIC1, 11, 0, 0),
+        GATE(PCLK_SPI0, "pclk_spi0", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 12, 0, 0),
+        GATE(PCLK_SPI1, "pclk_spi1", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 13, 0, 0),
+        GATE(PCLK_SPI2, "pclk_spi2", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 14, 0, 0),
+        GATE(PCLK_SPI3, "pclk_spi3", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 15, 0, 0),
+        GATE(PCLK_SPI4, "pclk_spi4", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 16, 0, 0),
+        GATE(PCLK_I2S1, "pclk_i2s1", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 17, CLK_SET_RATE_PARENT, 0),
+        GATE(PCLK_PCM1, "pclk_pcm1", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 18, 0, 0),
+        GATE(PCLK_SPDIF, "pclk_spdif", "mout_aclk_peric1_66_user",
+                ENABLE_PCLK_PERIC1, 19, 0, 0),
 
         GATE(SCLK_UART1, "sclk_uart1_user", "mout_sclk_uart1_user",
                 ENABLE_SCLK_PERIC10, 9, 0, 0),
@@ -569,6 +693,22 @@ static struct samsung_gate_clock peric1_gate_clks[] __initdata = {
                 ENABLE_SCLK_PERIC10, 10, 0, 0),
         GATE(SCLK_UART3, "sclk_uart3_user", "mout_sclk_uart3_user",
                 ENABLE_SCLK_PERIC10, 11, 0, 0),
+        GATE(SCLK_SPI0, "sclk_spi0_user", "mout_sclk_spi0_user",
+                ENABLE_SCLK_PERIC10, 12, CLK_SET_RATE_PARENT, 0),
+        GATE(SCLK_SPI1, "sclk_spi1_user", "mout_sclk_spi1_user",
+                ENABLE_SCLK_PERIC10, 13, CLK_SET_RATE_PARENT, 0),
+        GATE(SCLK_SPI2, "sclk_spi2_user", "mout_sclk_spi2_user",
+                ENABLE_SCLK_PERIC10, 14, CLK_SET_RATE_PARENT, 0),
+        GATE(SCLK_SPI3, "sclk_spi3_user", "mout_sclk_spi3_user",
+                ENABLE_SCLK_PERIC10, 15, CLK_SET_RATE_PARENT, 0),
+        GATE(SCLK_SPI4, "sclk_spi4_user", "mout_sclk_spi4_user",
+                ENABLE_SCLK_PERIC10, 16, CLK_SET_RATE_PARENT, 0),
+        GATE(SCLK_I2S1, "sclk_i2s1_user", "sclk_i2s1",
+                ENABLE_SCLK_PERIC10, 17, CLK_SET_RATE_PARENT, 0),
+        GATE(SCLK_PCM1, "sclk_pcm1_user", "sclk_pcm1",
+                ENABLE_SCLK_PERIC10, 18, CLK_SET_RATE_PARENT, 0),
+        GATE(SCLK_SPDIF, "sclk_spdif_user", "sclk_spdif",
+                ENABLE_SCLK_PERIC10, 19, CLK_SET_RATE_PARENT, 0),
 };
 
 static struct samsung_cmu_info peric1_cmu_info __initdata = {
@@ -647,7 +787,12 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
 /* Register Offset definitions for CMU_FSYS0 (0x10E90000) */
 #define MUX_SEL_FSYS00                  0x0200
 #define MUX_SEL_FSYS01                  0x0204
+#define MUX_SEL_FSYS02                  0x0208
+#define ENABLE_ACLK_FSYS00              0x0800
 #define ENABLE_ACLK_FSYS01              0x0804
+#define ENABLE_SCLK_FSYS01              0x0A04
+#define ENABLE_SCLK_FSYS02              0x0A08
+#define ENABLE_SCLK_FSYS04              0x0A10
 
 /*
  * List of parent clocks for Muxes in CMU_FSYS0
@@ -655,10 +800,29 @@ CLK_OF_DECLARE(exynos7_clk_peris, "samsung,exynos7-clock-peris",
 PNAME(mout_aclk_fsys0_200_p)    = { "fin_pll", "dout_aclk_fsys0_200" };
 PNAME(mout_sclk_mmc2_p)         = { "fin_pll", "sclk_mmc2" };
 
+PNAME(mout_sclk_usbdrd300_p)    = { "fin_pll", "sclk_usbdrd300" };
+PNAME(mout_phyclk_usbdrd300_udrd30_phyclk_p)    = { "fin_pll",
+                                "phyclk_usbdrd300_udrd30_phyclock" };
+PNAME(mout_phyclk_usbdrd300_udrd30_pipe_pclk_p) = { "fin_pll",
+                                "phyclk_usbdrd300_udrd30_pipe_pclk" };
+
+/* fixed rate clocks used in the FSYS0 block */
+struct samsung_fixed_rate_clock fixed_rate_clks_fsys0[] __initdata = {
+        FRATE(0, "phyclk_usbdrd300_udrd30_phyclock", NULL,
+                CLK_IS_ROOT, 60000000),
+        FRATE(0, "phyclk_usbdrd300_udrd30_pipe_pclk", NULL,
+                CLK_IS_ROOT, 125000000),
+};
+
 static unsigned long fsys0_clk_regs[] __initdata = {
         MUX_SEL_FSYS00,
         MUX_SEL_FSYS01,
+        MUX_SEL_FSYS02,
+        ENABLE_ACLK_FSYS00,
         ENABLE_ACLK_FSYS01,
+        ENABLE_SCLK_FSYS01,
+        ENABLE_SCLK_FSYS02,
+        ENABLE_SCLK_FSYS04,
 };
 
 static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
@@ -666,11 +830,49 @@ static struct samsung_mux_clock fsys0_mux_clks[] __initdata = {
                 MUX_SEL_FSYS00, 24, 1),
 
         MUX(0, "mout_sclk_mmc2_user", mout_sclk_mmc2_p, MUX_SEL_FSYS01, 24, 1),
+        MUX(0, "mout_sclk_usbdrd300_user", mout_sclk_usbdrd300_p,
+                MUX_SEL_FSYS01, 28, 1),
+
+        MUX(0, "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
+                mout_phyclk_usbdrd300_udrd30_pipe_pclk_p,
+                MUX_SEL_FSYS02, 24, 1),
+        MUX(0, "mout_phyclk_usbdrd300_udrd30_phyclk_user",
+                mout_phyclk_usbdrd300_udrd30_phyclk_p,
+                MUX_SEL_FSYS02, 28, 1),
 };
 
 static struct samsung_gate_clock fsys0_gate_clks[] __initdata = {
+        GATE(ACLK_AXIUS_USBDRD30X_FSYS0X, "aclk_axius_usbdrd30x_fsys0x",
+                "mout_aclk_fsys0_200_user",
+                ENABLE_ACLK_FSYS00, 19, 0, 0),
+        GATE(ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys0_200_user",
+                        ENABLE_ACLK_FSYS00, 3, 0, 0),
+        GATE(ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys0_200_user",
+                        ENABLE_ACLK_FSYS00, 4, 0, 0),
+
+        GATE(ACLK_USBDRD300, "aclk_usbdrd300", "mout_aclk_fsys0_200_user",
+                ENABLE_ACLK_FSYS01, 29, 0, 0),
         GATE(ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys0_200_user",
                 ENABLE_ACLK_FSYS01, 31, 0, 0),
+
+        GATE(SCLK_USBDRD300_SUSPENDCLK, "sclk_usbdrd300_suspendclk",
+                "mout_sclk_usbdrd300_user",
+                ENABLE_SCLK_FSYS01, 4, 0, 0),
+        GATE(SCLK_USBDRD300_REFCLK, "sclk_usbdrd300_refclk", "fin_pll",
+                ENABLE_SCLK_FSYS01, 8, 0, 0),
+
+        GATE(PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER,
+                "phyclk_usbdrd300_udrd30_pipe_pclk_user",
+                "mout_phyclk_usbdrd300_udrd30_pipe_pclk_user",
+                ENABLE_SCLK_FSYS02, 24, 0, 0),
+        GATE(PHYCLK_USBDRD300_UDRD30_PHYCLK_USER,
+                "phyclk_usbdrd300_udrd30_phyclk_user",
+                "mout_phyclk_usbdrd300_udrd30_phyclk_user",
+                ENABLE_SCLK_FSYS02, 28, 0, 0),
+
+        GATE(OSCCLK_PHY_CLKOUT_USB30_PHY, "oscclk_phy_clkout_usb30_phy",
+                "fin_pll",
+                ENABLE_SCLK_FSYS04, 28, 0, 0),
 };
 
 static struct samsung_cmu_info fsys0_cmu_info __initdata = {
@@ -741,3 +943,205 @@ static void __init exynos7_clk_fsys1_init(struct device_node *np)
 
 CLK_OF_DECLARE(exynos7_clk_fsys1, "samsung,exynos7-clock-fsys1",
         exynos7_clk_fsys1_init);
+
+#define MUX_SEL_MSCL                    0x0200
+#define DIV_MSCL                        0x0600
+#define ENABLE_ACLK_MSCL                0x0800
+#define ENABLE_PCLK_MSCL                0x0900
+
+/* List of parent clocks for Muxes in CMU_MSCL */
+PNAME(mout_aclk_mscl_532_user_p)        = { "fin_pll", "aclk_mscl_532" };
+
+static unsigned long mscl_clk_regs[] __initdata = {
+        MUX_SEL_MSCL,
+        DIV_MSCL,
+        ENABLE_ACLK_MSCL,
+        ENABLE_PCLK_MSCL,
+};
+
+static struct samsung_mux_clock mscl_mux_clks[] __initdata = {
+        MUX(USERMUX_ACLK_MSCL_532, "usermux_aclk_mscl_532",
+                mout_aclk_mscl_532_user_p, MUX_SEL_MSCL, 0, 1),
+};
+static struct samsung_div_clock mscl_div_clks[] __initdata = {
+        DIV(DOUT_PCLK_MSCL, "dout_pclk_mscl", "usermux_aclk_mscl_532",
+                        DIV_MSCL, 0, 3),
+};
+static struct samsung_gate_clock mscl_gate_clks[] __initdata = {
+
+        GATE(ACLK_MSCL_0, "aclk_mscl_0", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 31, 0, 0),
+        GATE(ACLK_MSCL_1, "aclk_mscl_1", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 30, 0, 0),
+        GATE(ACLK_JPEG, "aclk_jpeg", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 29, 0, 0),
+        GATE(ACLK_G2D, "aclk_g2d", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 28, 0, 0),
+        GATE(ACLK_LH_ASYNC_SI_MSCL_0, "aclk_lh_async_si_mscl_0",
+                        "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 27, 0, 0),
+        GATE(ACLK_LH_ASYNC_SI_MSCL_1, "aclk_lh_async_si_mscl_1",
+                        "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 26, 0, 0),
+        GATE(ACLK_XIU_MSCLX_0, "aclk_xiu_msclx_0", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 25, 0, 0),
+        GATE(ACLK_XIU_MSCLX_1, "aclk_xiu_msclx_1", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 24, 0, 0),
+        GATE(ACLK_AXI2ACEL_BRIDGE, "aclk_axi2acel_bridge",
+                        "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 23, 0, 0),
+        GATE(ACLK_QE_MSCL_0, "aclk_qe_mscl_0", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 22, 0, 0),
+        GATE(ACLK_QE_MSCL_1, "aclk_qe_mscl_1", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 21, 0, 0),
+        GATE(ACLK_QE_JPEG, "aclk_qe_jpeg", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 20, 0, 0),
+        GATE(ACLK_QE_G2D, "aclk_qe_g2d", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 19, 0, 0),
+        GATE(ACLK_PPMU_MSCL_0, "aclk_ppmu_mscl_0", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 18, 0, 0),
+        GATE(ACLK_PPMU_MSCL_1, "aclk_ppmu_mscl_1", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 17, 0, 0),
+        GATE(ACLK_MSCLNP_133, "aclk_msclnp_133", "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 16, 0, 0),
+        GATE(ACLK_AHB2APB_MSCL0P, "aclk_ahb2apb_mscl0p",
+                        "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 15, 0, 0),
+        GATE(ACLK_AHB2APB_MSCL1P, "aclk_ahb2apb_mscl1p",
+                        "usermux_aclk_mscl_532",
+                        ENABLE_ACLK_MSCL, 14, 0, 0),
+
+        GATE(PCLK_MSCL_0, "pclk_mscl_0", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 31, 0, 0),
+        GATE(PCLK_MSCL_1, "pclk_mscl_1", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 30, 0, 0),
+        GATE(PCLK_JPEG, "pclk_jpeg", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 29, 0, 0),
+        GATE(PCLK_G2D, "pclk_g2d", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 28, 0, 0),
+        GATE(PCLK_QE_MSCL_0, "pclk_qe_mscl_0", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 27, 0, 0),
+        GATE(PCLK_QE_MSCL_1, "pclk_qe_mscl_1", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 26, 0, 0),
+        GATE(PCLK_QE_JPEG, "pclk_qe_jpeg", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 25, 0, 0),
+        GATE(PCLK_QE_G2D, "pclk_qe_g2d", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 24, 0, 0),
+        GATE(PCLK_PPMU_MSCL_0, "pclk_ppmu_mscl_0", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 23, 0, 0),
+        GATE(PCLK_PPMU_MSCL_1, "pclk_ppmu_mscl_1", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 22, 0, 0),
+        GATE(PCLK_AXI2ACEL_BRIDGE, "pclk_axi2acel_bridge", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 21, 0, 0),
+        GATE(PCLK_PMU_MSCL, "pclk_pmu_mscl", "dout_pclk_mscl",
+                        ENABLE_PCLK_MSCL, 20, 0, 0),
+};
+
+static struct samsung_cmu_info mscl_cmu_info __initdata = {
+        .mux_clks               = mscl_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(mscl_mux_clks),
+        .div_clks               = mscl_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(mscl_div_clks),
+        .gate_clks              = mscl_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(mscl_gate_clks),
+        .nr_clk_ids             = MSCL_NR_CLK,
+        .clk_regs               = mscl_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(mscl_clk_regs),
+};
+
+static void __init exynos7_clk_mscl_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &mscl_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_mscl, "samsung,exynos7-clock-mscl",
+                exynos7_clk_mscl_init);
+
+/* Register Offset definitions for CMU_AUD (0x114C0000) */
+#define MUX_SEL_AUD                     0x0200
+#define DIV_AUD0                        0x0600
+#define DIV_AUD1                        0x0604
+#define ENABLE_ACLK_AUD                 0x0800
+#define ENABLE_PCLK_AUD                 0x0900
+#define ENABLE_SCLK_AUD                 0x0A00
+
+/*
+ * List of parent clocks for Muxes in CMU_AUD
+ */
+PNAME(mout_aud_pll_user_p) = { "fin_pll", "fout_aud_pll" };
+PNAME(mout_aud_group_p) = { "dout_aud_cdclk", "ioclk_audiocdclk0" };
+
+static unsigned long aud_clk_regs[] __initdata = {
+        MUX_SEL_AUD,
+        DIV_AUD0,
+        DIV_AUD1,
+        ENABLE_ACLK_AUD,
+        ENABLE_PCLK_AUD,
+        ENABLE_SCLK_AUD,
+};
+
+static struct samsung_mux_clock aud_mux_clks[] __initdata = {
+        MUX(0, "mout_sclk_i2s", mout_aud_group_p, MUX_SEL_AUD, 12, 1),
+        MUX(0, "mout_sclk_pcm", mout_aud_group_p, MUX_SEL_AUD, 16, 1),
+        MUX(0, "mout_aud_pll_user", mout_aud_pll_user_p, MUX_SEL_AUD, 20, 1),
+};
+
+static struct samsung_div_clock aud_div_clks[] __initdata = {
+        DIV(0, "dout_aud_ca5", "mout_aud_pll_user", DIV_AUD0, 0, 4),
+        DIV(0, "dout_aclk_aud", "dout_aud_ca5", DIV_AUD0, 4, 4),
+        DIV(0, "dout_aud_pclk_dbg", "dout_aud_ca5", DIV_AUD0, 8, 4),
+
+        DIV(0, "dout_sclk_i2s", "mout_sclk_i2s", DIV_AUD1, 0, 4),
+        DIV(0, "dout_sclk_pcm", "mout_sclk_pcm", DIV_AUD1, 4, 8),
+        DIV(0, "dout_sclk_uart", "dout_aud_cdclk", DIV_AUD1, 12, 4),
+        DIV(0, "dout_sclk_slimbus", "dout_aud_cdclk", DIV_AUD1, 16, 5),
+        DIV(0, "dout_aud_cdclk", "mout_aud_pll_user", DIV_AUD1, 24, 4),
+};
+
+static struct samsung_gate_clock aud_gate_clks[] __initdata = {
+        GATE(SCLK_PCM, "sclk_pcm", "dout_sclk_pcm",
+                        ENABLE_SCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
+        GATE(SCLK_I2S, "sclk_i2s", "dout_sclk_i2s",
+                        ENABLE_SCLK_AUD, 28, CLK_SET_RATE_PARENT, 0),
+        GATE(0, "sclk_uart", "dout_sclk_uart", ENABLE_SCLK_AUD, 29, 0, 0),
+        GATE(0, "sclk_slimbus", "dout_sclk_slimbus",
+                        ENABLE_SCLK_AUD, 30, 0, 0),
+
+        GATE(0, "pclk_dbg_aud", "dout_aud_pclk_dbg", ENABLE_PCLK_AUD, 19, 0, 0),
+        GATE(0, "pclk_gpio_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 20, 0, 0),
+        GATE(0, "pclk_wdt1", "dout_aclk_aud", ENABLE_PCLK_AUD, 22, 0, 0),
+        GATE(0, "pclk_wdt0", "dout_aclk_aud", ENABLE_PCLK_AUD, 23, 0, 0),
+        GATE(0, "pclk_slimbus", "dout_aclk_aud", ENABLE_PCLK_AUD, 24, 0, 0),
+        GATE(0, "pclk_uart", "dout_aclk_aud", ENABLE_PCLK_AUD, 25, 0, 0),
+        GATE(PCLK_PCM, "pclk_pcm", "dout_aclk_aud",
+                        ENABLE_PCLK_AUD, 26, CLK_SET_RATE_PARENT, 0),
+        GATE(PCLK_I2S, "pclk_i2s", "dout_aclk_aud",
+                        ENABLE_PCLK_AUD, 27, CLK_SET_RATE_PARENT, 0),
+        GATE(0, "pclk_timer", "dout_aclk_aud", ENABLE_PCLK_AUD, 28, 0, 0),
+        GATE(0, "pclk_smmu_aud", "dout_aclk_aud", ENABLE_PCLK_AUD, 31, 0, 0),
+
+        GATE(0, "aclk_smmu_aud", "dout_aclk_aud", ENABLE_ACLK_AUD, 27, 0, 0),
+        GATE(0, "aclk_acel_lh_async_si_top", "dout_aclk_aud",
+                         ENABLE_ACLK_AUD, 28, 0, 0),
+        GATE(ACLK_ADMA, "aclk_dmac", "dout_aclk_aud", ENABLE_ACLK_AUD, 31, 0, 0),
+};
+
+static struct samsung_cmu_info aud_cmu_info __initdata = {
+        .mux_clks               = aud_mux_clks,
+        .nr_mux_clks            = ARRAY_SIZE(aud_mux_clks),
+        .div_clks               = aud_div_clks,
+        .nr_div_clks            = ARRAY_SIZE(aud_div_clks),
+        .gate_clks              = aud_gate_clks,
+        .nr_gate_clks           = ARRAY_SIZE(aud_gate_clks),
+        .nr_clk_ids             = AUD_NR_CLK,
+        .clk_regs               = aud_clk_regs,
+        .nr_clk_regs            = ARRAY_SIZE(aud_clk_regs),
+};
+
+static void __init exynos7_clk_aud_init(struct device_node *np)
+{
+        samsung_cmu_register_one(np, &aud_cmu_info);
+}
+
+CLK_OF_DECLARE(exynos7_clk_aud, "samsung,exynos7-clock-aud",
+                exynos7_clk_aud_init);
diff --git a/include/dt-bindings/clock/exynos7-clk.h b/include/dt-bindings/clock/exynos7-clk.h
index 8e4681b07ae7..e33c75a3c09d 100644
--- a/include/dt-bindings/clock/exynos7-clk.h
+++ b/include/dt-bindings/clock/exynos7-clk.h
@@ -17,7 +17,11 @@
 #define DOUT_SCLK_CC_PLL                4
 #define DOUT_SCLK_MFC_PLL               5
 #define DOUT_ACLK_CCORE_133             6
-#define TOPC_NR_CLK                     7
+#define DOUT_ACLK_MSCL_532              7
+#define ACLK_MSCL_532                   8
+#define DOUT_SCLK_AUD_PLL               9
+#define FOUT_AUD_PLL                    10
+#define TOPC_NR_CLK                     11
 
 /* TOP0 */
 #define DOUT_ACLK_PERIC1                1
@@ -26,7 +30,15 @@
 #define CLK_SCLK_UART1                  4
 #define CLK_SCLK_UART2                  5
 #define CLK_SCLK_UART3                  6
-#define TOP0_NR_CLK                     7
+#define CLK_SCLK_SPI0                   7
+#define CLK_SCLK_SPI1                   8
+#define CLK_SCLK_SPI2                   9
+#define CLK_SCLK_SPI3                   10
+#define CLK_SCLK_SPI4                   11
+#define CLK_SCLK_SPDIF                  12
+#define CLK_SCLK_PCM1                   13
+#define CLK_SCLK_I2S1                   14
+#define TOP0_NR_CLK                     15
 
 /* TOP1 */
 #define DOUT_ACLK_FSYS1_200             1
@@ -70,7 +82,23 @@
 #define PCLK_HSI2C6                     9
 #define PCLK_HSI2C7                     10
 #define PCLK_HSI2C8                     11
-#define PERIC1_NR_CLK                   12
+#define PCLK_SPI0                       12
+#define PCLK_SPI1                       13
+#define PCLK_SPI2                       14
+#define PCLK_SPI3                       15
+#define PCLK_SPI4                       16
+#define SCLK_SPI0                       17
+#define SCLK_SPI1                       18
+#define SCLK_SPI2                       19
+#define SCLK_SPI3                       20
+#define SCLK_SPI4                       21
+#define PCLK_I2S1                       22
+#define PCLK_PCM1                       23
+#define PCLK_SPDIF                      24
+#define SCLK_I2S1                       25
+#define SCLK_PCM1                       26
+#define SCLK_SPDIF                      27
+#define PERIC1_NR_CLK                   28
 
 /* PERIS */
 #define PCLK_CHIPID                     1
@@ -82,11 +110,63 @@
 
 /* FSYS0 */
 #define ACLK_MMC2                       1
-#define FSYS0_NR_CLK                    2
+#define ACLK_AXIUS_USBDRD30X_FSYS0X     2
+#define ACLK_USBDRD300                  3
+#define SCLK_USBDRD300_SUSPENDCLK       4
+#define SCLK_USBDRD300_REFCLK           5
+#define PHYCLK_USBDRD300_UDRD30_PIPE_PCLK_USER          6
+#define PHYCLK_USBDRD300_UDRD30_PHYCLK_USER             7
+#define OSCCLK_PHY_CLKOUT_USB30_PHY             8
+#define ACLK_PDMA0                      9
+#define ACLK_PDMA1                      10
+#define FSYS0_NR_CLK                    11
 
 /* FSYS1 */
 #define ACLK_MMC1                       1
 #define ACLK_MMC0                       2
 #define FSYS1_NR_CLK                    3
 
+/* MSCL */
+#define USERMUX_ACLK_MSCL_532           1
+#define DOUT_PCLK_MSCL                  2
+#define ACLK_MSCL_0                     3
+#define ACLK_MSCL_1                     4
+#define ACLK_JPEG                       5
+#define ACLK_G2D                        6
+#define ACLK_LH_ASYNC_SI_MSCL_0         7
+#define ACLK_LH_ASYNC_SI_MSCL_1         8
+#define ACLK_AXI2ACEL_BRIDGE            9
+#define ACLK_XIU_MSCLX_0                10
+#define ACLK_XIU_MSCLX_1                11
+#define ACLK_QE_MSCL_0                  12
+#define ACLK_QE_MSCL_1                  13
+#define ACLK_QE_JPEG                    14
+#define ACLK_QE_G2D                     15
+#define ACLK_PPMU_MSCL_0                16
+#define ACLK_PPMU_MSCL_1                17
+#define ACLK_MSCLNP_133                 18
+#define ACLK_AHB2APB_MSCL0P             19
+#define ACLK_AHB2APB_MSCL1P             20
+
+#define PCLK_MSCL_0                     21
+#define PCLK_MSCL_1                     22
+#define PCLK_JPEG                       23
+#define PCLK_G2D                        24
+#define PCLK_QE_MSCL_0                  25
+#define PCLK_QE_MSCL_1                  26
+#define PCLK_QE_JPEG                    27
+#define PCLK_QE_G2D                     28
+#define PCLK_PPMU_MSCL_0                29
+#define PCLK_PPMU_MSCL_1                30
+#define PCLK_AXI2ACEL_BRIDGE            31
+#define PCLK_PMU_MSCL                   32
+#define MSCL_NR_CLK                     33
+
+/* AUD */
+#define SCLK_I2S                        1
+#define SCLK_PCM                        2
+#define PCLK_I2S                        3
+#define PCLK_PCM                        4
+#define ACLK_ADMA                       5
+#define AUD_NR_CLK                      6
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS7_H */