[MIPS] Allow hardwiring of the CPU type to a single type for optimization.

This saves a few k on systems which only ever ship with a single CPU type.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

20 files changed, 89 insertions, 86 deletions

diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 6d55e8aab668..6a17c9b508ea 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -263,7 +263,7 @@ static inline void dec_kn03_be_init(void)
          */
         *mcr = (*mcr & ~(KN03_MCR_DIAGCHK | KN03_MCR_DIAGGEN)) |
                KN03_MCR_CORRECT;
-        if (current_cpu_data.cputype == CPU_R4400SC)
+        if (current_cpu_type() == CPU_R4400SC)
                 *mbcs |= KN4K_MB_CSR_EE;
         fast_iob();
 }
diff --git a/arch/mips/dec/kn02xa-berr.c b/arch/mips/dec/kn02xa-berr.c
index 7a053aadcd3a..5f04545c3606 100644
--- a/arch/mips/dec/kn02xa-berr.c
+++ b/arch/mips/dec/kn02xa-berr.c
@@ -132,7 +132,7 @@ void __init dec_kn02xa_be_init(void)
         volatile u32 *mbcs = (void *)CKSEG1ADDR(KN4K_SLOT_BASE + KN4K_MB_CSR);
 
         /* For KN04 we need to make sure EE (?) is enabled in the MB.  */
-        if (current_cpu_data.cputype == CPU_R4000SC)
+        if (current_cpu_type() == CPU_R4000SC)
                 *mbcs |= KN4K_MB_CSR_EE;
         fast_iob();
 
diff --git a/arch/mips/dec/prom/init.c b/arch/mips/dec/prom/init.c
index 808c182fd3fa..93f1239af524 100644
--- a/arch/mips/dec/prom/init.c
+++ b/arch/mips/dec/prom/init.c
@@ -108,8 +108,8 @@ void __init prom_init(void)
 
         /* Were we compiled with the right CPU option? */
 #if defined(CONFIG_CPU_R3000)
-        if ((current_cpu_data.cputype == CPU_R4000SC) ||
-            (current_cpu_data.cputype == CPU_R4400SC)) {
+        if ((current_cpu_type() == CPU_R4000SC) ||
+            (current_cpu_type() == CPU_R4400SC)) {
                 static char r4k_msg[] __initdata =
                         "Please recompile with \"CONFIG_CPU_R4x00 = y\".\n";
                 printk(cpu_msg);
@@ -119,8 +119,8 @@ void __init prom_init(void)
 #endif
 
 #if defined(CONFIG_CPU_R4X00)
-        if ((current_cpu_data.cputype == CPU_R3000) ||
-            (current_cpu_data.cputype == CPU_R3000A)) {
+        if ((current_cpu_type() == CPU_R3000) ||
+            (current_cpu_type() == CPU_R3000A)) {
                 static char r3k_msg[] __initdata =
                         "Please recompile with \"CONFIG_CPU_R3000 = y\".\n";
                 printk(cpu_msg);
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index d96f8218a91e..ac762d8d802d 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -954,7 +954,7 @@ asmlinkage void do_reserved(struct pt_regs *regs)
  */
 static inline void parity_protection_init(void)
 {
-        switch (current_cpu_data.cputype) {
+        switch (current_cpu_type()) {
         case CPU_24K:
         case CPU_34K:
         case CPU_5KC:
@@ -1549,8 +1549,8 @@ void __init trap_init(void)
         set_except_vector(12, handle_ov);
         set_except_vector(13, handle_tr);
 
-        if (current_cpu_data.cputype == CPU_R6000 ||
-            current_cpu_data.cputype == CPU_R6000A) {
+        if (current_cpu_type() == CPU_R6000 ||
+            current_cpu_type() == CPU_R6000A) {
                 /*
                  * The R6000 is the only R-series CPU that features a machine
                  * check exception (similar to the R4000 cache error) and
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index cf48371e5690..8b7b7c57baca 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -328,7 +328,7 @@ static inline void local_r4k___flush_cache_all(void * args)
         r4k_blast_dcache();
         r4k_blast_icache();
 
-        switch (current_cpu_data.cputype) {
+        switch (current_cpu_type()) {
         case CPU_R4000SC:
         case CPU_R4000MC:
         case CPU_R4400SC:
@@ -377,10 +377,10 @@ static inline void local_r4k_flush_cache_mm(void * args)
          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
          * caches, so we can bail out early.
          */
-        if (current_cpu_data.cputype == CPU_R4000SC ||
-            current_cpu_data.cputype == CPU_R4000MC ||
-            current_cpu_data.cputype == CPU_R4400SC ||
-            current_cpu_data.cputype == CPU_R4400MC) {
+        if (current_cpu_type() == CPU_R4000SC ||
+            current_cpu_type() == CPU_R4000MC ||
+            current_cpu_type() == CPU_R4400SC ||
+            current_cpu_type() == CPU_R4400MC) {
                 r4k_blast_scache();
                 return;
         }
@@ -1197,7 +1197,7 @@ static void __init coherency_setup(void)
          * this bit and; some wire it to zero, others like Toshiba had the
          * silly idea of putting something else there ...
          */
-        switch (current_cpu_data.cputype) {
+        switch (current_cpu_type()) {
         case CPU_R4000PC:
         case CPU_R4000SC:
         case CPU_R4000MC:
diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c
index 560a6de96556..9ea121e8cdce 100644
--- a/arch/mips/mm/c-tx39.c
+++ b/arch/mips/mm/c-tx39.c
@@ -69,7 +69,7 @@ static void tx39h_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 /* TX39H2,TX39H3 */
 static inline void tx39_blast_dcache_page(unsigned long addr)
 {
-        if (current_cpu_data.cputype != CPU_TX3912)
+        if (current_cpu_type() != CPU_TX3912)
                 blast_dcache16_page(addr);
 }
 
@@ -307,7 +307,7 @@ static __init void tx39_probe_cache(void)
                                   TX39_CONF_DCS_SHIFT));
 
         current_cpu_data.icache.linesz = 16;
-        switch (current_cpu_data.cputype) {
+        switch (current_cpu_type()) {
         case CPU_TX3912:
                 current_cpu_data.icache.ways = 1;
                 current_cpu_data.dcache.ways = 1;
@@ -341,7 +341,7 @@ void __init tx39_cache_init(void)
 
         tx39_probe_cache();
 
-        switch (current_cpu_data.cputype) {
+        switch (current_cpu_type()) {
         case CPU_TX3912:
                 /* TX39/H core (writethru direct-map cache) */
                 flush_cache_all = tx39h_flush_icache_all;
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index f60b3dc0fc62..98b5e5bac02e 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -35,8 +35,8 @@ static inline unsigned long dma_addr_to_virt(dma_addr_t dma_addr)