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authorChris Wilson <chris@chris-wilson.co.uk>2013-01-15 07:05:55 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2013-01-15 07:34:57 -0500
commit0f3b6849dd55943d915f4b461d7db5e8308d4083 (patch)
tree2bf578f7f72fb6177f6664de6bb3997aa4f9b353
parent93927ca52a55c23e0a6a305e7e9082e8411ac9fa (diff)
drm/i915: Record DERRMR, FORCEWAKE and RING_CTL in error-state
These are useful for investigating hangs involving WAIT_FOR_EVENT. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> [danvet: Apply a droplet of Future-Proof in the if-ladder.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c3
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h3
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c11
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
4 files changed, 19 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e6a11ca85eaf..7944d301518a 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -641,6 +641,7 @@ static void i915_ring_error_state(struct seq_file *m,
641 seq_printf(m, "%s command stream:\n", ring_str(ring)); 641 seq_printf(m, "%s command stream:\n", ring_str(ring));
642 seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]); 642 seq_printf(m, " HEAD: 0x%08x\n", error->head[ring]);
643 seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]); 643 seq_printf(m, " TAIL: 0x%08x\n", error->tail[ring]);
644 seq_printf(m, " CTL: 0x%08x\n", error->ctl[ring]);
644 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]); 645 seq_printf(m, " ACTHD: 0x%08x\n", error->acthd[ring]);
645 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]); 646 seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir[ring]);
646 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]); 647 seq_printf(m, " IPEHR: 0x%08x\n", error->ipehr[ring]);
@@ -693,6 +694,8 @@ static int i915_error_state(struct seq_file *m, void *unused)
693 seq_printf(m, "EIR: 0x%08x\n", error->eir); 694 seq_printf(m, "EIR: 0x%08x\n", error->eir);
694 seq_printf(m, "IER: 0x%08x\n", error->ier); 695 seq_printf(m, "IER: 0x%08x\n", error->ier);
695 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er); 696 seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
697 seq_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
698 seq_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
696 seq_printf(m, "CCID: 0x%08x\n", error->ccid); 699 seq_printf(m, "CCID: 0x%08x\n", error->ccid);
697 700
698 for (i = 0; i < dev_priv->num_fence_regs; i++) 701 for (i = 0; i < dev_priv->num_fence_regs; i++)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ed3059575576..12ab3bdea54d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -188,10 +188,13 @@ struct drm_i915_error_state {
188 u32 pgtbl_er; 188 u32 pgtbl_er;
189 u32 ier; 189 u32 ier;
190 u32 ccid; 190 u32 ccid;
191 u32 derrmr;
192 u32 forcewake;
191 bool waiting[I915_NUM_RINGS]; 193 bool waiting[I915_NUM_RINGS];
192 u32 pipestat[I915_MAX_PIPES]; 194 u32 pipestat[I915_MAX_PIPES];
193 u32 tail[I915_NUM_RINGS]; 195 u32 tail[I915_NUM_RINGS];
194 u32 head[I915_NUM_RINGS]; 196 u32 head[I915_NUM_RINGS];
197 u32 ctl[I915_NUM_RINGS];
195 u32 ipeir[I915_NUM_RINGS]; 198 u32 ipeir[I915_NUM_RINGS];
196 u32 ipehr[I915_NUM_RINGS]; 199 u32 ipehr[I915_NUM_RINGS];
197 u32 instdone[I915_NUM_RINGS]; 200 u32 instdone[I915_NUM_RINGS];
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2220dec3e5d9..fe843389c7b4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1157,6 +1157,7 @@ static void i915_record_ring_state(struct drm_device *dev,
1157 error->acthd[ring->id] = intel_ring_get_active_head(ring); 1157 error->acthd[ring->id] = intel_ring_get_active_head(ring);
1158 error->head[ring->id] = I915_READ_HEAD(ring); 1158 error->head[ring->id] = I915_READ_HEAD(ring);
1159 error->tail[ring->id] = I915_READ_TAIL(ring); 1159 error->tail[ring->id] = I915_READ_TAIL(ring);
1160 error->ctl[ring->id] = I915_READ_CTL(ring);
1160 1161
1161 error->cpu_ring_head[ring->id] = ring->head; 1162 error->cpu_ring_head[ring->id] = ring->head;
1162 error->cpu_ring_tail[ring->id] = ring->tail; 1163 error->cpu_ring_tail[ring->id] = ring->tail;
@@ -1251,6 +1252,16 @@ static void i915_capture_error_state(struct drm_device *dev)
1251 else 1252 else
1252 error->ier = I915_READ(IER); 1253 error->ier = I915_READ(IER);
1253 1254
1255 if (INTEL_INFO(dev)->gen >= 6)
1256 error->derrmr = I915_READ(DERRMR);
1257
1258 if (IS_VALLEYVIEW(dev))
1259 error->forcewake = I915_READ(FORCEWAKE_VLV);
1260 else if (INTEL_INFO(dev)->gen >= 7)
1261 error->forcewake = I915_READ(FORCEWAKE_MT);
1262 else if (INTEL_INFO(dev)->gen == 6)
1263 error->forcewake = I915_READ(FORCEWAKE);
1264
1254 for_each_pipe(pipe) 1265 for_each_pipe(pipe)
1255 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); 1266 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1256 1267
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 186ee5c85b51..b401788e1791 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -512,6 +512,8 @@
512#define GEN7_ERR_INT 0x44040 512#define GEN7_ERR_INT 0x44040
513#define ERR_INT_MMIO_UNCLAIMED (1<<13) 513#define ERR_INT_MMIO_UNCLAIMED (1<<13)
514 514
515#define DERRMR 0x44050
516
515/* GM45+ chicken bits -- debug workaround bits that may be required 517/* GM45+ chicken bits -- debug workaround bits that may be required
516 * for various sorts of correct behavior. The top 16 bits of each are 518 * for various sorts of correct behavior. The top 16 bits of each are
517 * the enables for writing to the corresponding low bit. 519 * the enables for writing to the corresponding low bit.