Merge branch 'mymerge' of ssh://ozlabs.org/home/sfr/kernel-sfr

3 files changed, 110 insertions, 181 deletions

diff --git a/include/asm-ppc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h
index 6e9635114433..59a80163f75f 100644
--- a/include/asm-ppc/dma-mapping.h
+++ b/include/asm-powerpc/dma-mapping.h
@@ -1,15 +1,22 @@
 /*
- * This is based on both include/asm-sh/dma-mapping.h and
- * include/asm-ppc/pci.h
+ * Copyright (C) 2004 IBM
+ *
+ * Implements the generic device dma API for powerpc.
+ * the pci and vio busses
  */
-#ifndef __ASM_PPC_DMA_MAPPING_H
-#define __ASM_PPC_DMA_MAPPING_H
+#ifndef _ASM_DMA_MAPPING_H
+#define _ASM_DMA_MAPPING_H
 
 #include <linux/config.h>
+#include <linux/types.h>
+#include <linux/cache.h>
 /* need struct page definitions */
 #include <linux/mm.h>
 #include <asm/scatterlist.h>
 #include <asm/io.h>
+#include <asm/bug.h>
+
+#define DMA_ERROR_CODE          (~(dma_addr_t)0x0)
 
 #ifdef CONFIG_NOT_COHERENT_CACHE
 /*
@@ -24,22 +31,12 @@ extern void __dma_free_coherent(size_t size, void *vaddr);
 extern void __dma_sync(void *vaddr, size_t size, int direction);
 extern void __dma_sync_page(struct page *page, unsigned long offset,
                                  size_t size, int direction);
-#define dma_cache_inv(_start,_size) \
-        invalidate_dcache_range(_start, (_start + _size))
-#define dma_cache_wback(_start,_size) \
-        clean_dcache_range(_start, (_start + _size))
-#define dma_cache_wback_inv(_start,_size) \
-        flush_dcache_range(_start, (_start + _size))
 
 #else /* ! CONFIG_NOT_COHERENT_CACHE */
 /*
  * Cache coherent cores.
  */
 
-#define dma_cache_inv(_start,_size)             do { } while (0)
-#define dma_cache_wback(_start,_size)           do { } while (0)
-#define dma_cache_wback_inv(_start,_size)       do { } while (0)
-
 #define __dma_alloc_coherent(gfp, size, handle) NULL
 #define __dma_free_coherent(size, addr)         do { } while (0)
 #define __dma_sync(addr, size, rw)              do { } while (0)
@@ -47,6 +44,30 @@ extern void __dma_sync_page(struct page *page, unsigned long offset,
 
 #endif /* ! CONFIG_NOT_COHERENT_CACHE */
 
+#ifdef CONFIG_PPC64
+
+extern int dma_supported(struct device *dev, u64 mask);
+extern int dma_set_mask(struct device *dev, u64 dma_mask);
+extern void *dma_alloc_coherent(struct device *dev, size_t size,
+                dma_addr_t *dma_handle, gfp_t flag);
+extern void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
+                dma_addr_t dma_handle);
+extern dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
+                size_t size, enum dma_data_direction direction);
+extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
+                size_t size, enum dma_data_direction direction);
+extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
+                unsigned long offset, size_t size,
+                enum dma_data_direction direction);
+extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
+                size_t size, enum dma_data_direction direction);
+extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+                enum dma_data_direction direction);
+extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+                int nhwentries, enum dma_data_direction direction);
+
+#else /* CONFIG_PPC64 */
+
 #define dma_supported(dev, mask)        (1)
 
 static inline int dma_set_mask(struct device *dev, u64 dma_mask)
@@ -144,29 +165,27 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 /* We don't do anything here. */
 #define dma_unmap_sg(dev, sg, nents, dir)       do { } while (0)
 
-static inline void
-dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
-                        size_t size,
-                        enum dma_data_direction direction)
+#endif /* CONFIG_PPC64 */
+
+static inline void dma_sync_single_for_cpu(struct device *dev,
+                dma_addr_t dma_handle, size_t size,
+                enum dma_data_direction direction)
 {
         BUG_ON(direction == DMA_NONE);
-
         __dma_sync(bus_to_virt(dma_handle), size, direction);
 }
 
-static inline void
-dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
-                        size_t size,
-                        enum dma_data_direction direction)
+static inline void dma_sync_single_for_device(struct device *dev,
+                dma_addr_t dma_handle, size_t size,
+                enum dma_data_direction direction)
 {
         BUG_ON(direction == DMA_NONE);
-
         __dma_sync(bus_to_virt(dma_handle), size, direction);
 }
 
-static inline void
-dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
-                    enum dma_data_direction direction)
+static inline void dma_sync_sg_for_cpu(struct device *dev,
+                struct scatterlist *sg, int nents,
+                enum dma_data_direction direction)
 {
         int i;
 
@@ -176,9 +195,9 @@ dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
                 __dma_sync_page(sg->page, sg->offset, sg->length, direction);
 }
 
-static inline void
-dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
-                    enum dma_data_direction direction)
+static inline void dma_sync_sg_for_device(struct device *dev,
+                struct scatterlist *sg, int nents,
+                enum dma_data_direction direction)
 {
         int i;
 
@@ -188,6 +207,15 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
                 __dma_sync_page(sg->page, sg->offset, sg->length, direction);
 }
 
+static inline int dma_mapping_error(dma_addr_t dma_addr)
+{
+#ifdef CONFIG_PPC64
+        return (dma_addr == DMA_ERROR_CODE);
+#else
+        return 0;
+#endif
+}
+
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
 #ifdef CONFIG_NOT_COHERENT_CACHE
@@ -198,40 +226,60 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
 
 static inline int dma_get_cache_alignment(void)
 {
+#ifdef CONFIG_PPC64
+        /* no easy way to get cache size on all processors, so return
+         * the maximum possible, to be safe */
+        return (1 << L1_CACHE_SHIFT_MAX);
+#else
         /*
          * Each processor family will define its own L1_CACHE_SHIFT,
          * L1_CACHE_BYTES wraps to this, so this is always safe.