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authorDave Airlie <airlied@redhat.com>2014-03-27 20:22:41 -0400
committerDave Airlie <airlied@redhat.com>2014-05-18 21:13:56 -0400
commit0e5ce92438146655d60447802d2c11bdbc089329 (patch)
treeb01e2275a5fd0ead6cd16e3af4e7e659fd5d9cd5
parent318cfa29d0d787962b4a54c5b82740115a4809e9 (diff)
drm/ast: rename the mindwm/moutdwm and deinline them
we'll need these elsewhere for dp501. Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/gpu/drm/ast/ast_post.c450
1 files changed, 225 insertions, 225 deletions
diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
index 667fabfee91d..e8a64383256e 100644
--- a/drivers/gpu/drm/ast/ast_post.c
+++ b/drivers/gpu/drm/ast/ast_post.c
@@ -107,7 +107,7 @@ ast_set_def_ext_reg(struct drm_device *dev)
107 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg); 107 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
108} 108}
109 109
110static inline u32 mindwm(struct ast_private *ast, u32 r) 110static u32 ast_mindwm(struct ast_private *ast, u32 r)
111{ 111{
112 uint32_t data; 112 uint32_t data;
113 113
@@ -120,7 +120,7 @@ static inline u32 mindwm(struct ast_private *ast, u32 r)
120 return ast_read32(ast, 0x10000 + (r & 0x0000ffff)); 120 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
121} 121}
122 122
123static inline void moutdwm(struct ast_private *ast, u32 r, u32 v) 123static void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
124{ 124{
125 uint32_t data; 125 uint32_t data;
126 ast_write32(ast, 0xf004, r & 0xffff0000); 126 ast_write32(ast, 0xf004, r & 0xffff0000);
@@ -163,28 +163,28 @@ static u32 mmctestburst2_ast2150(struct ast_private *ast, u32 datagen)
163{ 163{
164 u32 data, timeout; 164 u32 data, timeout;
165 165
166 moutdwm(ast, 0x1e6e0070, 0x00000000); 166 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
167 moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3)); 167 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
168 timeout = 0; 168 timeout = 0;
169 do { 169 do {
170 data = mindwm(ast, 0x1e6e0070) & 0x40; 170 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
171 if (++timeout > TIMEOUT_AST2150) { 171 if (++timeout > TIMEOUT_AST2150) {
172 moutdwm(ast, 0x1e6e0070, 0x00000000); 172 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
173 return 0xffffffff; 173 return 0xffffffff;
174 } 174 }
175 } while (!data); 175 } while (!data);
176 moutdwm(ast, 0x1e6e0070, 0x00000000); 176 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
177 moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3)); 177 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
178 timeout = 0; 178 timeout = 0;
179 do { 179 do {
180 data = mindwm(ast, 0x1e6e0070) & 0x40; 180 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
181 if (++timeout > TIMEOUT_AST2150) { 181 if (++timeout > TIMEOUT_AST2150) {
182 moutdwm(ast, 0x1e6e0070, 0x00000000); 182 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
183 return 0xffffffff; 183 return 0xffffffff;
184 } 184 }
185 } while (!data); 185 } while (!data);
186 data = (mindwm(ast, 0x1e6e0070) & 0x80) >> 7; 186 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
187 moutdwm(ast, 0x1e6e0070, 0x00000000); 187 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
188 return data; 188 return data;
189} 189}
190 190
@@ -193,18 +193,18 @@ static u32 mmctestsingle2_ast2150(struct ast_private *ast, u32 datagen)
193{ 193{
194 u32 data, timeout; 194 u32 data, timeout;
195 195
196 moutdwm(ast, 0x1e6e0070, 0x00000000); 196 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
197 moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); 197 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
198 timeout = 0; 198 timeout = 0;
199 do { 199 do {
200 data = mindwm(ast, 0x1e6e0070) & 0x40; 200 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
201 if (++timeout > TIMEOUT_AST2150) { 201 if (++timeout > TIMEOUT_AST2150) {
202 moutdwm(ast, 0x1e6e0070, 0x00000000); 202 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
203 return 0xffffffff; 203 return 0xffffffff;
204 } 204 }
205 } while (!data); 205 } while (!data);
206 data = (mindwm(ast, 0x1e6e0070) & 0x80) >> 7; 206 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
207 moutdwm(ast, 0x1e6e0070, 0x00000000); 207 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
208 return data; 208 return data;
209} 209}
210#endif 210#endif
@@ -224,7 +224,7 @@ static int cbrscan_ast2150(struct ast_private *ast, int busw)
224 u32 patcnt, loop; 224 u32 patcnt, loop;
225 225
226 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) { 226 for (patcnt = 0; patcnt < CBR_PATNUM_AST2150; patcnt++) {
227 moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]); 227 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
228 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) { 228 for (loop = 0; loop < CBR_PASSNUM_AST2150; loop++) {
229 if (cbrtest_ast2150(ast)) 229 if (cbrtest_ast2150(ast))
230 break; 230 break;
@@ -246,7 +246,7 @@ cbr_start:
246 passcnt = 0; 246 passcnt = 0;
247 247
248 for (dlli = 0; dlli < 100; dlli++) { 248 for (dlli = 0; dlli < 100; dlli++) {
249 moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); 249 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
250 data = cbrscan_ast2150(ast, busw); 250 data = cbrscan_ast2150(ast, busw);
251 if (data != 0) { 251 if (data != 0) {
252 if (data & 0x1) { 252 if (data & 0x1) {
@@ -263,7 +263,7 @@ cbr_start:
263 goto cbr_start; 263 goto cbr_start;
264 264
265 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4); 265 dlli = dll_min[0] + (((dll_max[0] - dll_min[0]) * 7) >> 4);
266 moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24)); 266 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
267} 267}
268 268
269 269
@@ -437,20 +437,20 @@ static int mmc_test_burst(struct ast_private *ast, u32 datagen)
437{ 437{
438 u32 data, timeout; 438 u32 data, timeout;
439 439
440 moutdwm(ast, 0x1e6e0070, 0x00000000); 440 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
441 moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3)); 441 ast_moutdwm(ast, 0x1e6e0070, 0x000000c1 | (datagen << 3));
442 timeout = 0; 442 timeout = 0;
443 do { 443 do {
444 data = mindwm(ast, 0x1e6e0070) & 0x3000; 444 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
445 if (data & 0x2000) { 445 if (data & 0x2000) {
446 return 0; 446 return 0;
447 } 447 }
448 if (++timeout > TIMEOUT) { 448 if (++timeout > TIMEOUT) {
449 moutdwm(ast, 0x1e6e0070, 0x00000000); 449 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
450 return 0; 450 return 0;
451 } 451 }
452 } while (!data); 452 } while (!data);
453 moutdwm(ast, 0x1e6e0070, 0x00000000); 453 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
454 return 1; 454 return 1;
455} 455}
456 456
@@ -458,19 +458,19 @@ static int mmc_test_burst2(struct ast_private *ast, u32 datagen)
458{ 458{
459 u32 data, timeout; 459 u32 data, timeout;
460 460
461 moutdwm(ast, 0x1e6e0070, 0x00000000); 461 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
462 moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3)); 462 ast_moutdwm(ast, 0x1e6e0070, 0x00000041 | (datagen << 3));
463 timeout = 0; 463 timeout = 0;
464 do { 464 do {
465 data = mindwm(ast, 0x1e6e0070) & 0x1000; 465 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
466 if (++timeout > TIMEOUT) { 466 if (++timeout > TIMEOUT) {
467 moutdwm(ast, 0x1e6e0070, 0x0); 467 ast_moutdwm(ast, 0x1e6e0070, 0x0);
468 return -1; 468 return -1;
469 } 469 }
470 } while (!data); 470 } while (!data);
471 data = mindwm(ast, 0x1e6e0078); 471 data = ast_mindwm(ast, 0x1e6e0078);
472 data = (data | (data >> 16)) & 0xffff; 472 data = (data | (data >> 16)) & 0xffff;
473 moutdwm(ast, 0x1e6e0070, 0x0); 473 ast_moutdwm(ast, 0x1e6e0070, 0x0);
474 return data; 474 return data;
475} 475}
476 476
@@ -478,19 +478,19 @@ static int mmc_test_single(struct ast_private *ast, u32 datagen)
478{ 478{
479 u32 data, timeout; 479 u32 data, timeout;
480 480
481 moutdwm(ast, 0x1e6e0070, 0x00000000); 481 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
482 moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3)); 482 ast_moutdwm(ast, 0x1e6e0070, 0x000000c5 | (datagen << 3));
483 timeout = 0; 483 timeout = 0;
484 do { 484 do {
485 data = mindwm(ast, 0x1e6e0070) & 0x3000; 485 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
486 if (data & 0x2000) 486 if (data & 0x2000)
487 return 0; 487 return 0;
488 if (++timeout > TIMEOUT) { 488 if (++timeout > TIMEOUT) {
489 moutdwm(ast, 0x1e6e0070, 0x0); 489 ast_moutdwm(ast, 0x1e6e0070, 0x0);
490 return 0; 490 return 0;
491 } 491 }
492 } while (!data); 492 } while (!data);
493 moutdwm(ast, 0x1e6e0070, 0x0); 493 ast_moutdwm(ast, 0x1e6e0070, 0x0);
494 return 1; 494 return 1;
495} 495}
496 496
@@ -498,19 +498,19 @@ static int mmc_test_single2(struct ast_private *ast, u32 datagen)
498{ 498{
499 u32 data, timeout; 499 u32 data, timeout;
500 500
501 moutdwm(ast, 0x1e6e0070, 0x00000000); 501 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
502 moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3)); 502 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
503 timeout = 0; 503 timeout = 0;
504 do { 504 do {
505 data = mindwm(ast, 0x1e6e0070) & 0x1000; 505 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
506 if (++timeout > TIMEOUT) { 506 if (++timeout > TIMEOUT) {
507 moutdwm(ast, 0x1e6e0070, 0x0); 507 ast_moutdwm(ast, 0x1e6e0070, 0x0);
508 return -1; 508 return -1;
509 } 509 }
510 } while (!data); 510 } while (!data);
511 data = mindwm(ast, 0x1e6e0078); 511 data = ast_mindwm(ast, 0x1e6e0078);
512 data = (data | (data >> 16)) & 0xffff; 512 data = (data | (data >> 16)) & 0xffff;
513 moutdwm(ast, 0x1e6e0070, 0x0); 513 ast_moutdwm(ast, 0x1e6e0070, 0x0);
514 return data; 514 return data;
515} 515}
516 516
@@ -539,7 +539,7 @@ static int cbr_scan(struct ast_private *ast)
539 539
540 data2 = 3; 540 data2 = 3;
541 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { 541 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
542 moutdwm(ast, 0x1e6e007c, pattern[patcnt]); 542 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
543 for (loop = 0; loop < CBR_PASSNUM2; loop++) { 543 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
544 if ((data = cbr_test(ast)) != 0) { 544 if ((data = cbr_test(ast)) != 0) {
545 data2 &= data; 545 data2 &= data;
@@ -574,7 +574,7 @@ static u32 cbr_scan2(struct ast_private *ast)
574 574
575 data2 = 0xffff; 575 data2 = 0xffff;
576 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { 576 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
577 moutdwm(ast, 0x1e6e007c, pattern[patcnt]); 577 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
578 for (loop = 0; loop < CBR_PASSNUM2; loop++) { 578 for (loop = 0; loop < CBR_PASSNUM2; loop++) {
579 if ((data = cbr_test2(ast)) != 0) { 579 if ((data = cbr_test2(ast)) != 0) {
580 data2 &= data; 580 data2 &= data;
@@ -603,7 +603,7 @@ static u32 cbr_scan3(struct ast_private *ast)
603 u32 patcnt, loop; 603 u32 patcnt, loop;
604 604
605 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) { 605 for (patcnt = 0; patcnt < CBR_PATNUM; patcnt++) {
606 moutdwm(ast, 0x1e6e007c, pattern[patcnt]); 606 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
607 for (loop = 0; loop < 2; loop++) { 607 for (loop = 0; loop < 2; loop++) {
608 if (cbr_test3(ast)) 608 if (cbr_test3(ast))
609 break; 609 break;
@@ -625,8 +625,8 @@ FINETUNE_START:
625 } 625 }
626 passcnt = 0; 626 passcnt = 0;
627 for (dlli = 0; dlli < 76; dlli++) { 627 for (dlli = 0; dlli < 76; dlli++) {
628 moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24)); 628 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
629 moutdwm(ast, 0x1E6E0074, CBR_SIZE1); 629 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
630 data = cbr_scan2(ast); 630 data = cbr_scan2(ast);
631 if (data != 0) { 631 if (data != 0) {
632 mask = 0x00010001; 632 mask = 0x00010001;
@@ -684,7 +684,7 @@ FINETUNE_DONE:
684 data |= dlli << 21; 684 data |= dlli << 21;
685 } 685 }
686 } 686 }
687 moutdwm(ast, 0x1E6E0080, data); 687 ast_moutdwm(ast, 0x1E6E0080, data);
688 688
689 data = 0; 689 data = 0;
690 for (cnt = 8; cnt < 16; cnt++) { 690 for (cnt = 8; cnt < 16; cnt++) {
@@ -709,7 +709,7 @@ FINETUNE_DONE:
709 data |= dlli << 21; 709 data |= dlli << 21;
710 } 710 }
711 } 711 }
712 moutdwm(ast, 0x1E6E0084, data); 712 ast_moutdwm(ast, 0x1E6E0084, data);
713 return status; 713 return status;
714} /* finetuneDQI_L */ 714} /* finetuneDQI_L */
715 715
@@ -722,10 +722,10 @@ static void finetuneDQSI(struct ast_private *ast)
722 char tag[2][76]; 722 char tag[2][76];
723 723
724 /* Disable DQI CBR */ 724 /* Disable DQI CBR */
725 reg_mcr0c = mindwm(ast, 0x1E6E000C); 725 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
726 reg_mcr18 = mindwm(ast, 0x1E6E0018); 726 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
727 reg_mcr18 &= 0x0000ffff; 727 reg_mcr18 &= 0x0000ffff;
728 moutdwm(ast, 0x1E6E0018, reg_mcr18); 728 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
729 729
730 for (dlli = 0; dlli < 76; dlli++) { 730 for (dlli = 0; dlli < 76; dlli++) {
731 tag[0][dlli] = 0x0; 731 tag[0][dlli] = 0x0;
@@ -740,13 +740,13 @@ static void finetuneDQSI(struct ast_private *ast)
740 for (dqidly = 0; dqidly < 32; dqidly++) { 740 for (dqidly = 0; dqidly < 32; dqidly++) {
741 passcnt[0] = passcnt[1] = 0; 741 passcnt[0] = passcnt[1] = 0;
742 for (dqsip = 0; dqsip < 2; dqsip++) { 742 for (dqsip = 0; dqsip < 2; dqsip++) {
743 moutdwm(ast, 0x1E6E000C, 0); 743 ast_moutdwm(ast, 0x1E6E000C, 0);
744 moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23)); 744 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
745 moutdwm(ast, 0x1E6E000C, reg_mcr0c); 745 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
746 for (dlli = 0; dlli < 76; dlli++) { 746 for (dlli = 0; dlli < 76; dlli++) {
747 moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); 747 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
748 moutdwm(ast, 0x1E6E0070, 0); 748 ast_moutdwm(ast, 0x1E6E0070, 0);
749 moutdwm(ast, 0x1E6E0074, CBR_SIZE0); 749 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
750 if (cbr_scan3(ast)) { 750 if (cbr_scan3(ast)) {
751 if (dlli == 0) 751 if (dlli == 0)
752 break; 752 break;
@@ -800,7 +800,7 @@ static void finetuneDQSI(struct ast_private *ast)
800 } 800 }
801 } 801 }
802 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23); 802 reg_mcr18 = reg_mcr18 | (g_dqidly << 16) | (g_dqsip << 23);
803 moutdwm(ast, 0x1E6E0018, reg_mcr18); 803 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
804 804
805} 805}
806static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param) 806static bool cbr_dll2(struct ast_private *ast, struct ast2300_dram_param *param)
@@ -817,8 +817,8 @@ CBR_START2:
817 dllmax[0] = dllmax[1] = 0x0; 817 dllmax[0] = dllmax[1] = 0x0;
818 passcnt = 0; 818 passcnt = 0;
819 for (dlli = 0; dlli < 76; dlli++) { 819 for (dlli = 0; dlli < 76; dlli++) {
820 moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24)); 820 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
821 moutdwm(ast, 0x1E6E0074, CBR_SIZE2); 821 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
822 data = cbr_scan(ast); 822 data = cbr_scan(ast);
823 if (data != 0) { 823 if (data != 0) {
824 if (data & 0x1) { 824 if (data & 0x1) {
@@ -855,7 +855,7 @@ CBR_DONE2:
855 dlli = (dllmin[1] + dllmax[1]) >> 1; 855 dlli = (dllmin[1] + dllmax[1]) >> 1;
856 dlli <<= 8; 856 dlli <<= 8;
857 dlli += (dllmin[0] + dllmax[0]) >> 1; 857 dlli += (dllmin[0] + dllmax[0]) >> 1;
858 moutdwm(ast, 0x1E6E0068, mindwm(ast, 0x1E720058) | (dlli << 16)); 858 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
859 return status; 859 return status;
860} /* CBRDLL2 */ 860} /* CBRDLL2 */
861 861
@@ -863,10 +863,10 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
863{ 863{
864 u32 trap, trap_AC2, trap_MRS; 864 u32 trap, trap_AC2, trap_MRS;
865 865
866 moutdwm(ast, 0x1E6E2000, 0x1688A8A8); 866 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
867 867
868 /* Ger trap info */ 868 /* Ger trap info */
869 trap = (mindwm(ast, 0x1E6E2070) >> 25) & 0x3; 869 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
870 trap_AC2 = 0x00020000 + (trap << 16); 870 trap_AC2 = 0x00020000 + (trap << 16);
871 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19); 871 trap_AC2 |= 0x00300000 + ((trap & 0x2) << 19);
872 trap_MRS = 0x00000010 + (trap << 4); 872 trap_MRS = 0x00000010 + (trap << 4);
@@ -880,7 +880,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
880 880
881 switch (param->dram_freq) { 881 switch (param->dram_freq) {
882 case 336: 882 case 336:
883 moutdwm(ast, 0x1E6E2020, 0x0190); 883 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
884 param->wodt = 0; 884 param->wodt = 0;
885 param->reg_AC1 = 0x22202725; 885 param->reg_AC1 = 0x22202725;
886 param->reg_AC2 = 0xAA007613 | trap_AC2; 886 param->reg_AC2 = 0xAA007613 | trap_AC2;
@@ -908,7 +908,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
908 break; 908 break;
909 default: 909 default:
910 case 396: 910 case 396:
911 moutdwm(ast, 0x1E6E2020, 0x03F1); 911 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
912 param->wodt = 1; 912 param->wodt = 1;
913 param->reg_AC1 = 0x33302825; 913 param->reg_AC1 = 0x33302825;
914 param->reg_AC2 = 0xCC009617 | trap_AC2; 914 param->reg_AC2 = 0xCC009617 | trap_AC2;
@@ -938,7 +938,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
938 break; 938 break;
939 939
940 case 408: 940 case 408:
941 moutdwm(ast, 0x1E6E2020, 0x01F0); 941 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
942 param->wodt = 1; 942 param->wodt = 1;
943 param->reg_AC1 = 0x33302825; 943 param->reg_AC1 = 0x33302825;
944 param->reg_AC2 = 0xCC009617 | trap_AC2; 944 param->reg_AC2 = 0xCC009617 | trap_AC2;
@@ -968,7 +968,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
968 968
969 break; 969 break;
970 case 456: 970 case 456:
971 moutdwm(ast, 0x1E6E2020, 0x0230); 971 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
972 param->wodt = 0; 972 param->wodt = 0;
973 param->reg_AC1 = 0x33302926; 973 param->reg_AC1 = 0x33302926;
974 param->reg_AC2 = 0xCD44961A; 974 param->reg_AC2 = 0xCD44961A;
@@ -982,7 +982,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
982 param->dll2_finetune_step = 4; 982 param->dll2_finetune_step = 4;
983 break; 983 break;
984 case 504: 984 case 504:
985 moutdwm(ast, 0x1E6E2020, 0x0270); 985 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
986 param->wodt = 1; 986 param->wodt = 1;
987 param->reg_AC1 = 0x33302926; 987 param->reg_AC1 = 0x33302926;
988 param->reg_AC2 = 0xDE44A61D; 988 param->reg_AC2 = 0xDE44A61D;
@@ -996,7 +996,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
996 param->dll2_finetune_step = 4; 996 param->dll2_finetune_step = 4;
997 break; 997 break;
998 case 528: 998 case 528:
999 moutdwm(ast, 0x1E6E2020, 0x0290); 999 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
1000 param->wodt = 1; 1000 param->wodt = 1;
1001 param->rodt = 1; 1001 param->rodt = 1;
1002 param->reg_AC1 = 0x33302926; 1002 param->reg_AC1 = 0x33302926;
@@ -1012,7 +1012,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1012 param->dll2_finetune_step = 3; 1012 param->dll2_finetune_step = 3;
1013 break; 1013 break;
1014 case 576: 1014 case 576:
1015 moutdwm(ast, 0x1E6E2020, 0x0140); 1015 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1016 param->reg_MADJ = 0x00136868; 1016 param->reg_MADJ = 0x00136868;
1017 param->reg_SADJ = 0x00004534; 1017 param->reg_SADJ = 0x00004534;
1018 param->wodt = 1; 1018 param->wodt = 1;
@@ -1030,7 +1030,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1030 param->dll2_finetune_step = 3; 1030 param->dll2_finetune_step = 3;
1031 break; 1031 break;
1032 case 600: 1032 case 600:
1033 moutdwm(ast, 0x1E6E2020, 0x02E1); 1033 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1034 param->reg_MADJ = 0x00136868; 1034 param->reg_MADJ = 0x00136868;
1035 param->reg_SADJ = 0x00004534; 1035 param->reg_SADJ = 0x00004534;
1036 param->wodt = 1; 1036 param->wodt = 1;
@@ -1048,7 +1048,7 @@ static void get_ddr3_info(struct ast_private *ast, struct ast2300_dram_param *pa
1048 param->dll2_finetune_step = 3; 1048 param->dll2_finetune_step = 3;
1049 break; 1049 break;
1050 case 624: 1050 case 624:
1051 moutdwm(ast, 0x1E6E2020, 0x0160); 1051 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1052 param->reg_MADJ = 0x00136868; 1052 param->reg_MADJ = 0x00136868;
1053 param->reg_SADJ = 0x00004534; 1053 param->reg_SADJ = 0x00004534;
1054 param->wodt = 1; 1054 param->wodt = 1;
@@ -1106,95 +1106,95 @@ static void ddr3_init(struct ast_private *ast, struct ast2300_dram_param *param)
1106 u32 data, data2, retry = 0; 1106 u32 data, data2, retry = 0;
1107 1107
1108ddr3_init_start: 1108ddr3_init_start:
1109 moutdwm(ast, 0x1E6E0000, 0xFC600309); 1109 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1110 moutdwm(ast, 0x1E6E0018, 0x00000100); 1110 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1111 moutdwm(ast, 0x1E6E0024, 0x00000000); 1111 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1112 moutdwm(ast, 0x1E6E0034, 0x00000000); 1112 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1113 udelay(10); 1113 udelay(10);
1114 moutdwm(ast, 0x1E6E0064, param->reg_MADJ); 1114 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1115 moutdwm(ast, 0x1E6E0068, param->reg_SADJ); 1115 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1116 udelay(10); 1116 udelay(10);
1117 moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); 1117 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1118 udelay(10); 1118 udelay(10);
1119 1119
1120 moutdwm(ast, 0x1E6E0004, param->dram_config); 1120 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1121 moutdwm(ast, 0x1E6E0008, 0x90040f); 1121 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1122 moutdwm(ast, 0x1E6E0010, param->reg_AC1); 1122 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1123 moutdwm(ast, 0x1E6E0014, param->reg_AC2); 1123 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1124 moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); 1124 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1125 moutdwm(ast, 0x1E6E0080, 0x00000000); 1125 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1126 moutdwm(ast, 0x1E6E0084, 0x00000000); 1126 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1127 moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); 1127 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1128 moutdwm(ast, 0x1E6E0018, 0x4000A170); 1128 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1129 moutdwm(ast, 0x1E6E0018, 0x00002370); 1129 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1130 moutdwm(ast, 0x1E6E0038, 0x00000000); 1130 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1131 moutdwm(ast, 0x1E6E0040, 0xFF444444); 1131 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1132 moutdwm(ast, 0x1E6E0044, 0x22222222); 1132 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1133 moutdwm(ast, 0x1E6E0048, 0x22222222); 1133 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1134 moutdwm(ast, 0x1E6E004C, 0x00000002); 1134 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1135 moutdwm(ast, 0x1E6E0050, 0x80000000); 1135 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1136 moutdwm(ast, 0x1E6E0050, 0x00000000); 1136 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1137 moutdwm(ast, 0x1E6E0054, 0); 1137 ast_moutdwm(ast, 0x1E6E0054, 0);
1138 moutdwm(ast, 0x1E6E0060, param->reg_DRV); 1138 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1139 moutdwm(ast, 0x1E6E006C, param->reg_IOZ); 1139 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1140 moutdwm(ast, 0x1E6E0070, 0x00000000); 1140 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1141 moutdwm(ast, 0x1E6E0074, 0x00000000); 1141 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1142 moutdwm(ast, 0x1E6E0078, 0x00000000); 1142 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1143 moutdwm(ast, 0x1E6E007C, 0x00000000); 1143 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1144 /* Wait MCLK2X lock to MCLK */ 1144 /* Wait MCLK2X lock to MCLK */
1145 do { 1145 do {
1146 data = mindwm(ast, 0x1E6E001C); 1146 data = ast_mindwm(ast, 0x1E6E001C);
1147 } while (!(data & 0x08000000)); 1147 } while (!(data & 0x08000000));
1148 data = mindwm(ast, 0x1E6E001C); 1148 data = ast_mindwm(ast, 0x1E6E001C);
1149 data = (data >> 8) & 0xff; 1149 data = (data >> 8) & 0xff;
1150 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { 1150 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1151 data2 = (mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; 1151 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1152 if ((data2 & 0xff) > param->madj_max) { 1152 if ((data2 & 0xff) > param->madj_max) {
1153 break; 1153 break;
1154 } 1154 }
1155 moutdwm(ast, 0x1E6E0064, data2); 1155 ast_moutdwm(ast, 0x1E6E0064, data2);
1156 if (data2 & 0x00100000) { 1156 if (data2 & 0x00100000) {
1157 data2 = ((data2 & 0xff) >> 3) + 3; 1157 data2 = ((data2 & 0xff) >> 3) + 3;
1158 } else { 1158 } else {
1159 data2 = ((data2 & 0xff) >> 2) + 5; 1159 data2 = ((data2 & 0xff) >> 2) + 5;
1160 } 1160 }
1161 data = mindwm(ast, 0x1E6E0068) & 0xffff00ff; 1161 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1162 data2 += data & 0xff; 1162 data2 += data & 0xff;
1163 data = data | (data2 << 8); 1163 data = data | (data2 << 8);
1164 moutdwm(ast, 0x1E6E0068, data); 1164 ast_moutdwm(ast, 0x1E6E0068, data);
1165 udelay(10); 1165 udelay(10);
1166 moutdwm(ast, 0x1E6E0064, mindwm(ast, 0x1E6E0064) | 0xC0000); 1166 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1167 udelay(10); 1167 udelay(10);
1168 data = mindwm(ast, 0x1E6E0018) & 0xfffff1ff; 1168 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1169 moutdwm(ast, 0x1E6E0018, data); 1169 ast_moutdwm(ast, 0x1E6E0018, data);
1170 data = data | 0x200; 1170 data = data | 0x200;
1171 moutdwm(ast, 0x1E6E0018, data); 1171 ast_moutdwm(ast, 0x1E6E0018, data);
1172 do { 1172 do {
1173 data = mindwm(ast, 0x1E6E001C); 1173 data = ast_mindwm(ast, 0x1E6E001C);
1174 } while (!(data & 0x08000000)); 1174 } while (!(data & 0x08000000));
1175 1175
1176 data = mindwm(ast, 0x1E6E001C); 1176 data = ast_mindwm(ast, 0x1E6E001C);
1177 data = (data >> 8) & 0xff; 1177 data = (data >> 8) & 0xff;
1178 } 1178 }
1179 moutdwm(ast, 0x1E720058, mindwm(ast, 0x1E6E0068) & 0xffff); 1179 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1180 data = mindwm(ast, 0x1E6E0018) | 0xC00; 1180 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1181 moutdwm(ast, 0x1E6E0018, data); 1181 ast_moutdwm(ast, 0x1E6E0018, data);
1182 1182
1183 moutdwm(ast, 0x1E6E0034, 0x00000001); 1183 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1184 moutdwm(ast, 0x1E6E000C, 0x00000040); 1184 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1185 udelay(50); 1185 udelay(50);
1186 /* Mode Register Setting */ 1186 /* Mode Register Setting */
1187 moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); 1187 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1188 moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1188 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1189 moutdwm(ast, 0x1E6E0028, 0x00000005); 1189 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1190 moutdwm(ast, 0x1E6E0028, 0x00000007); 1190 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1191 moutdwm(ast, 0x1E6E0028, 0x00000003); 1191 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1192 moutdwm(ast, 0x1E6E0028, 0x00000001); 1192 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1193 moutdwm(ast, 0x1E6E002C, param->reg_MRS); 1193 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1194 moutdwm(ast, 0x1E6E000C, 0x00005C08); 1194 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1195 moutdwm(ast, 0x1E6E0028, 0x00000001); 1195 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1196 1196
1197 moutdwm(ast, 0x1E6E000C, 0x00005C01); 1197 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1198 data = 0; 1198 data = 0;
1199 if (param->wodt) { 1199 if (param->wodt) {
1200 data = 0x300; 1200 data = 0x300;
@@ -1202,23 +1202,23 @@ ddr3_init_start:
1202 if (param->rodt) { 1202 if (param->rodt) {
1203 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); 1203 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1204 } 1204 }
1205 moutdwm(ast, 0x1E6E0034, data | 0x3); 1205 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1206 1206
1207 /* Calibrate the DQSI delay */ 1207 /* Calibrate the DQSI delay */
1208 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) 1208 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1209 goto ddr3_init_start; 1209 goto ddr3_init_start;
1210 1210
1211 moutdwm(ast, 0x1E6E0120, param->reg_FREQ); 1211 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1212 /* ECC Memory Initialization */ 1212 /* ECC Memory Initialization */
1213#ifdef ECC 1213#ifdef ECC
1214 moutdwm(ast, 0x1E6E007C, 0x00000000); 1214 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1215 moutdwm(ast, 0x1E6E0070, 0x221); 1215 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1216 do { 1216 do {
1217 data = mindwm(ast, 0x1E6E0070); 1217 data = ast_mindwm(ast, 0x1E6E0070);
1218 } while (!(data & 0x00001000)); 1218 } while (!(data & 0x00001000));
1219 moutdwm(ast, 0x1E6E0070, 0x00000000); 1219 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1220 moutdwm(ast, 0x1E6E0050, 0x80000000); 1220 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1221 moutdwm(ast, 0x1E6E0050, 0x00000000); 1221 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1222#endif 1222#endif
1223 1223
1224 1224
@@ -1228,10 +1228,10 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1228{ 1228{
1229 u32 trap, trap_AC2, trap_MRS; 1229 u32 trap, trap_AC2, trap_MRS;
1230 1230
1231 moutdwm(ast, 0x1E6E2000, 0x1688A8A8); 1231 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1232 1232
1233 /* Ger trap info */ 1233 /* Ger trap info */
1234 trap = (mindwm(ast, 0x1E6E2070) >> 25) & 0x3; 1234 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1235 trap_AC2 = (trap << 20) | (trap << 16); 1235 trap_AC2 = (trap << 20) | (trap << 16);
1236 trap_AC2 += 0x00110000; 1236 trap_AC2 += 0x00110000;
1237 trap_MRS = 0x00000040 | (trap << 4); 1237 trap_MRS = 0x00000040 | (trap << 4);
@@ -1245,7 +1245,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1245 1245
1246 switch (param->dram_freq) { 1246 switch (param->dram_freq) {
1247 case 264: 1247 case 264:
1248 moutdwm(ast, 0x1E6E2020, 0x0130); 1248 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1249 param->wodt = 0; 1249 param->wodt = 0;
1250 param->reg_AC1 = 0x11101513; 1250 param->reg_AC1 = 0x11101513;
1251 param->reg_AC2 = 0x78117011; 1251 param->reg_AC2 = 0x78117011;
@@ -1260,7 +1260,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1260 param->dll2_finetune_step = 3; 1260 param->dll2_finetune_step = 3;
1261 break; 1261 break;
1262 case 336: 1262 case 336:
1263 moutdwm(ast, 0x1E6E2020, 0x0190); 1263 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1264 param->wodt = 1; 1264 param->wodt = 1;
1265 param->reg_AC1 = 0x22202613; 1265 param->reg_AC1 = 0x22202613;
1266 param->reg_AC2 = 0xAA009016 | trap_AC2; 1266 param->reg_AC2 = 0xAA009016 | trap_AC2;
@@ -1291,7 +1291,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1291 break; 1291 break;
1292 default: 1292 default:
1293 case 396: 1293 case 396:
1294 moutdwm(ast, 0x1E6E2020, 0x03F1); 1294 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1295 param->wodt = 1; 1295 param->wodt = 1;
1296 param->rodt = 0; 1296 param->rodt = 0;
1297 param->reg_AC1 = 0x33302714; 1297 param->reg_AC1 = 0x33302714;
@@ -1325,7 +1325,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1325 break; 1325 break;
1326 1326
1327 case 408: 1327 case 408:
1328 moutdwm(ast, 0x1E6E2020, 0x01F0); 1328 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1329 param->wodt = 1; 1329 param->wodt = 1;
1330 param->rodt = 0; 1330 param->rodt = 0;
1331 param->reg_AC1 = 0x33302714; 1331 param->reg_AC1 = 0x33302714;
@@ -1358,7 +1358,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1358 1358
1359 break; 1359 break;
1360 case 456: 1360 case 456:
1361 moutdwm(ast, 0x1E6E2020, 0x0230); 1361 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1362 param->wodt = 0; 1362 param->wodt = 0;
1363 param->reg_AC1 = 0x33302815; 1363 param->reg_AC1 = 0x33302815;
1364 param->reg_AC2 = 0xCD44B01E; 1364 param->reg_AC2 = 0xCD44B01E;
@@ -1373,7 +1373,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1373 param->dll2_finetune_step = 3; 1373 param->dll2_finetune_step = 3;
1374 break; 1374 break;
1375 case 504: 1375 case 504:
1376 moutdwm(ast, 0x1E6E2020, 0x0261); 1376 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1377 param->wodt = 1; 1377 param->wodt = 1;
1378 param->rodt = 1; 1378 param->rodt = 1;
1379 param->reg_AC1 = 0x33302815; 1379 param->reg_AC1 = 0x33302815;
@@ -1389,7 +1389,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1389 param->dll2_finetune_step = 3; 1389 param->dll2_finetune_step = 3;
1390 break; 1390 break;
1391 case 528: 1391 case 528:
1392 moutdwm(ast, 0x1E6E2020, 0x0120); 1392 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1393 param->wodt = 1; 1393 param->wodt = 1;
1394 param->rodt = 1; 1394 param->rodt = 1;
1395 param->reg_AC1 = 0x33302815; 1395 param->reg_AC1 = 0x33302815;
@@ -1405,7 +1405,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1405 param->dll2_finetune_step = 3; 1405 param->dll2_finetune_step = 3;
1406 break; 1406 break;
1407 case 552: 1407 case 552:
1408 moutdwm(ast, 0x1E6E2020, 0x02A1); 1408 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1409 param->wodt = 1; 1409 param->wodt = 1;
1410 param->rodt = 1; 1410 param->rodt = 1;
1411 param->reg_AC1 = 0x43402915; 1411 param->reg_AC1 = 0x43402915;
@@ -1421,7 +1421,7 @@ static void get_ddr2_info(struct ast_private *ast, struct ast2300_dram_param *pa
1421 param->dll2_finetune_step = 3; 1421 param->dll2_finetune_step = 3;
1422 break; 1422 break;
1423 case 576: 1423 case 576:
1424 moutdwm(ast, 0x1E6E2020, 0x0140); 1424 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1425 param->wodt = 1; 1425 param->wodt = 1;
1426 param->rodt = 1; 1426 param->rodt = 1;
1427 param->reg_AC1 = 0x43402915; 1427 param->reg_AC1 = 0x43402915;
@@ -1476,99 +1476,99 @@ static void ddr2_init(struct ast_private *ast, struct ast2300_dram_param *param)
1476 u32 data, data2, retry = 0; 1476 u32 data, data2, retry = 0;
1477 1477
1478ddr2_init_start: 1478ddr2_init_start:
1479 moutdwm(ast, 0x1E6E0000, 0xFC600309); 1479 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1480 moutdwm(ast, 0x1E6E0018, 0x00000100); 1480 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1481 moutdwm(ast, 0x1E6E0024, 0x00000000); 1481 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1482 moutdwm(ast, 0x1E6E0064, param->reg_MADJ); 1482 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1483 moutdwm(ast, 0x1E6E0068, param->reg_SADJ); 1483 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1484 udelay(10); 1484 udelay(10);
1485 moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000); 1485 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1486 udelay(10); 1486 udelay(10);
1487 1487
1488 moutdwm(ast, 0x1E6E0004, param->dram_config); 1488 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1489 moutdwm(ast, 0x1E6E0008, 0x90040f); 1489 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1490 moutdwm(ast, 0x1E6E0010, param->reg_AC1); 1490 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1491 moutdwm(ast, 0x1E6E0014, param->reg_AC2); 1491 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1492 moutdwm(ast, 0x1E6E0020, param->reg_DQSIC); 1492 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1493 moutdwm(ast, 0x1E6E0080, 0x00000000); 1493 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1494 moutdwm(ast, 0x1E6E0084, 0x00000000); 1494 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1495 moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY); 1495 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1496 moutdwm(ast, 0x1E6E0018, 0x4000A130); 1496 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1497 moutdwm(ast, 0x1E6E0018, 0x00002330); 1497 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1498 moutdwm(ast, 0x1E6E0038, 0x00000000); 1498 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1499 moutdwm(ast, 0x1E6E0040, 0xFF808000); 1499 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1500 moutdwm(ast, 0x1E6E0044, 0x88848466); 1500 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1501 moutdwm(ast, 0x1E6E0048, 0x44440008); 1501 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1502 moutdwm(ast, 0x1E6E004C, 0x00000000); 1502 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1503 moutdwm(ast, 0x1E6E0050, 0x80000000); 1503 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1504 moutdwm(ast, 0x1E6E0050, 0x00000000); 1504 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1505 moutdwm(ast, 0x1E6E0054, 0); 1505 ast_moutdwm(ast, 0x1E6E0054, 0);
1506 moutdwm(ast, 0x1E6E0060, param->reg_DRV); 1506 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1507 moutdwm(ast, 0x1E6E006C, param->reg_IOZ); 1507 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1508 moutdwm(ast, 0x1E6E0070, 0x00000000); 1508 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1509 moutdwm(ast, 0x1E6E0074, 0x00000000); 1509 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1510 moutdwm(ast, 0x1E6E0078, 0x00000000); 1510 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1511 moutdwm(ast, 0x1E6E007C, 0x00000000); 1511 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1512 1512
1513 /* Wait MCLK2X lock to MCLK */ 1513 /* Wait MCLK2X lock to MCLK */
1514 do { 1514 do {
1515 data = mindwm(ast, 0x1E6E001C); 1515 data = ast_mindwm(ast, 0x1E6E001C);
1516 } while (!(data & 0x08000000)); 1516 } while (!(data & 0x08000000));
1517 data = mindwm(ast, 0x1E6E001C); 1517 data = ast_mindwm(ast, 0x1E6E001C);
1518 data = (data >> 8) & 0xff; 1518 data = (data >> 8) & 0xff;
1519 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) { 1519 while ((data & 0x08) || ((data & 0x7) < 2) || (data < 4)) {
1520 data2 = (mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4; 1520 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1521 if ((data2 & 0xff) > param->madj_max) { 1521 if ((data2 & 0xff) > param->madj_max) {
1522 break; 1522 break;
1523 } 1523 }
1524 moutdwm(ast, 0x1E6E0064, data2); 1524 ast_moutdwm(ast, 0x1E6E0064, data2);
1525 if (data2 & 0x00100000) { 1525 if (data2 & 0x00100000) {
1526 data2 = ((data2 & 0xff) >> 3) + 3; 1526 data2 = ((data2 & 0xff) >> 3) + 3;
1527 } else { 1527 } else {
1528 data2 = ((data2 & 0xff) >> 2) + 5; 1528 data2 = ((data2 & 0xff) >> 2) + 5;
1529 } 1529 }
1530 data = mindwm(ast, 0x1E6E0068) & 0xffff00ff; 1530 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1531 data2 += data & 0xff; 1531 data2 += data & 0xff;
1532 data = data | (data2 << 8); 1532 data = data | (data2 << 8);
1533 moutdwm(ast, 0x1E6E0068, data); 1533 ast_moutdwm(ast, 0x1E6E0068, data);
1534 udelay(10); 1534 udelay(10);
1535 moutdwm(ast, 0x1E6E0064, mindwm(ast, 0x1E6E0064) | 0xC0000); 1535 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1536 udelay(10); 1536 udelay(10);
1537 data = mindwm(ast, 0x1E6E0018) & 0xfffff1ff; 1537 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1538 moutdwm(ast, 0x1E6E0018, data); 1538 ast_moutdwm(ast, 0x1E6E0018, data);
1539 data = data | 0x200; 1539 data = data | 0x200;
1540 moutdwm(ast, 0x1E6E0018, data); 1540 ast_moutdwm(ast, 0x1E6E0018, data);
1541 do { 1541 do {
1542 data = mindwm(ast, 0x1E6E001C); 1542 data = ast_mindwm(ast, 0x1E6E001C);
1543 } while (!(data & 0x08000000)); 1543 } while (!(data & 0x08000000));
1544 1544
1545 data = mindwm(ast, 0x1E6E001C); 1545 data = ast_mindwm(ast, 0x1E6E001C);
1546 data = (data >> 8) & 0xff; 1546 data = (data >> 8) & 0xff;
1547 } 1547 }
1548 moutdwm(ast, 0x1E720058, mindwm(ast, 0x1E6E0008) & 0xffff); 1548 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1549 data = mindwm(ast, 0x1E6E0018) | 0xC00; 1549 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1550 moutdwm(ast, 0x1E6E0018, data); 1550 ast_moutdwm(ast, 0x1E6E0018, data);
1551 1551
1552 moutdwm(ast, 0x1E6E0034, 0x00000001); 1552 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1553 moutdwm(ast, 0x1E6E000C, 0x00000000); 1553 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1554 udelay(50); 1554 udelay(50);
1555 /* Mode Register Setting */ 1555 /* Mode Register Setting */
1556 moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100); 1556 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1557 moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1557 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1558 moutdwm(ast, 0x1E6E0028, 0x00000005); 1558 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1559 moutdwm(ast, 0x1E6E0028, 0x00000007); 1559 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1560 moutdwm(ast, 0x1E6E0028, 0x00000003); 1560 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1561 moutdwm(ast, 0x1E6E0028, 0x00000001); 1561 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1562 1562
1563 moutdwm(ast, 0x1E6E000C, 0x00005C08); 1563 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1564 moutdwm(ast, 0x1E6E002C, param->reg_MRS); 1564 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1565 moutdwm(ast, 0x1E6E0028, 0x00000001); 1565 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1566 moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380); 1566 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1567 moutdwm(ast, 0x1E6E0028, 0x00000003); 1567 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1568 moutdwm(ast, 0x1E6E0030, param->reg_EMRS); 1568 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1569 moutdwm(ast, 0x1E6E0028, 0x00000003); 1569 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1570 1570
1571 moutdwm(ast, 0x1E6E000C, 0x7FFF5C01); 1571 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1572 data = 0; 1572 data = 0;
1573 if (param->wodt) { 1573 if (param->wodt) {
1574 data = 0x500; 1574 data = 0x500;
@@ -1576,8 +1576,8 @@ ddr2_init_start:
1576 if (param->rodt) { 1576 if (param->rodt) {
1577 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3); 1577 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1578 } 1578 }
1579 moutdwm(ast, 0x1E6E0034, data | 0x3); 1579 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1580 moutdwm(ast, 0x1E6E0120, param->reg_FREQ); 1580 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1581 1581
1582 /* Calibrate the DQSI delay */ 1582 /* Calibrate the DQSI delay */
1583 if ((cbr_dll2(ast, param) == false) && (retry++ < 10)) 1583 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
@@ -1585,14 +1585,14 @@ ddr2_init_start:
1585 1585
1586 /* ECC Memory Initialization */ 1586 /* ECC Memory Initialization */
1587#ifdef ECC 1587#ifdef ECC
1588 moutdwm(ast, 0x1E6E007C, 0x00000000); 1588 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1589 moutdwm(ast, 0x1E6E0070, 0x221); 1589 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1590 do { 1590 do {
1591 data = mindwm(ast, 0x1E6E0070); 1591 data = ast_mindwm(ast, 0x1E6E0070);
1592 } while (!(data & 0x00001000)); 1592 } while (!(data & 0x00001000));
1593 moutdwm(ast, 0x1E6E0070, 0x00000000); 1593 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1594 moutdwm(ast, 0x1E6E0050, 0x80000000); 1594 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1595 moutdwm(ast, 0x1E6E0050, 0x00000000); 1595 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1596#endif 1596#endif
1597 1597
1598} 1598}
@@ -1638,8 +1638,8 @@ static void ast_init_dram_2300(struct drm_device *dev)
1638 ddr2_init(ast, &param); 1638 ddr2_init(ast, &param);
1639 } 1639 }
1640 1640
1641 temp = mindwm(ast, 0x1e6e2040); 1641 temp = ast_mindwm(ast, 0x1e6e2040);
1642 moutdwm(ast, 0x1e6e2040, temp | 0x40); 1642 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1643 } 1643 }
1644 1644
1645 /* wait ready */ 1645 /* wait ready */