clk: tegra: Use XUSB-compatible SATA PLL sequence

Use a sequence for enabling hardware control of the SATA PLL
that works both when using the SATA lane with SATA and when
using it with XUSB.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index f070c365f5f7..c7c6d8fb32fb 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -112,6 +112,9 @@
 
 #define SATA_PLL_CFG0           0x490
 #define SATA_PLL_CFG0_PADPLL_RESET_SWCTL        BIT(0)
+#define SATA_PLL_CFG0_PADPLL_USE_LOCKDET        BIT(2)
+#define SATA_PLL_CFG0_SEQ_ENABLE                BIT(24)
+#define SATA_PLL_CFG0_SEQ_START_STATE           BIT(25)
 
 #define PLLE_MISC_PLLE_PTS      BIT(8)
 #define PLLE_MISC_IDDQ_SW_VALUE BIT(13)
@@ -1367,6 +1370,14 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
         /* Enable hw control of SATA pll */
         val = pll_readl(SATA_PLL_CFG0, pll);
         val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
+        val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
+        val |= SATA_PLL_CFG0_SEQ_START_STATE;
+        pll_writel(val, SATA_PLL_CFG0, pll);
+
+        udelay(1);
+
+        val = pll_readl(SATA_PLL_CFG0, pll);
+        val |= SATA_PLL_CFG0_SEQ_ENABLE;
         pll_writel(val, SATA_PLL_CFG0, pll);
 
 out: