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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-06 20:28:13 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-06 20:28:13 -0500
commit0e4c9dc2f2e0fb6d3838eba34382fc6d2d1c381c (patch)
tree14d4ba299004c27ae16169c78233babb0630f139
parent1197ab2942f920f261952de0c392ac749a35796b (diff)
parent99f8bd8556ad829e042e66c1b25a35f1bcc38981 (diff)
Merge branch 'rmobile-latest' of git://github.com/pmundt/linux-sh
* 'rmobile-latest' of git://github.com/pmundt/linux-sh: (21 commits) ARM: mach-shmobile: ag5evm needs CONFIG_I2C ARM: mach-shmobile: sh73a0 and AG5EVM PINT support ARM: mach-shmobile: Add support for PINT though INTC macros ARM: mach-shmobile: SDHI0 GPIO hotplug for AG5EVM ARM: mach-shmobile: Use common INTC IRQ code on sh73a0 ARM: mach-shmobile: Use common INTC IRQ code on sh7372 ARM: mach-shmobile: Use common INTC IRQ code on sh7377 ARM: mach-shmobile: Use common INTC IRQ code on sh7367 ARM: mach-shmobile: sh73a0 GPIO IRQ support ARM: sh7372 ap4evb NOR Flash USB boot fix ARM: mach-shmobile: sh7372 Mackerel NOR Flash USB boot fix sh: intc: Allow triggering on both edges for ARM SoCs ARM: mach-shmobile: Break out INTC IRQ code ARM: mach-shmobile: Kota2 SDHI0 and SDHI1 support ARM: mach-shmobile: Kota2 SCIFA4 and SCIFB support ARM: mach-shmobile: Kota2 MMCIF support ARM: mach-shmobile: Kota2 GPIO LEDs support ARM: mach-shmobile: Kota2 GPIO Keys support ARM: mach-shmobile: Kota2 KEYSC support ARM: mach-shmobile: Kota2 SCIFA2 and SMSC911X support ...
Diffstat
-rw-r--r--arch/arm/mach-shmobile/Kconfig8
-rw-r--r--arch/arm/mach-shmobile/Makefile1
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c36
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c4
-rw-r--r--arch/arm/mach-shmobile/board-kota2.c447
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c4
-rw-r--r--arch/arm/mach-shmobile/include/mach/intc.h246
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h17
-rw-r--r--arch/arm/mach-shmobile/intc-sh7367.c40
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c72
-rw-r--r--arch/arm/mach-shmobile/intc-sh7377.c67
-rw-r--r--arch/arm/mach-shmobile/intc-sh73a0.c187
-rw-r--r--arch/arm/mach-shmobile/pfc-sh73a0.c120
-rw-r--r--arch/arm/mach-shmobile/platsmp.c10
-rw-r--r--drivers/sh/intc/chip.c2
15 files changed, 1063 insertions, 198 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0c8f6cf3e948..0828fab2b65c 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -26,6 +26,7 @@ config ARCH_SH73A0
26 select SH_CLK_CPG 26 select SH_CLK_CPG
27 select ARCH_WANT_OPTIONAL_GPIOLIB 27 select ARCH_WANT_OPTIONAL_GPIOLIB
28 select ARM_GIC 28 select ARM_GIC
29 select I2C
29 30
30comment "SH-Mobile Board Type" 31comment "SH-Mobile Board Type"
31 32
@@ -69,6 +70,11 @@ config MACH_MACKEREL
69 depends on ARCH_SH7372 70 depends on ARCH_SH7372
70 select ARCH_REQUIRE_GPIOLIB 71 select ARCH_REQUIRE_GPIOLIB
71 72
73config MACH_KOTA2
74 bool "KOTA2 board"
75 select ARCH_REQUIRE_GPIOLIB
76 depends on ARCH_SH73A0
77
72comment "SH-Mobile System Configuration" 78comment "SH-Mobile System Configuration"
73 79
74menu "Memory configuration" 80menu "Memory configuration"
@@ -78,6 +84,7 @@ config MEMORY_START
78 default "0x50000000" if MACH_G3EVM 84 default "0x50000000" if MACH_G3EVM
79 default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \ 85 default "0x40000000" if MACH_G4EVM || MACH_AP4EVB || MACH_AG5EVM || \
80 MACH_MACKEREL 86 MACH_MACKEREL
87 default "0x41000000" if MACH_KOTA2
81 default "0x00000000" 88 default "0x00000000"
82 ---help--- 89 ---help---
83 Tweak this only when porting to a new machine which does not 90 Tweak this only when porting to a new machine which does not
@@ -89,6 +96,7 @@ config MEMORY_SIZE
89 default "0x08000000" if MACH_G3EVM 96 default "0x08000000" if MACH_G3EVM
90 default "0x08000000" if MACH_G4EVM 97 default "0x08000000" if MACH_G4EVM
91 default "0x20000000" if MACH_AG5EVM 98 default "0x20000000" if MACH_AG5EVM
99 default "0x1e000000" if MACH_KOTA2
92 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL 100 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
93 default "0x04000000" 101 default "0x04000000"
94 help 102 help
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 612b27000c3e..2aec2f732515 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o
41obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o 41obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
42obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o 42obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
43obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o 43obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
44obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
44 45
45# Framework support 46# Framework support
46obj-$(CONFIG_SMP) += $(smp-y) 47obj-$(CONFIG_SMP) += $(smp-y)
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 475342bcc95c..83624e26b884 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -59,7 +59,7 @@ static struct resource smsc9220_resources[] = {
59 .flags = IORESOURCE_MEM, 59 .flags = IORESOURCE_MEM,
60 }, 60 },
61 [1] = { 61 [1] = {
62 .start = gic_spi(33), /* PINT1 */ 62 .start = SH73A0_PINT0_IRQ(2), /* PINTA2 */
63 .flags = IORESOURCE_IRQ, 63 .flags = IORESOURCE_IRQ,
64 }, 64 },
65}; 65};
@@ -339,6 +339,18 @@ static struct platform_device mipidsi0_device = {
339 }, 339 },
340}; 340};
341 341
342/* SDHI0 */
343static irqreturn_t ag5evm_sdhi0_gpio_cd(int irq, void *arg)
344{
345 struct device *dev = arg;
346 struct sh_mobile_sdhi_info *info = dev->platform_data;
347 struct tmio_mmc_data *pdata = info->pdata;
348
349 tmio_mmc_cd_wakeup(pdata);
350
351 return IRQ_HANDLED;
352}
353
342static struct sh_mobile_sdhi_info sdhi0_info = { 354static struct sh_mobile_sdhi_info sdhi0_info = {
343 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 355 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
344 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 356 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
@@ -462,19 +474,6 @@ static void __init ag5evm_map_io(void)
462 shmobile_setup_console(); 474 shmobile_setup_console();
463} 475}
464 476
465#define PINTC_ADDR 0xe6900000
466#define PINTER0A (PINTC_ADDR + 0xa0)
467#define PINTCR0A (PINTC_ADDR + 0xb0)
468
469void __init ag5evm_init_irq(void)
470{
471 sh73a0_init_irq();
472
473 /* setup PINT: enable PINTA2 as active low */
474 __raw_writel(__raw_readl(PINTER0A) | (1<<29), PINTER0A);
475 __raw_writew(__raw_readw(PINTCR0A) | (2<<10), PINTCR0A);
476}
477
478#define DSI0PHYCR 0xe615006c 477#define DSI0PHYCR 0xe615006c
479 478
480static void __init ag5evm_init(void) 479static void __init ag5evm_init(void)
@@ -570,6 +569,13 @@ static void __init ag5evm_init(void)
570 gpio_request(GPIO_FN_SDHID0_1, NULL); 569 gpio_request(GPIO_FN_SDHID0_1, NULL);
571 gpio_request(GPIO_FN_SDHID0_0, NULL); 570 gpio_request(GPIO_FN_SDHID0_0, NULL);
572 571
572 if (!request_irq(intcs_evt2irq(0x3c0), ag5evm_sdhi0_gpio_cd,
573 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
574 "sdhi0 cd", &sdhi0_device.dev))
575 sdhi0_info.tmio_flags |= TMIO_MMC_HAS_COLD_CD;
576 else
577 pr_warn("Unable to setup SDHI0 GPIO IRQ\n");
578
573 /* enable SDHI1 on CN4 [WLAN I/F] */ 579 /* enable SDHI1 on CN4 [WLAN I/F] */
574 gpio_request(GPIO_FN_SDHICLK1, NULL); 580 gpio_request(GPIO_FN_SDHICLK1, NULL);
575 gpio_request(GPIO_FN_SDHICMD1_PU, NULL); 581 gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
@@ -601,7 +607,7 @@ struct sys_timer ag5evm_timer = {
601 607
602MACHINE_START(AG5EVM, "ag5evm") 608MACHINE_START(AG5EVM, "ag5evm")
603 .map_io = ag5evm_map_io, 609 .map_io = ag5evm_map_io,
604 .init_irq = ag5evm_init_irq, 610 .init_irq = sh73a0_init_irq,
605 .handle_irq = shmobile_handle_irq_gic, 611 .handle_irq = shmobile_handle_irq_gic,
606 .init_machine = ag5evm_init, 612 .init_machine = ag5evm_init,
607 .timer = &ag5evm_timer, 613 .timer = &ag5evm_timer,
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index f9f66c20c9f1..a3aa0f6df964 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -200,8 +200,8 @@ static struct physmap_flash_data nor_flash_data = {
200 200
201static struct resource nor_flash_resources[] = { 201static struct resource nor_flash_resources[] = {
202 [0] = { 202 [0] = {
203 .start = 0x00000000, 203 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */
204 .end = 0x08000000 - 1, 204 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
205 .flags = IORESOURCE_MEM, 205 .flags = IORESOURCE_MEM,
206 } 206 }
207}; 207};
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
new file mode 100644
index 000000000000..adc73122bf20
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -0,0 +1,447 @@
1/*
2 * kota2 board support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 * Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com>
7 * Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/platform_device.h>
28#include <linux/delay.h>
29#include <linux/io.h>
30#include <linux/smsc911x.h>
31#include <linux/gpio.h>
32#include <linux/input.h>
33#include <linux/input/sh_keysc.h>
34#include <linux/gpio_keys.h>
35#include <linux/leds.h>
36#include <linux/mmc/host.h>
37#include <linux/mmc/sh_mmcif.h>
38#include <linux/mfd/tmio.h>
39#include <linux/mmc/sh_mobile_sdhi.h>
40#include <mach/hardware.h>
41#include <mach/sh73a0.h>
42#include <mach/common.h>
43#include <asm/mach-types.h>
44#include <asm/mach/arch.h>
45#include <asm/mach/map.h>
46#include <asm/mach/time.h>
47#include <asm/hardware/gic.h>
48#include <asm/hardware/cache-l2x0.h>
49#include <asm/traps.h>
50
51static struct resource smsc9220_resources[] = {
52 [0] = {
53 .start = 0x14000000, /* CS5A */
54 .end = 0x140000ff, /* A1->A7 */
55 .flags = IORESOURCE_MEM,
56 },
57 [1] = {
58 .start = gic_spi(33), /* PINTA2 @ PORT144 */
59 .flags = IORESOURCE_IRQ,
60 },
61};
62
63static struct smsc911x_platform_config smsc9220_platdata = {
64 .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
65 .phy_interface = PHY_INTERFACE_MODE_MII,
66 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
67 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
68};
69
70static struct platform_device eth_device = {
71 .name = "smsc911x",
72 .id = 0,
73 .dev = {
74 .platform_data = &smsc9220_platdata,
75 },
76 .resource = smsc9220_resources,
77 .num_resources = ARRAY_SIZE(smsc9220_resources),
78};
79
80static struct sh_keysc_info keysc_platdata = {
81 .mode = SH_KEYSC_MODE_6,
82 .scan_timing = 3,
83 .delay = 100,
84 .keycodes = {
85 KEY_NUMERIC_STAR, KEY_NUMERIC_0, KEY_NUMERIC_POUND,
86 0, 0, 0, 0, 0,
87 KEY_NUMERIC_7, KEY_NUMERIC_8, KEY_NUMERIC_9,
88 0, KEY_DOWN, 0, 0, 0,
89 KEY_NUMERIC_4, KEY_NUMERIC_5, KEY_NUMERIC_6,
90 KEY_LEFT, KEY_ENTER, KEY_RIGHT, 0, 0,
91 KEY_NUMERIC_1, KEY_NUMERIC_2, KEY_NUMERIC_3,
92 0, KEY_UP, 0, 0, 0,
93 0, 0, 0, 0, 0, 0, 0, 0,
94 0, 0, 0, 0, 0, 0, 0, 0,
95 0, 0, 0, 0, 0, 0, 0, 0,
96 0, 0, 0, 0, 0, 0, 0, 0,
97 },
98};
99
100static struct resource keysc_resources[] = {
101 [0] = {
102 .name = "KEYSC",
103 .start = 0xe61b0000,
104 .end = 0xe61b0098 - 1,
105 .flags = IORESOURCE_MEM,
106 },
107 [1] = {
108 .start = gic_spi(71),
109 .flags = IORESOURCE_IRQ,
110 },
111};
112
113static struct platform_device keysc_device = {
114 .name = "sh_keysc",
115 .id = 0,
116 .num_resources = ARRAY_SIZE(keysc_resources),
117 .resource = keysc_resources,
118 .dev = {
119 .platform_data = &keysc_platdata,
120 },
121};
122
123#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
124
125static struct gpio_keys_button gpio_buttons[] = {
126 GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */
127 GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */
128 GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */
129 GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */
130 GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */
131 GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */
132 GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */
133 GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */
134 /* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */
135 GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */
136 /* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */
137};
138
139static struct gpio_keys_platform_data gpio_key_info = {
140 .buttons = gpio_buttons,
141 .nbuttons = ARRAY_SIZE(gpio_buttons),
142 .poll_interval = 250, /* polled for now */
143};
144
145static struct platform_device gpio_keys_device = {
146 .name = "gpio-keys-polled", /* polled for now */
147 .id = -1,
148 .dev = {
149 .platform_data = &gpio_key_info,
150 },
151};
152
153#define GPIO_LED(n, g) { .name = n, .gpio = g }
154
155static struct gpio_led gpio_leds[] = {
156 GPIO_LED("V2513", GPIO_PORT153), /* PORT153 [TPU1T02] -> V2513 */
157 GPIO_LED("V2514", GPIO_PORT199), /* PORT199 [TPU4TO1] -> V2514 */
158 GPIO_LED("V2515", GPIO_PORT197), /* PORT197 [TPU2TO1] -> V2515 */
159 GPIO_LED("KEYLED", GPIO_PORT163), /* PORT163 [TPU3TO0] -> KEYLED */
160 GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */
161 GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */
162 GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */
163};
164
165static struct gpio_led_platform_data gpio_leds_info = {
166 .leds = gpio_leds,
167 .num_leds = ARRAY_SIZE(gpio_leds),
168};
169
170static struct platform_device gpio_leds_device = {
171 .name = "leds-gpio",
172 .id = -1,
173 .dev = {
174 .platform_data = &gpio_leds_info,
175 },
176};
177
178static struct resource mmcif_resources[] = {
179 [0] = {
180 .name = "MMCIF",
181 .start = 0xe6bd0000,
182 .end = 0xe6bd00ff,
183 .flags = IORESOURCE_MEM,
184 },
185 [1] = {
186 .start = gic_spi(140),
187 .flags = IORESOURCE_IRQ,
188 },
189 [2] = {
190 .start = gic_spi(141),
191 .flags = IORESOURCE_IRQ,
192 },
193};
194
195static struct sh_mmcif_plat_data mmcif_info = {
196 .ocr = MMC_VDD_165_195,
197 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
198};
199
200static struct platform_device mmcif_device = {
201 .name = "sh_mmcif",
202 .id = 0,
203 .dev = {
204 .platform_data = &mmcif_info,
205 },
206 .num_resources = ARRAY_SIZE(mmcif_resources),
207 .resource = mmcif_resources,
208};
209
210static struct sh_mobile_sdhi_info sdhi0_info = {
211 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
212 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
213};
214
215static struct resource sdhi0_resources[] = {
216 [0] = {
217 .name = "SDHI0",
218 .start = 0xee100000,
219 .end = 0xee1000ff,
220 .flags = IORESOURCE_MEM,
221 },
222 [1] = {
223 .start = gic_spi(83),
224 .flags = IORESOURCE_IRQ,
225 },
226 [2] = {
227 .start = gic_spi(84),
228 .flags = IORESOURCE_IRQ,
229 },
230 [3] = {
231 .start = gic_spi(85),
232 .flags = IORESOURCE_IRQ,
233 },
234};
235
236static struct platform_device sdhi0_device = {
237 .name = "sh_mobile_sdhi",
238 .id = 0,
239 .num_resources = ARRAY_SIZE(sdhi0_resources),
240 .resource = sdhi0_resources,
241 .dev = {
242 .platform_data = &sdhi0_info,
243 },
244};
245
246static struct sh_mobile_sdhi_info sdhi1_info = {
247 .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
248 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
249};
250
251static struct resource sdhi1_resources[] = {
252 [0] = {
253 .name = "SDHI1",
254 .start = 0xee120000,
255 .end = 0xee1200ff,
256 .flags = IORESOURCE_MEM,
257 },
258 [1] = {
259 .start = gic_spi(87),
260 .flags = IORESOURCE_IRQ,
261 },
262 [2] = {
263 .start = gic_spi(88),
264 .flags = IORESOURCE_IRQ,
265 },
266 [3] = {
267 .start = gic_spi(89),
268 .flags = IORESOURCE_IRQ,
269 },
270};
271
272static struct platform_device sdhi1_device = {
273 .name = "sh_mobile_sdhi",
274 .id = 1,
275 .num_resources = ARRAY_SIZE(sdhi1_resources),
276 .resource = sdhi1_resources,
277 .dev = {
278 .platform_data = &sdhi1_info,
279 },
280};
281
282static struct platform_device *kota2_devices[] __initdata = {
283 &eth_device,
284 &keysc_device,
285 &gpio_keys_device,
286 &gpio_leds_device,
287 &mmcif_device,
288 &sdhi0_device,
289 &sdhi1_device,
290};
291
292static struct map_desc kota2_io_desc[] __initdata = {
293 /* create a 1:1 entity map for 0xe6xxxxxx
294 * used by CPGA, INTC and PFC.
295 */
296 {
297 .virtual = 0xe6000000,
298 .pfn = __phys_to_pfn(0xe6000000),
299 .length = 256 << 20,
300 .type = MT_DEVICE_NONSHARED
301 },
302};
303
304static void __init kota2_map_io(void)
305{
306 iotable_init(kota2_io_desc, ARRAY_SIZE(kota2_io_desc));
307
308 /* setup early devices and console here as well */
309 sh73a0_add_early_devices();
310 shmobile_setup_console();
311}
312
313#define PINTER0A 0xe69000a0
314#define PINTCR0A 0xe69000b0
315
316void __init kota2_init_irq(void)
317{
318 sh73a0_init_irq();
319
320 /* setup PINT: enable PINTA2 as active low */
321 __raw_writel(1 << 29, PINTER0A);
322 __raw_writew(2 << 10, PINTCR0A);
323}
324
325static void __init kota2_init(void)
326{
327 sh73a0_pinmux_init();
328
329 /* SCIFA2 (UART2) */
330 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
331 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
332 gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
333 gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
334
335 /* SCIFA4 (UART1) */
336 gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
337 gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
338 gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
339 gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
340
341 /* SMSC911X */
342 gpio_request(GPIO_FN_D0_NAF0, NULL);
343 gpio_request(GPIO_FN_D1_NAF1, NULL);
344 gpio_request(GPIO_FN_D2_NAF2, NULL);
345 gpio_request(GPIO_FN_D3_NAF3, NULL);
346 gpio_request(GPIO_FN_D4_NAF4, NULL);
347 gpio_request(GPIO_FN_D5_NAF5, NULL);
348 gpio_request(GPIO_FN_D6_NAF6, NULL);
349 gpio_request(GPIO_FN_D7_NAF7, NULL);
350 gpio_request(GPIO_FN_D8_NAF8, NULL);
351 gpio_request(GPIO_FN_D9_NAF9, NULL);
352 gpio_request(GPIO_FN_D10_NAF10, NULL);
353 gpio_request(GPIO_FN_D11_NAF11, NULL);
354 gpio_request(GPIO_FN_D12_NAF12, NULL);
355 gpio_request(GPIO_FN_D13_NAF13, NULL);
356 gpio_request(GPIO_FN_D14_NAF14, NULL);
357 gpio_request(GPIO_FN_D15_NAF15, NULL);
358 gpio_request(GPIO_FN_CS5A_, NULL);
359 gpio_request(GPIO_FN_WE0__FWE, NULL);
360 gpio_request(GPIO_PORT144, NULL); /* PINTA2 */
361 gpio_direction_input(GPIO_PORT144);
362 gpio_request(GPIO_PORT145, NULL); /* RESET */
363 gpio_direction_output(GPIO_PORT145, 1);
364
365 /* KEYSC */
366 gpio_request(GPIO_FN_KEYIN0_PU, NULL);
367 gpio_request(GPIO_FN_KEYIN1_PU, NULL);
368 gpio_request(GPIO_FN_KEYIN2_PU, NULL);
369 gpio_request(GPIO_FN_KEYIN3_PU, NULL);
370 gpio_request(GPIO_FN_KEYIN4_PU, NULL);
371 gpio_request(GPIO_FN_KEYIN5_PU, NULL);
372 gpio_request(GPIO_FN_KEYIN6_PU, NULL);
373 gpio_request(GPIO_FN_KEYIN7_PU, NULL);
374 gpio_request(GPIO_FN_KEYOUT0, NULL);
375 gpio_request(GPIO_FN_KEYOUT1, NULL);
376 gpio_request(GPIO_FN_KEYOUT2, NULL);
377 gpio_request(GPIO_FN_KEYOUT3, NULL);
378 gpio_request(GPIO_FN_KEYOUT4, NULL);
379 gpio_request(GPIO_FN_KEYOUT5, NULL);
380 gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
381 gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
382 gpio_request(GPIO_FN_KEYOUT8, NULL);
383
384 /* MMCIF */
385 gpio_request(GPIO_FN_MMCCLK0, NULL);
386 gpio_request(GPIO_FN_MMCD0_0, NULL);
387 gpio_request(GPIO_FN_MMCD0_1, NULL);
388 gpio_request(GPIO_FN_MMCD0_2, NULL);
389 gpio_request(GPIO_FN_MMCD0_3, NULL);
390 gpio_request(GPIO_FN_MMCD0_4, NULL);
391 gpio_request(GPIO_FN_MMCD0_5, NULL);
392 gpio_request(GPIO_FN_MMCD0_6, NULL);
393 gpio_request(GPIO_FN_MMCD0_7, NULL);
394 gpio_request(GPIO_FN_MMCCMD0, NULL);
395 gpio_request(GPIO_PORT208, NULL); /* Reset */
396 gpio_direction_output(GPIO_PORT208, 1);
397
398 /* SDHI0 (microSD) */
399 gpio_request(GPIO_FN_SDHICD0_PU, NULL);
400 gpio_request(GPIO_FN_SDHICMD0_PU, NULL);
401 gpio_request(GPIO_FN_SDHICLK0, NULL);
402 gpio_request(GPIO_FN_SDHID0_3_PU, NULL);
403 gpio_request(GPIO_FN_SDHID0_2_PU, NULL);
404 gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
405 gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
406
407 /* SCIFB (BT) */
408 gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL);
409 gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL);
410 gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL);
411 gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL);
412 gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL);
413
414 /* SDHI1 (BCM4330) */
415 gpio_request(GPIO_FN_SDHICLK1, NULL);
416 gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
417 gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
418 gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
419 gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
420 gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
421
422#ifdef CONFIG_CACHE_L2X0
423 /* Early BRESP enable, Shared attribute override enable, 64K*8way */
424 l2x0_init(__io(0xf0100000), 0x40460000, 0x82000fff);
425#endif
426 sh73a0_add_standard_devices();
427 platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));
428}
429
430static void __init kota2_timer_init(void)
431{
432 sh73a0_clock_init();
433 shmobile_timer.init();
434 return;
435}
436
437struct sys_timer kota2_timer = {
438 .init = kota2_timer_init,
439};
440
441MACHINE_START(KOTA2, "kota2")
442 .map_io = kota2_map_io,
443 .init_irq = kota2_init_irq,
444 .handle_irq = shmobile_handle_irq_gic,
445 .init_machine = kota2_init,
446 .timer = &kota2_timer,
447MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 682042306ea2..9c5e598e0e3d 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -273,8 +273,8 @@ static struct physmap_flash_data nor_flash_data = {
273 273
274static struct resource nor_flash_resources[] = { 274static struct resource nor_flash_resources[] = {
275 [0] = { 275 [0] = {
276 .start = 0x00000000, 276 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */
277 .end = 0x08000000 - 1, 277 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
278 .flags = IORESOURCE_MEM, 278 .flags = IORESOURCE_MEM,
279 } 279 }
280}; 280};
diff --git a/arch/arm/mach-shmobile/include/mach/intc.h b/arch/arm/mach-shmobile/include/mach/intc.h
new file mode 100644
index 000000000000..8b22258c8caa
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/intc.h
@@ -0,0 +1,246 @@
1#ifndef __ASM_MACH_INTC_H
2#define __ASM_MACH_INTC_H
3#include <linux/sh_intc.h>
4
5#define INTC_IRQ_PINS_ENUM_16L(p) \
6 p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
7 p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7, \
8 p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
9 p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15
10
11#define INTC_IRQ_PINS_ENUM_16H(p) \
12 p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
13 p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23, \
14 p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
15 p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31
16
17#define INTC_IRQ_PINS_VECT_16L(p, vect) \
18 vect(p ## _IRQ0, 0x0200), vect(p ## _IRQ1, 0x0220), \
19 vect(p ## _IRQ2, 0x0240), vect(p ## _IRQ3, 0x0260), \
20 vect(p ## _IRQ4, 0x0280), vect(p ## _IRQ5, 0x02a0), \
21 vect(p ## _IRQ6, 0x02c0), vect(p ## _IRQ7, 0x02e0), \
22 vect(p ## _IRQ8, 0x0300), vect(p ## _IRQ9, 0x0320), \
23 vect(p ## _IRQ10, 0x0340), vect(p ## _IRQ11, 0x0360), \
24 vect(p ## _IRQ12, 0x0380), vect(p ## _IRQ13, 0x03a0), \
25 vect(p ## _IRQ14, 0x03c0), vect(p ## _IRQ15, 0x03e0)
26
27#define INTC_IRQ_PINS_VECT_16H(p, vect) \
28 vect(p ## _IRQ16, 0x3200), vect(p ## _IRQ17, 0x3220), \
29 vect(p ## _IRQ18, 0x3240), vect(p ## _IRQ19, 0x3260), \
30 vect(p ## _IRQ20, 0x3280), vect(p ## _IRQ21, 0x32a0), \
31 vect(p ## _IRQ22, 0x32c0), vect(p ## _IRQ23, 0x32e0), \
32 vect(p ## _IRQ24, 0x3300), vect(p ## _IRQ25, 0x3320), \
33 vect(p ## _IRQ26, 0x3340), vect(p ## _IRQ27, 0x3360), \
34 vect(p ## _IRQ28, 0x3380), vect(p ## _IRQ29, 0x33a0), \
35 vect(p ## _IRQ30, 0x33c0), vect(p ## _IRQ31, 0x33e0)
36
37#define INTC_IRQ_PINS_MASK_16L(p, base) \
38 { base + 0x40, base + 0x60, 8, /* INTMSK00A / INTMSKCLR00A */ \
39 { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
40 p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
41 { base + 0x44, base + 0x64, 8, /* INTMSK10A / INTMSKCLR10A */ \
42 { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
43 p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
44
45#define INTC_IRQ_PINS_MASK_16H(p, base) \
46 { base + 0x48, base + 0x68, 8, /* INTMSK20A / INTMSKCLR20A */ \
47 { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
48 p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
49 { base + 0x4c, base + 0x6c, 8, /* INTMSK30A / INTMSKCLR30A */ \
50 { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
51 p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
52
53#define INTC_IRQ_PINS_PRIO_16L(p, base) \
54 { base + 0x10, 0, 32, 4, /* INTPRI00A */ \
55 { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
56 p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
57 { base + 0x14, 0, 32, 4, /* INTPRI10A */ \
58 { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
59 p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
60
61#define INTC_IRQ_PINS_PRIO_16H(p, base) \
62 { base + 0x18, 0, 32, 4, /* INTPRI20A */ \
63 { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
64 p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
65 { base + 0x1c, 0, 32, 4, /* INTPRI30A */ \
66 { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
67 p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
68
69#define INTC_IRQ_PINS_SENSE_16L(p, base) \
70 { base + 0x00, 32, 4, /* ICR1A */ \
71 { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
72 p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
73 { base + 0x04, 32, 4, /* ICR2A */ \
74 { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
75 p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
76
77#define INTC_IRQ_PINS_SENSE_16H(p, base) \
78 { base + 0x08, 32, 4, /* ICR3A */ \
79 { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
80 p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
81 { base + 0x0c, 32, 4, /* ICR4A */ \
82 { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
83 p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
84
85#define INTC_IRQ_PINS_ACK_16L(p, base) \
86 { base + 0x20, 0, 8, /* INTREQ00A */ \
87 { p ## _IRQ0, p ## _IRQ1, p ## _IRQ2, p ## _IRQ3, \
88 p ## _IRQ4, p ## _IRQ5, p ## _IRQ6, p ## _IRQ7 } }, \
89 { base + 0x24, 0, 8, /* INTREQ10A */ \
90 { p ## _IRQ8, p ## _IRQ9, p ## _IRQ10, p ## _IRQ11, \
91 p ## _IRQ12, p ## _IRQ13, p ## _IRQ14, p ## _IRQ15 } }
92
93#define INTC_IRQ_PINS_ACK_16H(p, base) \
94 { base + 0x28, 0, 8, /* INTREQ20A */ \
95 { p ## _IRQ16, p ## _IRQ17, p ## _IRQ18, p ## _IRQ19, \
96 p ## _IRQ20, p ## _IRQ21, p ## _IRQ22, p ## _IRQ23 } }, \
97 { base + 0x2c, 0, 8, /* INTREQ30A */ \
98 { p ## _IRQ24, p ## _IRQ25, p ## _IRQ26, p ## _IRQ27, \
99 p ## _IRQ28, p ## _IRQ29, p ## _IRQ30, p ## _IRQ31 } }
100
101#define INTC_IRQ_PINS_16(p, base, vect, str) \
102 \
103static struct resource p ## _resources[] __initdata = { \
104 [0] = { \
105 .start = base, \
106 .end = base + 0x64, \
107 .flags = IORESOURCE_MEM, \
108 }, \
109}; \
110 \
111enum { \
112 p ## _UNUSED = 0, \
113 INTC_IRQ_PINS_ENUM_16L(p), \
114}; \
115 \
116static struct intc_vect p ## _vectors[] __initdata = { \
117 INTC_IRQ_PINS_VECT_16L(p, vect), \
118}; \
119 \
120static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
121 INTC_IRQ_PINS_MASK_16L(p, base), \
122}; \
123 \
124static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
125 INTC_IRQ_PINS_PRIO_16L(p, base), \
126}; \
127 \
128static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
129 INTC_IRQ_PINS_SENSE_16L(p, base), \
130}; \
131 \
132static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
133 INTC_IRQ_PINS_ACK_16L(p, base), \
134}; \
135 \
136static struct intc_desc p ## _desc __initdata = { \
137 .name = str, \
138 .resource = p ## _resources, \
139 .num_resources = ARRAY_SIZE(p ## _resources), \
140 .hw = INTC_HW_DESC(p ## _vectors, NULL, \
141 p ## _mask_registers, p ## _prio_registers, \
142 p ## _sense_registers, p ## _ack_registers) \
143}
144
145#define INTC_IRQ_PINS_32(p, base, vect, str) \
146 \
147static struct resource p ## _resources[] __initdata = { \
148 [0] = { \
149 .start = base, \
150 .end = base + 0x6c, \
151 .flags = IORESOURCE_MEM, \
152 }, \
153}; \
154 \
155enum { \
156 p ## _UNUSED = 0, \
157 INTC_IRQ_PINS_ENUM_16L(p), \
158 INTC_IRQ_PINS_ENUM_16H(p), \
159}; \
160 \
161static struct intc_vect p ## _vectors[] __initdata = { \
162 INTC_IRQ_PINS_VECT_16L(p, vect), \
163 INTC_IRQ_PINS_VECT_16H(p, vect), \
164}; \
165 \
166static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
167 INTC_IRQ_PINS_MASK_16L(p, base), \
168 INTC_IRQ_PINS_MASK_16H(p, base), \
169}; \
170 \
171static struct intc_prio_reg p ## _prio_registers[] __initdata = { \
172 INTC_IRQ_PINS_PRIO_16L(p, base), \
173 INTC_IRQ_PINS_PRIO_16H(p, base), \
174}; \
175 \
176static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
177 INTC_IRQ_PINS_SENSE_16L(p, base), \
178 INTC_IRQ_PINS_SENSE_16H(p, base), \
179}; \
180 \
181static struct intc_mask_reg p ## _ack_registers[] __initdata = { \
182 INTC_IRQ_PINS_ACK_16L(p, base), \
183 INTC_IRQ_PINS_ACK_16H(p, base), \
184}; \
185 \
186static struct intc_desc p ## _desc __initdata = { \
187 .name = str, \
188 .resource = p ## _resources, \
189 .num_resources = ARRAY_SIZE(p ## _resources), \
190 .hw = INTC_HW_DESC(p ## _vectors, NULL, \
191 p ## _mask_registers, p ## _prio_registers, \
192 p ## _sense_registers, p ## _ack_registers) \
193}
194
195#define INTC_PINT_E_EMPTY
196#define INTC_PINT_E_NONE 0, 0, 0, 0, 0, 0, 0, 0,
197#define INTC_PINT_E(p) \
198 PINT ## p ## 0, PINT ## p ## 1, PINT ## p ## 2, PINT ## p ## 3, \
199 PINT ## p ## 4, PINT ## p ## 5, PINT ## p ## 6, PINT ## p ## 7,
200
201#define INTC_PINT_V_NONE
202#define INTC_PINT_V(p, vect) \
203 vect(PINT ## p ## 0, 0), vect(PINT ## p ## 1, 1), \
204 vect(PINT ## p ## 2, 2), vect(PINT ## p ## 3, 3), \
205 vect(PINT ## p ## 4, 4), vect(PINT ## p ## 5, 5), \
206 vect(PINT ## p ## 6, 6), vect(PINT ## p ## 7, 7),
207
208#define INTC_PINT(p, mask_reg, sense_base, str, \
209 enums_1, enums_2, enums_3, enums_4, \
210 vect_1, vect_2, vect_3, vect_4, \
211 mask_a, mask_b, mask_c, mask_d, \
212 sense_a, sense_b, sense_c, sense_d) \
213 \
214enum { \
215 PINT ## p ## _UNUSED = 0, \
216 enums_1 enums_2 enums_3 enums_4 \
217}; \
218 \
219static struct intc_vect p ## _vectors[] __initdata = { \
220 vect_1 vect_2 vect_3 vect_4 \
221}; \
222 \
223static struct intc_mask_reg p ## _mask_registers[] __initdata = { \
224 { mask_reg, 0, 32, /* PINTER */ \
225 { mask_a mask_b mask_c mask_d } } \
226}; \
227 \
228static struct intc_sense_reg p ## _sense_registers[] __initdata = { \
229 { sense_base + 0x00, 16, 2, /* PINTCR */ \
230 { sense_a } }, \
231 { sense_base + 0x04, 16, 2, /* PINTCR */ \
232 { sense_b } }, \
233 { sense_base + 0x08, 16, 2, /* PINTCR */ \
234 { sense_c } }, \
235 { sense_base + 0x0c, 16, 2, /* PINTCR */ \
236 { sense_d } }, \
237}; \
238 \
239static struct intc_desc p ## _desc __initdata = { \
240 .name = str, \
241 .hw = INTC_HW_DESC(p ## _vectors, NULL, \
242 p ## _mask_registers, NULL, \
243 p ## _sense_registers, NULL), \
244}
245
246#endif /* __ASM_MACH_INTC_H */
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 216c3d695ef1..18ae6a990bc2 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -451,11 +451,23 @@ enum {
451 GPIO_FN_KEYIN5_PU, 451 GPIO_FN_KEYIN5_PU,
452 GPIO_FN_KEYIN6_PU, 452 GPIO_FN_KEYIN6_PU,
453 GPIO_FN_KEYIN7_PU, 453 GPIO_FN_KEYIN7_PU,
454 GPIO_FN_SDHICD0_PU,
455 GPIO_FN_SDHID0_0_PU,
456 GPIO_FN_SDHID0_1_PU,
457 GPIO_FN_SDHID0_2_PU,
458 GPIO_FN_SDHID0_3_PU,
459 GPIO_FN_SDHICMD0_PU,
460 GPIO_FN_SDHIWP0_PU,
454 GPIO_FN_SDHID1_0_PU, 461 GPIO_FN_SDHID1_0_PU,
455 GPIO_FN_SDHID1_1_PU, 462 GPIO_FN_SDHID1_1_PU,
456 GPIO_FN_SDHID1_2_PU, 463 GPIO_FN_SDHID1_2_PU,
457 GPIO_FN_SDHID1_3_PU, 464 GPIO_FN_SDHID1_3_PU,
458 GPIO_FN_SDHICMD1_PU, 465 GPIO_FN_SDHICMD1_PU,
466 GPIO_FN_SDHID2_0_PU,
467 GPIO_FN_SDHID2_1_PU,
468 GPIO_FN_SDHID2_2_PU,
469 GPIO_FN_SDHID2_3_PU,
470 GPIO_FN_SDHICMD2_PU,
459 GPIO_FN_MMCCMD0_PU, 471 GPIO_FN_MMCCMD0_PU,
460 GPIO_FN_MMCCMD1_PU, 472 GPIO_FN_MMCCMD1_PU,
461 GPIO_FN_FSIACK_PU, 473 GPIO_FN_FSIACK_PU,
@@ -463,6 +475,7 @@ enum {
463 GPIO_FN_FSIAIBT_PU, 475 GPIO_FN_FSIAIBT_PU,
464 GPIO_FN_FSIAISLD_PU, 476 GPIO_FN_FSIAISLD_PU,
465}; 477};
478
466/* DMA slave IDs */ 479/* DMA slave IDs */
467enum { 480enum {
468 SHDMA_SLAVE_INVALID, 481 SHDMA_SLAVE_INVALID,
@@ -494,4 +507,8 @@ enum {
494 SHDMA_SLAVE_MMCIF_RX, 507 SHDMA_SLAVE_MMCIF_RX,
495}; 508};
496 509
510/* PINT interrupts are located at Linux IRQ 768 and up */
511#define SH73A0_PINT0_IRQ(irq) ((irq) + 768)
512#define SH73A0_PINT1_IRQ(irq) ((irq) + 800)
513
497#endif /* __ASM_SH73A0_H__ */ 514#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
index cc442d198cdc..cfde9bfc3669 100644
--- a/arch/arm/mach-shmobile/intc-sh7367.c
+++ b/arch/arm/mach-shmobile/intc-sh7367.c
@@ -22,6 +22,7 @@
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/sh_intc.h> 24#include <linux/sh_intc.h>
25#include <mach/intc.h>
25#include <asm/mach-types.h> 26#include <asm/mach-types.h>
26#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
27 28
@@ -31,8 +32,6 @@ enum {
31 DISABLED, 32 DISABLED,
32 33
33 /* interrupt sources INTCA */ 34 /* interrupt sources INTCA */
34 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
35 IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
36 DIRC, 35 DIRC,
37 CRYPT1_ERR, CRYPT2_STD, 36 CRYPT1_ERR, CRYPT2_STD,
38 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, 37 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
@@ -76,14 +75,6 @@ enum {
76}; 75};
77 76
78static struct intc_vect intca_vectors[] __initdata = { 77static struct intc_vect intca_vectors[] __initdata = {
79 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
80 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
81 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
82 INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
83 INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
84 INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
85 INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
86 INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
87 INTC_VECT(DIRC, 0x0560), 78 INTC_VECT(DIRC, 0x0560),
88 INTC_VECT(CRYPT1_ERR, 0x05e0), 79 INTC_VECT(CRYPT1_ERR, 0x05e0),
89 INTC_VECT(CRYPT2_STD, 0x0700), 80 INTC_VECT(CRYPT2_STD, 0x0700),
@@ -163,10 +154,6 @@ static struct intc_group intca_groups[] __initdata = {
163}; 154};
164 155
165static struct intc_mask_reg intca_mask_registers[] __initdata = { 156static struct intc_mask_reg intca_mask_registers[] __initdata = {
166 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
167 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
168 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
169 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
170 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ 157 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
171 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, 158 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
172 ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } }, 159 ARM11_IRQPMU, 0, ARM11_COMMTX, ARM11_COMMRX } },
@@ -212,11 +199,6 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
212}; 199};
213 200
214static struct intc_prio_reg intca_prio_registers[] __initdata = { 201static struct intc_prio_reg intca_prio_registers[] __initdata = {
215 { 0xe6900010, 0, 32, 4, /* INTPRI00A */
216 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
217 { 0xe6900014, 0, 32, 4, /* INTPRI10A */
218 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
219
220 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, 202 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
221 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } }, 203 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, ETM11, BBIF1, BBIF2 } },
222 { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD, 204 { 0xe6940008, 0, 16, 4, /* IPRCA */ { CRYPT1_ERR, CRYPT2_STD,
@@ -240,29 +222,18 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
240 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } }, 222 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
241}; 223};
242 224
243static struct intc_sense_reg intca_sense_registers[] __initdata = {
244 { 0xe6900000, 16, 2, /* ICR1A */
245 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
246 { 0xe6900004, 16, 2, /* ICR2A */
247 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
248};
249
250static struct intc_mask_reg intca_ack_registers[] __initdata = {
251 { 0xe6900020, 0, 8, /* INTREQ00A */
252 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
253 { 0xe6900024, 0, 8, /* INTREQ10A */
254 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
255};
256
257static struct intc_desc intca_desc __initdata = { 225static struct intc_desc intca_desc __initdata = {
258 .name = "sh7367-intca", 226 .name = "sh7367-intca",
259 .force_enable = ENABLED, 227 .force_enable = ENABLED,
260 .force_disable = DISABLED, 228 .force_disable = DISABLED,
261 .hw = INTC_HW_DESC(intca_vectors, intca_groups, 229 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
262 intca_mask_registers, intca_prio_registers, 230 intca_mask_registers, intca_prio_registers,
263 intca_sense_registers, intca_ack_registers), 231 NULL, NULL),
264}; 232};
265 233
234INTC_IRQ_PINS_16(intca_irq_pins, 0xe6900000,
235 INTC_VECT, "sh7367-intca-irq-pins");
236
266enum { 237enum {
267 UNUSED_INTCS = 0, 238 UNUSED_INTCS = 0,
268 239
@@ -432,6 +403,7 @@ void __init sh7367_init_irq(void)
432 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); 403 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
433 404
434 register_intc_controller(&intca_desc); 405 register_intc_controller(&intca_desc);
406 register_intc_controller(&intca_irq_pins_desc);
435 register_intc_controller(&intcs_desc); 407 register_intc_controller(&intcs_desc);
436 408
437 /* demux using INTEVTSA */ 409 /* demux using INTEVTSA */
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 29cdc0522d9c..2d8856df80e2 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -22,6 +22,7 @@
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/sh_intc.h> 24#include <linux/sh_intc.h>
25#include <mach/intc.h>
25#include <asm/mach-types.h> 26#include <asm/mach-types.h>
26#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
27 28
@@ -29,10 +30,6 @@ enum {
29 UNUSED_INTCA = 0, 30 UNUSED_INTCA = 0,
30 31
31 /* interrupt sources INTCA */ 32 /* interrupt sources INTCA */
32 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
33 IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
34 IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
35 IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
36 DIRC, 33 DIRC,
37 CRYPT_STD, 34 CRYPT_STD,
38 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1, 35 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
@@ -86,22 +83,6 @@ enum {
86}; 83};
87 84
88static struct intc_vect intca_vectors[] __initdata = { 85static struct intc_vect intca_vectors[] __initdata = {
89 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
90 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
91 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
92 INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
93 INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
94 INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
95 INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
96 INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
97 INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
98 INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
99 INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ21A, 0x32a0),
100 INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
101 INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
102 INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
103 INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
104 INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
105 INTC_VECT(DIRC, 0x0560), 86 INTC_VECT(DIRC, 0x0560),
106 INTC_VECT(CRYPT_STD, 0x0700), 87 INTC_VECT(CRYPT_STD, 0x0700),
107 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0), 88 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
@@ -203,15 +184,6 @@ static struct intc_group intca_groups[] __initdata = {
203}; 184};
204 185
205static struct intc_mask_reg intca_mask_registers[] __initdata = { 186static struct intc_mask_reg intca_mask_registers[] __initdata = {
206 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
207 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
208 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
209 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
210 { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
211 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
212 { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
213 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
214
215 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ 187 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
216 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, 188 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
217 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, 189 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
@@ -282,15 +254,6 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
282}; 254};
283 255
284static struct intc_prio_reg intca_prio_registers[] __initdata = { 256static struct intc_prio_reg intca_prio_registers[] __initdata = {
285 { 0xe6900010, 0, 32, 4, /* INTPRI00A */
286 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
287 { 0xe6900014, 0, 32, 4, /* INTPRI10A */
288 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
289 { 0xe6900018, 0, 32, 4, /* INTPRI20A */
290 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
291 { 0xe690001c, 0, 32, 4, /* INTPRI30A */
292 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
293
294 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } }, 257 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
295 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, 258 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
296 { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD, 259 { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
@@ -336,33 +299,13 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
336 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } }, 299 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
337}; 300};
338 301
339static struct intc_sense_reg intca_sense_registers[] __initdata = { 302static DECLARE_INTC_DESC(intca_desc, "sh7372-intca",
340 { 0xe6900000, 32, 4, /* ICR1A */ 303 intca_vectors, intca_groups,
341 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } }, 304 intca_mask_registers, intca_prio_registers,
342 { 0xe6900004, 32, 4, /* ICR2A */ 305 NULL);
343 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
344 { 0xe6900008, 32, 4, /* ICR3A */
345 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
346 { 0xe690000c, 32, 4, /* ICR4A */
347 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
348};
349
350static struct intc_mask_reg intca_ack_registers[] __initdata = {
351 { 0xe6900020, 0, 8, /* INTREQ00A */
352 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
353 { 0xe6900024, 0, 8, /* INTREQ10A */
354 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
355 { 0xe6900028, 0, 8, /* INTREQ20A */
356 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
357 { 0xe690002c, 0, 8, /* INTREQ30A */
358 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
359};
360
361static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca",
362 intca_vectors, intca_groups,
363 intca_mask_registers, intca_prio_registers,
364 intca_sense_registers, intca_ack_registers);
365 306
307INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
308 INTC_VECT, "sh7372-intca-irq-pins");
366enum { 309enum {
367 UNUSED_INTCS = 0, 310 UNUSED_INTCS = 0,
368 ENABLED_INTCS, 311 ENABLED_INTCS,
@@ -618,6 +561,7 @@ void __init sh7372_init_irq(void)
618 intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE); 561 intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
619 562
620 register_intc_controller(&intca_desc); 563 register_intc_controller(&intca_desc);
564 register_intc_controller(&intca_irq_pins_desc);
621 register_intc_controller(&intcs_desc); 565 register_intc_controller(&intcs_desc);
622 566
623 /* demux using INTEVTSA */ 567 /* demux using INTEVTSA */
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
index fe45154ce660..2af4e6e9bc5b 100644
--- a/arch/arm/mach-shmobile/intc-sh7377.c
+++ b/arch/arm/mach-shmobile/intc-sh7377.c
@@ -22,6 +22,7 @@
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/sh_intc.h> 24#include <linux/sh_intc.h>
25#include <mach/intc.h>
25#include <asm/mach-types.h> 26#include <asm/mach-types.h>
26#include <asm/mach/arch.h> 27#include <asm/mach/arch.h>
27 28
@@ -31,10 +32,6 @@ enum {
31 DISABLED, 32 DISABLED,
32 33
33 /* interrupt sources INTCA */ 34 /* interrupt sources INTCA */
34 IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
35 IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A,
36 IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A,
37 IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A,
38 DIRC, 35 DIRC,
39 _2DG, 36 _2DG,
40 CRYPT_STD, 37 CRYPT_STD,
@@ -91,22 +88,6 @@ enum {
91}; 88};
92 89
93static struct intc_vect intca_vectors[] __initdata = { 90static struct intc_vect intca_vectors[] __initdata = {
94 INTC_VECT(IRQ0A, 0x0200), INTC_VECT(IRQ1A, 0x0220),
95 INTC_VECT(IRQ2A, 0x0240), INTC_VECT(IRQ3A, 0x0260),
96 INTC_VECT(IRQ4A, 0x0280), INTC_VECT(IRQ5A, 0x02a0),
97 INTC_VECT(IRQ6A, 0x02c0), INTC_VECT(IRQ7A, 0x02e0),
98 INTC_VECT(IRQ8A, 0x0300), INTC_VECT(IRQ9A, 0x0320),
99 INTC_VECT(IRQ10A, 0x0340), INTC_VECT(IRQ11A, 0x0360),
100 INTC_VECT(IRQ12A, 0x0380), INTC_VECT(IRQ13A, 0x03a0),
101 INTC_VECT(IRQ14A, 0x03c0), INTC_VECT(IRQ15A, 0x03e0),
102 INTC_VECT(IRQ16A, 0x3200), INTC_VECT(IRQ17A, 0x3220),
103 INTC_VECT(IRQ18A, 0x3240), INTC_VECT(IRQ19A, 0x3260),
104 INTC_VECT(IRQ20A, 0x3280), INTC_VECT(IRQ31A, 0x32a0),
105 INTC_VECT(IRQ22A, 0x32c0), INTC_VECT(IRQ23A, 0x32e0),
106 INTC_VECT(IRQ24A, 0x3300), INTC_VECT(IRQ25A, 0x3320),
107 INTC_VECT(IRQ26A, 0x3340), INTC_VECT(IRQ27A, 0x3360),
108 INTC_VECT(IRQ28A, 0x3380), INTC_VECT(IRQ29A, 0x33a0),
109 INTC_VECT(IRQ30A, 0x33c0), INTC_VECT(IRQ31A, 0x33e0),
110 INTC_VECT(DIRC, 0x0560), 91 INTC_VECT(DIRC, 0x0560),
111 INTC_VECT(_2DG, 0x05e0), 92 INTC_VECT(_2DG, 0x05e0),
112 INTC_VECT(CRYPT_STD, 0x0700), 93 INTC_VECT(CRYPT_STD, 0x0700),
@@ -203,15 +184,6 @@ static struct intc_group intca_groups[] __initdata = {
203}; 184};
204 185
205static struct intc_mask_reg intca_mask_registers[] __initdata = { 186static struct intc_mask_reg intca_mask_registers[] __initdata = {
206 { 0xe6900040, 0xe6900060, 8, /* INTMSK00A / INTMSKCLR00A */
207 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
208 { 0xe6900044, 0xe6900064, 8, /* INTMSK10A / INTMSKCLR10A */
209 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
210 { 0xe6900048, 0xe6900068, 8, /* INTMSK20A / INTMSKCLR20A */
211 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
212 { 0xe690004c, 0xe690006c, 8, /* INTMSK30A / INTMSKCLR30A */
213 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
214
215 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */ 187 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
216 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0, 188 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
217 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } }, 189 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
@@ -273,15 +245,6 @@ static struct intc_mask_reg intca_mask_registers[] __initdata = {
273}; 245};
274 246
275static struct intc_prio_reg intca_prio_registers[] __initdata = { 247static struct intc_prio_reg intca_prio_registers[] __initdata = {
276 { 0xe6900010, 0, 32, 4, /* INTPRI00A */
277 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
278 { 0xe6900014, 0, 32, 4, /* INTPRI10A */
279 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
280 { 0xe6900018, 0, 32, 4, /* INTPRI10A */
281 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
282 { 0xe690001c, 0, 32, 4, /* INTPRI30A */
283 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
284
285 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } }, 248 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, LCRC } },
286 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } }, 249 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
287 { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD, 250 { 0xe6940008, 0, 16, 4, /* IPRCA */ { _2DG, CRYPT_STD,
@@ -315,37 +278,18 @@ static struct intc_prio_reg intca_prio_registers[] __initdata = {
315 { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } }, 278 { 0xe694003c, 0, 16, 4, /* IPRPA3 */ { SCIFA6, 0, 0, 0 } },
316}; 279};
317 280
318static struct intc_sense_reg intca_sense_registers[] __initdata = {
319 { 0xe6900000, 16, 2, /* ICR1A */
320 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
321 { 0xe6900004, 16, 2, /* ICR2A */
322 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
323 { 0xe6900008, 16, 2, /* ICR3A */
324 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
325 { 0xe690000c, 16, 2, /* ICR4A */
326 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
327};
328
329static struct intc_mask_reg intca_ack_registers[] __initdata = {
330 { 0xe6900020, 0, 8, /* INTREQ00A */
331 { IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A } },
332 { 0xe6900024, 0, 8, /* INTREQ10A */
333 { IRQ8A, IRQ9A, IRQ10A, IRQ11A, IRQ12A, IRQ13A, IRQ14A, IRQ15A } },
334 { 0xe6900028, 0, 8, /* INTREQ20A */
335 { IRQ16A, IRQ17A, IRQ18A, IRQ19A, IRQ20A, IRQ21A, IRQ22A, IRQ23A } },
336 { 0xe690002c, 0, 8, /* INTREQ30A */
337 { IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
338};
339
340static struct intc_desc intca_desc __initdata = { 281static struct intc_desc intca_desc __initdata = {
341 .name = "sh7377-intca", 282 .name = "sh7377-intca",
342 .force_enable = ENABLED, 283 .force_enable = ENABLED,
343 .force_disable = DISABLED, 284 .force_disable = DISABLED,
344 .hw = INTC_HW_DESC(intca_vectors, intca_groups, 285 .hw = INTC_HW_DESC(intca_vectors, intca_groups,
345 intca_mask_registers, intca_prio_registers, 286 intca_mask_registers, intca_prio_registers,
346 intca_sense_registers, intca_ack_registers), 287 NULL, NULL),
347}; 288};
348 289
290INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
291 INTC_VECT, "sh7377-intca-irq-pins");
292
349/* this macro ignore entry which is also in INTCA */ 293/* this macro ignore entry which is also in INTCA */
350#define __IGNORE(a...) 294#define __IGNORE(a...)
351#define __IGNORE0(a...) 0 295#define __IGNORE0(a...) 0
@@ -638,6 +582,7 @@ void __init sh7377_init_irq(void)
638 void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE); 582 void __iomem *intevtsa = ioremap_nocache(INTEVTSA, PAGE_SIZE);
639 583
640 register_intc_controller(&intca_desc); 584 register_intc_controller(&intca_desc);
585 register_intc_controller(&intca_irq_pins_desc);
641 register_intc_controller(&intcs_desc); 586 register_intc_controller(&intcs_desc);
642 587
643 /* demux using INTEVTSA */ 588 /* demux using INTEVTSA */
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c
index a911a60e7719..1eda6b0b69e3 100644
--- a/arch/arm/mach-shmobile/intc-sh73a0.c
+++ b/arch/arm/mach-shmobile/intc-sh73a0.c
@@ -22,6 +22,8 @@
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/sh_intc.h> 24#include <linux/sh_intc.h>
25#include <mach/intc.h>
26#include <mach/sh73a0.h>
25#include <asm/hardware/gic.h> 27#include <asm/hardware/gic.h>
26#include <asm/mach-types.h> 28#include <asm/mach-types.h>
27#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
@@ -255,20 +257,205 @@ static int sh73a0_set_wake(struct irq_data *data, unsigned int on)
255 return 0; /* always allow wakeup */ 257 return 0; /* always allow wakeup */
256} 258}
257 259
260#define RELOC_BASE 0x1000
261
262/* INTCA IRQ pins at INTCS + 0x1000 to make space for GIC+INTC handling */
263#define INTCS_VECT_RELOC(n, vect) INTCS_VECT((n), (vect) + RELOC_BASE)
264
265INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
266 INTCS_VECT_RELOC, "sh73a0-intca-irq-pins");
267
268static int to_gic_irq(struct irq_data *data)
269{
270 unsigned int vect = irq2evt(data->irq) - INTCS_VECT_BASE;
271
272 if (vect >= 0x3200)
273 vect -= 0x3000;
274 else
275 vect -= 0x0200;
276
277 return gic_spi((vect >> 5) + 1);
278}
279
280static int to_intca_reloc_irq(struct irq_data *data)
281{
282 return data->irq + (RELOC_BASE >> 5);
283}
284
285#define irq_cb(cb, irq) irq_get_chip(irq)->cb(irq_get_irq_data(irq))
286#define irq_cbp(cb, irq, p...) irq_get_chip(irq)->cb(irq_get_irq_data(irq), p)
287
288static void intca_gic_enable(struct irq_data *data)
289{
290 irq_cb(irq_unmask, to_intca_reloc_irq(data));
291 irq_cb(irq_unmask, to_gic_irq(data));
292}
293
294static void intca_gic_disable(struct irq_data *data)
295{
296 irq_cb(irq_mask, to_gic_irq(data));
297 irq_cb(irq_mask, to_intca_reloc_irq(data));
298}
299
300static void intca_gic_mask_ack(struct irq_data *data)
301{
302 irq_cb(irq_mask, to_gic_irq(data));
303 irq_cb(irq_mask_ack, to_intca_reloc_irq(data));
304}
305
306static void intca_gic_eoi(struct irq_data *data)
307{
308 irq_cb(irq_eoi, to_gic_irq(data));
309}
310
311static int intca_gic_set_type(struct irq_data *data, unsigned int type)
312{
313 return irq_cbp(irq_set_type, to_intca_reloc_irq(data), type);
314}
315
316static int intca_gic_set_wake(struct irq_data *data, unsigned int on)
317{
318 return irq_cbp(irq_set_wake, to_intca_reloc_irq(data), on);
319}
320
321#ifdef CONFIG_SMP
322static int intca_gic_set_affinity(struct irq_data *data,
323 const struct cpumask *cpumask,
324 bool force)
325{
326 return irq_cbp(irq_set_affinity, to_gic_irq(data), cpumask, force);
327}
328#endif
329
330struct irq_chip intca_gic_irq_chip = {
331 .name = "INTCA-GIC",
332 .irq_mask = intca_gic_disable,
333 .irq_unmask = intca_gic_enable,
334 .irq_mask_ack = intca_gic_mask_ack,
335 .irq_eoi = intca_gic_eoi,
336 .irq_enable = intca_gic_enable,
337 .irq_disable = intca_gic_disable,
338 .irq_shutdown = intca_gic_disable,
339 .irq_set_type = intca_gic_set_type,
340 .irq_set_wake = intca_gic_set_wake,
341#ifdef CONFIG_SMP
342 .irq_set_affinity = intca_gic_set_affinity,
343#endif
344};
345
346static int to_intc_vect(int irq)
347{
348 unsigned int irq_pin = irq - gic_spi(1);
349 unsigned int offs;
350
351 if (irq_pin < 16)
352 offs = 0x0200;
353 else
354 offs = 0x3000;
355
356 return offs + (irq_pin << 5);
357}
358
359static irqreturn_t sh73a0_irq_pin_demux(int irq, void *dev_id)
360{
361 generic_handle_irq(intcs_evt2irq(to_intc_vect(irq)));
362 return IRQ_HANDLED;
363}
364
365static struct irqaction sh73a0_irq_pin_cascade[32];
366
367#define PINTER0 0xe69000a0
368#define PINTER1 0xe69000a4
369#define PINTRR0 0xe69000d0
370#define PINTRR1 0xe69000d4
371
372#define PINT0A_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq))
373#define PINT0B_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 8))
374#define PINT0C_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 16))
375#define PINT0D_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT0_IRQ(irq + 24))
376#define PINT1E_IRQ(n, irq) INTC_IRQ((n), SH73A0_PINT1_IRQ(irq))
377
378INTC_PINT(intc_pint0, PINTER0, 0xe69000b0, "sh73a0-pint0", \
379 INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
380 INTC_PINT_V(A, PINT0A_IRQ), INTC_PINT_V(B, PINT0B_IRQ), \
381 INTC_PINT_V(C, PINT0C_IRQ), INTC_PINT_V(D, PINT0D_IRQ), \
382 INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D), \
383 INTC_PINT_E(A), INTC_PINT_E(B), INTC_PINT_E(C), INTC_PINT_E(D));
384
385INTC_PINT(intc_pint1, PINTER1, 0xe69000c0, "sh73a0-pint1", \
386 INTC_PINT_E(E), INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, INTC_PINT_E_EMPTY, \
387 INTC_PINT_V(E, PINT1E_IRQ), INTC_PINT_V_NONE, \
388 INTC_PINT_V_NONE, INTC_PINT_V_NONE, \
389 INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E(E), \
390 INTC_PINT_E(E), INTC_PINT_E_NONE, INTC_PINT_E_NONE, INTC_PINT_E_NONE);
391
392static struct irqaction sh73a0_pint0_cascade;
393static struct irqaction sh73a0_pint1_cascade;
394
395static void pint_demux(unsigned long rr, unsigned long er, int base_irq)
396{
397 unsigned long value = ioread32(rr) & ioread32(er);
398 int k;
399
400 for (k = 0; k < 32; k++) {
401 if (value & (1 << (31 - k))) {
402 generic_handle_irq(base_irq + k);
403 iowrite32(~(1 << (31 - k)), rr);
404 }
405 }
406}
407
408static irqreturn_t sh73a0_pint0_demux(int irq, void *dev_id)
409{
410 pint_demux(PINTRR0, PINTER0, SH73A0_PINT0_IRQ(0));
411 return IRQ_HANDLED;
412}
413
414static irqreturn_t sh73a0_pint1_demux(int irq, void *dev_id)
415{
416 pint_demux(PINTRR1, PINTER1, SH73A0_PINT1_IRQ(0));
417 return IRQ_HANDLED;
418}
419
258void __init sh73a0_init_irq(void) 420void __init sh73a0_init_irq(void)
259{ 421{
260 void __iomem *gic_dist_base = __io(0xf0001000); 422 void __iomem *gic_dist_base = __io(0xf0001000);
261 void __iomem *gic_cpu_base = __io(0xf0000100); 423 void __iomem *gic_cpu_base = __io(0xf0000100);
262 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); 424 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE);
425 int k, n;
263 426
264 gic_init(0, 29, gic_dist_base, gic_cpu_base); 427 gic_init(0, 29, gic_dist_base, gic_cpu_base);
265 gic_arch_extn.irq_set_wake = sh73a0_set_wake; 428 gic_arch_extn.irq_set_wake = sh73a0_set_wake;
266 429
267 register_intc_controller(&intcs_desc); 430 register_intc_controller(&intcs_desc);
431 register_intc_controller(&intca_irq_pins_desc);
432 register_intc_controller(&intc_pint0_desc);
433 register_intc_controller(&intc_pint1_desc);
268 434
269 /* demux using INTEVTSA */ 435 /* demux using INTEVTSA */
270 sh73a0_intcs_cascade.name = "INTCS cascade"; 436 sh73a0_intcs_cascade.name = "INTCS cascade";
271 sh73a0_intcs_cascade.handler = sh73a0_intcs_demux; 437 sh73a0_intcs_cascade.handler = sh73a0_intcs_demux;
272 sh73a0_intcs_cascade.dev_id = intevtsa; 438 sh73a0_intcs_cascade.dev_id = intevtsa;
273 setup_irq(gic_spi(50), &sh73a0_intcs_cascade); 439 setup_irq(gic_spi(50), &sh73a0_intcs_cascade);
440
441 /* IRQ pins require special handling through INTCA and GIC */
442 for (k = 0; k < 32; k++) {
443 sh73a0_irq_pin_cascade[k].name = "INTCA-GIC cascade";
444 sh73a0_irq_pin_cascade[k].handler = sh73a0_irq_pin_demux;
445 setup_irq(gic_spi(1 + k), &sh73a0_irq_pin_cascade[k]);
446
447 n = intcs_evt2irq(to_intc_vect(gic_spi(1 + k)));
448 irq_set_chip_and_handler_name(n, &intca_gic_irq_chip,
449 handle_level_irq, "level");
450 set_irq_flags(n, IRQF_VALID); /* yuck */
451 }
452
453 /* PINT pins are sanely tied to the GIC as SPI */
454 sh73a0_pint0_cascade.name = "PINT0 cascade";
455 sh73a0_pint0_cascade.handler = sh73a0_pint0_demux;
456 setup_irq(gic_spi(33), &sh73a0_pint0_cascade);
457
458 sh73a0_pint1_cascade.name = "PINT1 cascade";
459 sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
460 setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
274} 461}
diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c
index 3eed44eb98b4..5abe02fbd6b9 100644
--- a/arch/arm/mach-shmobile/pfc-sh73a0.c
+++ b/arch/arm/mach-shmobile/pfc-sh73a0.c
@@ -22,6 +22,7 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/gpio.h> 23#include <linux/gpio.h>
24#include <mach/sh73a0.h> 24#include <mach/sh73a0.h>
25#include <mach/irqs.h>
25 26
26#define _1(fn, pfx, sfx) fn(pfx, sfx) 27#define _1(fn, pfx, sfx) fn(pfx, sfx)
27 28
@@ -488,13 +489,26 @@ enum {
488 KEYIN5_PU_MARK, 489 KEYIN5_PU_MARK,
489 KEYIN6_PU_MARK, 490 KEYIN6_PU_MARK,
490 KEYIN7_PU_MARK, 491 KEYIN7_PU_MARK,
492 SDHICD0_PU_MARK,
493 SDHID0_0_PU_MARK,
494 SDHID0_1_PU_MARK,
495 SDHID0_2_PU_MARK,
496 SDHID0_3_PU_MARK,
497 SDHICMD0_PU_MARK,
498 SDHIWP0_PU_MARK,
491 SDHID1_0_PU_MARK, 499 SDHID1_0_PU_MARK,
492 SDHID1_1_PU_MARK, 500 SDHID1_1_PU_MARK,
493 SDHID1_2_PU_MARK, 501 SDHID1_2_PU_MARK,
494 SDHID1_3_PU_MARK, 502 SDHID1_3_PU_MARK,
495 SDHICMD1_PU_MARK, 503 SDHICMD1_PU_MARK,
504 SDHID2_0_PU_MARK,
505 SDHID2_1_PU_MARK,
506 SDHID2_2_PU_MARK,
507 SDHID2_3_PU_MARK,
508 SDHICMD2_PU_MARK,
496 MMCCMD0_PU_MARK, 509 MMCCMD0_PU_MARK,
497 MMCCMD1_PU_MARK, 510 MMCCMD1_PU_MARK,
511 FSIBISLD_PU_MARK,
498 FSIACK_PU_MARK, 512 FSIACK_PU_MARK,
499 FSIAILR_PU_MARK, 513 FSIAILR_PU_MARK,
500 FSIAIBT_PU_MARK, 514 FSIAIBT_PU_MARK,
@@ -1387,19 +1401,28 @@ static pinmux_enum_t pinmux_data[] = {
1387 PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), 1401 PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1388 PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), 1402 PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1389 PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), 1403 PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1390 PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0), 1404 PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU,
1391 PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0), 1405 MSEL4CR_MSEL15_0),
1392 PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0), 1406 PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU,
1393 PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0), 1407 MSEL4CR_MSEL15_0),
1394 PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), \ 1408 PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU,
1409 MSEL4CR_MSEL15_0),
1410 PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
1411 MSEL4CR_MSEL15_0),
1412 PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
1413 MSEL4CR_MSEL15_0), \
1395 PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), 1414 PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1396 PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), \ 1415 PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU,
1416 MSEL4CR_MSEL15_0), \
1397 PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), 1417 PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1398 PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), \ 1418 PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU,
1419 MSEL4CR_MSEL15_0), \
1399 PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), 1420 PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1400 PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), \ 1421 PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU,
1422 MSEL4CR_MSEL15_0), \
1401 PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), 1423 PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1402 PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0), 1424 PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU,
1425 MSEL4CR_MSEL15_0),
1403 PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ 1426 PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1404 PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), 1427 PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1405 PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), 1428 PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
@@ -1516,16 +1539,29 @@ static pinmux_enum_t pinmux_data[] = {
1516 PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), 1539 PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU),
1517 PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), 1540 PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU),
1518 1541
1519 PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_IN_PU, PORT259_FN1), 1542 PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU),
1520 PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_IN_PU, PORT260_FN1), 1543 PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU),
1521 PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_IN_PU, PORT261_FN1), 1544 PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU),
1522 PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_IN_PU, PORT262_FN1), 1545 PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU),
1523 PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_IN_PU, PORT263_FN1), 1546 PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU),
1547 PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU),
1548 PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU),
1549 PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU),
1550 PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU),
1551 PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU),
1552 PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU),
1553 PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU),
1554 PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU),
1555 PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU),
1556 PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU),
1557 PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU),
1558 PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU),
1524 1559
1525 PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, 1560 PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU,
1526 MSEL4CR_MSEL15_0), 1561 MSEL4CR_MSEL15_0),
1527 PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT279_IN_PU, 1562 PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU,
1528 MSEL4CR_MSEL15_1), 1563 MSEL4CR_MSEL15_1),
1564 PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU),
1529 PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), 1565 PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU),
1530 PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), 1566 PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU),
1531 PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), 1567 PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU),
@@ -2181,11 +2217,23 @@ static struct pinmux_gpio pinmux_gpios[] = {
2181 GPIO_FN(KEYIN5_PU), 2217 GPIO_FN(KEYIN5_PU),
2182 GPIO_FN(KEYIN6_PU), 2218 GPIO_FN(KEYIN6_PU),
2183 GPIO_FN(KEYIN7_PU), 2219 GPIO_FN(KEYIN7_PU),
2220 GPIO_FN(SDHICD0_PU),
2221 GPIO_FN(SDHID0_0_PU),
2222 GPIO_FN(SDHID0_1_PU),
2223 GPIO_FN(SDHID0_2_PU),
2224 GPIO_FN(SDHID0_3_PU),
2225 GPIO_FN(SDHICMD0_PU),
2226 GPIO_FN(SDHIWP0_PU),
2184 GPIO_FN(SDHID1_0_PU), 2227 GPIO_FN(SDHID1_0_PU),
2185 GPIO_FN(SDHID1_1_PU), 2228 GPIO_FN(SDHID1_1_PU),
2186 GPIO_FN(SDHID1_2_PU), 2229 GPIO_FN(SDHID1_2_PU),
2187 GPIO_FN(SDHID1_3_PU), 2230 GPIO_FN(SDHID1_3_PU),
2188 GPIO_FN(SDHICMD1_PU), 2231 GPIO_FN(SDHICMD1_PU),
2232 GPIO_FN(SDHID2_0_PU),
2233 GPIO_FN(SDHID2_1_PU),
2234 GPIO_FN(SDHID2_2_PU),
2235 GPIO_FN(SDHID2_3_PU),
2236 GPIO_FN(SDHICMD2_PU),
2189 GPIO_FN(MMCCMD0_PU), 2237 GPIO_FN(MMCCMD0_PU),
2190 GPIO_FN(MMCCMD1_PU), 2238 GPIO_FN(MMCCMD1_PU),
2191 GPIO_FN(FSIACK_PU), 2239 GPIO_FN(FSIACK_PU),
@@ -2718,6 +2766,45 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2718 { }, 2766 { },
2719}; 2767};
2720 2768
2769/* IRQ pins through INTCS with IRQ0->15 from 0x200 and IRQ16-31 from 0x3200 */
2770#define EXT_IRQ16L(n) intcs_evt2irq(0x200 + ((n) << 5))
2771#define EXT_IRQ16H(n) intcs_evt2irq(0x3200 + ((n - 16) << 5))
2772
2773static struct pinmux_irq pinmux_irqs[] = {
2774 PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0),
2775 PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0),
2776 PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0),
2777 PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0),
2778 PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0),
2779 PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0),
2780 PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0),
2781 PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0),
2782 PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0),
2783 PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0),
2784 PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0),
2785 PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0),
2786 PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0),
2787 PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0),
2788 PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0),
2789 PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0),
2790 PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0),
2791 PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0),
2792 PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0),
2793 PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0),
2794 PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0),
2795 PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0),
2796 PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0),
2797 PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0),
2798 PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0),
2799 PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0),
2800 PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0),
2801 PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0),
2802 PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0),
2803 PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0),
2804 PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0),
2805 PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0),
2806};
2807
2721static struct pinmux_info sh73a0_pinmux_info = { 2808static struct pinmux_info sh73a0_pinmux_info = {
2722 .name = "sh73a0_pfc", 2809 .name = "sh73a0_pfc",
2723 .reserved_id = PINMUX_RESERVED, 2810 .reserved_id = PINMUX_RESERVED,
@@ -2738,6 +2825,9 @@ static struct pinmux_info sh73a0_pinmux_info = {
2738 2825
2739 .gpio_data = pinmux_data, 2826 .gpio_data = pinmux_data,
2740 .gpio_data_size = ARRAY_SIZE(pinmux_data), 2827 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2828
2829 .gpio_irq = pinmux_irqs,
2830 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2741}; 2831};
2742 2832
2743void sh73a0_pinmux_init(void) 2833void sh73a0_pinmux_init(void)
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index e4e485fa2532..c49a833bf9bb 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -21,9 +21,11 @@
21#include <asm/mach-types.h> 21#include <asm/mach-types.h>
22#include <mach/common.h> 22#include <mach/common.h>
23 23
24#define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2())
25
24static unsigned int __init shmobile_smp_get_core_count(void) 26static unsigned int __init shmobile_smp_get_core_count(void)
25{ 27{
26 if (machine_is_ag5evm()) 28 if (is_sh73a0())
27 return sh73a0_get_core_count(); 29 return sh73a0_get_core_count();
28 30
29 return 1; 31 return 1;
@@ -31,7 +33,7 @@ static unsigned int __init shmobile_smp_get_core_count(void)
31 33
32static void __init shmobile_smp_prepare_cpus(void) 34static void __init shmobile_smp_prepare_cpus(void)
33{ 35{
34 if (machine_is_ag5evm()) 36 if (is_sh73a0())
35 sh73a0_smp_prepare_cpus(); 37 sh73a0_smp_prepare_cpus();
36} 38}
37 39
@@ -39,13 +41,13 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
39{ 41{
40 trace_hardirqs_off(); 42 trace_hardirqs_off();
41 43
42 if (machine_is_ag5evm()) 44 if (is_sh73a0())
43 sh73a0_secondary_init(cpu); 45 sh73a0_secondary_init(cpu);
44} 46}
45 47
46int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) 48int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
47{ 49{
48 if (machine_is_ag5evm()) 50 if (is_sh73a0())
49 return sh73a0_boot_secondary(cpu); 51 return sh73a0_boot_secondary(cpu);
50 52
51 return -ENOSYS; 53 return -ENOSYS;
diff --git a/drivers/sh/intc/chip.c b/drivers/sh/intc/chip.c
index e0ada3773786..7b246efa94ea 100644
--- a/drivers/sh/intc/chip.c
+++ b/drivers/sh/intc/chip.c
@@ -186,7 +186,7 @@ static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
186 !defined(CONFIG_CPU_SUBTYPE_SH7709) 186 !defined(CONFIG_CPU_SUBTYPE_SH7709)
187 [IRQ_TYPE_LEVEL_HIGH] = VALID(3), 187 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
188#endif 188#endif
189#if defined(CONFIG_ARCH_SH7372) 189#if defined(CONFIG_ARM) /* all recent SH-Mobile / R-Mobile ARM support this */
190 [IRQ_TYPE_EDGE_BOTH] = VALID(4), 190 [IRQ_TYPE_EDGE_BOTH] = VALID(4),
191#endif 191#endif
192}; 192};
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-03 18:48:37 -0500