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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2014-09-04 03:44:18 -0400
committerDave Airlie <airlied@redhat.com>2014-09-14 21:37:43 -0400
commit0dd68309b9c516eac76549b71f68f01f57bb0c71 (patch)
tree66b958e685c72bb58004f344fd04c7406073d792
parent98faa78ce7f1f986e11e7805d31b409782a6d2d4 (diff)
drm/ast: Try to use MMIO registers when PIO isn't supported
If the PIO resources haven't been assigned, then we have no choice but try to use the MMIO version. This is the case for example on POWER8 which doesn't support PIO at all. Chips rev 0x20 or later have MMIO decoding enabled by default. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Dave Airlie <airlied@redhat.com>
-rw-r--r--drivers/gpu/drm/ast/ast_drv.h5
-rw-r--r--drivers/gpu/drm/ast/ast_main.c20
2 files changed, 21 insertions, 4 deletions
diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
index cb91c2acc3cb..a24cad4d1322 100644
--- a/drivers/gpu/drm/ast/ast_drv.h
+++ b/drivers/gpu/drm/ast/ast_drv.h
@@ -125,8 +125,9 @@ struct ast_gem_object;
125 125
126#define AST_IO_AR_PORT_WRITE (0x40) 126#define AST_IO_AR_PORT_WRITE (0x40)
127#define AST_IO_MISC_PORT_WRITE (0x42) 127#define AST_IO_MISC_PORT_WRITE (0x42)
128#define AST_IO_VGA_ENABLE_PORT (0x43)
128#define AST_IO_SEQ_PORT (0x44) 129#define AST_IO_SEQ_PORT (0x44)
129#define AST_DAC_INDEX_READ (0x3c7) 130#define AST_IO_DAC_INDEX_READ (0x47)
130#define AST_IO_DAC_INDEX_WRITE (0x48) 131#define AST_IO_DAC_INDEX_WRITE (0x48)
131#define AST_IO_DAC_DATA (0x49) 132#define AST_IO_DAC_DATA (0x49)
132#define AST_IO_GR_PORT (0x4E) 133#define AST_IO_GR_PORT (0x4E)
@@ -134,6 +135,8 @@ struct ast_gem_object;
134#define AST_IO_INPUT_STATUS1_READ (0x5A) 135#define AST_IO_INPUT_STATUS1_READ (0x5A)
135#define AST_IO_MISC_PORT_READ (0x4C) 136#define AST_IO_MISC_PORT_READ (0x4C)
136 137
138#define AST_IO_MM_OFFSET (0x380)
139
137#define __ast_read(x) \ 140#define __ast_read(x) \
138static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \ 141static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
139u##x val = 0;\ 142u##x val = 0;\
diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index a2cc6be97983..c2ff7933a90e 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -359,10 +359,24 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
359 ret = -EIO; 359 ret = -EIO;
360 goto out_free; 360 goto out_free;
361 } 361 }
362 ast->ioregs = pci_iomap(dev->pdev, 2, 0); 362
363 /*
364 * If we don't have IO space at all, use MMIO now and
365 * assume the chip has MMIO enabled by default (rev 0x20
366 * and higher).
367 */
368 if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) {
369 DRM_INFO("platform has no IO space, trying MMIO\n");
370 ast->ioregs = ast->regs + AST_IO_MM_OFFSET;
371 }
372
373 /* "map" IO regs if the above hasn't done so already */
363 if (!ast->ioregs) { 374 if (!ast->ioregs) {
364 ret = -EIO; 375 ast->ioregs = pci_iomap(dev->pdev, 2, 0);
365 goto out_free; 376 if (!ast->ioregs) {
377 ret = -EIO;
378 goto out_free;
379 }
366 } 380 }
367 381
368 ast_detect_chip(dev); 382 ast_detect_chip(dev);