Pull altix-mmr into release branch

6 files changed, 80 insertions, 65 deletions

diff --git a/arch/ia64/sn/pci/pcibr/pcibr_reg.c b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
index 21426d02fbe6..4f718c3e93d3 100644
--- a/arch/ia64/sn/pci/pcibr/pcibr_reg.c
+++ b/arch/ia64/sn/pci/pcibr/pcibr_reg.c
@@ -8,6 +8,7 @@
 
 #include <linux/interrupt.h>
 #include <linux/types.h>
+#include <asm/sn/io.h>
 #include <asm/sn/pcibr_provider.h>
 #include <asm/sn/pcibus_provider_defs.h>
 #include <asm/sn/pcidev.h>
@@ -29,10 +30,10 @@ void pcireg_control_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
                 case PCIBR_BRIDGETYPE_TIOCP:
-                        ptr->tio.cp_control &= ~bits;
+                        __sn_clrq_relaxed(&ptr->tio.cp_control, bits);
                         break;
                 case PCIBR_BRIDGETYPE_PIC:
-                        ptr->pic.p_wid_control &= ~bits;
+                        __sn_clrq_relaxed(&ptr->pic.p_wid_control, bits);
                         break;
                 default:
                         panic
@@ -49,10 +50,10 @@ void pcireg_control_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
                 case PCIBR_BRIDGETYPE_TIOCP:
-                        ptr->tio.cp_control |= bits;
+                        __sn_setq_relaxed(&ptr->tio.cp_control, bits);
                         break;
                 case PCIBR_BRIDGETYPE_PIC:
-                        ptr->pic.p_wid_control |= bits;
+                        __sn_setq_relaxed(&ptr->pic.p_wid_control, bits);
                         break;
                 default:
                         panic
@@ -73,10 +74,10 @@ uint64_t pcireg_tflush_get(struct pcibus_info *pcibus_info)
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
                 case PCIBR_BRIDGETYPE_TIOCP:
-                        ret = ptr->tio.cp_tflush;
+                        ret = __sn_readq_relaxed(&ptr->tio.cp_tflush);
                         break;
                 case PCIBR_BRIDGETYPE_PIC:
-                        ret = ptr->pic.p_wid_tflush;
+                        ret = __sn_readq_relaxed(&ptr->pic.p_wid_tflush);
                         break;
                 default:
                         panic
@@ -103,10 +104,10 @@ uint64_t pcireg_intr_status_get(struct pcibus_info * pcibus_info)
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
                 case PCIBR_BRIDGETYPE_TIOCP:
-                        ret = ptr->tio.cp_int_status;
+                        ret = __sn_readq_relaxed(&ptr->tio.cp_int_status);
                         break;
                 case PCIBR_BRIDGETYPE_PIC:
-                        ret = ptr->pic.p_int_status;
+                        ret = __sn_readq_relaxed(&ptr->pic.p_int_status);
                         break;
                 default:
                         panic
@@ -127,10 +128,10 @@ void pcireg_intr_enable_bit_clr(struct pcibus_info *pcibus_info, uint64_t bits)
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
                 case PCIBR_BRIDGETYPE_TIOCP:
-                        ptr->tio.cp_int_enable &= ~bits;
+                        __sn_clrq_relaxed(&ptr->tio.cp_int_enable, bits);
                         break;
                 case PCIBR_BRIDGETYPE_PIC:
-                        ptr->pic.p_int_enable &= ~bits;
+                        __sn_clrq_relaxed(&ptr->pic.p_int_enable, ~bits);
                         break;
                 default:
                         panic
@@ -147,10 +148,10 @@ void pcireg_intr_enable_bit_set(struct pcibus_info *pcibus_info, uint64_t bits)
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
                 case PCIBR_BRIDGETYPE_TIOCP:
-                        ptr->tio.cp_int_enable |= bits;
+                        __sn_setq_relaxed(&ptr->tio.cp_int_enable, bits);
                         break;
                 case PCIBR_BRIDGETYPE_PIC:
-                        ptr->pic.p_int_enable |= bits;
+                        __sn_setq_relaxed(&ptr->pic.p_int_enable, bits);
                         break;
                 default:
                         panic
@@ -171,14 +172,16 @@ void pcireg_intr_addr_addr_set(struct pcibus_info *pcibus_info, int int_n,
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
                 case PCIBR_BRIDGETYPE_TIOCP:
-                        ptr->tio.cp_int_addr[int_n] &= ~TIOCP_HOST_INTR_ADDR;
-                        ptr->tio.cp_int_addr[int_n] |=
-                            (addr & TIOCP_HOST_INTR_ADDR);
+                        __sn_clrq_relaxed(&ptr->tio.cp_int_addr[int_n],
+                            TIOCP_HOST_INTR_ADDR);
+                        __sn_setq_relaxed(&ptr->tio.cp_int_addr[int_n],
+                            (addr & TIOCP_HOST_INTR_ADDR));
                         break;
                 case PCIBR_BRIDGETYPE_PIC:
-                        ptr->pic.p_int_addr[int_n] &= ~PIC_HOST_INTR_ADDR;
-                        ptr->pic.p_int_addr[int_n] |=
-                            (addr & PIC_HOST_INTR_ADDR);
+                        __sn_clrq_relaxed(&ptr->pic.p_int_addr[int_n],
+                            PIC_HOST_INTR_ADDR);
+                        __sn_setq_relaxed(&ptr->pic.p_int_addr[int_n],
+                            (addr & PIC_HOST_INTR_ADDR));
                         break;
                 default:
                         panic
@@ -198,10 +201,10 @@ void pcireg_force_intr_set(struct pcibus_info *pcibus_info, int int_n)
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
                 case PCIBR_BRIDGETYPE_TIOCP:
-                        ptr->tio.cp_force_pin[int_n] = 1;
+                        writeq(1, &ptr->tio.cp_force_pin[int_n]);
                         break;
                 case PCIBR_BRIDGETYPE_PIC:
-                        ptr->pic.p_force_pin[int_n] = 1;
+                        writeq(1, &ptr->pic.p_force_pin[int_n]);
                         break;
                 default:
                         panic
@@ -222,10 +225,12 @@ uint64_t pcireg_wrb_flush_get(struct pcibus_info *pcibus_info, int device)
         if (pcibus_info) {
                 switch (pcibus_info->pbi_bridge_type) {
                 case PCIBR_BRIDGETYPE_TIOCP:
-                        ret = ptr->tio.cp_wr_req_buf[device];
+                        ret =
+                            __sn_readq_relaxed(&ptr->tio.cp_wr_req_buf[device]);
                         break;
                 case PCIBR_BRIDGETYPE_PIC:
-                        ret = ptr->pic.p_wr_req_buf[device];
+                        ret =
+                            __sn_readq_relaxed(&ptr->pic.p_wr_req_buf[device]);
                         break;
                 default:
                       panic("pcireg_wrb_flush_get: unknown bridgetype bridge 0x%p", (void *)ptr);
@@ -244,10 +249,10 @@ void pcireg_int_ate_set(struct pcibus_info *pcibus_info, int ate_index,
         if (pcibus_info) {