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authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-15 20:07:25 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-15 20:07:25 -0400
commit0c48ca8512ec099059fc532de57dbc6ffbccfb86 (patch)
tree5069ee9f240f4897c21e11f9f88b0d5c78bed2a6
parent72c79bdbda396b7f67e97b2a89410ac91d814c1b (diff)
parentbb2551da10b659eab27330483828b88e898e7952 (diff)
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm exynos/intel updates from Dave Airlie: "Two minor updates from Jesse for Intel SNB fixes, and a few fixes from Samsung for exynos. The pull req has Alan's commit in it since Intel based their tree on my tree at that time, but it all seems fine wrt merging." * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm exynos: use drm_fb_helper_set_par directly drm/exynos: Fix fb_videomode <-> drm_mode_modeinfo conversion drm/exynos: fix runtime_pm fimd device state on probe drm/exynos: use correct 'exynos-drm' name for platform device drm/i915: support 32 bit BGR formats in sprite planes drm/i915: fix color order for BGR formats on SNB drm/gma500: Fix Cedarview boot failures in 3.3-rc
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_connector.c16
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_drv.c2
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fbdev.c28
-rw-r--r--drivers/gpu/drm/exynos/exynos_drm_fimd.c17
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h2
-rw-r--r--drivers/gpu/drm/i915/intel_display.c1
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c6
7 files changed, 21 insertions, 51 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_drm_connector.c b/drivers/gpu/drm/exynos/exynos_drm_connector.c
index 618bd4d87d28..99d5527b2ca6 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_connector.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_connector.c
@@ -54,14 +54,14 @@ convert_to_display_mode(struct drm_display_mode *mode,
54 mode->vrefresh = timing->refresh; 54 mode->vrefresh = timing->refresh;
55 55
56 mode->hdisplay = timing->xres; 56 mode->hdisplay = timing->xres;
57 mode->hsync_start = mode->hdisplay + timing->left_margin; 57 mode->hsync_start = mode->hdisplay + timing->right_margin;
58 mode->hsync_end = mode->hsync_start + timing->hsync_len; 58 mode->hsync_end = mode->hsync_start + timing->hsync_len;
59 mode->htotal = mode->hsync_end + timing->right_margin; 59 mode->htotal = mode->hsync_end + timing->left_margin;
60 60
61 mode->vdisplay = timing->yres; 61 mode->vdisplay = timing->yres;
62 mode->vsync_start = mode->vdisplay + timing->upper_margin; 62 mode->vsync_start = mode->vdisplay + timing->lower_margin;
63 mode->vsync_end = mode->vsync_start + timing->vsync_len; 63 mode->vsync_end = mode->vsync_start + timing->vsync_len;
64 mode->vtotal = mode->vsync_end + timing->lower_margin; 64 mode->vtotal = mode->vsync_end + timing->upper_margin;
65 mode->width_mm = panel->width_mm; 65 mode->width_mm = panel->width_mm;
66 mode->height_mm = panel->height_mm; 66 mode->height_mm = panel->height_mm;
67 67
@@ -85,14 +85,14 @@ convert_to_video_timing(struct fb_videomode *timing,
85 timing->refresh = drm_mode_vrefresh(mode); 85 timing->refresh = drm_mode_vrefresh(mode);
86 86
87 timing->xres = mode->hdisplay; 87 timing->xres = mode->hdisplay;
88 timing->left_margin = mode->hsync_start - mode->hdisplay; 88 timing->right_margin = mode->hsync_start - mode->hdisplay;
89 timing->hsync_len = mode->hsync_end - mode->hsync_start; 89 timing->hsync_len = mode->hsync_end - mode->hsync_start;
90 timing->right_margin = mode->htotal - mode->hsync_end; 90 timing->left_margin = mode->htotal - mode->hsync_end;
91 91
92 timing->yres = mode->vdisplay; 92 timing->yres = mode->vdisplay;
93 timing->upper_margin = mode->vsync_start - mode->vdisplay; 93 timing->lower_margin = mode->vsync_start - mode->vdisplay;
94 timing->vsync_len = mode->vsync_end - mode->vsync_start; 94 timing->vsync_len = mode->vsync_end - mode->vsync_start;
95 timing->lower_margin = mode->vtotal - mode->vsync_end; 95 timing->upper_margin = mode->vtotal - mode->vsync_end;
96 96
97 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 97 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
98 timing->vmode = FB_VMODE_INTERLACED; 98 timing->vmode = FB_VMODE_INTERLACED;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c
index 58820ebd3558..09cc13f791b3 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_drv.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c
@@ -246,7 +246,7 @@ static struct platform_driver exynos_drm_platform_driver = {
246 .remove = __devexit_p(exynos_drm_platform_remove), 246 .remove = __devexit_p(exynos_drm_platform_remove),
247 .driver = { 247 .driver = {
248 .owner = THIS_MODULE, 248 .owner = THIS_MODULE,
249 .name = DRIVER_NAME, 249 .name = "exynos-drm",
250 }, 250 },
251}; 251};
252 252
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index 3508700e529b..54f8f074822f 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -46,39 +46,13 @@ struct exynos_drm_fbdev {
46 struct exynos_drm_gem_obj *exynos_gem_obj; 46 struct exynos_drm_gem_obj *exynos_gem_obj;
47}; 47};
48 48
49static int exynos_drm_fbdev_set_par(struct fb_info *info)
50{
51 struct fb_var_screeninfo *var = &info->var;
52
53 switch (var->bits_per_pixel) {
54 case 32:
55 case 24:
56 case 18:
57 case 16:
58 case 12:
59 info->fix.visual = FB_VISUAL_TRUECOLOR;
60 break;
61 case 1:
62 info->fix.visual = FB_VISUAL_MONO01;
63 break;
64 default:
65 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
66 break;
67 }
68
69 info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
70
71 return drm_fb_helper_set_par(info);
72}
73
74
75static struct fb_ops exynos_drm_fb_ops = { 49static struct fb_ops exynos_drm_fb_ops = {
76 .owner = THIS_MODULE, 50 .owner = THIS_MODULE,
77 .fb_fillrect = cfb_fillrect, 51 .fb_fillrect = cfb_fillrect,
78 .fb_copyarea = cfb_copyarea, 52 .fb_copyarea = cfb_copyarea,
79 .fb_imageblit = cfb_imageblit, 53 .fb_imageblit = cfb_imageblit,
80 .fb_check_var = drm_fb_helper_check_var, 54 .fb_check_var = drm_fb_helper_check_var,
81 .fb_set_par = exynos_drm_fbdev_set_par, 55 .fb_set_par = drm_fb_helper_set_par,
82 .fb_blank = drm_fb_helper_blank, 56 .fb_blank = drm_fb_helper_blank,
83 .fb_pan_display = drm_fb_helper_pan_display, 57 .fb_pan_display = drm_fb_helper_pan_display,
84 .fb_setcmap = drm_fb_helper_setcmap, 58 .fb_setcmap = drm_fb_helper_setcmap,
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 360adf2bba04..56458eea0501 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -817,8 +817,6 @@ static int __devinit fimd_probe(struct platform_device *pdev)
817 goto err_clk_get; 817 goto err_clk_get;
818 } 818 }
819 819
820 clk_enable(ctx->bus_clk);
821
822 ctx->lcd_clk = clk_get(dev, "sclk_fimd"); 820 ctx->lcd_clk = clk_get(dev, "sclk_fimd");
823 if (IS_ERR(ctx->lcd_clk)) { 821 if (IS_ERR(ctx->lcd_clk)) {
824 dev_err(dev, "failed to get lcd clock\n"); 822 dev_err(dev, "failed to get lcd clock\n");
@@ -826,8 +824,6 @@ static int __devinit fimd_probe(struct platform_device *pdev)
826 goto err_bus_clk; 824 goto err_bus_clk;
827 } 825 }
828 826
829 clk_enable(ctx->lcd_clk);
830
831 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 827 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
832 if (!res) { 828 if (!res) {
833 dev_err(dev, "failed to find registers\n"); 829 dev_err(dev, "failed to find registers\n");
@@ -864,17 +860,11 @@ static int __devinit fimd_probe(struct platform_device *pdev)
864 goto err_req_irq; 860 goto err_req_irq;
865 } 861 }
866 862
867 ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
868 ctx->vidcon0 = pdata->vidcon0; 863 ctx->vidcon0 = pdata->vidcon0;
869 ctx->vidcon1 = pdata->vidcon1; 864 ctx->vidcon1 = pdata->vidcon1;
870 ctx->default_win = pdata->default_win; 865 ctx->default_win = pdata->default_win;
871 ctx->panel = panel; 866 ctx->panel = panel;
872 867
873 panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
874
875 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
876 panel->timing.pixclock, ctx->clkdiv);
877
878 subdrv = &ctx->subdrv; 868 subdrv = &ctx->subdrv;
879 869
880 subdrv->probe = fimd_subdrv_probe; 870 subdrv->probe = fimd_subdrv_probe;
@@ -889,10 +879,15 @@ static int __devinit fimd_probe(struct platform_device *pdev)
889 879
890 platform_set_drvdata(pdev, ctx); 880 platform_set_drvdata(pdev, ctx);
891 881
892 pm_runtime_set_active(dev);
893 pm_runtime_enable(dev); 882 pm_runtime_enable(dev);
894 pm_runtime_get_sync(dev); 883 pm_runtime_get_sync(dev);
895 884
885 ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
886 panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
887
888 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
889 panel->timing.pixclock, ctx->clkdiv);
890
896 for (win = 0; win < WINDOWS_NR; win++) 891 for (win = 0; win < WINDOWS_NR; win++)
897 fimd_clear_win(ctx, win); 892 fimd_clear_win(ctx, win);
898 893
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 03c53fcf8653..558ac716a328 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2689,7 +2689,7 @@
2689#define DVS_FORMAT_RGBX888 (2<<25) 2689#define DVS_FORMAT_RGBX888 (2<<25)
2690#define DVS_FORMAT_RGBX161616 (3<<25) 2690#define DVS_FORMAT_RGBX161616 (3<<25)
2691#define DVS_SOURCE_KEY (1<<22) 2691#define DVS_SOURCE_KEY (1<<22)
2692#define DVS_RGB_ORDER_RGBX (1<<20) 2692#define DVS_RGB_ORDER_XBGR (1<<20)
2693#define DVS_YUV_BYTE_ORDER_MASK (3<<16) 2693#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
2694#define DVS_YUV_ORDER_YUYV (0<<16) 2694#define DVS_YUV_ORDER_YUYV (0<<16)
2695#define DVS_YUV_ORDER_UYVY (1<<16) 2695#define DVS_YUV_ORDER_UYVY (1<<16)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f851db7be2cc..397087cf689e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7828,6 +7828,7 @@ int intel_framebuffer_init(struct drm_device *dev,
7828 case DRM_FORMAT_RGB332: 7828 case DRM_FORMAT_RGB332:
7829 case DRM_FORMAT_RGB565: 7829 case DRM_FORMAT_RGB565:
7830 case DRM_FORMAT_XRGB8888: 7830 case DRM_FORMAT_XRGB8888:
7831 case DRM_FORMAT_XBGR8888:
7831 case DRM_FORMAT_ARGB8888: 7832 case DRM_FORMAT_ARGB8888:
7832 case DRM_FORMAT_XRGB2101010: 7833 case DRM_FORMAT_XRGB2101010:
7833 case DRM_FORMAT_ARGB2101010: 7834 case DRM_FORMAT_ARGB2101010:
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 2288abf88cce..a0835040c86b 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -225,16 +225,16 @@ snb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
225 225
226 /* Mask out pixel format bits in case we change it */ 226 /* Mask out pixel format bits in case we change it */
227 dvscntr &= ~DVS_PIXFORMAT_MASK; 227 dvscntr &= ~DVS_PIXFORMAT_MASK;
228 dvscntr &= ~DVS_RGB_ORDER_RGBX; 228 dvscntr &= ~DVS_RGB_ORDER_XBGR;
229 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK; 229 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
230 230
231 switch (fb->pixel_format) { 231 switch (fb->pixel_format) {
232 case DRM_FORMAT_XBGR8888: 232 case DRM_FORMAT_XBGR8888:
233 dvscntr |= DVS_FORMAT_RGBX888; 233 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
234 pixel_size = 4; 234 pixel_size = 4;
235 break; 235 break;
236 case DRM_FORMAT_XRGB8888: 236 case DRM_FORMAT_XRGB8888:
237 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_RGBX; 237 dvscntr |= DVS_FORMAT_RGBX888;
238 pixel_size = 4; 238 pixel_size = 4;
239 break; 239 break;
240 case DRM_FORMAT_YUYV: 240 case DRM_FORMAT_YUYV: