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authorRafał Miłecki <zajec5@gmail.com>2013-04-12 11:58:13 -0400
committerRafał Miłecki <zajec5@gmail.com>2013-04-23 06:27:58 -0400
commit0c201cfbfd47c40ee0cedbcd96e4fbaa85c5fc50 (patch)
tree2a6df5d18a0d4ebe92b07ab982fe8697fe9c1388
parent31bfffbae102591f347c02a9545a7362f57a21ea (diff)
b43: N-PHY: don't use deprecated b43_radio_foo16
All radio ops are 16b (there is only 1 exception for reg 0x1), so we deprecated b43_radio_read16 and b43_radio_write16 long time ago. Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
-rw-r--r--drivers/net/wireless/b43/phy_n.c118
1 files changed, 59 insertions, 59 deletions
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index 22316d570271..868260794735 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -1372,7 +1372,7 @@ static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code,
1372 val = 0x11; 1372 val = 0x11;
1373 reg = (i == 0) ? 0x2000 : 0x3000; 1373 reg = (i == 0) ? 0x2000 : 0x3000;
1374 reg |= B2055_PADDRV; 1374 reg |= B2055_PADDRV;
1375 b43_radio_write16(dev, reg, val); 1375 b43_radio_write(dev, reg, val);
1376 1376
1377 reg = (i == 0) ? 1377 reg = (i == 0) ?
1378 B43_NPHY_AFECTL_OVER1 : 1378 B43_NPHY_AFECTL_OVER1 :
@@ -1822,21 +1822,21 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
1822 override = 0x110; 1822 override = 0x110;
1823 1823
1824 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1); 1824 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1825 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX); 1825 regs_save_radio[0] = b43_radio_read(dev, B2055_C1_PD_RXTX);
1826 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override); 1826 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1827 b43_radio_write16(dev, B2055_C1_PD_RXTX, val); 1827 b43_radio_write(dev, B2055_C1_PD_RXTX, val);
1828 1828
1829 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2); 1829 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1830 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX); 1830 regs_save_radio[1] = b43_radio_read(dev, B2055_C2_PD_RXTX);
1831 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override); 1831 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1832 b43_radio_write16(dev, B2055_C2_PD_RXTX, val); 1832 b43_radio_write(dev, B2055_C2_PD_RXTX, val);
1833 1833
1834 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07; 1834 state[0] = b43_radio_read(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1835 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07; 1835 state[1] = b43_radio_read(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1836 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8); 1836 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1837 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8); 1837 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1838 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07; 1838 state[2] = b43_radio_read(dev, B2055_C1_SP_RSSI) & 0x07;
1839 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07; 1839 state[3] = b43_radio_read(dev, B2055_C2_SP_RSSI) & 0x07;
1840 1840
1841 b43_nphy_rssi_select(dev, 5, type); 1841 b43_nphy_rssi_select(dev, 5, type);
1842 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type); 1842 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, N_RAIL_I, type);
@@ -1932,9 +1932,9 @@ static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, enum n_rssi_type type)
1932 b43_nphy_rssi_select(dev, 0, type); 1932 b43_nphy_rssi_select(dev, 0, type);
1933 1933
1934 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]); 1934 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1935 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]); 1935 b43_radio_write(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1936 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]); 1936 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1937 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]); 1937 b43_radio_write(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1938 1938
1939 b43_nphy_classifier(dev, 7, class); 1939 b43_nphy_classifier(dev, 7, class);
1940 b43_nphy_write_clip_detection(dev, clip_state); 1940 b43_nphy_write_clip_detection(dev, clip_state);
@@ -3941,75 +3941,75 @@ static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
3941 tmp = (i == 0) ? 0x2000 : 0x3000; 3941 tmp = (i == 0) ? 0x2000 : 0x3000;
3942 offset = i * 11; 3942 offset = i * 11;
3943 3943
3944 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL); 3944 save[offset + 0] = b43_radio_read(dev, B2055_CAL_RVARCTL);
3945 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL); 3945 save[offset + 1] = b43_radio_read(dev, B2055_CAL_LPOCTL);
3946 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS); 3946 save[offset + 2] = b43_radio_read(dev, B2055_CAL_TS);
3947 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS); 3947 save[offset + 3] = b43_radio_read(dev, B2055_CAL_RCCALRTS);
3948 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS); 3948 save[offset + 4] = b43_radio_read(dev, B2055_CAL_RCALRTS);
3949 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV); 3949 save[offset + 5] = b43_radio_read(dev, B2055_PADDRV);
3950 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1); 3950 save[offset + 6] = b43_radio_read(dev, B2055_XOCTL1);
3951 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2); 3951 save[offset + 7] = b43_radio_read(dev, B2055_XOCTL2);
3952 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL); 3952 save[offset + 8] = b43_radio_read(dev, B2055_XOREGUL);
3953 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC); 3953 save[offset + 9] = b43_radio_read(dev, B2055_XOMISC);
3954 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1); 3954 save[offset + 10] = b43_radio_read(dev, B2055_PLL_LFC1);
3955 3955
3956 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) { 3956 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
3957 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A); 3957 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
3958 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 3958 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3959 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 3959 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
3960 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 3960 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
3961 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 3961 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
3962 if (nphy->ipa5g_on) { 3962 if (nphy->ipa5g_on) {
3963 b43_radio_write16(dev, tmp | B2055_PADDRV, 4); 3963 b43_radio_write(dev, tmp | B2055_PADDRV, 4);
3964 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1); 3964 b43_radio_write(dev, tmp | B2055_XOCTL1, 1);
3965 } else { 3965 } else {
3966 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 3966 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
3967 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F); 3967 b43_radio_write(dev, tmp | B2055_XOCTL1, 0x2F);
3968 } 3968 }
3969 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 3969 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
3970 } else { 3970 } else {
3971 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06); 3971 b43_radio_write(dev, tmp | B2055_CAL_RVARCTL, 0x06);
3972 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40); 3972 b43_radio_write(dev, tmp | B2055_CAL_LPOCTL, 0x40);
3973 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55); 3973 b43_radio_write(dev, tmp | B2055_CAL_TS, 0x55);
3974 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0); 3974 b43_radio_write(dev, tmp | B2055_CAL_RCCALRTS, 0);
3975 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0); 3975 b43_radio_write(dev, tmp | B2055_CAL_RCALRTS, 0);
3976 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0); 3976 b43_radio_write(dev, tmp | B2055_XOCTL1, 0);
3977 if (nphy->ipa2g_on) { 3977 if (nphy->ipa2g_on) {
3978 b43_radio_write16(dev, tmp | B2055_PADDRV, 6); 3978 b43_radio_write(dev, tmp | B2055_PADDRV, 6);
3979 b43_radio_write16(dev, tmp | B2055_XOCTL2, 3979 b43_radio_write(dev, tmp | B2055_XOCTL2,
3980 (dev->phy.rev < 5) ? 0x11 : 0x01); 3980 (dev->phy.rev < 5) ? 0x11 : 0x01);
3981 } else { 3981 } else {
3982 b43_radio_write16(dev, tmp | B2055_PADDRV, 0); 3982 b43_radio_write(dev, tmp | B2055_PADDRV, 0);
3983 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0); 3983 b43_radio_write(dev, tmp | B2055_XOCTL2, 0);
3984 } 3984 }
3985 } 3985 }
3986 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0); 3986 b43_radio_write(dev, tmp | B2055_XOREGUL, 0);
3987 b43_radio_write16(dev, tmp | B2055_XOMISC, 0); 3987 b43_radio_write(dev, tmp | B2055_XOMISC, 0);
3988 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0); 3988 b43_radio_write(dev, tmp | B2055_PLL_LFC1, 0);
3989 } 3989 }
3990 } else { 3990 } else {
3991 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1); 3991 save[0] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL1);
3992 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29); 3992 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
3993 3993
3994 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2); 3994 save[1] = b43_radio_read(dev, B2055_C1_TX_RF_IQCAL2);
3995 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54); 3995 b43_radio_write(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
3996 3996
3997 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1); 3997 save[2] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL1);
3998 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29); 3998 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
3999 3999
4000 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2); 4000 save[3] = b43_radio_read(dev, B2055_C2_TX_RF_IQCAL2);
4001 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54); 4001 b43_radio_write(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
4002 4002
4003 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX); 4003 save[3] = b43_radio_read(dev, B2055_C1_PWRDET_RXTX);
4004 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX); 4004 save[4] = b43_radio_read(dev, B2055_C2_PWRDET_RXTX);
4005 4005
4006 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) & 4006 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
4007 B43_NPHY_BANDCTL_5GHZ)) { 4007 B43_NPHY_BANDCTL_5GHZ)) {
4008 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04); 4008 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x04);
4009 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04); 4009 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x04);
4010 } else { 4010 } else {
4011 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20); 4011 b43_radio_write(dev, B2055_C1_PWRDET_RXTX, 0x20);
4012 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20); 4012 b43_radio_write(dev, B2055_C2_PWRDET_RXTX, 0x20);
4013 } 4013 }
4014 4014
4015 if (dev->phy.rev < 2) { 4015 if (dev->phy.rev < 2) {