diff options
author | Stanislaw Gruszka <sgruszka@redhat.com> | 2011-08-24 11:37:16 -0400 |
---|---|---|
committer | Stanislaw Gruszka <sgruszka@redhat.com> | 2011-11-15 05:22:56 -0500 |
commit | 0c1a94e299eed7ea11ebc407d1e08a26c594abe5 (patch) | |
tree | f70b464dda43fc2604bd1399348da07d191b0169 | |
parent | 1c8cae575b14ffad6af9c80927a08aa783f0ed78 (diff) |
iwlegacy: rename i/o direct methods
Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com>
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-3945.c | 30 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-4965-lib.c | 18 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-4965-tx.c | 10 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-4965-ucode.c | 4 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-csr.h | 4 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-io.h | 11 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-rx.c | 4 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl-tx.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl3945-base.c | 6 | ||||
-rw-r--r-- | drivers/net/wireless/iwlegacy/iwl4965-base.c | 16 |
10 files changed, 52 insertions, 53 deletions
diff --git a/drivers/net/wireless/iwlegacy/iwl-3945.c b/drivers/net/wireless/iwlegacy/iwl-3945.c index 8c3ae39b0738..fc8ddb68c7c4 100644 --- a/drivers/net/wireless/iwlegacy/iwl-3945.c +++ b/drivers/net/wireless/iwlegacy/iwl-3945.c | |||
@@ -773,11 +773,11 @@ static void il3945_set_pwr_vmain(struct il_priv *il) | |||
773 | 773 | ||
774 | static int il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq) | 774 | static int il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq) |
775 | { | 775 | { |
776 | il_write_direct32(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma); | 776 | il_wr(il, FH39_RCSR_RBD_BASE(0), rxq->bd_dma); |
777 | il_write_direct32(il, FH39_RCSR_RPTR_ADDR(0), | 777 | il_wr(il, FH39_RCSR_RPTR_ADDR(0), |
778 | rxq->rb_stts_dma); | 778 | rxq->rb_stts_dma); |
779 | il_write_direct32(il, FH39_RCSR_WPTR(0), 0); | 779 | il_wr(il, FH39_RCSR_WPTR(0), 0); |
780 | il_write_direct32(il, FH39_RCSR_CONFIG(0), | 780 | il_wr(il, FH39_RCSR_CONFIG(0), |
781 | FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | | 781 | FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | |
782 | FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | | 782 | FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | |
783 | FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | | 783 | FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | |
@@ -788,7 +788,7 @@ static int il3945_rx_init(struct il_priv *il, struct il_rx_queue *rxq) | |||
788 | FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); | 788 | FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); |
789 | 789 | ||
790 | /* fake read to flush all prev I/O */ | 790 | /* fake read to flush all prev I/O */ |
791 | il_read_direct32(il, FH39_RSSR_CTRL); | 791 | il_rd(il, FH39_RSSR_CTRL); |
792 | 792 | ||
793 | return 0; | 793 | return 0; |
794 | } | 794 | } |
@@ -810,10 +810,10 @@ static int il3945_tx_reset(struct il_priv *il) | |||
810 | il_write_prph(il, ALM_SCD_TXF4MF_REG, 0x000004); | 810 | il_write_prph(il, ALM_SCD_TXF4MF_REG, 0x000004); |
811 | il_write_prph(il, ALM_SCD_TXF5MF_REG, 0x000005); | 811 | il_write_prph(il, ALM_SCD_TXF5MF_REG, 0x000005); |
812 | 812 | ||
813 | il_write_direct32(il, FH39_TSSR_CBB_BASE, | 813 | il_wr(il, FH39_TSSR_CBB_BASE, |
814 | il->_3945.shared_phys); | 814 | il->_3945.shared_phys); |
815 | 815 | ||
816 | il_write_direct32(il, FH39_TSSR_MSG_CONFIG, | 816 | il_wr(il, FH39_TSSR_MSG_CONFIG, |
817 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | | 817 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | |
818 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | | 818 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | |
819 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | | 819 | FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | |
@@ -987,7 +987,7 @@ int il3945_hw_nic_init(struct il_priv *il) | |||
987 | il_rx_queue_update_write_ptr(il, rxq); | 987 | il_rx_queue_update_write_ptr(il, rxq); |
988 | */ | 988 | */ |
989 | 989 | ||
990 | il_write_direct32(il, FH39_RCSR_WPTR(0), rxq->write & ~7); | 990 | il_wr(il, FH39_RCSR_WPTR(0), rxq->write & ~7); |
991 | 991 | ||
992 | rc = il3945_txq_ctx_reset(il); | 992 | rc = il3945_txq_ctx_reset(il); |
993 | if (rc) | 993 | if (rc) |
@@ -1030,8 +1030,8 @@ void il3945_hw_txq_ctx_stop(struct il_priv *il) | |||
1030 | 1030 | ||
1031 | /* reset TFD queues */ | 1031 | /* reset TFD queues */ |
1032 | for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { | 1032 | for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { |
1033 | il_write_direct32(il, FH39_TCSR_CONFIG(txq_id), 0x0); | 1033 | il_wr(il, FH39_TCSR_CONFIG(txq_id), 0x0); |
1034 | il_poll_direct_bit(il, FH39_TSSR_TX_STATUS, | 1034 | il_poll_bit(il, FH39_TSSR_TX_STATUS, |
1035 | FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id), | 1035 | FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id), |
1036 | 1000); | 1036 | 1000); |
1037 | } | 1037 | } |
@@ -2183,8 +2183,8 @@ int il3945_hw_rxq_stop(struct il_priv *il) | |||
2183 | { | 2183 | { |
2184 | int rc; | 2184 | int rc; |
2185 | 2185 | ||
2186 | il_write_direct32(il, FH39_RCSR_CONFIG(0), 0); | 2186 | il_wr(il, FH39_RCSR_CONFIG(0), 0); |
2187 | rc = il_poll_direct_bit(il, FH39_RSSR_STATUS, | 2187 | rc = il_poll_bit(il, FH39_RSSR_STATUS, |
2188 | FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); | 2188 | FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); |
2189 | if (rc < 0) | 2189 | if (rc < 0) |
2190 | IL_ERR("Can't stop Rx DMA.\n"); | 2190 | IL_ERR("Can't stop Rx DMA.\n"); |
@@ -2200,10 +2200,10 @@ int il3945_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq) | |||
2200 | 2200 | ||
2201 | shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr); | 2201 | shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr); |
2202 | 2202 | ||
2203 | il_write_direct32(il, FH39_CBCC_CTRL(txq_id), 0); | 2203 | il_wr(il, FH39_CBCC_CTRL(txq_id), 0); |
2204 | il_write_direct32(il, FH39_CBCC_BASE(txq_id), 0); | 2204 | il_wr(il, FH39_CBCC_BASE(txq_id), 0); |
2205 | 2205 | ||
2206 | il_write_direct32(il, FH39_TCSR_CONFIG(txq_id), | 2206 | il_wr(il, FH39_TCSR_CONFIG(txq_id), |
2207 | FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | | 2207 | FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | |
2208 | FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | | 2208 | FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | |
2209 | FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | | 2209 | FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | |
diff --git a/drivers/net/wireless/iwlegacy/iwl-4965-lib.c b/drivers/net/wireless/iwlegacy/iwl-4965-lib.c index 6503b8faf08b..8fafd201717c 100644 --- a/drivers/net/wireless/iwlegacy/iwl-4965-lib.c +++ b/drivers/net/wireless/iwlegacy/iwl-4965-lib.c | |||
@@ -103,17 +103,17 @@ int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq) | |||
103 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; | 103 | rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; |
104 | 104 | ||
105 | /* Stop Rx DMA */ | 105 | /* Stop Rx DMA */ |
106 | il_write_direct32(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | 106 | il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
107 | 107 | ||
108 | /* Reset driver's Rx queue write index */ | 108 | /* Reset driver's Rx queue write index */ |
109 | il_write_direct32(il, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); | 109 | il_wr(il, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); |
110 | 110 | ||
111 | /* Tell device where to find RBD circular buffer in DRAM */ | 111 | /* Tell device where to find RBD circular buffer in DRAM */ |
112 | il_write_direct32(il, FH_RSCSR_CHNL0_RBDCB_BASE_REG, | 112 | il_wr(il, FH_RSCSR_CHNL0_RBDCB_BASE_REG, |
113 | (u32)(rxq->bd_dma >> 8)); | 113 | (u32)(rxq->bd_dma >> 8)); |
114 | 114 | ||
115 | /* Tell device where in DRAM to update its Rx status */ | 115 | /* Tell device where in DRAM to update its Rx status */ |
116 | il_write_direct32(il, FH_RSCSR_CHNL0_STTS_WPTR_REG, | 116 | il_wr(il, FH_RSCSR_CHNL0_STTS_WPTR_REG, |
117 | rxq->rb_stts_dma >> 4); | 117 | rxq->rb_stts_dma >> 4); |
118 | 118 | ||
119 | /* Enable Rx DMA | 119 | /* Enable Rx DMA |
@@ -122,7 +122,7 @@ int il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq) | |||
122 | * RB timeout 0x10 | 122 | * RB timeout 0x10 |
123 | * 256 RBDs | 123 | * 256 RBDs |
124 | */ | 124 | */ |
125 | il_write_direct32(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, | 125 | il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, |
126 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | | 126 | FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | |
127 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | | 127 | FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | |
128 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | | 128 | FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | |
@@ -403,8 +403,8 @@ int il4965_rxq_stop(struct il_priv *il) | |||
403 | { | 403 | { |
404 | 404 | ||
405 | /* stop Rx DMA */ | 405 | /* stop Rx DMA */ |
406 | il_write_direct32(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); | 406 | il_wr(il, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); |
407 | il_poll_direct_bit(il, FH_MEM_RSSR_RX_STATUS_REG, | 407 | il_poll_bit(il, FH_MEM_RSSR_RX_STATUS_REG, |
408 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); | 408 | FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); |
409 | 409 | ||
410 | return 0; | 410 | return 0; |
@@ -1179,7 +1179,7 @@ int il4965_dump_fh(struct il_priv *il, char **buf, bool display) | |||
1179 | pos += scnprintf(*buf + pos, bufsz - pos, | 1179 | pos += scnprintf(*buf + pos, bufsz - pos, |
1180 | " %34s: 0X%08x\n", | 1180 | " %34s: 0X%08x\n", |
1181 | il4965_get_fh_string(fh_tbl[i]), | 1181 | il4965_get_fh_string(fh_tbl[i]), |
1182 | il_read_direct32(il, fh_tbl[i])); | 1182 | il_rd(il, fh_tbl[i])); |
1183 | } | 1183 | } |
1184 | return pos; | 1184 | return pos; |
1185 | } | 1185 | } |
@@ -1188,7 +1188,7 @@ int il4965_dump_fh(struct il_priv *il, char **buf, bool display) | |||
1188 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { | 1188 | for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { |
1189 | IL_ERR(" %34s: 0X%08x\n", | 1189 | IL_ERR(" %34s: 0X%08x\n", |
1190 | il4965_get_fh_string(fh_tbl[i]), | 1190 | il4965_get_fh_string(fh_tbl[i]), |
1191 | il_read_direct32(il, fh_tbl[i])); | 1191 | il_rd(il, fh_tbl[i])); |
1192 | } | 1192 | } |
1193 | return 0; | 1193 | return 0; |
1194 | } | 1194 | } |
diff --git a/drivers/net/wireless/iwlegacy/iwl-4965-tx.c b/drivers/net/wireless/iwlegacy/iwl-4965-tx.c index 66dd172fed60..25c9b7192d9a 100644 --- a/drivers/net/wireless/iwlegacy/iwl-4965-tx.c +++ b/drivers/net/wireless/iwlegacy/iwl-4965-tx.c | |||
@@ -640,7 +640,7 @@ int il4965_txq_ctx_alloc(struct il_priv *il) | |||
640 | il4965_txq_set_sched(il, 0); | 640 | il4965_txq_set_sched(il, 0); |
641 | 641 | ||
642 | /* Tell NIC where to find the "keep warm" buffer */ | 642 | /* Tell NIC where to find the "keep warm" buffer */ |
643 | il_write_direct32(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4); | 643 | il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4); |
644 | 644 | ||
645 | spin_unlock_irqrestore(&il->lock, flags); | 645 | spin_unlock_irqrestore(&il->lock, flags); |
646 | 646 | ||
@@ -679,7 +679,7 @@ void il4965_txq_ctx_reset(struct il_priv *il) | |||
679 | il4965_txq_set_sched(il, 0); | 679 | il4965_txq_set_sched(il, 0); |
680 | 680 | ||
681 | /* Tell NIC where to find the "keep warm" buffer */ | 681 | /* Tell NIC where to find the "keep warm" buffer */ |
682 | il_write_direct32(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4); | 682 | il_wr(il, FH_KW_MEM_ADDR_REG, il->kw.dma >> 4); |
683 | 683 | ||
684 | spin_unlock_irqrestore(&il->lock, flags); | 684 | spin_unlock_irqrestore(&il->lock, flags); |
685 | 685 | ||
@@ -707,14 +707,14 @@ void il4965_txq_ctx_stop(struct il_priv *il) | |||
707 | 707 | ||
708 | /* Stop each Tx DMA channel, and wait for it to be idle */ | 708 | /* Stop each Tx DMA channel, and wait for it to be idle */ |
709 | for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) { | 709 | for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) { |
710 | il_write_direct32(il, | 710 | il_wr(il, |
711 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); | 711 | FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); |
712 | if (il_poll_direct_bit(il, FH_TSSR_TX_STATUS_REG, | 712 | if (il_poll_bit(il, FH_TSSR_TX_STATUS_REG, |
713 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), | 713 | FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), |
714 | 1000)) | 714 | 1000)) |
715 | IL_ERR("Failing on timeout while stopping" | 715 | IL_ERR("Failing on timeout while stopping" |
716 | " DMA channel %d [0x%08x]", ch, | 716 | " DMA channel %d [0x%08x]", ch, |
717 | il_read_direct32(il, | 717 | il_rd(il, |
718 | FH_TSSR_TX_STATUS_REG)); | 718 | FH_TSSR_TX_STATUS_REG)); |
719 | } | 719 | } |
720 | spin_unlock_irqrestore(&il->lock, flags); | 720 | spin_unlock_irqrestore(&il->lock, flags); |
diff --git a/drivers/net/wireless/iwlegacy/iwl-4965-ucode.c b/drivers/net/wireless/iwlegacy/iwl-4965-ucode.c index 4f0e6fe5be50..bb0b7f5cb5ee 100644 --- a/drivers/net/wireless/iwlegacy/iwl-4965-ucode.c +++ b/drivers/net/wireless/iwlegacy/iwl-4965-ucode.c | |||
@@ -61,7 +61,7 @@ il4965_verify_inst_sparse(struct il_priv *il, __le32 *image, u32 len) | |||
61 | /* read data comes through single port, auto-incr addr */ | 61 | /* read data comes through single port, auto-incr addr */ |
62 | /* NOTE: Use the debugless read so we don't flood kernel log | 62 | /* NOTE: Use the debugless read so we don't flood kernel log |
63 | * if IL_DL_IO is set */ | 63 | * if IL_DL_IO is set */ |
64 | il_write_direct32(il, HBUS_TARG_MEM_RADDR, | 64 | il_wr(il, HBUS_TARG_MEM_RADDR, |
65 | i + IWL4965_RTC_INST_LOWER_BOUND); | 65 | i + IWL4965_RTC_INST_LOWER_BOUND); |
66 | val = _il_rd(il, HBUS_TARG_MEM_RDAT); | 66 | val = _il_rd(il, HBUS_TARG_MEM_RDAT); |
67 | if (val != le32_to_cpu(*image)) { | 67 | if (val != le32_to_cpu(*image)) { |
@@ -89,7 +89,7 @@ static int il4965_verify_inst_full(struct il_priv *il, __le32 *image, | |||
89 | 89 | ||
90 | D_INFO("ucode inst image size is %u\n", len); | 90 | D_INFO("ucode inst image size is %u\n", len); |
91 | 91 | ||
92 | il_write_direct32(il, HBUS_TARG_MEM_RADDR, | 92 | il_wr(il, HBUS_TARG_MEM_RADDR, |
93 | IWL4965_RTC_INST_LOWER_BOUND); | 93 | IWL4965_RTC_INST_LOWER_BOUND); |
94 | 94 | ||
95 | errcnt = 0; | 95 | errcnt = 0; |
diff --git a/drivers/net/wireless/iwlegacy/iwl-csr.h b/drivers/net/wireless/iwlegacy/iwl-csr.h index faffb8e180b4..c00ec353f556 100644 --- a/drivers/net/wireless/iwlegacy/iwl-csr.h +++ b/drivers/net/wireless/iwlegacy/iwl-csr.h | |||
@@ -72,7 +72,7 @@ | |||
72 | * | 72 | * |
73 | * Use _il_wr() and _il_rd() family to access these registers; | 73 | * Use _il_wr() and _il_rd() family to access these registers; |
74 | * these provide simple PCI bus access, without waking up the MAC. | 74 | * these provide simple PCI bus access, without waking up the MAC. |
75 | * Do not use il_write_direct32() family for these registers; | 75 | * Do not use il_wr() family for these registers; |
76 | * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. | 76 | * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ. |
77 | * The MAC (uCode processor, etc.) does not need to be powered up for accessing | 77 | * The MAC (uCode processor, etc.) does not need to be powered up for accessing |
78 | * the CSR registers. | 78 | * the CSR registers. |
@@ -368,7 +368,7 @@ | |||
368 | * to indirectly access device's internal memory or registers that | 368 | * to indirectly access device's internal memory or registers that |
369 | * may be powered-down. | 369 | * may be powered-down. |
370 | * | 370 | * |
371 | * Use il_write_direct32()/il_read_direct32() family | 371 | * Use il_wr()/il_rd() family |
372 | * for these registers; | 372 | * for these registers; |
373 | * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ | 373 | * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ |
374 | * to make sure the MAC (uCode processor, etc.) is powered up for accessing | 374 | * to make sure the MAC (uCode processor, etc.) is powered up for accessing |
diff --git a/drivers/net/wireless/iwlegacy/iwl-io.h b/drivers/net/wireless/iwlegacy/iwl-io.h index ecf799d9d22b..f435942ab458 100644 --- a/drivers/net/wireless/iwlegacy/iwl-io.h +++ b/drivers/net/wireless/iwlegacy/iwl-io.h | |||
@@ -144,7 +144,7 @@ static inline void _il_release_nic_access(struct il_priv *il) | |||
144 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); | 144 | CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); |
145 | } | 145 | } |
146 | 146 | ||
147 | static inline u32 il_read_direct32(struct il_priv *il, u32 reg) | 147 | static inline u32 il_rd(struct il_priv *il, u32 reg) |
148 | { | 148 | { |
149 | u32 value; | 149 | u32 value; |
150 | unsigned long reg_flags; | 150 | unsigned long reg_flags; |
@@ -159,7 +159,7 @@ static inline u32 il_read_direct32(struct il_priv *il, u32 reg) | |||
159 | } | 159 | } |
160 | 160 | ||
161 | static inline void | 161 | static inline void |
162 | il_write_direct32(struct il_priv *il, u32 reg, u32 value) | 162 | il_wr(struct il_priv *il, u32 reg, u32 value) |
163 | { | 163 | { |
164 | unsigned long reg_flags; | 164 | unsigned long reg_flags; |
165 | 165 | ||
@@ -178,17 +178,17 @@ static inline void il_write_reg_buf(struct il_priv *il, | |||
178 | 178 | ||
179 | if ((il != NULL) && (values != NULL)) { | 179 | if ((il != NULL) && (values != NULL)) { |
180 | for (; 0 < len; len -= count, reg += count, values++) | 180 | for (; 0 < len; len -= count, reg += count, values++) |
181 | il_write_direct32(il, reg, *values); | 181 | il_wr(il, reg, *values); |
182 | } | 182 | } |
183 | } | 183 | } |
184 | 184 | ||
185 | static inline int _il_poll_direct_bit(struct il_priv *il, u32 addr, | 185 | static inline int il_poll_bit(struct il_priv *il, u32 addr, |
186 | u32 mask, int timeout) | 186 | u32 mask, int timeout) |
187 | { | 187 | { |
188 | int t = 0; | 188 | int t = 0; |
189 | 189 | ||
190 | do { | 190 | do { |
191 | if ((il_read_direct32(il, addr) & mask) == mask) | 191 | if ((il_rd(il, addr) & mask) == mask) |
192 | return t; | 192 | return t; |
193 | udelay(IL_POLL_INTERVAL); | 193 | udelay(IL_POLL_INTERVAL); |
194 | t += IL_POLL_INTERVAL; | 194 | t += IL_POLL_INTERVAL; |
@@ -196,7 +196,6 @@ static inline int _il_poll_direct_bit(struct il_priv *il, u32 addr, | |||
196 | 196 | ||
197 | return -ETIMEDOUT; | 197 | return -ETIMEDOUT; |
198 | } | 198 | } |
199 | #define il_poll_direct_bit _il_poll_direct_bit | ||
200 | 199 | ||
201 | static inline u32 _il_read_prph(struct il_priv *il, u32 reg) | 200 | static inline u32 _il_read_prph(struct il_priv *il, u32 reg) |
202 | { | 201 | { |
diff --git a/drivers/net/wireless/iwlegacy/iwl-rx.c b/drivers/net/wireless/iwlegacy/iwl-rx.c index e481ca8c0cc9..b2ec2a214caa 100644 --- a/drivers/net/wireless/iwlegacy/iwl-rx.c +++ b/drivers/net/wireless/iwlegacy/iwl-rx.c | |||
@@ -150,14 +150,14 @@ il_rx_queue_update_write_ptr(struct il_priv *il, | |||
150 | } | 150 | } |
151 | 151 | ||
152 | q->write_actual = (q->write & ~0x7); | 152 | q->write_actual = (q->write & ~0x7); |
153 | il_write_direct32(il, rx_wrt_ptr_reg, | 153 | il_wr(il, rx_wrt_ptr_reg, |
154 | q->write_actual); | 154 | q->write_actual); |
155 | 155 | ||
156 | /* Else device is assumed to be awake */ | 156 | /* Else device is assumed to be awake */ |
157 | } else { | 157 | } else { |
158 | /* Device expects a multiple of 8 */ | 158 | /* Device expects a multiple of 8 */ |
159 | q->write_actual = (q->write & ~0x7); | 159 | q->write_actual = (q->write & ~0x7); |
160 | il_write_direct32(il, rx_wrt_ptr_reg, | 160 | il_wr(il, rx_wrt_ptr_reg, |
161 | q->write_actual); | 161 | q->write_actual); |
162 | } | 162 | } |
163 | 163 | ||
diff --git a/drivers/net/wireless/iwlegacy/iwl-tx.c b/drivers/net/wireless/iwlegacy/iwl-tx.c index 6b5e652c4fc3..fa23c983ef91 100644 --- a/drivers/net/wireless/iwlegacy/iwl-tx.c +++ b/drivers/net/wireless/iwlegacy/iwl-tx.c | |||
@@ -66,7 +66,7 @@ il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq) | |||
66 | return; | 66 | return; |
67 | } | 67 | } |
68 | 68 | ||
69 | il_write_direct32(il, HBUS_TARG_WRPTR, | 69 | il_wr(il, HBUS_TARG_WRPTR, |
70 | txq->q.write_ptr | (txq_id << 8)); | 70 | txq->q.write_ptr | (txq_id << 8)); |
71 | 71 | ||
72 | /* | 72 | /* |
diff --git a/drivers/net/wireless/iwlegacy/iwl3945-base.c b/drivers/net/wireless/iwlegacy/iwl3945-base.c index d45e9f532dcc..a0b5a74972a9 100644 --- a/drivers/net/wireless/iwlegacy/iwl3945-base.c +++ b/drivers/net/wireless/iwlegacy/iwl3945-base.c | |||
@@ -1520,7 +1520,7 @@ static void il3945_irq_tasklet(struct il_priv *il) | |||
1520 | il->isr_stats.tx++; | 1520 | il->isr_stats.tx++; |
1521 | 1521 | ||
1522 | _il_wr(il, CSR_FH_INT_STATUS, (1 << 6)); | 1522 | _il_wr(il, CSR_FH_INT_STATUS, (1 << 6)); |
1523 | il_write_direct32(il, FH39_TCSR_CREDIT | 1523 | il_wr(il, FH39_TCSR_CREDIT |
1524 | (FH39_SRVC_CHNL), 0x0); | 1524 | (FH39_SRVC_CHNL), 0x0); |
1525 | handled |= CSR_INT_BIT_FH_TX; | 1525 | handled |= CSR_INT_BIT_FH_TX; |
1526 | } | 1526 | } |
@@ -1698,7 +1698,7 @@ static int il3945_verify_inst_full(struct il_priv *il, __le32 *image, u32 len) | |||
1698 | 1698 | ||
1699 | D_INFO("ucode inst image size is %u\n", len); | 1699 | D_INFO("ucode inst image size is %u\n", len); |
1700 | 1700 | ||
1701 | il_write_direct32(il, HBUS_TARG_MEM_RADDR, | 1701 | il_wr(il, HBUS_TARG_MEM_RADDR, |
1702 | IWL39_RTC_INST_LOWER_BOUND); | 1702 | IWL39_RTC_INST_LOWER_BOUND); |
1703 | 1703 | ||
1704 | errcnt = 0; | 1704 | errcnt = 0; |
@@ -1745,7 +1745,7 @@ static int il3945_verify_inst_sparse(struct il_priv *il, __le32 *image, u32 len) | |||
1745 | /* read data comes through single port, auto-incr addr */ | 1745 | /* read data comes through single port, auto-incr addr */ |
1746 | /* NOTE: Use the debugless read so we don't flood kernel log | 1746 | /* NOTE: Use the debugless read so we don't flood kernel log |
1747 | * if IL_DL_IO is set */ | 1747 | * if IL_DL_IO is set */ |
1748 | il_write_direct32(il, HBUS_TARG_MEM_RADDR, | 1748 | il_wr(il, HBUS_TARG_MEM_RADDR, |
1749 | i + IWL39_RTC_INST_LOWER_BOUND); | 1749 | i + IWL39_RTC_INST_LOWER_BOUND); |
1750 | val = _il_rd(il, HBUS_TARG_MEM_RDAT); | 1750 | val = _il_rd(il, HBUS_TARG_MEM_RDAT); |
1751 | if (val != le32_to_cpu(*image)) { | 1751 | if (val != le32_to_cpu(*image)) { |
diff --git a/drivers/net/wireless/iwlegacy/iwl4965-base.c b/drivers/net/wireless/iwlegacy/iwl4965-base.c index f4eb037f563b..b0668ea9b104 100644 --- a/drivers/net/wireless/iwlegacy/iwl4965-base.c +++ b/drivers/net/wireless/iwlegacy/iwl4965-base.c | |||
@@ -416,7 +416,7 @@ int il4965_hw_tx_queue_init(struct il_priv *il, | |||
416 | int txq_id = txq->q.id; | 416 | int txq_id = txq->q.id; |
417 | 417 | ||
418 | /* Circular buffer (TFD queue in DRAM) physical base address */ | 418 | /* Circular buffer (TFD queue in DRAM) physical base address */ |
419 | il_write_direct32(il, FH_MEM_CBBC_QUEUE(txq_id), | 419 | il_wr(il, FH_MEM_CBBC_QUEUE(txq_id), |
420 | txq->q.dma_addr >> 8); | 420 | txq->q.dma_addr >> 8); |
421 | 421 | ||
422 | return 0; | 422 | return 0; |
@@ -548,13 +548,13 @@ static void il4965_rx_card_state_notif(struct il_priv *il, | |||
548 | _il_wr(il, CSR_UCODE_DRV_GP1_SET, | 548 | _il_wr(il, CSR_UCODE_DRV_GP1_SET, |
549 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | 549 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
550 | 550 | ||
551 | il_write_direct32(il, HBUS_TARG_MBX_C, | 551 | il_wr(il, HBUS_TARG_MBX_C, |
552 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | 552 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
553 | 553 | ||
554 | if (!(flags & RXON_CARD_DISABLED)) { | 554 | if (!(flags & RXON_CARD_DISABLED)) { |
555 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, | 555 | _il_wr(il, CSR_UCODE_DRV_GP1_CLR, |
556 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); | 556 | CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); |
557 | il_write_direct32(il, HBUS_TARG_MBX_C, | 557 | il_wr(il, HBUS_TARG_MBX_C, |
558 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); | 558 | HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); |
559 | } | 559 | } |
560 | } | 560 | } |
@@ -1639,14 +1639,14 @@ static int il4965_alive_notify(struct il_priv *il) | |||
1639 | 1639 | ||
1640 | /* Enable DMA channel */ | 1640 | /* Enable DMA channel */ |
1641 | for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++) | 1641 | for (chan = 0; chan < FH49_TCSR_CHNL_NUM ; chan++) |
1642 | il_write_direct32(il, | 1642 | il_wr(il, |
1643 | FH_TCSR_CHNL_TX_CONFIG_REG(chan), | 1643 | FH_TCSR_CHNL_TX_CONFIG_REG(chan), |
1644 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | | 1644 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | |
1645 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); | 1645 | FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); |
1646 | 1646 | ||
1647 | /* Update FH chicken bits */ | 1647 | /* Update FH chicken bits */ |
1648 | reg_val = il_read_direct32(il, FH_TX_CHICKEN_BITS_REG); | 1648 | reg_val = il_rd(il, FH_TX_CHICKEN_BITS_REG); |
1649 | il_write_direct32(il, FH_TX_CHICKEN_BITS_REG, | 1649 | il_wr(il, FH_TX_CHICKEN_BITS_REG, |
1650 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); | 1650 | reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); |
1651 | 1651 | ||
1652 | /* Disable chain mode for all queues */ | 1652 | /* Disable chain mode for all queues */ |
@@ -1657,7 +1657,7 @@ static int il4965_alive_notify(struct il_priv *il) | |||
1657 | 1657 | ||
1658 | /* TFD circular buffer read/write indexes */ | 1658 | /* TFD circular buffer read/write indexes */ |
1659 | il_write_prph(il, IWL49_SCD_QUEUE_RDPTR(i), 0); | 1659 | il_write_prph(il, IWL49_SCD_QUEUE_RDPTR(i), 0); |
1660 | il_write_direct32(il, HBUS_TARG_WRPTR, 0 | (i << 8)); | 1660 | il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8)); |
1661 | 1661 | ||
1662 | /* Max Tx Window size for Scheduler-ACK mode */ | 1662 | /* Max Tx Window size for Scheduler-ACK mode */ |
1663 | il_write_targ_mem(il, il->scd_base_addr + | 1663 | il_write_targ_mem(il, il->scd_base_addr + |
@@ -2731,7 +2731,7 @@ static void il4965_init_hw_rates(struct il_priv *il, | |||
2731 | */ | 2731 | */ |
2732 | void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 index) | 2732 | void il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 index) |
2733 | { | 2733 | { |
2734 | il_write_direct32(il, HBUS_TARG_WRPTR, | 2734 | il_wr(il, HBUS_TARG_WRPTR, |
2735 | (index & 0xff) | (txq_id << 8)); | 2735 | (index & 0xff) | (txq_id << 8)); |
2736 | il_write_prph(il, IWL49_SCD_QUEUE_RDPTR(txq_id), index); | 2736 | il_write_prph(il, IWL49_SCD_QUEUE_RDPTR(txq_id), index); |
2737 | } | 2737 | } |