diff options
author | Jon Smirl <jonsmirl@gmail.com> | 2009-05-23 19:13:03 -0400 |
---|---|---|
committer | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2009-05-24 14:31:04 -0400 |
commit | 0bc53a67ac831ec84f730a657dbcadd80a589ef5 (patch) | |
tree | 5a94ee1948af20a98aafeadd21ba880907c56513 | |
parent | cebe77674cab51a9ff1deaa077ab74aff3996764 (diff) |
ASoC: Add a few more mpc5200 PSC defines
Add a few more mpc5200 PSC defines. More bit fields defines for mpc5200
PSC registers.
Signed-off-by: Jon Smirl <jonsmirl@gmail.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
-rw-r--r-- | arch/powerpc/include/asm/mpc52xx_psc.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mpc52xx_psc.h b/arch/powerpc/include/asm/mpc52xx_psc.h index a218da6bec7c..fb8412057450 100644 --- a/arch/powerpc/include/asm/mpc52xx_psc.h +++ b/arch/powerpc/include/asm/mpc52xx_psc.h | |||
@@ -28,6 +28,10 @@ | |||
28 | #define MPC52xx_PSC_MAXNUM 6 | 28 | #define MPC52xx_PSC_MAXNUM 6 |
29 | 29 | ||
30 | /* Programmable Serial Controller (PSC) status register bits */ | 30 | /* Programmable Serial Controller (PSC) status register bits */ |
31 | #define MPC52xx_PSC_SR_UNEX_RX 0x0001 | ||
32 | #define MPC52xx_PSC_SR_DATA_VAL 0x0002 | ||
33 | #define MPC52xx_PSC_SR_DATA_OVR 0x0004 | ||
34 | #define MPC52xx_PSC_SR_CMDSEND 0x0008 | ||
31 | #define MPC52xx_PSC_SR_CDE 0x0080 | 35 | #define MPC52xx_PSC_SR_CDE 0x0080 |
32 | #define MPC52xx_PSC_SR_RXRDY 0x0100 | 36 | #define MPC52xx_PSC_SR_RXRDY 0x0100 |
33 | #define MPC52xx_PSC_SR_RXFULL 0x0200 | 37 | #define MPC52xx_PSC_SR_RXFULL 0x0200 |
@@ -61,6 +65,12 @@ | |||
61 | #define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 | 65 | #define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001 |
62 | 66 | ||
63 | /* PSC interrupt status/mask bits */ | 67 | /* PSC interrupt status/mask bits */ |
68 | #define MPC52xx_PSC_IMR_UNEX_RX_SLOT 0x0001 | ||
69 | #define MPC52xx_PSC_IMR_DATA_VALID 0x0002 | ||
70 | #define MPC52xx_PSC_IMR_DATA_OVR 0x0004 | ||
71 | #define MPC52xx_PSC_IMR_CMD_SEND 0x0008 | ||
72 | #define MPC52xx_PSC_IMR_ERROR 0x0040 | ||
73 | #define MPC52xx_PSC_IMR_DEOF 0x0080 | ||
64 | #define MPC52xx_PSC_IMR_TXRDY 0x0100 | 74 | #define MPC52xx_PSC_IMR_TXRDY 0x0100 |
65 | #define MPC52xx_PSC_IMR_RXRDY 0x0200 | 75 | #define MPC52xx_PSC_IMR_RXRDY 0x0200 |
66 | #define MPC52xx_PSC_IMR_DB 0x0400 | 76 | #define MPC52xx_PSC_IMR_DB 0x0400 |
@@ -117,6 +127,7 @@ | |||
117 | #define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24) | 127 | #define MPC52xx_PSC_SICR_SIM_FIR (0x6 << 24) |
118 | #define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24) | 128 | #define MPC52xx_PSC_SICR_SIM_CODEC_24 (0x7 << 24) |
119 | #define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24) | 129 | #define MPC52xx_PSC_SICR_SIM_CODEC_32 (0xf << 24) |
130 | #define MPC52xx_PSC_SICR_AWR (1 << 30) | ||
120 | #define MPC52xx_PSC_SICR_GENCLK (1 << 23) | 131 | #define MPC52xx_PSC_SICR_GENCLK (1 << 23) |
121 | #define MPC52xx_PSC_SICR_I2S (1 << 22) | 132 | #define MPC52xx_PSC_SICR_I2S (1 << 22) |
122 | #define MPC52xx_PSC_SICR_CLKPOL (1 << 21) | 133 | #define MPC52xx_PSC_SICR_CLKPOL (1 << 21) |