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authorBastian Hecht <hechtb@gmail.com>2013-03-27 09:54:04 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-04-01 22:02:09 -0400
commit0b7d78202260162057248875b1c9bac70d041e58 (patch)
tree59f3f08b9d71e1d3a7b4d45f657e9a8320e611d6
parentc91cf2fad00f24bfe268d30b75e4015aaa326c04 (diff)
ARM: shmobile: r8a7740: Migrate from INTC to GIC
With the added capabilty of the intc_irqpin driver to handle shared external IRQs, all prerequisites are fulfilled and we are ready to migrate completely to GIC. This includes the following steps: - Kconfig: select ARM_GIC and RENESAS_INTC_IRQPIN - intc-r8a7740: Throw out all legacy INTC code and init the GIC. We need to mask out all shared IRQs as it is needed by the shared intc_irqpin driver. - setup-r8a7740: Add 4 irqpin devices to handle external IRQs and update all IRQ numbers to point to the GIC SPI. - board-armadillo: Update all IRQ numbers to point to the GIC SPI. - pfc-r8a7740: Update all IRQ numbers of the GPIOs to point to the GIC SPI. Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat
-rw-r--r--arch/arm/mach-shmobile/Kconfig2
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c35
-rw-r--r--arch/arm/mach-shmobile/intc-r8a7740.c641
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c192
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c64
5 files changed, 239 insertions, 695 deletions
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 49cba4a511df..d569c34b1c86 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -30,8 +30,10 @@ config ARCH_R8A73A4
30config ARCH_R8A7740 30config ARCH_R8A7740
31 bool "R-Mobile A1 (R8A77400)" 31 bool "R-Mobile A1 (R8A77400)"
32 select ARCH_WANT_OPTIONAL_GPIOLIB 32 select ARCH_WANT_OPTIONAL_GPIOLIB
33 select ARM_GIC
33 select CPU_V7 34 select CPU_V7
34 select SH_CLK_CPG 35 select SH_CLK_CPG
36 select RENESAS_INTC_IRQPIN
35 37
36config ARCH_R8A7778 38config ARCH_R8A7778
37 bool "R-Car M1 (R8A77780)" 39 bool "R-Car M1 (R8A77780)"
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index f2ec0777cfbe..e451327278af 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -145,7 +145,7 @@
145 * see 145 * see
146 * usbhsf_power_ctrl() 146 * usbhsf_power_ctrl()
147 */ 147 */
148#define IRQ7 evt2irq(0x02e0) 148#define IRQ7 irq_pin(7)
149#define USBCR1 IOMEM(0xe605810a) 149#define USBCR1 IOMEM(0xe605810a)
150#define USBH 0xC6700000 150#define USBH 0xC6700000
151#define USBH_USBCTR 0x10834 151#define USBH_USBCTR 0x10834
@@ -330,7 +330,7 @@ static struct resource usbhsf_resources[] = {
330 .flags = IORESOURCE_MEM, 330 .flags = IORESOURCE_MEM,
331 }, 331 },
332 { 332 {
333 .start = evt2irq(0x0A20), 333 .start = gic_spi(51),
334 .flags = IORESOURCE_IRQ, 334 .flags = IORESOURCE_IRQ,
335 }, 335 },
336}; 336};
@@ -363,7 +363,7 @@ static struct resource sh_eth_resources[] = {
363 .end = 0xe9a02000 - 1, 363 .end = 0xe9a02000 - 1,
364 .flags = IORESOURCE_MEM, 364 .flags = IORESOURCE_MEM,
365 }, { 365 }, {
366 .start = evt2irq(0x0500), 366 .start = gic_spi(110),
367 .flags = IORESOURCE_IRQ, 367 .flags = IORESOURCE_IRQ,
368 }, 368 },
369}; 369};
@@ -417,7 +417,7 @@ static struct resource lcdc0_resources[] = {
417 .flags = IORESOURCE_MEM, 417 .flags = IORESOURCE_MEM,
418 }, 418 },
419 [1] = { 419 [1] = {
420 .start = intcs_evt2irq(0x580), 420 .start = gic_spi(177),
421 .flags = IORESOURCE_IRQ, 421 .flags = IORESOURCE_IRQ,
422 }, 422 },
423}; 423};
@@ -452,7 +452,7 @@ static struct resource hdmi_resources[] = {
452 .flags = IORESOURCE_MEM, 452 .flags = IORESOURCE_MEM,
453 }, 453 },
454 [1] = { 454 [1] = {
455 .start = evt2irq(0x1700), 455 .start = gic_spi(131),
456 .flags = IORESOURCE_IRQ, 456 .flags = IORESOURCE_IRQ,
457 }, 457 },
458 [2] = { 458 [2] = {
@@ -514,7 +514,7 @@ static struct resource hdmi_lcdc_resources[] = {
514 .flags = IORESOURCE_MEM, 514 .flags = IORESOURCE_MEM,
515 }, 515 },
516 [1] = { 516 [1] = {
517 .start = intcs_evt2irq(0x1780), 517 .start = gic_spi(178),
518 .flags = IORESOURCE_IRQ, 518 .flags = IORESOURCE_IRQ,
519 }, 519 },
520}; 520};
@@ -574,7 +574,7 @@ static struct regulator_consumer_supply fixed3v3_power_consumers[] =
574 * We can use IRQ31 as card detect irq, 574 * We can use IRQ31 as card detect irq,
575 * but it needs chattering removal operation 575 * but it needs chattering removal operation
576 */ 576 */
577#define IRQ31 evt2irq(0x33E0) 577#define IRQ31 irq_pin(31)
578static struct sh_mobile_sdhi_info sdhi0_info = { 578static struct sh_mobile_sdhi_info sdhi0_info = {
579 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 579 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
580 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 580 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
@@ -596,12 +596,12 @@ static struct resource sdhi0_resources[] = {
596 */ 596 */
597 { 597 {
598 .name = SH_MOBILE_SDHI_IRQ_SDCARD, 598 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
599 .start = evt2irq(0x0E20), 599 .start = gic_spi(118),
600 .flags = IORESOURCE_IRQ, 600 .flags = IORESOURCE_IRQ,
601 }, 601 },
602 { 602 {
603 .name = SH_MOBILE_SDHI_IRQ_SDIO, 603 .name = SH_MOBILE_SDHI_IRQ_SDIO,
604 .start = evt2irq(0x0E40), 604 .start = gic_spi(119),
605 .flags = IORESOURCE_IRQ, 605 .flags = IORESOURCE_IRQ,
606 }, 606 },
607}; 607};
@@ -633,15 +633,15 @@ static struct resource sdhi1_resources[] = {
633 .flags = IORESOURCE_MEM, 633 .flags = IORESOURCE_MEM,
634 }, 634 },
635 [1] = { 635 [1] = {
636 .start = evt2irq(0x0E80), 636 .start = gic_spi(121),
637 .flags = IORESOURCE_IRQ, 637 .flags = IORESOURCE_IRQ,
638 }, 638 },
639 [2] = { 639 [2] = {
640 .start = evt2irq(0x0EA0), 640 .start = gic_spi(122),
641 .flags = IORESOURCE_IRQ, 641 .flags = IORESOURCE_IRQ,
642 }, 642 },
643 [3] = { 643 [3] = {
644 .start = evt2irq(0x0EC0), 644 .start = gic_spi(123),
645 .flags = IORESOURCE_IRQ, 645 .flags = IORESOURCE_IRQ,
646 }, 646 },
647}; 647};
@@ -674,12 +674,12 @@ static struct resource sh_mmcif_resources[] = {
674 }, 674 },
675 [1] = { 675 [1] = {
676 /* MMC ERR */ 676 /* MMC ERR */
677 .start = evt2irq(0x1AC0), 677 .start = gic_spi(56),
678 .flags = IORESOURCE_IRQ, 678 .flags = IORESOURCE_IRQ,
679 }, 679 },
680 [2] = { 680 [2] = {
681 /* MMC NOR */ 681 /* MMC NOR */
682 .start = evt2irq(0x1AE0), 682 .start = gic_spi(57),
683 .flags = IORESOURCE_IRQ, 683 .flags = IORESOURCE_IRQ,
684 }, 684 },
685}; 685};
@@ -756,7 +756,7 @@ static struct resource ceu0_resources[] = {
756 .flags = IORESOURCE_MEM, 756 .flags = IORESOURCE_MEM,
757 }, 757 },
758 [1] = { 758 [1] = {
759 .start = intcs_evt2irq(0x0500), 759 .start = gic_spi(160),
760 .flags = IORESOURCE_IRQ, 760 .flags = IORESOURCE_IRQ,
761 }, 761 },
762 [2] = { 762 [2] = {
@@ -798,7 +798,7 @@ static struct resource fsi_resources[] = {
798 .flags = IORESOURCE_MEM, 798 .flags = IORESOURCE_MEM,
799 }, 799 },
800 [1] = { 800 [1] = {
801 .start = evt2irq(0x1840), 801 .start = gic_spi(9),
802 .flags = IORESOURCE_IRQ, 802 .flags = IORESOURCE_IRQ,
803 }, 803 },
804}; 804};
@@ -881,7 +881,7 @@ static struct platform_device i2c_gpio_device = {
881static struct i2c_board_info i2c0_devices[] = { 881static struct i2c_board_info i2c0_devices[] = {
882 { 882 {
883 I2C_BOARD_INFO("st1232-ts", 0x55), 883 I2C_BOARD_INFO("st1232-ts", 0x55),
884 .irq = evt2irq(0x0340), 884 .irq = irq_pin(10),
885 }, 885 },
886 { 886 {
887 I2C_BOARD_INFO("wm8978", 0x1a), 887 I2C_BOARD_INFO("wm8978", 0x1a),
@@ -1207,7 +1207,6 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
1207 .map_io = r8a7740_map_io, 1207 .map_io = r8a7740_map_io,
1208 .init_early = eva_add_early_devices, 1208 .init_early = eva_add_early_devices,
1209 .init_irq = r8a7740_init_irq, 1209 .init_irq = r8a7740_init_irq,
1210 .handle_irq = shmobile_handle_irq_intc,
1211 .init_machine = eva_init, 1210 .init_machine = eva_init,
1212 .init_late = shmobile_init_late, 1211 .init_late = shmobile_init_late,
1213 .init_time = eva_earlytimer_init, 1212 .init_time = eva_earlytimer_init,
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
index 9a69a31918ba..b741c8409a5a 100644
--- a/arch/arm/mach-shmobile/intc-r8a7740.c
+++ b/arch/arm/mach-shmobile/intc-r8a7740.c
@@ -18,620 +18,39 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/kernel.h>
22#include <linux/init.h> 21#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h> 22#include <linux/io.h>
26#include <linux/sh_intc.h> 23#include <linux/irqchip/arm-gic.h>
27#include <mach/intc.h>
28#include <mach/irqs.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32/*
33 * INTCA
34 */
35enum {
36 UNUSED_INTCA = 0,
37
38 /* interrupt sources INTCA */
39 DIRC,
40 ATAPI,
41 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI,
42 AP_ARM_COMMTX, AP_ARM_COMMRX,
43 MFI, MFIS,
44 BBIF1, BBIF2,
45 USBHSDMAC,
46 USBF_OUL_SOF, USBF_IXL_INT,
47 SGX540,
48 CMT1_0, CMT1_1, CMT1_2, CMT1_3,
49 CMT2,
50 CMT3,
51 KEYSC,
52 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
53 MSIOF2, MSIOF1,
54 SCIFA4, SCIFA5, SCIFB,
55 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
56 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3,
57 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3,
58 AP_ARM_L2CINT,
59 IRDA,
60 TPU0,
61 SCIFA6, SCIFA7,
62 GbEther,
63 ICBS0,
64 DDM,
65 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3,
66 RWDT0,
67 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
68 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
69 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
70 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
71 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
72 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
73 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
74 HDMI,
75 USBH_INT, USBH_OHCI, USBH_EHCI, USBH_PME, USBH_BIND,
76 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF,
77 SPU2_0, SPU2_1,
78 FSI, FMSI,
79 HDMI_SSS, HDMI_KEY,
80 IPMMU,
81 AP_ARM_CTIIRQ, AP_ARM_PMURQ,
82 MFIS2,
83 CPORTR2S,
84 CMT14, CMT15,
85 MMCIF_0, MMCIF_1, MMCIF_2,
86 SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
87 STPRO_0, STPRO_1, STPRO_2, STPRO_3, STPRO_4,
88
89 /* interrupt groups INTCA */
90 DMAC1_1, DMAC1_2,
91 DMAC2_1, DMAC2_2,
92 DMAC3_1, DMAC3_2,
93 AP_ARM1, AP_ARM2,
94 SDHI0, SDHI1, SDHI2,
95 SHWYSTAT,
96 USBF, USBH1, USBH2,
97 RSPI, SPU2, FLCTL, IIC1,
98};
99
100static struct intc_vect intca_vectors[] __initdata = {
101 INTC_VECT(DIRC, 0x0560),
102 INTC_VECT(ATAPI, 0x05E0),
103 INTC_VECT(IIC1_ALI, 0x0780),
104 INTC_VECT(IIC1_TACKI, 0x07A0),
105 INTC_VECT(IIC1_WAITI, 0x07C0),
106 INTC_VECT(IIC1_DTEI, 0x07E0),
107 INTC_VECT(AP_ARM_COMMTX, 0x0840),
108 INTC_VECT(AP_ARM_COMMRX, 0x0860),
109 INTC_VECT(MFI, 0x0900),
110 INTC_VECT(MFIS, 0x0920),
111 INTC_VECT(BBIF1, 0x0940),
112 INTC_VECT(BBIF2, 0x0960),
113 INTC_VECT(USBHSDMAC, 0x0A00),
114 INTC_VECT(USBF_OUL_SOF, 0x0A20),
115 INTC_VECT(USBF_IXL_INT, 0x0A40),
116 INTC_VECT(SGX540, 0x0A60),
117 INTC_VECT(CMT1_0, 0x0B00),
118 INTC_VECT(CMT1_1, 0x0B20),
119 INTC_VECT(CMT1_2, 0x0B40),
120 INTC_VECT(CMT1_3, 0x0B60),
121 INTC_VECT(CMT2, 0x0B80),
122 INTC_VECT(CMT3, 0x0BA0),
123 INTC_VECT(KEYSC, 0x0BE0),
124 INTC_VECT(SCIFA0, 0x0C00),
125 INTC_VECT(SCIFA1, 0x0C20),
126 INTC_VECT(SCIFA2, 0x0C40),
127 INTC_VECT(SCIFA3, 0x0C60),
128 INTC_VECT(MSIOF2, 0x0C80),
129 INTC_VECT(MSIOF1, 0x0D00),
130 INTC_VECT(SCIFA4, 0x0D20),
131 INTC_VECT(SCIFA5, 0x0D40),
132 INTC_VECT(SCIFB, 0x0D60),
133 INTC_VECT(FLCTL_FLSTEI, 0x0D80),
134 INTC_VECT(FLCTL_FLTENDI, 0x0DA0),
135 INTC_VECT(FLCTL_FLTREQ0I, 0x0DC0),
136 INTC_VECT(FLCTL_FLTREQ1I, 0x0DE0),
137 INTC_VECT(SDHI0_0, 0x0E00),
138 INTC_VECT(SDHI0_1, 0x0E20),
139 INTC_VECT(SDHI0_2, 0x0E40),
140 INTC_VECT(SDHI0_3, 0x0E60),
141 INTC_VECT(SDHI1_0, 0x0E80),
142 INTC_VECT(SDHI1_1, 0x0EA0),
143 INTC_VECT(SDHI1_2, 0x0EC0),
144 INTC_VECT(SDHI1_3, 0x0EE0),
145 INTC_VECT(AP_ARM_L2CINT, 0x0FA0),
146 INTC_VECT(IRDA, 0x0480),
147 INTC_VECT(TPU0, 0x04A0),
148 INTC_VECT(SCIFA6, 0x04C0),
149 INTC_VECT(SCIFA7, 0x04E0),
150 INTC_VECT(GbEther, 0x0500),
151 INTC_VECT(ICBS0, 0x0540),
152 INTC_VECT(DDM, 0x1140),
153 INTC_VECT(SDHI2_0, 0x1200),
154 INTC_VECT(SDHI2_1, 0x1220),
155 INTC_VECT(SDHI2_2, 0x1240),
156 INTC_VECT(SDHI2_3, 0x1260),
157 INTC_VECT(RWDT0, 0x1280),
158 INTC_VECT(DMAC1_1_DEI0, 0x2000),
159 INTC_VECT(DMAC1_1_DEI1, 0x2020),
160 INTC_VECT(DMAC1_1_DEI2, 0x2040),
161 INTC_VECT(DMAC1_1_DEI3, 0x2060),
162 INTC_VECT(DMAC1_2_DEI4, 0x2080),
163 INTC_VECT(DMAC1_2_DEI5, 0x20A0),
164 INTC_VECT(DMAC1_2_DADERR, 0x20C0),
165 INTC_VECT(DMAC2_1_DEI0, 0x2100),
166 INTC_VECT(DMAC2_1_DEI1, 0x2120),
167 INTC_VECT(DMAC2_1_DEI2, 0x2140),
168 INTC_VECT(DMAC2_1_DEI3, 0x2160),
169 INTC_VECT(DMAC2_2_DEI4, 0x2180),
170 INTC_VECT(DMAC2_2_DEI5, 0x21A0),
171 INTC_VECT(DMAC2_2_DADERR, 0x21C0),
172 INTC_VECT(DMAC3_1_DEI0, 0x2200),
173 INTC_VECT(DMAC3_1_DEI1, 0x2220),
174 INTC_VECT(DMAC3_1_DEI2, 0x2240),
175 INTC_VECT(DMAC3_1_DEI3, 0x2260),
176 INTC_VECT(DMAC3_2_DEI4, 0x2280),
177 INTC_VECT(DMAC3_2_DEI5, 0x22A0),
178 INTC_VECT(DMAC3_2_DADERR, 0x22C0),
179 INTC_VECT(SHWYSTAT_RT, 0x1300),
180 INTC_VECT(SHWYSTAT_HS, 0x1320),
181 INTC_VECT(SHWYSTAT_COM, 0x1340),
182 INTC_VECT(USBH_INT, 0x1540),
183 INTC_VECT(USBH_OHCI, 0x1560),
184 INTC_VECT(USBH_EHCI, 0x1580),
185 INTC_VECT(USBH_PME, 0x15A0),
186 INTC_VECT(USBH_BIND, 0x15C0),
187 INTC_VECT(HDMI, 0x1700),
188 INTC_VECT(RSPI_OVRF, 0x1780),
189 INTC_VECT(RSPI_SPTEF, 0x17A0),
190 INTC_VECT(RSPI_SPRF, 0x17C0),
191 INTC_VECT(SPU2_0, 0x1800),
192 INTC_VECT(SPU2_1, 0x1820),
193 INTC_VECT(FSI, 0x1840),
194 INTC_VECT(FMSI, 0x1860),
195 INTC_VECT(HDMI_SSS, 0x18A0),
196 INTC_VECT(HDMI_KEY, 0x18C0),
197 INTC_VECT(IPMMU, 0x1920),
198 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
199 INTC_VECT(AP_ARM_PMURQ, 0x19A0),
200 INTC_VECT(MFIS2, 0x1A00),
201 INTC_VECT(CPORTR2S, 0x1A20),
202 INTC_VECT(CMT14, 0x1A40),
203 INTC_VECT(CMT15, 0x1A60),
204 INTC_VECT(MMCIF_0, 0x1AA0),
205 INTC_VECT(MMCIF_1, 0x1AC0),
206 INTC_VECT(MMCIF_2, 0x1AE0),
207 INTC_VECT(SIM_ERI, 0x1C00),
208 INTC_VECT(SIM_RXI, 0x1C20),
209 INTC_VECT(SIM_TXI, 0x1C40),
210 INTC_VECT(SIM_TEI, 0x1C60),
211 INTC_VECT(STPRO_0, 0x1C80),
212 INTC_VECT(STPRO_1, 0x1CA0),
213 INTC_VECT(STPRO_2, 0x1CC0),
214 INTC_VECT(STPRO_3, 0x1CE0),
215 INTC_VECT(STPRO_4, 0x1D00),
216};
217
218static struct intc_group intca_groups[] __initdata = {
219 INTC_GROUP(DMAC1_1,
220 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
221 INTC_GROUP(DMAC1_2,
222 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR),
223 INTC_GROUP(DMAC2_1,
224 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
225 INTC_GROUP(DMAC2_2,
226 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR),
227 INTC_GROUP(DMAC3_1,
228 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
229 INTC_GROUP(DMAC3_2,
230 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR),
231 INTC_GROUP(AP_ARM1,
232 AP_ARM_COMMTX, AP_ARM_COMMRX),
233 INTC_GROUP(AP_ARM2,
234 AP_ARM_CTIIRQ, AP_ARM_PMURQ),
235 INTC_GROUP(USBF,
236 USBF_OUL_SOF, USBF_IXL_INT),
237 INTC_GROUP(SDHI0,
238 SDHI0_0, SDHI0_1, SDHI0_2, SDHI0_3),
239 INTC_GROUP(SDHI1,
240 SDHI1_0, SDHI1_1, SDHI1_2, SDHI1_3),
241 INTC_GROUP(SDHI2,
242 SDHI2_0, SDHI2_1, SDHI2_2, SDHI2_3),
243 INTC_GROUP(SHWYSTAT,
244 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
245 INTC_GROUP(USBH1, /* FIXME */
246 USBH_INT, USBH_OHCI),
247 INTC_GROUP(USBH2, /* FIXME */
248 USBH_EHCI,
249 USBH_PME, USBH_BIND),
250 INTC_GROUP(RSPI,
251 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF),
252 INTC_GROUP(SPU2,
253 SPU2_0, SPU2_1),
254 INTC_GROUP(FLCTL,
255 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
256 INTC_GROUP(IIC1,
257 IIC1_ALI, IIC1_TACKI, IIC1_WAITI, IIC1_DTEI),
258};
259
260static struct intc_mask_reg intca_mask_registers[] __initdata = {
261 { /* IMR0A / IMCR0A */ 0xe6940080, 0xe69400c0, 8,
262 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
263 0, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
264 { /* IMR1A / IMCR1A */ 0xe6940084, 0xe69400c4, 8,
265 { ATAPI, 0, DIRC, 0,
266 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
267 { /* IMR2A / IMCR2A */ 0xe6940088, 0xe69400c8, 8,
268 { 0, 0, 0, 0,
269 BBIF1, BBIF2, MFIS, MFI } },
270 { /* IMR3A / IMCR3A */ 0xe694008c, 0xe69400cc, 8,
271 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
272 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
273 { /* IMR4A / IMCR4A */ 0xe6940090, 0xe69400d0, 8,
274 { DDM, 0, 0, 0,
275 0, 0, 0, 0 } },
276 { /* IMR5A / IMCR5A */ 0xe6940094, 0xe69400d4, 8,
277 { KEYSC, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
278 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
279 { /* IMR6A / IMCR6A */ 0xe6940098, 0xe69400d8, 8,
280 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
281 0, 0, MSIOF2, 0 } },
282 { /* IMR7A / IMCR7A */ 0xe694009c, 0xe69400dc, 8,
283 { SDHI0_3, SDHI0_2, SDHI0_1, SDHI0_0,
284 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
285 { /* IMR8A / IMCR8A */ 0xe69400a0, 0xe69400e0, 8,
286 { SDHI1_3, SDHI1_2, SDHI1_1, SDHI1_0,
287 0, USBHSDMAC, 0, AP_ARM_L2CINT } },
288 { /* IMR9A / IMCR9A */ 0xe69400a4, 0xe69400e4, 8,
289 { CMT1_3, CMT1_2, CMT1_1, CMT1_0,
290 CMT2, USBF_IXL_INT, USBF_OUL_SOF, SGX540 } },
291 { /* IMR10A / IMCR10A */ 0xe69400a8, 0xe69400e8, 8,
292 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
293 0, 0, 0, 0 } },
294 { /* IMR11A / IMCR11A */ 0xe69400ac, 0xe69400ec, 8,
295 { IIC1_DTEI, IIC1_WAITI, IIC1_TACKI, IIC1_ALI,
296 ICBS0, 0, 0, 0 } },
297 { /* IMR12A / IMCR12A */ 0xe69400b0, 0xe69400f0, 8,
298 { 0, 0, TPU0, SCIFA6,
299 SCIFA7, GbEther, 0, 0 } },
300 { /* IMR13A / IMCR13A */ 0xe69400b4, 0xe69400f4, 8,
301 { SDHI2_3, SDHI2_2, SDHI2_1, SDHI2_0,
302 0, CMT3, 0, RWDT0 } },
303 { /* IMR0A3 / IMCR0A3 */ 0xe6950080, 0xe69500c0, 8,
304 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
305 0, 0, 0, 0 } },
306 /* IMR1A3 / IMCR1A3 */
307 { /* IMR2A3 / IMCR2A3 */ 0xe6950088, 0xe69500c8, 8,
308 { 0, 0, USBH_INT, USBH_OHCI,
309 USBH_EHCI, USBH_PME, USBH_BIND, 0 } },
310 /* IMR3A3 / IMCR3A3 */
311 { /* IMR4A3 / IMCR4A3 */ 0xe6950090, 0xe69500d0, 8,
312 { HDMI, 0, 0, 0,
313 RSPI_OVRF, RSPI_SPTEF, RSPI_SPRF, 0 } },
314 { /* IMR5A3 / IMCR5A3 */ 0xe6950094, 0xe69500d4, 8,
315 { SPU2_0, SPU2_1, FSI, FMSI,
316 0, HDMI_SSS, HDMI_KEY, 0 } },
317 { /* IMR6A3 / IMCR6A3 */ 0xe6950098, 0xe69500d8, 8,
318 { 0, IPMMU, 0, 0,
319 AP_ARM_CTIIRQ, AP_ARM_PMURQ, 0, 0 } },
320 { /* IMR7A3 / IMCR7A3 */ 0xe695009c, 0xe69500dc, 8,
321 { MFIS2, CPORTR2S, CMT14, CMT15,
322 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
323 /* IMR8A3 / IMCR8A3 */
324 { /* IMR9A3 / IMCR9A3 */ 0xe69500a4, 0xe69500e4, 8,
325 { SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEI,
326 STPRO_0, STPRO_1, STPRO_2, STPRO_3 } },
327 { /* IMR10A3 / IMCR10A3 */ 0xe69500a8, 0xe69500e8, 8,
328 { STPRO_4, 0, 0, 0,
329 0, 0, 0, 0 } },
330};
331
332static struct intc_prio_reg intca_prio_registers[] __initdata = {
333 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, ICBS0 } },
334 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
335 { 0xe6940008, 0, 16, 4, /* IPRCA */ { ATAPI, 0, CMT1_1, AP_ARM1 } },
336 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0, CMT1_2, 0 } },
337 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFIS, MFI, USBF } },
338 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC, DMAC1_2,
339 SGX540, CMT1_0 } },
340 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
341 SCIFA2, SCIFA3 } },
342 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC,
343 FLCTL, SDHI0 } },
344 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4, 0, IIC1 } },
345 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
346 AP_ARM_L2CINT, 0 } },
347 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_3, 0, SDHI1 } },
348 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, SCIFA6,
349 SCIFA7, GbEther } },
350 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
351 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
352 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
353 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
354 /* IPRBA3 */
355 /* IPRCA3 */
356 /* IPRDA3 */
357 { 0xe6950010, 0, 16, 4, /* IPREA3 */ { USBH1, 0, 0, 0 } },
358 { 0xe6950014, 0, 16, 4, /* IPRFA3 */ { USBH2, 0, 0, 0 } },
359 /* IPRGA3 */
360 /* IPRHA3 */
361 { 0xe6950020, 0, 16, 4, /* IPRIA3 */ { HDMI, 0, 0, 0 } },
362 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { RSPI, 0, 0, 0 } },
363 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
364 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, HDMI_SSS, HDMI_KEY, 0 } },
365 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU, 0, 0, 0 } },
366 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
367 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
368 CMT14, CMT15 } },
369 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, MMCIF_0, MMCIF_1, MMCIF_2 } },
370 /* IPRQA3 */
371 /* IPRRA3 */
372 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { SIM_ERI, SIM_RXI,
373 SIM_TXI, SIM_TEI } },
374 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { STPRO_0, STPRO_1,
375 STPRO_2, STPRO_3 } },
376 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { STPRO_4, 0, 0, 0 } },
377};
378
379static DECLARE_INTC_DESC(intca_desc, "r8a7740-intca",
380 intca_vectors, intca_groups,
381 intca_mask_registers, intca_prio_registers,
382 NULL);
383
384INTC_IRQ_PINS_32(intca_irq_pins, 0xe6900000,
385 INTC_VECT, "r8a7740-intca-irq-pins");
386
387
388/*
389 * INTCS
390 */
391enum {
392 UNUSED_INTCS = 0,
393
394 INTCS,
395
396 /* interrupt sources INTCS */
397
398 /* HUDI */
399 /* STPRO */
400 /* RTDMAC(1) */
401 VPU5HA2,
402 _2DG_TRAP, _2DG_GPM_INT, _2DG_CER_INT,
403 /* MFI */
404 /* BBIF2 */
405 VPU5F,
406 _2DG_BRK_INT,
407 /* SGX540 */
408 /* 2DDMAC */
409 /* IPMMU */
410 /* RTDMAC 2 */
411 /* KEYSC */
412 /* MSIOF */
413 IIC0_ALI, IIC0_TACKI, IIC0_WAITI, IIC0_DTEI,
414 TMU0_0, TMU0_1, TMU0_2,
415 CMT0,
416 /* CMT2 */
417 LMB,
418 CTI,
419 VOU,
420 /* RWDT0 */
421 ICB,
422 VIO6C,
423 CEU20, CEU21,
424 JPU,
425 LCDC0,
426 LCRC,
427 /* RTDMAC2(1) */
428 /* RTDMAC2(2) */
429 LCDC1,
430 /* SPU2 */
431 /* FSI */
432 /* FMSI */
433 TMU1_0, TMU1_1, TMU1_2,
434 CMT4,
435 DISP,
436 DSRV,
437 /* MFIS2 */
438 CPORTS2R,
439
440 /* interrupt groups INTCS */
441 _2DG1,
442 IIC0, TMU1,
443};
444
445static struct intc_vect intcs_vectors[] = {
446 /* HUDI */
447 /* STPRO */
448 /* RTDMAC(1) */
449 INTCS_VECT(VPU5HA2, 0x0880),
450 INTCS_VECT(_2DG_TRAP, 0x08A0),
451 INTCS_VECT(_2DG_GPM_INT, 0x08C0),
452 INTCS_VECT(_2DG_CER_INT, 0x08E0),
453 /* MFI */
454 /* BBIF2 */
455 INTCS_VECT(VPU5F, 0x0980),
456 INTCS_VECT(_2DG_BRK_INT, 0x09A0),
457 /* SGX540 */
458 /* 2DDMAC */
459 /* IPMMU */
460 /* RTDMAC(2) */
461 /* KEYSC */
462 /* MSIOF */
463 INTCS_VECT(IIC0_ALI, 0x0E00),
464 INTCS_VECT(IIC0_TACKI, 0x0E20),
465 INTCS_VECT(IIC0_WAITI, 0x0E40),
466 INTCS_VECT(IIC0_DTEI, 0x0E60),
467 INTCS_VECT(TMU0_0, 0x0E80),
468 INTCS_VECT(TMU0_1, 0x0EA0),
469 INTCS_VECT(TMU0_2, 0x0EC0),
470 INTCS_VECT(CMT0, 0x0F00),
471 /* CMT2 */
472 INTCS_VECT(LMB, 0x0F60),
473 INTCS_VECT(CTI, 0x0400),
474 INTCS_VECT(VOU, 0x0420),
475 /* RWDT0 */
476 INTCS_VECT(ICB, 0x0480),
477 INTCS_VECT(VIO6C, 0x04E0),
478 INTCS_VECT(CEU20, 0x0500),
479 INTCS_VECT(CEU21, 0x0520),
480 INTCS_VECT(JPU, 0x0560),
481 INTCS_VECT(LCDC0, 0x0580),
482 INTCS_VECT(LCRC, 0x05A0),
483 /* RTDMAC2(1) */
484 /* RTDMAC2(2) */
485 INTCS_VECT(LCDC1, 0x1780),
486 /* SPU2 */
487 /* FSI */
488 /* FMSI */
489 INTCS_VECT(TMU1_0, 0x1900),
490 INTCS_VECT(TMU1_1, 0x1920),
491 INTCS_VECT(TMU1_2, 0x1940),
492 INTCS_VECT(CMT4, 0x1980),
493 INTCS_VECT(DISP, 0x19A0),
494 INTCS_VECT(DSRV, 0x19C0),
495 /* MFIS2 */
496 INTCS_VECT(CPORTS2R, 0x1A20),
497
498 INTC_VECT(INTCS, 0xf80),
499};
500
501static struct intc_group intcs_groups[] __initdata = {
502 INTC_GROUP(_2DG1, /*FIXME*/
503 _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP),
504 INTC_GROUP(IIC0,
505 IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI),
506 INTC_GROUP(TMU1,
507 TMU1_0, TMU1_1, TMU1_2),
508};
509
510static struct intc_mask_reg intcs_mask_registers[] = {
511 /* IMR0SA / IMCR0SA */ /* all 0 */
512 { /* IMR1SA / IMCR1SA */ 0xffd20184, 0xffd201c4, 8,
513 { _2DG_CER_INT, _2DG_GPM_INT, _2DG_TRAP, VPU5HA2,
514 0, 0, 0, 0 /*STPRO*/ } },
515 { /* IMR2SA / IMCR2SA */ 0xffd20188, 0xffd201c8, 8,
516 { 0/*STPRO*/, 0, CEU21, VPU5F,
517 0/*BBIF2*/, 0, 0, 0/*MFI*/ } },
518 { /* IMR3SA / IMCR3SA */ 0xffd2018c, 0xffd201cc, 8,
519 { 0, 0, 0, 0, /*2DDMAC*/
520 VIO6C, 0, 0, ICB } },
521 { /* IMR4SA / IMCR4SA */ 0xffd20190, 0xffd201d0, 8,
522 { 0, 0, VOU, CTI,
523 JPU, 0, LCRC, LCDC0 } },
524 /* IMR5SA / IMCR5SA */ /*KEYSC/RTDMAC2/RTDMAC1*/
525 /* IMR6SA / IMCR6SA */ /*MSIOF/SGX540*/
526 { /* IMR7SA / IMCR7SA */ 0xffd2019c, 0xffd201dc, 8,
527 { 0, TMU0_2, TMU0_1, TMU0_0,
528 0, 0, 0, 0 } },
529 { /* IMR8SA / IMCR8SA */ 0xffd201a0, 0xffd201e0, 8,
530 { 0, 0, 0, 0,
531 CEU20, 0, 0, 0 } },
532 { /* IMR9SA / IMCR9SA */ 0xffd201a4, 0xffd201e4, 8,
533 { 0, 0/*RWDT0*/, 0/*CMT2*/, CMT0,
534 0, 0, 0, 0 } },
535 /* IMR10SA / IMCR10SA */ /*IPMMU*/
536 { /* IMR11SA / IMCR11SA */ 0xffd201ac, 0xffd201ec, 8,
537 { IIC0_DTEI, IIC0_WAITI, IIC0_TACKI, IIC0_ALI,
538 0, _2DG_BRK_INT, LMB, 0 } },
539 /* IMR12SA / IMCR12SA */
540 /* IMR13SA / IMCR13SA */
541 /* IMR0SA3 / IMCR0SA3 */ /*RTDMAC2(1)/RTDMAC2(2)*/
542 /* IMR1SA3 / IMCR1SA3 */
543 /* IMR2SA3 / IMCR2SA3 */
544 /* IMR3SA3 / IMCR3SA3 */
545 { /* IMR4SA3 / IMCR4SA3 */ 0xffd50190, 0xffd501d0, 8,
546 { 0, 0, 0, 0,
547 LCDC1, 0, 0, 0 } },
548 /* IMR5SA3 / IMCR5SA3 */ /* SPU2/FSI/FMSI */
549 { /* IMR6SA3 / IMCR6SA3 */ 0xffd50198, 0xffd501d8, 8,
550 { TMU1_0, TMU1_1, TMU1_2, 0,
551 CMT4, DISP, DSRV, 0 } },
552 { /* IMR7SA3 / IMCR7SA3 */ 0xffd5019c, 0xffd501dc, 8,
553 { 0/*MFIS2*/, CPORTS2R, 0, 0,
554 0, 0, 0, 0 } },
555 { /* INTAMASK */ 0xffd20104, 0, 16,
556 { 0, 0, 0, 0, 0, 0, 0, 0,
557 0, 0, 0, 0, 0, 0, 0, INTCS } },
558};
559
560/* Priority is needed for INTCA to receive the INTCS interrupt */
561static struct intc_prio_reg intcs_prio_registers[] = {
562 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, VOU, 0/*2DDMAC*/, ICB } },
563 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU, LCDC0, 0, LCRC } },
564 /* IPRCS */ /*BBIF2*/
565 /* IPRDS */
566 { 0xffd20010, 0, 16, 4, /* IPRES */ { 0/*RTDMAC(1)*/, VPU5HA2,
567 0/*MFI*/, VPU5F } },
568 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0/*KEYSC*/, 0/*RTDMAC(2)*/,
569 0/*CMT2*/, CMT0 } },
570 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU0_0, TMU0_1,
571 TMU0_2, _2DG1 } },
572 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0/*STPRO*/, 0/*STPRO*/,
573 _2DG_BRK_INT/*FIXME*/ } },
574 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, 0/*MSIOF*/, 0, IIC0 } },
575 { 0xffd20024, 0, 16, 4, /* IPRJS */ { CEU20, 0/*SGX540*/, 0, 0 } },
576 { 0xffd20028, 0, 16, 4, /* IPRKS */ { VIO6C, 0, LMB, 0 } },
577 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { 0/*IPMMU*/, 0, CEU21, 0 } },
578 /* IPRMS */ /*RWDT0*/
579 /* IPRAS3 */ /*RTDMAC2(1)*/
580 /* IPRBS3 */ /*RTDMAC2(2)*/
581 /* IPRCS3 */
582 /* IPRDS3 */
583 /* IPRES3 */
584 /* IPRFS3 */
585 /* IPRGS3 */
586 /* IPRHS3 */
587 /* IPRIS3 */
588 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, 0, 0, 0 } },
589 /* IPRKS3 */ /*SPU2/FSI/FMSi*/
590 /* IPRLS3 */
591 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
592 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DISP, DSRV, 0 } },
593 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { 0/*MFIS2*/, CPORTS2R, 0, 0 } },
594 /* IPRPS3 */
595};
596
597static struct resource intcs_resources[] __initdata = {
598 [0] = {
599 .start = 0xffd20000,
600 .end = 0xffd201ff,
601 .flags = IORESOURCE_MEM,
602 },
603 [1] = {
604 .start = 0xffd50000,
605 .end = 0xffd501ff,
606 .flags = IORESOURCE_MEM,
607 }
608};
609
610static struct intc_desc intcs_desc __initdata = {
611 .name = "r8a7740-intcs",
612 .resource = intcs_resources,
613 .num_resources = ARRAY_SIZE(intcs_resources),
614 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
615 intcs_prio_registers, NULL, NULL),
616};
617
618static void intcs_demux(unsigned int irq, struct irq_desc *desc)
619{
620 void __iomem *reg = (void *)irq_get_handler_data(irq);
621 unsigned int evtcodeas = ioread32(reg);
622
623 generic_handle_irq(intcs_evt2irq(evtcodeas));
624}
625 24
626void __init r8a7740_init_irq(void) 25void __init r8a7740_init_irq(void)
627{ 26{
628 void __iomem *intevtsa = ioremap_nocache(0xffd20100, PAGE_SIZE); 27 void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
629 28 void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
630 register_intc_controller(&intca_desc); 29 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
631 register_intc_controller(&intca_irq_pins_desc); 30 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
632 register_intc_controller(&intcs_desc); 31 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
633 32
634 /* demux using INTEVTSA */ 33 /* initialize the Generic Interrupt Controller PL390 r0p0 */
635 irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa); 34 gic_init(0, 29, gic_dist_base, gic_cpu_base);
636 irq_set_chained_handler(evt2irq(0xf80), intcs_demux); 35
36 /* route signals to GIC */
37 iowrite32(0x0, pfc_inta_ctrl);
38
39 /*
40 * To mask the shared interrupt to SPI 149 we must ensure to set
41 * PRIO *and* MASK. Else we run into IRQ floods when registering
42 * the intc_irqpin devices
43 */
44 iowrite32(0x0, intc_prio_base + 0x0);
45 iowrite32(0x0, intc_prio_base + 0x4);
46 iowrite32(0x0, intc_prio_base + 0x8);
47 iowrite32(0x0, intc_prio_base + 0xc);
48 iowrite8(0xff, intc_msk_base + 0x0);
49 iowrite8(0xff, intc_msk_base + 0x4);
50 iowrite8(0xff, intc_msk_base + 0x8);
51 iowrite8(0xff, intc_msk_base + 0xc);
52
53 iounmap(intc_prio_base);
54 iounmap(intc_msk_base);
55 iounmap(pfc_inta_ctrl);
637} 56}
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 8b85d4d8fab6..228d7aba4a7c 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -22,6 +22,7 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/platform_data/irq-renesas-intc-irqpin.h>
25#include <linux/platform_device.h> 26#include <linux/platform_device.h>
26#include <linux/of_platform.h> 27#include <linux/of_platform.h>
27#include <linux/serial_sci.h> 28#include <linux/serial_sci.h>
@@ -94,6 +95,126 @@ void __init r8a7740_pinmux_init(void)
94 platform_device_register(&r8a7740_pfc_device); 95 platform_device_register(&r8a7740_pfc_device);
95} 96}
96 97
98static struct renesas_intc_irqpin_config irqpin0_platform_data = {
99 .irq_base = irq_pin(0), /* IRQ0 -> IRQ7 */
100};
101
102static struct resource irqpin0_resources[] = {
103 DEFINE_RES_MEM(0xe6900000, 4), /* ICR1A */
104 DEFINE_RES_MEM(0xe6900010, 4), /* INTPRI00A */
105 DEFINE_RES_MEM(0xe6900020, 1), /* INTREQ00A */
106 DEFINE_RES_MEM(0xe6900040, 1), /* INTMSK00A */
107 DEFINE_RES_MEM(0xe6900060, 1), /* INTMSKCLR00A */
108 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ0 */
109 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ1 */
110 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ2 */
111 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ3 */
112 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ4 */
113 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ5 */
114 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ6 */
115 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ7 */
116};
117
118static struct platform_device irqpin0_device = {
119 .name = "renesas_intc_irqpin",
120 .id = 0,
121 .resource = irqpin0_resources,
122 .num_resources = ARRAY_SIZE(irqpin0_resources),
123 .dev = {
124 .platform_data = &irqpin0_platform_data,
125 },
126};
127
128static struct renesas_intc_irqpin_config irqpin1_platform_data = {
129 .irq_base = irq_pin(8), /* IRQ8 -> IRQ15 */
130};
131
132static struct resource irqpin1_resources[] = {
133 DEFINE_RES_MEM(0xe6900004, 4), /* ICR2A */
134 DEFINE_RES_MEM(0xe6900014, 4), /* INTPRI10A */
135 DEFINE_RES_MEM(0xe6900024, 1), /* INTREQ10A */
136 DEFINE_RES_MEM(0xe6900044, 1), /* INTMSK10A */
137 DEFINE_RES_MEM(0xe6900064, 1), /* INTMSKCLR10A */
138 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ8 */
139 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ9 */
140 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ10 */
141 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ11 */
142 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ12 */
143 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ13 */
144 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ14 */
145 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ15 */
146};
147
148static struct platform_device irqpin1_device = {
149 .name = "renesas_intc_irqpin",
150 .id = 1,
151 .resource = irqpin1_resources,
152 .num_resources = ARRAY_SIZE(irqpin1_resources),
153 .dev = {
154 .platform_data = &irqpin1_platform_data,
155 },
156};
157
158static struct renesas_intc_irqpin_config irqpin2_platform_data = {
159 .irq_base = irq_pin(16), /* IRQ16 -> IRQ23 */
160};
161
162static struct resource irqpin2_resources[] = {
163 DEFINE_RES_MEM(0xe6900008, 4), /* ICR3A */
164 DEFINE_RES_MEM(0xe6900018, 4), /* INTPRI30A */
165 DEFINE_RES_MEM(0xe6900028, 1), /* INTREQ30A */
166 DEFINE_RES_MEM(0xe6900048, 1), /* INTMSK30A */
167 DEFINE_RES_MEM(0xe6900068, 1), /* INTMSKCLR30A */
168 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ16 */
169 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ17 */
170 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ18 */
171 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ19 */
172 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ20 */
173 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ21 */
174 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ22 */
175 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ23 */
176};
177
178static struct platform_device irqpin2_device = {
179 .name = "renesas_intc_irqpin",
180 .id = 2,
181 .resource = irqpin2_resources,
182 .num_resources = ARRAY_SIZE(irqpin2_resources),
183 .dev = {
184 .platform_data = &irqpin2_platform_data,
185 },
186};
187
188static struct renesas_intc_irqpin_config irqpin3_platform_data = {
189 .irq_base = irq_pin(24), /* IRQ24 -> IRQ31 */
190};
191
192static struct resource irqpin3_resources[] = {
193 DEFINE_RES_MEM(0xe690000c, 4), /* ICR3A */
194 DEFINE_RES_MEM(0xe690001c, 4), /* INTPRI30A */
195 DEFINE_RES_MEM(0xe690002c, 1), /* INTREQ30A */
196 DEFINE_RES_MEM(0xe690004c, 1), /* INTMSK30A */
197 DEFINE_RES_MEM(0xe690006c, 1), /* INTMSKCLR30A */
198 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ24 */
199 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ25 */
200 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ26 */
201 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ27 */
202 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ28 */
203 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ29 */
204 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ30 */
205 DEFINE_RES_IRQ(gic_spi(149)), /* IRQ31 */
206};
207
208static struct platform_device irqpin3_device = {
209 .name = "renesas_intc_irqpin",
210 .id = 3,
211 .resource = irqpin3_resources,
212 .num_resources = ARRAY_SIZE(irqpin3_resources),
213 .dev = {
214 .platform_data = &irqpin3_platform_data,
215 },
216};
217
97/* SCIFA0 */ 218/* SCIFA0 */
98static struct plat_sci_port scif0_platform_data = { 219static struct plat_sci_port scif0_platform_data = {
99 .mapbase = 0xe6c40000, 220 .mapbase = 0xe6c40000,
@@ -101,7 +222,7 @@ static struct plat_sci_port scif0_platform_data = {
101 .scscr = SCSCR_RE | SCSCR_TE, 222 .scscr = SCSCR_RE | SCSCR_TE,
102 .scbrr_algo_id = SCBRR_ALGO_4, 223 .scbrr_algo_id = SCBRR_ALGO_4,
103 .type = PORT_SCIFA, 224 .type = PORT_SCIFA,
104 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c00)), 225 .irqs = SCIx_IRQ_MUXED(gic_spi(100)),
105}; 226};
106 227
107static struct platform_device scif0_device = { 228static struct platform_device scif0_device = {
@@ -119,7 +240,7 @@ static struct plat_sci_port scif1_platform_data = {
119 .scscr = SCSCR_RE | SCSCR_TE, 240 .scscr = SCSCR_RE | SCSCR_TE,
120 .scbrr_algo_id = SCBRR_ALGO_4, 241 .scbrr_algo_id = SCBRR_ALGO_4,
121 .type = PORT_SCIFA, 242 .type = PORT_SCIFA,
122 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c20)), 243 .irqs = SCIx_IRQ_MUXED(gic_spi(101)),
123}; 244};
124 245
125static struct platform_device scif1_device = { 246static struct platform_device scif1_device = {
@@ -137,7 +258,7 @@ static struct plat_sci_port scif2_platform_data = {
137 .scscr = SCSCR_RE | SCSCR_TE, 258 .scscr = SCSCR_RE | SCSCR_TE,
138 .scbrr_algo_id = SCBRR_ALGO_4, 259 .scbrr_algo_id = SCBRR_ALGO_4,
139 .type = PORT_SCIFA, 260 .type = PORT_SCIFA,
140 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c40)), 261 .irqs = SCIx_IRQ_MUXED(gic_spi(102)),
141}; 262};
142 263
143static struct platform_device scif2_device = { 264static struct platform_device scif2_device = {
@@ -155,7 +276,7 @@ static struct plat_sci_port scif3_platform_data = {
155 .scscr = SCSCR_RE | SCSCR_TE, 276 .scscr = SCSCR_RE | SCSCR_TE,
156 .scbrr_algo_id = SCBRR_ALGO_4, 277 .scbrr_algo_id = SCBRR_ALGO_4,
157 .type = PORT_SCIFA, 278 .type = PORT_SCIFA,
158 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0c60)), 279 .irqs = SCIx_IRQ_MUXED(gic_spi(103)),
159}; 280};
160 281
161static struct platform_device scif3_device = { 282static struct platform_device scif3_device = {
@@ -173,7 +294,7 @@ static struct plat_sci_port scif4_platform_data = {
173 .scscr = SCSCR_RE | SCSCR_TE, 294 .scscr = SCSCR_RE | SCSCR_TE,
174 .scbrr_algo_id = SCBRR_ALGO_4, 295 .scbrr_algo_id = SCBRR_ALGO_4,
175 .type = PORT_SCIFA, 296 .type = PORT_SCIFA,
176 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d20)), 297 .irqs = SCIx_IRQ_MUXED(gic_spi(104)),
177}; 298};
178 299
179static struct platform_device scif4_device = { 300static struct platform_device scif4_device = {
@@ -191,7 +312,7 @@ static struct plat_sci_port scif5_platform_data = {
191 .scscr = SCSCR_RE | SCSCR_TE, 312 .scscr = SCSCR_RE | SCSCR_TE,
192 .scbrr_algo_id = SCBRR_ALGO_4, 313 .scbrr_algo_id = SCBRR_ALGO_4,
193 .type = PORT_SCIFA, 314 .type = PORT_SCIFA,
194 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d40)), 315 .irqs = SCIx_IRQ_MUXED(gic_spi(105)),
195}; 316};
196 317
197static struct platform_device scif5_device = { 318static struct platform_device scif5_device = {
@@ -209,7 +330,7 @@ static struct plat_sci_port scif6_platform_data = {
209 .scscr = SCSCR_RE | SCSCR_TE, 330 .scscr = SCSCR_RE | SCSCR_TE,
210 .scbrr_algo_id = SCBRR_ALGO_4, 331 .scbrr_algo_id = SCBRR_ALGO_4,
211 .type = PORT_SCIFA, 332 .type = PORT_SCIFA,
212 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04c0)), 333 .irqs = SCIx_IRQ_MUXED(gic_spi(106)),
213}; 334};
214 335
215static struct platform_device scif6_device = { 336static struct platform_device scif6_device = {
@@ -227,7 +348,7 @@ static struct plat_sci_port scif7_platform_data = {
227 .scscr = SCSCR_RE | SCSCR_TE, 348 .scscr = SCSCR_RE | SCSCR_TE,
228 .scbrr_algo_id = SCBRR_ALGO_4, 349 .scbrr_algo_id = SCBRR_ALGO_4,
229 .type = PORT_SCIFA, 350 .type = PORT_SCIFA,
230 .irqs = SCIx_IRQ_MUXED(evt2irq(0x04e0)), 351 .irqs = SCIx_IRQ_MUXED(gic_spi(107)),
231}; 352};
232 353
233static struct platform_device scif7_device = { 354static struct platform_device scif7_device = {
@@ -245,7 +366,7 @@ static struct plat_sci_port scifb_platform_data = {
245 .scscr = SCSCR_RE | SCSCR_TE, 366 .scscr = SCSCR_RE | SCSCR_TE,
246 .scbrr_algo_id = SCBRR_ALGO_4, 367 .scbrr_algo_id = SCBRR_ALGO_4,
247 .type = PORT_SCIFB, 368 .type = PORT_SCIFB,
248 .irqs = SCIx_IRQ_MUXED(evt2irq(0x0d60)), 369 .irqs = SCIx_IRQ_MUXED(gic_spi(108)),
249}; 370};
250 371
251static struct platform_device scifb_device = { 372static struct platform_device scifb_device = {
@@ -273,7 +394,7 @@ static struct resource cmt10_resources[] = {
273 .flags = IORESOURCE_MEM, 394 .flags = IORESOURCE_MEM,
274 }, 395 },
275 [1] = { 396 [1] = {
276 .start = evt2irq(0x0b00), 397 .start = gic_spi(58),
277 .flags = IORESOURCE_IRQ, 398 .flags = IORESOURCE_IRQ,
278 }, 399 },
279}; 400};
@@ -304,7 +425,7 @@ static struct resource tmu00_resources[] = {
304 .flags = IORESOURCE_MEM, 425 .flags = IORESOURCE_MEM,
305 }, 426 },
306 [1] = { 427 [1] = {
307 .start = intcs_evt2irq(0xe80), 428 .start = gic_spi(198),
308 .flags = IORESOURCE_IRQ, 429 .flags = IORESOURCE_IRQ,
309 }, 430 },
310}; 431};
@@ -334,7 +455,7 @@ static struct resource tmu01_resources[] = {
334 .flags = IORESOURCE_MEM, 455 .flags = IORESOURCE_MEM,
335 }, 456 },
336 [1] = { 457 [1] = {
337 .start = intcs_evt2irq(0xea0), 458 .start = gic_spi(199),
338 .flags = IORESOURCE_IRQ, 459 .flags = IORESOURCE_IRQ,
339 }, 460 },
340}; 461};
@@ -364,7 +485,7 @@ static struct resource tmu02_resources[] = {
364 .flags = IORESOURCE_MEM, 485 .flags = IORESOURCE_MEM,
365 }, 486 },
366 [1] = { 487 [1] = {
367 .start = intcs_evt2irq(0xec0), 488 .start = gic_spi(200),
368 .flags = IORESOURCE_IRQ, 489 .flags = IORESOURCE_IRQ,
369 }, 490 },
370}; 491};
@@ -411,6 +532,10 @@ static struct platform_device ipmmu_device = {
411}; 532};
412 533
413static struct platform_device *r8a7740_early_devices[] __initdata = { 534static struct platform_device *r8a7740_early_devices[] __initdata = {
535 &irqpin0_device,
536 &irqpin1_device,
537 &irqpin2_device,
538 &irqpin3_device,
414 &scif0_device, 539 &scif0_device,
415 &scif1_device, 540 &scif1_device,
416 &scif2_device, 541 &scif2_device,
@@ -525,14 +650,14 @@ static struct resource r8a7740_dmae0_resources[] = {
525 }, 650 },
526 { 651 {
527 .name = "error_irq", 652 .name = "error_irq",
528 .start = evt2irq(0x20c0), 653 .start = gic_spi(34),
529 .end = evt2irq(0x20c0), 654 .end = gic_spi(34),
530 .flags = IORESOURCE_IRQ, 655 .flags = IORESOURCE_IRQ,
531 }, 656 },
532 { 657 {
533 /* IRQ for channels 0-5 */ 658 /* IRQ for channels 0-5 */
534 .start = evt2irq(0x2000), 659 .start = gic_spi(28),
535 .end = evt2irq(0x20a0), 660 .end = gic_spi(33),
536 .flags = IORESOURCE_IRQ, 661 .flags = IORESOURCE_IRQ,
537 }, 662 },
538}; 663};
@@ -553,14 +678,14 @@ static struct resource r8a7740_dmae1_resources[] = {
553 }, 678 },
554 { 679 {
555 .name = "error_irq", 680 .name = "error_irq",
556 .start = evt2irq(0x21c0), 681 .start = gic_spi(41),
557 .end = evt2irq(0x21c0), 682 .end = gic_spi(41),
558 .flags = IORESOURCE_IRQ, 683 .flags = IORESOURCE_IRQ,
559 }, 684 },
560 { 685 {
561 /* IRQ for channels 0-5 */ 686 /* IRQ for channels 0-5 */
562 .start = evt2irq(0x2100), 687 .start = gic_spi(35),
563 .end = evt2irq(0x21a0), 688 .end = gic_spi(40),
564 .flags = IORESOURCE_IRQ, 689 .flags = IORESOURCE_IRQ,
565 }, 690 },
566}; 691};
@@ -581,14 +706,14 @@ static struct resource r8a7740_dmae2_resources[] = {
581 }, 706 },
582 { 707 {
583 .name = "error_irq", 708 .name = "error_irq",
584 .start = evt2irq(0x22c0), 709 .start = gic_spi(48),
585 .end = evt2irq(0x22c0), 710 .end = gic_spi(48),
586 .flags = IORESOURCE_IRQ, 711 .flags = IORESOURCE_IRQ,
587 }, 712 },
588 { 713 {
589 /* IRQ for channels 0-5 */ 714 /* IRQ for channels 0-5 */
590 .start = evt2irq(0x2200), 715 .start = gic_spi(42),
591 .end = evt2irq(0x22a0), 716 .end = gic_spi(47),
592 .flags = IORESOURCE_IRQ, 717 .flags = IORESOURCE_IRQ,
593 }, 718 },
594}; 719};
@@ -677,8 +802,8 @@ static struct resource r8a7740_usb_dma_resources[] = {
677 }, 802 },
678 { 803 {
679 /* IRQ for channels */ 804 /* IRQ for channels */
680 .start = evt2irq(0x0a00), 805 .start = gic_spi(49),
681 .end = evt2irq(0x0a00), 806 .end = gic_spi(49),
682 .flags = IORESOURCE_IRQ, 807 .flags = IORESOURCE_IRQ,
683 }, 808 },
684}; 809};
@@ -702,8 +827,8 @@ static struct resource i2c0_resources[] = {
702 .flags = IORESOURCE_MEM, 827 .flags = IORESOURCE_MEM,
703 }, 828 },
704 [1] = { 829 [1] = {
705 .start = intcs_evt2irq(0xe00), 830 .start = gic_spi(201),
706 .end = intcs_evt2irq(0xe60), 831 .end = gic_spi(204),
707 .flags = IORESOURCE_IRQ, 832 .flags = IORESOURCE_IRQ,
708 }, 833 },
709}; 834};
@@ -716,8 +841,8 @@ static struct resource i2c1_resources[] = {
716 .flags = IORESOURCE_MEM, 841 .flags = IORESOURCE_MEM,
717 }, 842 },
718 [1] = { 843 [1] = {
719 .start = evt2irq(0x780), /* IIC1_ALI1 */ 844 .start = gic_spi(70), /* IIC1_ALI1 */
720 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */ 845 .end = gic_spi(73), /* IIC1_DTEI1 */
721 .flags = IORESOURCE_IRQ, 846 .flags = IORESOURCE_IRQ,
722 }, 847 },
723}; 848};
@@ -738,8 +863,8 @@ static struct platform_device i2c1_device = {
738 863
739static struct resource pmu_resources[] = { 864static struct resource pmu_resources[] = {
740 [0] = { 865 [0] = {
741 .start = evt2irq(0x19a0), 866 .start = gic_spi(83),
742 .end = evt2irq(0x19a0), 867 .end = gic_spi(83),
743 .flags = IORESOURCE_IRQ, 868 .flags = IORESOURCE_IRQ,
744 }, 869 },
745}; 870};
@@ -904,7 +1029,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
904 .map_io = r8a7740_map_io, 1029 .map_io = r8a7740_map_io,
905 .init_early = r8a7740_add_early_devices_dt, 1030 .init_early = r8a7740_add_early_devices_dt,
906 .init_irq = r8a7740_init_irq, 1031 .init_irq = r8a7740_init_irq,
907 .handle_irq = shmobile_handle_irq_intc,
908 .init_machine = r8a7740_add_standard_devices_dt, 1032 .init_machine = r8a7740_add_standard_devices_dt,
909 .init_time = shmobile_timer_init, 1033 .init_time = shmobile_timer_init,
910 .dt_compat = r8a7740_boards_compat_dt, 1034 .dt_compat = r8a7740_boards_compat_dt,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 214788c4a606..2b528280e3c1 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -2545,38 +2545,38 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2545}; 2545};
2546 2546
2547static struct pinmux_irq pinmux_irqs[] = { 2547static struct pinmux_irq pinmux_irqs[] = {
2548 PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */ 2548 PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */
2549 PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */ 2549 PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */
2550 PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */ 2550 PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */
2551 PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */ 2551 PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */
2552 PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */ 2552 PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */
2553 PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */ 2553 PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */
2554 PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */ 2554 PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
2555 PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */ 2555 PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
2556 PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */ 2556 PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */
2557 PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */ 2557 PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
2558 PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */ 2558 PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */
2559 PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */ 2559 PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */
2560 PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */ 2560 PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */
2561 PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */ 2561 PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */
2562 PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */ 2562 PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */
2563 PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */ 2563 PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */
2564 PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */ 2564 PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */
2565 PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */ 2565 PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */
2566 PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */ 2566 PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */
2567 PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */ 2567 PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */
2568 PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */ 2568 PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */
2569 PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */ 2569 PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */
2570 PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */ 2570 PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */
2571 PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */ 2571 PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */
2572 PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */ 2572 PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */
2573 PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */ 2573 PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */
2574 PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */ 2574 PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */
2575 PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */ 2575 PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */
2576 PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */ 2576 PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */
2577 PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */ 2577 PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */
2578 PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */ 2578 PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */
2579 PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */ 2579 PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */
2580}; 2580};
2581 2581
2582struct sh_pfc_soc_info r8a7740_pinmux_info = { 2582struct sh_pfc_soc_info r8a7740_pinmux_info = {
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-18 05:14:53 -0400