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authorOlof Johansson <olof@lixom.net>2014-05-21 17:45:05 -0400
committerOlof Johansson <olof@lixom.net>2014-05-21 17:45:05 -0400
commit0b3534be6580b8b72997e5c37a921103b8885cc1 (patch)
tree876774dc6f1a8693d7bc430034746f344914443c
parent16ae66cc33c4ee3a0b3d3bb5d444aefa18134b37 (diff)
parent46ae42498ef6febdaa6b51359f1ede38cd6b5a47 (diff)
Merge tag 'imx-soc-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
Merge "ARM: imx: soc changes for 3.16" from Shawn Guo: i.MX SoC changes for 3.16: - A few cleanups on mx21ads board file, which should make the later conversion to DT a little bit easier. - Add some missing clocks and drop unused clk lookups for i.MX1 and i.MX27 clock drivers - Add initial i.MX SoloX (imx6sx) SoC support - Remove mx51_babbage and mach-cpuimx51sd board files, as the equivalent DT support is ready for the boards - Clean up device tree timer initialization a little bit - Add missing i2c4 clock for i.MX6 DualLite/Solo - Add missing CKO clock i.MX25 - Add shared gate clock support for i.MX specific clk_gate2 - Add low-level debug support for SoC VF610 - Some random code cleanups and defconfig updates * tag 'imx-soc-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (33 commits) ARM: mx25: Add CLKO support ARM: i.MX1 clk: Remove clk_register_clkdev() for unused clocks ARM: i.MX1 clk: Add missing clocks ARM: imx: add basic imx6sx SoC support ARM: imx: add clock driver for imx6sx ARM: imx: add low-level debug support for imx6sx ARM: mx51: Remove mach-cpuimx51sd board file ARM: i.MX: Setup IRQ handler from IRQ driver ARM: i.MX27 pca100: remove deprecated IRQF_DISABLED ARM: imx/mxs defconfigs: add MTD_SPI_NOR (new dependency for M25P80) ARM: i.MX: Fix eMMa PrP resource size ARM: imx_v4_v5_defconfig: drop CONFIG_COMMON_CLK_DEBUG option ARM: i.MX27 clk: Remove clk_register_clkdev() for unused clocks ARM: i.MX27 clk: Add missing clocks for MSHC and RTIC ARM: imx6q: add the missing esai_ahb clock ARM: imx: add shared gate clock support ARM: imx: lock is always valid for clk_gate2 ARM: imx: define struct clk_gate2 on our own ARM: i.MX: Remove #ifdef CONFIG_OF ARM: imx_v6_v7_defconfig: enable option CONFIG_LOCALVERSION_AUTO ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/imx25-clock.txt3
-rw-r--r--Documentation/devicetree/bindings/clock/imx27-clock.txt7
-rw-r--r--Documentation/devicetree/bindings/clock/imx6q-clock.txt1
-rw-r--r--Documentation/devicetree/bindings/clock/imx6sx-clock.txt13
-rw-r--r--arch/arm/Kconfig.debug22
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig8
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig12
-rw-r--r--arch/arm/configs/mxs_defconfig7
-rw-r--r--arch/arm/include/debug/imx-uart.h11
-rw-r--r--arch/arm/include/debug/vf.S15
-rw-r--r--arch/arm/mach-imx/Kconfig69
-rw-r--r--arch/arm/mach-imx/Makefile6
-rw-r--r--arch/arm/mach-imx/avic.c4
-rw-r--r--arch/arm/mach-imx/clk-gate2.c47
-rw-r--r--arch/arm/mach-imx/clk-imx1.c41
-rw-r--r--arch/arm/mach-imx/clk-imx25.c24
-rw-r--r--arch/arm/mach-imx/clk-imx27.c27
-rw-r--r--arch/arm/mach-imx/clk-imx31.c2
-rw-r--r--arch/arm/mach-imx/clk-imx51-imx53.c20
-rw-r--r--arch/arm/mach-imx/clk-imx6q.c21
-rw-r--r--arch/arm/mach-imx/clk-imx6sl.c6
-rw-r--r--arch/arm/mach-imx/clk-imx6sx.c524
-rw-r--r--arch/arm/mach-imx/clk.h13
-rw-r--r--arch/arm/mach-imx/common.h15
-rw-r--r--arch/arm/mach-imx/cpu.c3
-rw-r--r--arch/arm/mach-imx/devices/platform-mx2-emma.c2
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c231
-rw-r--r--arch/arm/mach-imx/imx25-dt.c1
-rw-r--r--arch/arm/mach-imx/imx27-dt.c1
-rw-r--r--arch/arm/mach-imx/imx31-dt.c1
-rw-r--r--arch/arm/mach-imx/imx35-dt.c1
-rw-r--r--arch/arm/mach-imx/imx51-dt.c1
-rw-r--r--arch/arm/mach-imx/mach-apf9328.c1
-rw-r--r--arch/arm/mach-imx/mach-armadillo5x0.c1
-rw-r--r--arch/arm/mach-imx/mach-bug.c1
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c1
-rw-r--r--arch/arm/mach-imx/mach-cpuimx35.c1
-rw-r--r--arch/arm/mach-imx/mach-cpuimx51sd.c364
-rw-r--r--arch/arm/mach-imx/mach-eukrea_cpuimx25.c1
-rw-r--r--arch/arm/mach-imx/mach-imx27_visstrim_m10.c1
-rw-r--r--arch/arm/mach-imx/mach-imx27ipcam.c1
-rw-r--r--arch/arm/mach-imx/mach-imx27lite.c1
-rw-r--r--arch/arm/mach-imx/mach-imx50.c1
-rw-r--r--arch/arm/mach-imx/mach-imx53.c1
-rw-r--r--arch/arm/mach-imx/mach-imx6sx.c51
-rw-r--r--arch/arm/mach-imx/mach-kzm_arm11_01.c1
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c2
-rw-r--r--arch/arm/mach-imx/mach-mx21ads.c174
-rw-r--r--arch/arm/mach-imx/mach-mx25_3ds.c1
-rw-r--r--arch/arm/mach-imx/mach-mx27_3ds.c1
-rw-r--r--arch/arm/mach-imx/mach-mx27ads.c1
-rw-r--r--arch/arm/mach-imx/mach-mx31_3ds.c1
-rw-r--r--arch/arm/mach-imx/mach-mx31ads.c1
-rw-r--r--arch/arm/mach-imx/mach-mx31lilly.c1
-rw-r--r--arch/arm/mach-imx/mach-mx31lite.c1
-rw-r--r--arch/arm/mach-imx/mach-mx31moboard.c1
-rw-r--r--arch/arm/mach-imx/mach-mx35_3ds.c1
-rw-r--r--arch/arm/mach-imx/mach-mx51_babbage.c428
-rw-r--r--arch/arm/mach-imx/mach-mxt_td60.c1
-rw-r--r--arch/arm/mach-imx/mach-pca100.c4
-rw-r--r--arch/arm/mach-imx/mach-pcm037.c1
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c1
-rw-r--r--arch/arm/mach-imx/mach-pcm043.c1
-rw-r--r--arch/arm/mach-imx/mach-qong.c1
-rw-r--r--arch/arm/mach-imx/mach-scb9328.c1
-rw-r--r--arch/arm/mach-imx/mach-vpr200.c1
-rw-r--r--arch/arm/mach-imx/mxc.h6
-rw-r--r--arch/arm/mach-imx/time.c15
-rw-r--r--arch/arm/mach-imx/tzic.c4
-rw-r--r--include/dt-bindings/clock/imx6sx-clock.h256
70 files changed, 1152 insertions, 1339 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx25-clock.txt b/Documentation/devicetree/bindings/clock/imx25-clock.txt
index db4f2f05c4d0..ba6b312ff8a5 100644
--- a/Documentation/devicetree/bindings/clock/imx25-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx25-clock.txt
@@ -139,6 +139,9 @@ clocks and IDs.
139 uart5_ipg 124 139 uart5_ipg 124
140 reserved 125 140 reserved 125
141 wdt_ipg 126 141 wdt_ipg 126
142 cko_div 127
143 cko_sel 128
144 cko 129
142 145
143Examples: 146Examples:
144 147
diff --git a/Documentation/devicetree/bindings/clock/imx27-clock.txt b/Documentation/devicetree/bindings/clock/imx27-clock.txt
index 7a2070393732..6bc9fd2c6631 100644
--- a/Documentation/devicetree/bindings/clock/imx27-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx27-clock.txt
@@ -98,7 +98,12 @@ clocks and IDs.
98 fpm 83 98 fpm 83
99 mpll_osc_sel 84 99 mpll_osc_sel 84
100 mpll_sel 85 100 mpll_sel 85
101 spll_gate 86 101 spll_gate 86
102 mshc_div 87
103 rtic_ipg_gate 88
104 mshc_ipg_gate 89
105 rtic_ahb_gate 90
106 mshc_baud_gate 91
102 107
103Examples: 108Examples:
104 109
diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 6aab72bf67ea..90ec91fe5ce0 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -220,6 +220,7 @@ clocks and IDs.
220 lvds2_sel 205 220 lvds2_sel 205
221 lvds1_gate 206 221 lvds1_gate 206
222 lvds2_gate 207 222 lvds2_gate 207
223 esai_ahb 208
223 224
224Examples: 225Examples:
225 226
diff --git a/Documentation/devicetree/bindings/clock/imx6sx-clock.txt b/Documentation/devicetree/bindings/clock/imx6sx-clock.txt
new file mode 100644
index 000000000000..22362b9b7ba3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/imx6sx-clock.txt
@@ -0,0 +1,13 @@
1* Clock bindings for Freescale i.MX6 SoloX
2
3Required properties:
4- compatible: Should be "fsl,imx6sx-ccm"
5- reg: Address and length of the register set
6- #clock-cells: Should be <1>
7- clocks: list of clock specifiers, must contain an entry for each required
8 entry in clock-names
9- clock-names: should include entries "ckil", "osc", "ipp_di0" and "ipp_di1"
10
11The clock consumer should specify the desired clock by having the clock
12ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx6sx-clock.h
13for the full list of i.MX6 SoloX clock IDs.
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index eab8ecbe69c1..4dd565f84f6f 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -317,6 +317,13 @@ choice
317 Say Y here if you want kernel low-level debugging support 317 Say Y here if you want kernel low-level debugging support
318 on i.MX6SL. 318 on i.MX6SL.
319 319
320 config DEBUG_IMX6SX_UART
321 bool "i.MX6SX Debug UART"
322 depends on SOC_IMX6SX
323 help
324 Say Y here if you want kernel low-level debugging support
325 on i.MX6SX.
326
320 config DEBUG_KEYSTONE_UART0 327 config DEBUG_KEYSTONE_UART0
321 bool "Kernel low-level debugging on KEYSTONE2 using UART0" 328 bool "Kernel low-level debugging on KEYSTONE2 using UART0"
322 depends on ARCH_KEYSTONE 329 depends on ARCH_KEYSTONE
@@ -935,13 +942,23 @@ config DEBUG_IMX_UART_PORT
935 DEBUG_IMX51_UART || \ 942 DEBUG_IMX51_UART || \
936 DEBUG_IMX53_UART || \ 943 DEBUG_IMX53_UART || \
937 DEBUG_IMX6Q_UART || \ 944 DEBUG_IMX6Q_UART || \
938 DEBUG_IMX6SL_UART 945 DEBUG_IMX6SL_UART || \
946 DEBUG_IMX6SX_UART
939 default 1 947 default 1
940 depends on ARCH_MXC 948 depends on ARCH_MXC
941 help 949 help
942 Choose UART port on which kernel low-level debug messages 950 Choose UART port on which kernel low-level debug messages
943 should be output. 951 should be output.
944 952
953config DEBUG_VF_UART_PORT
954 int "Vybrid Debug UART Port Selection" if DEBUG_VF_UART
955 default 1
956 range 0 3
957 depends on SOC_VF610
958 help
959 Choose UART port on which kernel low-level debug messages
960 should be output.
961
945config DEBUG_TEGRA_UART 962config DEBUG_TEGRA_UART
946 bool 963 bool
947 depends on ARCH_TEGRA 964 depends on ARCH_TEGRA
@@ -970,7 +987,8 @@ config DEBUG_LL_INCLUDE
970 DEBUG_IMX51_UART || \ 987 DEBUG_IMX51_UART || \
971 DEBUG_IMX53_UART ||\ 988 DEBUG_IMX53_UART ||\
972 DEBUG_IMX6Q_UART || \ 989 DEBUG_IMX6Q_UART || \
973 DEBUG_IMX6SL_UART 990 DEBUG_IMX6SL_UART || \
991 DEBUG_IMX6SX_UART
974 default "debug/msm.S" if DEBUG_MSM_UART 992 default "debug/msm.S" if DEBUG_MSM_UART
975 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART 993 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
976 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 994 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index f1aeb7d72712..bada59d93b67 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -80,6 +80,7 @@ CONFIG_MTD_UBI=y
80CONFIG_EEPROM_AT24=y 80CONFIG_EEPROM_AT24=y
81CONFIG_EEPROM_AT25=y 81CONFIG_EEPROM_AT25=y
82CONFIG_ATA=y 82CONFIG_ATA=y
83CONFIG_BLK_DEV_SD=y
83CONFIG_PATA_IMX=y 84CONFIG_PATA_IMX=y
84CONFIG_NETDEVICES=y 85CONFIG_NETDEVICES=y
85CONFIG_CS89x0=y 86CONFIG_CS89x0=y
@@ -153,8 +154,12 @@ CONFIG_USB_HID=m
153CONFIG_USB=y 154CONFIG_USB=y
154CONFIG_USB_EHCI_HCD=y 155CONFIG_USB_EHCI_HCD=y
155CONFIG_USB_EHCI_MXC=y 156CONFIG_USB_EHCI_MXC=y
157CONFIG_USB_STORAGE=y
158CONFIG_USB_CHIPIDEA=y
159CONFIG_USB_CHIPIDEA_UDC=y
160CONFIG_USB_CHIPIDEA_HOST=y
161CONFIG_NOP_USB_XCEIV=y
156CONFIG_MMC=y 162CONFIG_MMC=y
157CONFIG_MMC_UNSAFE_RESUME=y
158CONFIG_MMC_SDHCI=y 163CONFIG_MMC_SDHCI=y
159CONFIG_MMC_SDHCI_PLTFM=y 164CONFIG_MMC_SDHCI_PLTFM=y
160CONFIG_MMC_SDHCI_ESDHC_IMX=y 165CONFIG_MMC_SDHCI_ESDHC_IMX=y
@@ -177,7 +182,6 @@ CONFIG_RTC_DRV_MXC=y
177CONFIG_DMADEVICES=y 182CONFIG_DMADEVICES=y
178CONFIG_IMX_SDMA=y 183CONFIG_IMX_SDMA=y
179CONFIG_IMX_DMA=y 184CONFIG_IMX_DMA=y
180CONFIG_COMMON_CLK_DEBUG=y
181# CONFIG_IOMMU_SUPPORT is not set 185# CONFIG_IOMMU_SUPPORT is not set
182CONFIG_EXT2_FS=y 186CONFIG_EXT2_FS=y
183CONFIG_EXT3_FS=y 187CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 09e974392fa1..ef8815327e5b 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -1,4 +1,3 @@
1# CONFIG_LOCALVERSION_AUTO is not set
2CONFIG_KERNEL_LZO=y 1CONFIG_KERNEL_LZO=y
3CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
4CONFIG_NO_HZ=y 3CONFIG_NO_HZ=y
@@ -33,7 +32,6 @@ CONFIG_MACH_PCM043=y
33CONFIG_MACH_MX35_3DS=y 32CONFIG_MACH_MX35_3DS=y
34CONFIG_MACH_VPR200=y 33CONFIG_MACH_VPR200=y
35CONFIG_MACH_IMX51_DT=y 34CONFIG_MACH_IMX51_DT=y
36CONFIG_MACH_EUKREA_CPUIMX51SD=y
37CONFIG_SOC_IMX50=y 35CONFIG_SOC_IMX50=y
38CONFIG_SOC_IMX53=y 36CONFIG_SOC_IMX53=y
39CONFIG_SOC_IMX6Q=y 37CONFIG_SOC_IMX6Q=y
@@ -46,7 +44,11 @@ CONFIG_VMSPLIT_2G=y
46CONFIG_PREEMPT_VOLUNTARY=y 44CONFIG_PREEMPT_VOLUNTARY=y
47CONFIG_AEABI=y 45CONFIG_AEABI=y
48CONFIG_HIGHMEM=y 46CONFIG_HIGHMEM=y
47CONFIG_CMA=y
49CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" 48CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
49CONFIG_CPU_FREQ=y
50CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
51CONFIG_ARM_IMX6Q_CPUFREQ=y
50CONFIG_VFP=y 52CONFIG_VFP=y
51CONFIG_NEON=y 53CONFIG_NEON=y
52CONFIG_BINFMT_MISC=m 54CONFIG_BINFMT_MISC=m
@@ -72,6 +74,7 @@ CONFIG_RFKILL_INPUT=y
72CONFIG_DEVTMPFS=y 74CONFIG_DEVTMPFS=y
73CONFIG_DEVTMPFS_MOUNT=y 75CONFIG_DEVTMPFS_MOUNT=y
74# CONFIG_STANDALONE is not set 76# CONFIG_STANDALONE is not set
77CONFIG_DMA_CMA=y
75CONFIG_IMX_WEIM=y 78CONFIG_IMX_WEIM=y
76CONFIG_CONNECTOR=y 79CONFIG_CONNECTOR=y
77CONFIG_MTD=y 80CONFIG_MTD=y
@@ -89,6 +92,7 @@ CONFIG_MTD_SST25L=y
89CONFIG_MTD_NAND=y 92CONFIG_MTD_NAND=y
90CONFIG_MTD_NAND_GPMI_NAND=y 93CONFIG_MTD_NAND_GPMI_NAND=y
91CONFIG_MTD_NAND_MXC=y 94CONFIG_MTD_NAND_MXC=y
95CONFIG_MTD_SPI_NOR=y
92CONFIG_MTD_UBI=y 96CONFIG_MTD_UBI=y
93CONFIG_BLK_DEV_LOOP=y 97CONFIG_BLK_DEV_LOOP=y
94CONFIG_BLK_DEV_RAM=y 98CONFIG_BLK_DEV_RAM=y
@@ -183,6 +187,7 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y
183CONFIG_VIDEO_CODA=y 187CONFIG_VIDEO_CODA=y
184CONFIG_SOC_CAMERA_OV2640=y 188CONFIG_SOC_CAMERA_OV2640=y
185CONFIG_DRM=y 189CONFIG_DRM=y
190CONFIG_DRM_PANEL_SIMPLE=y
186CONFIG_BACKLIGHT_LCD_SUPPORT=y 191CONFIG_BACKLIGHT_LCD_SUPPORT=y
187CONFIG_LCD_CLASS_DEVICE=y 192CONFIG_LCD_CLASS_DEVICE=y
188CONFIG_LCD_L4F00242T03=y 193CONFIG_LCD_L4F00242T03=y
@@ -215,7 +220,6 @@ CONFIG_USB_GADGET=y
215CONFIG_USB_ETH=m 220CONFIG_USB_ETH=m
216CONFIG_USB_MASS_STORAGE=m 221CONFIG_USB_MASS_STORAGE=m
217CONFIG_MMC=y 222CONFIG_MMC=y
218CONFIG_MMC_UNSAFE_RESUME=y
219CONFIG_MMC_SDHCI=y 223CONFIG_MMC_SDHCI=y
220CONFIG_MMC_SDHCI_PLTFM=y 224CONFIG_MMC_SDHCI_PLTFM=y
221CONFIG_MMC_SDHCI_ESDHC_IMX=y 225CONFIG_MMC_SDHCI_ESDHC_IMX=y
@@ -245,7 +249,7 @@ CONFIG_DRM_IMX_TVE=y
245CONFIG_DRM_IMX_LDB=y 249CONFIG_DRM_IMX_LDB=y
246CONFIG_DRM_IMX_IPUV3_CORE=y 250CONFIG_DRM_IMX_IPUV3_CORE=y
247CONFIG_DRM_IMX_IPUV3=y 251CONFIG_DRM_IMX_IPUV3=y
248CONFIG_COMMON_CLK_DEBUG=y 252CONFIG_DRM_IMX_HDMI=y
249# CONFIG_IOMMU_SUPPORT is not set 253# CONFIG_IOMMU_SUPPORT is not set
250CONFIG_PWM=y 254CONFIG_PWM=y
251CONFIG_PWM_IMX=y 255CONFIG_PWM_IMX=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 6150108e15de..a9f992335eb2 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -26,7 +26,6 @@ CONFIG_ARCH_MXS=y
26# CONFIG_ARM_THUMB is not set 26# CONFIG_ARM_THUMB is not set
27CONFIG_PREEMPT_VOLUNTARY=y 27CONFIG_PREEMPT_VOLUNTARY=y
28CONFIG_AEABI=y 28CONFIG_AEABI=y
29CONFIG_FPE_NWFPE=y
30CONFIG_NET=y 29CONFIG_NET=y
31CONFIG_PACKET=y 30CONFIG_PACKET=y
32CONFIG_UNIX=y 31CONFIG_UNIX=y
@@ -51,10 +50,10 @@ CONFIG_MTD_CMDLINE_PARTS=y
51CONFIG_MTD_BLOCK=y 50CONFIG_MTD_BLOCK=y
52CONFIG_MTD_DATAFLASH=y 51CONFIG_MTD_DATAFLASH=y
53CONFIG_MTD_M25P80=y 52CONFIG_MTD_M25P80=y
54# CONFIG_M25PXX_USE_FAST_READ is not set
55CONFIG_MTD_SST25L=y 53CONFIG_MTD_SST25L=y
56CONFIG_MTD_NAND=y 54CONFIG_MTD_NAND=y
57CONFIG_MTD_NAND_GPMI_NAND=y 55CONFIG_MTD_NAND_GPMI_NAND=y
56CONFIG_MTD_SPI_NOR=y
58CONFIG_MTD_UBI=y 57CONFIG_MTD_UBI=y
59# CONFIG_BLK_DEV is not set 58# CONFIG_BLK_DEV is not set
60CONFIG_EEPROM_AT24=y 59CONFIG_EEPROM_AT24=y
@@ -120,7 +119,6 @@ CONFIG_USB_GADGET=y
120CONFIG_USB_ETH=m 119CONFIG_USB_ETH=m
121CONFIG_USB_MASS_STORAGE=m 120CONFIG_USB_MASS_STORAGE=m
122CONFIG_MMC=y 121CONFIG_MMC=y
123CONFIG_MMC_UNSAFE_RESUME=y
124CONFIG_MMC_MXS=y 122CONFIG_MMC_MXS=y
125CONFIG_NEW_LEDS=y 123CONFIG_NEW_LEDS=y
126CONFIG_LEDS_CLASS=y 124CONFIG_LEDS_CLASS=y
@@ -138,7 +136,6 @@ CONFIG_DMADEVICES=y
138CONFIG_MXS_DMA=y 136CONFIG_MXS_DMA=y
139CONFIG_STAGING=y 137CONFIG_STAGING=y
140CONFIG_MXS_LRADC=y 138CONFIG_MXS_LRADC=y
141CONFIG_COMMON_CLK_DEBUG=y
142CONFIG_IIO=y 139CONFIG_IIO=y
143CONFIG_IIO_SYSFS_TRIGGER=y 140CONFIG_IIO_SYSFS_TRIGGER=y
144CONFIG_PWM=y 141CONFIG_PWM=y
@@ -180,7 +177,7 @@ CONFIG_BLK_DEV_IO_TRACE=y
180CONFIG_STRICT_DEVMEM=y 177CONFIG_STRICT_DEVMEM=y
181CONFIG_DEBUG_USER=y 178CONFIG_DEBUG_USER=y
182# CONFIG_CRYPTO_ANSI_CPRNG is not set 179# CONFIG_CRYPTO_ANSI_CPRNG is not set
183# CONFIG_CRYPTO_HW is not set 180CONFIG_CRYPTO_DEV_MXS_DCP=y
184CONFIG_CRC_ITU_T=m 181CONFIG_CRC_ITU_T=m
185CONFIG_CRC7=m 182CONFIG_CRC7=m
186CONFIG_FONTS=y 183CONFIG_FONTS=y
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 42b823cd2d22..032a316eb802 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -81,6 +81,15 @@
81#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR 81#define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
82#define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n) 82#define IMX6SL_UART_BASE(n) IMX6SL_UART_BASE_ADDR(n)
83 83
84#define IMX6SX_UART1_BASE_ADDR 0x02020000
85#define IMX6SX_UART2_BASE_ADDR 0x021e8000
86#define IMX6SX_UART3_BASE_ADDR 0x021ec000
87#define IMX6SX_UART4_BASE_ADDR 0x021f0000
88#define IMX6SX_UART5_BASE_ADDR 0x021f4000
89#define IMX6SX_UART6_BASE_ADDR 0x022a0000
90#define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR
91#define IMX6SX_UART_BASE(n) IMX6SX_UART_BASE_ADDR(n)
92
84#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT) 93#define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
85 94
86#ifdef CONFIG_DEBUG_IMX1_UART 95#ifdef CONFIG_DEBUG_IMX1_UART
@@ -103,6 +112,8 @@
103#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q) 112#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6Q)
104#elif defined(CONFIG_DEBUG_IMX6SL_UART) 113#elif defined(CONFIG_DEBUG_IMX6SL_UART)
105#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL) 114#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SL)
115#elif defined(CONFIG_DEBUG_IMX6SX_UART)
116#define UART_PADDR IMX_DEBUG_UART_BASE(IMX6SX)
106#endif 117#endif
107 118
108#endif /* __DEBUG_IMX_UART_H */ 119#endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/include/debug/vf.S b/arch/arm/include/debug/vf.S
index ba12cc44b2cb..b88933849a17 100644
--- a/arch/arm/include/debug/vf.S
+++ b/arch/arm/include/debug/vf.S
@@ -7,9 +7,20 @@
7 * 7 *
8 */ 8 */
9 9
10#define VF_UART0_BASE_ADDR 0x40027000
11#define VF_UART1_BASE_ADDR 0x40028000
12#define VF_UART2_BASE_ADDR 0x40029000
13#define VF_UART3_BASE_ADDR 0x4002a000
14#define VF_UART_BASE_ADDR(n) VF_UART##n##_BASE_ADDR
15#define VF_UART_BASE(n) VF_UART_BASE_ADDR(n)
16#define VF_UART_PHYSICAL_BASE VF_UART_BASE(CONFIG_DEBUG_VF_UART_PORT)
17
18#define VF_UART_VIRTUAL_BASE 0xfe000000
19
10 .macro addruart, rp, rv, tmp 20 .macro addruart, rp, rv, tmp
11 ldr \rp, =0x40028000 @ physical 21 ldr \rp, =VF_UART_PHYSICAL_BASE @ physical
12 ldr \rv, =0xfe028000 @ virtual 22 and \rv, \rp, #0xffffff @ offset within 16MB section
23 add \rv, \rv, #VF_UART_VIRTUAL_BASE
13 .endm 24 .endm
14 25
15 .macro senduart, rd, rx 26 .macro senduart, rd, rx
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5740296dc429..4776e1ffacd5 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -702,61 +702,6 @@ endif
702 702
703if ARCH_MULTI_V7 703if ARCH_MULTI_V7
704 704
705comment "i.MX51 machines:"
706
707config MACH_IMX51_DT
708 bool "Support i.MX51 platforms from device tree"
709 select SOC_IMX51
710 help
711 Include support for Freescale i.MX51 based platforms
712 using the device tree for discovery
713
714config MACH_MX51_BABBAGE
715 bool "Support MX51 BABBAGE platforms"
716 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
717 select IMX_HAVE_PLATFORM_IMX2_WDT
718 select IMX_HAVE_PLATFORM_IMX_I2C
719 select IMX_HAVE_PLATFORM_IMX_UART
720 select IMX_HAVE_PLATFORM_MXC_EHCI
721 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
722 select IMX_HAVE_PLATFORM_SPI_IMX
723 select SOC_IMX51
724 help
725 Include support for MX51 Babbage platform, also known as MX51EVK in
726 u-boot. This includes specific configurations for the board and its
727 peripherals.
728
729config MACH_EUKREA_CPUIMX51SD
730 bool "Support Eukrea CPUIMX51SD module"
731 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
732 select IMX_HAVE_PLATFORM_IMX2_WDT
733 select IMX_HAVE_PLATFORM_IMX_I2C
734 select IMX_HAVE_PLATFORM_IMX_UART
735 select IMX_HAVE_PLATFORM_MXC_EHCI
736 select IMX_HAVE_PLATFORM_MXC_NAND
737 select IMX_HAVE_PLATFORM_SPI_IMX
738 select SOC_IMX51
739 help
740 Include support for Eukrea CPUIMX51SD platform. This includes
741 specific configurations for the module and its peripherals.
742
743choice
744 prompt "Baseboard"
745 depends on MACH_EUKREA_CPUIMX51SD
746 default MACH_EUKREA_MBIMXSD51_BASEBOARD
747
748config MACH_EUKREA_MBIMXSD51_BASEBOARD
749 prompt "Eukrea MBIMXSD development board"
750 bool
751 select IMX_HAVE_PLATFORM_IMX_SSI
752 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
753 select LEDS_GPIO_REGISTER
754 help
755 This adds board specific devices that can be found on Eukrea's
756 MBIMXSD evaluation board.
757
758endchoice
759
760comment "Device tree only" 705comment "Device tree only"
761 706
762config SOC_IMX50 707config SOC_IMX50
@@ -768,6 +713,12 @@ config SOC_IMX50
768 help 713 help
769 This enables support for Freescale i.MX50 processor. 714 This enables support for Freescale i.MX50 processor.
770 715
716config MACH_IMX51_DT
717 bool "i.MX51 support"
718 select SOC_IMX51
719 help
720 This enables support for Freescale i.MX51 processor
721
771config SOC_IMX53 722config SOC_IMX53
772 bool "i.MX53 support" 723 bool "i.MX53 support"
773 select HAVE_IMX_SRC 724 select HAVE_IMX_SRC
@@ -812,6 +763,14 @@ config SOC_IMX6SL
812 help 763 help
813 This enables support for Freescale i.MX6 SoloLite processor. 764 This enables support for Freescale i.MX6 SoloLite processor.
814 765
766config SOC_IMX6SX
767 bool "i.MX6 SoloX support"
768 select PINCTRL_IMX6SX
769 select SOC_IMX6
770
771 help
772 This enables support for Freescale i.MX6 SoloX processor.
773
815config SOC_VF610 774config SOC_VF610
816 bool "Vybrid Family VF610 support" 775 bool "Vybrid Family VF610 support"
817 select ARM_GIC 776 select ARM_GIC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f4ed83032dd0..bbe93bbfd003 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_SMP) += headsmp.o platsmp.o
101obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 101obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
102obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o 102obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
103obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o 103obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
104obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
104 105
105ifeq ($(CONFIG_SUSPEND),y) 106ifeq ($(CONFIG_SUSPEND),y)
106AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a 107AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
@@ -108,11 +109,6 @@ obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
108endif 109endif
109obj-$(CONFIG_SOC_IMX6) += pm-imx6.o 110obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
110 111
111# i.MX5 based machines
112obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
113obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
114obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
115
116obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o 112obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
117obj-$(CONFIG_SOC_IMX50) += mach-imx50.o 113obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
118obj-$(CONFIG_SOC_IMX53) += mach-imx53.o 114obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index 8d1df2e4b7ac..24b103c67f82 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -135,7 +135,7 @@ static __init void avic_init_gc(int idx, unsigned int irq_start)
135 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); 135 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
136} 136}
137 137
138asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs) 138static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
139{ 139{
140 u32 nivector; 140 u32 nivector;
141 141
@@ -190,6 +190,8 @@ void __init mxc_init_irq(void __iomem *irqbase)
190 for (i = 0; i < 8; i++) 190 for (i = 0; i < 8; i++)
191 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i)); 191 __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
192 192
193 set_handle_irq(avic_handle_irq);
194
193#ifdef CONFIG_FIQ 195#ifdef CONFIG_FIQ
194 /* Initialize FIQ */ 196 /* Initialize FIQ */
195 init_FIQ(FIQ_START); 197 init_FIQ(FIQ_START);
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index a2ecc006b322..4ba587da89d2 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -27,48 +27,61 @@
27 * parent - fixed parent. No clk_set_parent support 27 * parent - fixed parent. No clk_set_parent support
28 */ 28 */
29 29
30#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 30struct clk_gate2 {
31 struct clk_hw hw;
32 void __iomem *reg;
33 u8 bit_idx;
34 u8 flags;
35 spinlock_t *lock;
36 unsigned int *share_count;
37};
38
39#define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
31 40
32static int clk_gate2_enable(struct clk_hw *hw) 41static int clk_gate2_enable(struct clk_hw *hw)
33{ 42{
34 struct clk_gate *gate = to_clk_gate(hw); 43 struct clk_gate2 *gate = to_clk_gate2(hw);
35 u32 reg; 44 u32 reg;
36 unsigned long flags = 0; 45 unsigned long flags = 0;
37 46
38 if (gate->lock) 47 spin_lock_irqsave(gate->lock, flags);
39 spin_lock_irqsave(gate->lock, flags); 48
49 if (gate->share_count && (*gate->share_count)++ > 0)
50 goto out;
40 51
41 reg = readl(gate->reg); 52 reg = readl(gate->reg);
42 reg |= 3 << gate->bit_idx; 53 reg |= 3 << gate->bit_idx;
43 writel(reg, gate->reg); 54 writel(reg, gate->reg);
44 55
45 if (gate->lock) 56out:
46 spin_unlock_irqrestore(gate->lock, flags); 57 spin_unlock_irqrestore(gate->lock, flags);
47 58
48 return 0; 59 return 0;
49} 60}
50 61
51static void clk_gate2_disable(struct clk_hw *hw) 62static void clk_gate2_disable(struct clk_hw *hw)
52{ 63{
53 struct clk_gate *gate = to_clk_gate(hw); 64 struct clk_gate2 *gate = to_clk_gate2(hw);
54 u32 reg; 65 u32 reg;
55 unsigned long flags = 0; 66 unsigned long flags = 0;
56 67
57 if (gate->lock) 68 spin_lock_irqsave(gate->lock, flags);
58 spin_lock_irqsave(gate->lock, flags); 69
70 if (gate->share_count && --(*gate->share_count) > 0)
71 goto out;
59 72
60 reg = readl(gate->reg); 73 reg = readl(gate->reg);
61 reg &= ~(3 << gate->bit_idx); 74 reg &= ~(3 << gate->bit_idx);
62 writel(reg, gate->reg); 75 writel(reg, gate->reg);
63 76
64 if (gate->lock) 77out:
65 spin_unlock_irqrestore(gate->lock, flags); 78 spin_unlock_irqrestore(gate->lock, flags);
66} 79}
67 80
68static int clk_gate2_is_enabled(struct clk_hw *hw) 81static int clk_gate2_is_enabled(struct clk_hw *hw)
69{ 82{
70 u32 reg; 83 u32 reg;
71 struct clk_gate *gate = to_clk_gate(hw); 84 struct clk_gate2 *gate = to_clk_gate2(hw);
72 85
73 reg = readl(gate->reg); 86 reg = readl(gate->reg);
74 87
@@ -87,21 +100,23 @@ static struct clk_ops clk_gate2_ops = {
87struct clk *clk_register_gate2(struct device *dev, const char *name, 100struct clk *clk_register_gate2(struct device *dev, const char *name,
88 const char *parent_name, unsigned long flags, 101 const char *parent_name, unsigned long flags,
89 void __iomem *reg, u8 bit_idx, 102 void __iomem *reg, u8 bit_idx,
90 u8 clk_gate2_flags, spinlock_t *lock) 103 u8 clk_gate2_flags, spinlock_t *lock,
104 unsigned int *share_count)
91{ 105{
92 struct clk_gate *gate; 106 struct clk_gate2 *gate;
93 struct clk *clk; 107 struct clk *clk;
94 struct clk_init_data init; 108 struct clk_init_data init;
95 109
96 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 110 gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
97 if (!gate) 111 if (!gate)
98 return ERR_PTR(-ENOMEM); 112 return ERR_PTR(-ENOMEM);
99 113
100 /* struct clk_gate assignments */ 114 /* struct clk_gate2 assignments */
101 gate->reg = reg; 115 gate->reg = reg;
102 gate->bit_idx = bit_idx; 116 gate->bit_idx = bit_idx;
103 gate->flags = clk_gate2_flags; 117 gate->flags = clk_gate2_flags;
104 gate->lock = lock; 118 gate->lock = lock;
119 gate->share_count = share_count;
105 120
106 init.name = name; 121 init.name = name;
107 init.ops = &clk_gate2_ops; 122 init.ops = &clk_gate2_ops;
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
index 15f9d223cf0b..7f739be3de2c 100644
--- a/arch/arm/mach-imx/clk-imx1.c
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -40,12 +40,14 @@
40#define SCM_GCCR IO_ADDR_SCM(0xc) 40#define SCM_GCCR IO_ADDR_SCM(0xc)
41 41
42static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", }; 42static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
43static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem", 43static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
44 "fclk", }; 44 "prem", "fclk", };
45
45enum imx1_clks { 46enum imx1_clks {
46 dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, spll, mcu, 47 dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, mpll_gate,
47 fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate, 48 spll, spll_gate, mcu, fclk, hclk, clk48m, per1, per2, per3, clko,
48 mma_gate, usbd_gate, clk_max 49 uart3_gate, ssi2_gate, brom_gate, dma_gate, csi_gate, mma_gate,
50 usbd_gate, clk_max
49}; 51};
50 52
51static struct clk *clk[clk_max]; 53static struct clk *clk[clk_max];
@@ -62,17 +64,22 @@ int __init mx1_clocks_init(unsigned long fref)
62 clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, 64 clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
63 ARRAY_SIZE(prem_sel_clks)); 65 ARRAY_SIZE(prem_sel_clks));
64 clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0); 66 clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
67 clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
65 clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0); 68 clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
69 clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
66 clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1); 70 clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
67 clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 15, 1); 71 clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
68 clk[hclk] = imx_clk_divider("hclk", "spll", CCM_CSCR, 10, 4); 72 clk[hclk] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
69 clk[clk48m] = imx_clk_divider("clk48m", "spll", CCM_CSCR, 26, 3); 73 clk[clk48m] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
70 clk[per1] = imx_clk_divider("per1", "spll", CCM_PCDR, 0, 4); 74 clk[per1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
71 clk[per2] = imx_clk_divider("per2", "spll", CCM_PCDR, 4, 4); 75 clk[per2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
72 clk[per3] = imx_clk_divider("per3", "spll", CCM_PCDR, 16, 7); 76 clk[per3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
73 clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, 77 clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
74 ARRAY_SIZE(clko_sel_clks)); 78 ARRAY_SIZE(clko_sel_clks));
75 clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 4); 79 clk[uart3_gate] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
80 clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
81 clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
82 clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
76 clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2); 83 clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
77 clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1); 84 clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
78 clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0); 85 clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
@@ -84,9 +91,6 @@ int __init mx1_clocks_init(unsigned long fref)
84 91
85 clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma"); 92 clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
86 clk_register_clkdev(clk[hclk], "ipg", "imx1-dma"); 93 clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
87 clk_register_clkdev(clk[csi_gate], NULL, "mx1-camera.0");
88 clk_register_clkdev(clk[mma_gate], "mma", NULL);
89 clk_register_clkdev(clk[usbd_gate], NULL, "imx_udc.0");
90 clk_register_clkdev(clk[per1], "per", "imx-gpt.0"); 94 clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
91 clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0"); 95 clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
92 clk_register_clkdev(clk[per1], "per", "imx1-uart.0"); 96 clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
@@ -94,20 +98,15 @@ int __init mx1_clocks_init(unsigned long fref)
94 clk_register_clkdev(clk[per1], "per", "imx1-uart.1"); 98 clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
95 clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1"); 99 clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
96 clk_register_clkdev(clk[per1], "per", "imx1-uart.2"); 100 clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
97 clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.2"); 101 clk_register_clkdev(clk[uart3_gate], "ipg", "imx1-uart.2");
98 clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0"); 102 clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
99 clk_register_clkdev(clk[per2], "per", "imx1-cspi.0"); 103 clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
100 clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0"); 104 clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
101 clk_register_clkdev(clk[per2], "per", "imx1-cspi.1"); 105 clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
102 clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1"); 106 clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
103 clk_register_clkdev(clk[per2], NULL, "imx-mmc.0");
104 clk_register_clkdev(clk[per2], "per", "imx1-fb.0"); 107 clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
105 clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0"); 108 clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
106 clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0"); 109 clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
107 clk_register_clkdev(clk[hclk], "mshc", NULL);
108 clk_register_clkdev(clk[per3], "ssi", NULL);
109 clk_register_clkdev(clk[clk32], NULL, "imx1-rtc.0");
110 clk_register_clkdev(clk[clko], "clko", NULL);
111 110
112 mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT); 111 mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
113 112
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index dc36e6c2f1da..ae578c096ad8 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -62,6 +62,10 @@ static struct clk_onecell_data clk_data;
62 62
63static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", }; 63static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
64static const char *per_sel_clks[] = { "ahb", "upll", }; 64static const char *per_sel_clks[] = { "ahb", "upll", };
65static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
66 "ipg", "dummy", "dummy", "dummy",
67 "dummy", "dummy", "per0", "per2",
68 "per13", "per14", "usbotg_ahb", "dummy",};
65 69
66enum mx25_clks { 70enum mx25_clks {
67 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg, 71 dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg,
@@ -82,7 +86,7 @@ enum mx25_clks {
82 pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg, 86 pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg,
83 sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg, 87 sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg,
84 uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17, 88 uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17,
85 wdt_ipg, clk_max 89 wdt_ipg, cko_div, cko_sel, cko, clk_max
86}; 90};
87 91
88static struct clk *clk[clk_max]; 92static struct clk *clk[clk_max];
@@ -117,6 +121,9 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
117 clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); 121 clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
118 clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); 122 clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
119 clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks)); 123 clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
124 clk[cko_div] = imx_clk_divider("cko_div", "cko_sel", ccm(CCM_MCR), 24, 6);
125 clk[cko_sel] = imx_clk_mux("cko_sel", ccm(CCM_MCR), 20, 4, cko_sel_clks, ARRAY_SIZE(cko_sel_clks));
126 clk[cko] = imx_clk_gate("cko", "cko_div", ccm(CCM_MCR), 30);
120 clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6); 127 clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);
121 clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6); 128 clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6);
122 clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6); 129 clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6);
@@ -230,6 +237,12 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
230 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0"); 237 clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
231 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0"); 238 clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
232 239
240 /*
241 * Let's initially set up CLKO parent as ipg, since this configuration
242 * is used on some imx25 board designs to clock the audio codec.
243 */
244 clk_set_parent(clk[cko_sel], clk[ipg]);
245
233 return 0; 246 return 0;
234} 247}
235 248
@@ -304,8 +317,6 @@ int __init mx25_clocks_init(void)
304int __init mx25_clocks_init_dt(void) 317int __init mx25_clocks_init_dt(void)
305{ 318{
306 struct device_node *np; 319 struct device_node *np;
307 void __iomem *base;
308 int irq;
309 unsigned long osc_rate = 24000000; 320 unsigned long osc_rate = 24000000;
310 321
311 /* retrieve the freqency of fixed clocks from device tree */ 322 /* retrieve the freqency of fixed clocks from device tree */
@@ -325,12 +336,7 @@ int __init mx25_clocks_init_dt(void)
325 336
326 __mx25_clocks_init(osc_rate); 337 __mx25_clocks_init(osc_rate);
327 338
328 np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"); 339 mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"));
329 base = of_iomap(np, 0);
330 WARN_ON(!base);
331 irq = irq_of_parse_and_map(np, 0);
332
333 mxc_timer_init(base, irq);
334 340
335 return 0; 341 return 0;
336} 342}
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index d2da8908b268..317a662626d6 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -82,7 +82,8 @@ enum mx27_clks {
82 csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate, 82 csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
83 uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate, 83 uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
84 uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel, 84 uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
85 mpll_sel, spll_gate, clk_max 85 mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate,
86 rtic_ahb_gate, mshc_baud_gate, clk_max
86}; 87};
87 88
88static struct clk *clk[clk_max]; 89static struct clk *clk[clk_max];
@@ -117,6 +118,7 @@ int __init mx27_clocks_init(unsigned long fref)
117 clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1); 118 clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
118 } 119 }
119 120
121 clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
120 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4); 122 clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
121 clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6); 123 clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
122 clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6); 124 clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
@@ -145,9 +147,11 @@ int __init mx27_clocks_init(unsigned long fref)
145 clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5); 147 clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
146 clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6); 148 clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
147 clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7); 149 clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
150 clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
148 clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9); 151 clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
149 clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11); 152 clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
150 clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12); 153 clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
154 clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
151 clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14); 155 clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
152 clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15); 156 clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
153 clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16); 157 clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
@@ -166,6 +170,7 @@ int __init mx27_clocks_init(unsigned long fref)
166 clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29); 170 clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
167 clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30); 171 clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
168 clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31); 172 clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
173 clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
169 clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3); 174 clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1, 3);
170 clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4); 175 clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1, 4);
171 clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5); 176 clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1, 5);
@@ -177,6 +182,7 @@ int __init mx27_clocks_init(unsigned long fref)
177 clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11); 182 clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
178 clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12); 183 clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
179 clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13); 184 clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
185 clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
180 clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15); 186 clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
181 clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16); 187 clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
182 clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17); 188 clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
@@ -221,16 +227,6 @@ int __init mx27_clocks_init(unsigned long fref)
221 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5"); 227 clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
222 clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0"); 228 clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
223 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0"); 229 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
224 clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
225 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.1");
226 clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
227 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.2");
228 clk_register_clkdev(clk[gpt4_ipg_gate], "ipg", "imx-gpt.3");
229 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.3");
230 clk_register_clkdev(clk[gpt5_ipg_gate], "ipg", "imx-gpt.4");
231 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
232 clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
233 clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
234 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0"); 230 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
235 clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0"); 231 clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
236 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1"); 232 clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
@@ -278,14 +274,7 @@ int __init mx27_clocks_init(unsigned long fref)
278 clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0"); 274 clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
279 clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0"); 275 clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
280 clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0"); 276 clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
281 clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL);
282 clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
283 clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
284 clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
285 clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
286 clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
287 clk_register_clkdev(clk[cpu_div], NULL, "cpu0"); 277 clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
288 clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
289 278
290 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1); 279 mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
291 280
@@ -296,7 +285,6 @@ int __init mx27_clocks_init(unsigned long fref)
296 return 0; 285 return 0;
297} 286}
298 287
299#ifdef CONFIG_OF
300int __init mx27_clocks_init_dt(void) 288int __init mx27_clocks_init_dt(void)
301{ 289{
302 struct device_node *np; 290 struct device_node *np;
@@ -312,4 +300,3 @@ int __init mx27_clocks_init_dt(void)
312 300
313 return mx27_clocks_init(fref); 301 return mx27_clocks_init(fref);
314} 302}
315#endif
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index b5b65f3efaf1..4a9de0835eb1 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -191,7 +191,6 @@ int __init mx31_clocks_init(unsigned long fref)
191 return 0; 191 return 0;
192} 192}
193 193
194#ifdef CONFIG_OF
195int __init mx31_clocks_init_dt(void) 194int __init mx31_clocks_init_dt(void)
196{ 195{
197 struct device_node *np; 196 struct device_node *np;
@@ -207,4 +206,3 @@ int __init mx31_clocks_init_dt(void)
207 206
208 return mx31_clocks_init(fref); 207 return mx31_clocks_init(fref);
209} 208}
210#endif
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 568ef0a4de84..21d2b111c83d 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -322,9 +322,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
322 322
323static void __init mx50_clocks_init(struct device_node *np) 323static void __init mx50_clocks_init(struct device_node *np)
324{ 324{
325 void __iomem *base;
326 unsigned long r; 325 unsigned long r;
327 int i, irq; 326 int i;
328 327
329 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); 328 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
330 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); 329 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
@@ -372,11 +371,7 @@ static void __init mx50_clocks_init(struct device_node *np)
372 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); 371 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
373 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); 372 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
374 373
375 np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"); 374 mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"));
376 base = of_iomap(np, 0);
377 WARN_ON(!base);
378 irq = irq_of_parse_and_map(np, 0);
379 mxc_timer_init(base, irq);
380} 375}
381CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init); 376CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
382 377
@@ -436,7 +431,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
436 431
437 clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2"); 432 clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
438 clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL); 433 clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
439 clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx51-vpu.0");
440 clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0"); 434 clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
441 clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0"); 435 clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
442 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0"); 436 clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
@@ -492,9 +486,8 @@ CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
492 486
493static void __init mx53_clocks_init(struct device_node *np) 487static void __init mx53_clocks_init(struct device_node *np)
494{ 488{
495 int i, irq; 489 int i;
496 unsigned long r; 490 unsigned long r;
497 void __iomem *base;
498 491
499 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE); 492 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
500 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE); 493 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
@@ -561,7 +554,6 @@ static void __init mx53_clocks_init(struct device_node *np)
561 554
562 mx5_clocks_common_init(0, 0, 0, 0); 555 mx5_clocks_common_init(0, 0, 0, 0);
563 556
564 clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx53-vpu.0");
565 clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2"); 557 clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
566 clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0"); 558 clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
567 clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0"); 559 clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
@@ -592,10 +584,6 @@ static void __init mx53_clocks_init(struct device_node *np)
592 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000); 584 r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
593 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r); 585 clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
594 586
595 np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"); 587 mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"));
596 base = of_iomap(np, 0);
597 WARN_ON(!base);
598 irq = irq_of_parse_and_map(np, 0);
599 mxc_timer_init(base, irq);
600} 588}
601CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init); 589CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 2b4d6acfa34a..8e795dea02ec 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -107,7 +107,7 @@ enum mx6q_clks {
107 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, 107 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
108 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, 108 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
109 spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, 109 spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
110 lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max 110 lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max
111}; 111};
112 112
113static struct clk *clk[clk_max]; 113static struct clk *clk[clk_max];
@@ -140,11 +140,13 @@ static struct clk_div_table video_div_table[] = {
140 { /* sentinel */ } 140 { /* sentinel */ }
141}; 141};
142 142
143static unsigned int share_count_esai;
144
143static void __init imx6q_clocks_init(struct device_node *ccm_node) 145static void __init imx6q_clocks_init(struct device_node *ccm_node)
144{ 146{
145 struct device_node *np; 147 struct device_node *np;
146 void __iomem *base; 148 void __iomem *base;
147 int i, irq; 149 int i;
148 int ret; 150 int ret;
149 151
150 clk[dummy] = imx_clk_fixed("dummy", 0); 152 clk[dummy] = imx_clk_fixed("dummy", 0);
@@ -352,9 +354,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
352 clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2); 354 clk[ecspi2] = imx_clk_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
353 clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4); 355 clk[ecspi3] = imx_clk_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
354 clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6); 356 clk[ecspi4] = imx_clk_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
355 clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8); 357 if (cpu_is_imx6dl())
358 /* ecspi5 is replaced with i2c4 on imx6dl & imx6s */
359 clk[ecspi5] = imx_clk_gate2("i2c4", "ipg_per", base + 0x6c, 8);
360 else
361 clk[ecspi5] = imx_clk_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
356 clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10); 362 clk[enet] = imx_clk_gate2("enet", "ipg", base + 0x6c, 10);
357 clk[esai] = imx_clk_gate2("esai", "esai_podf", base + 0x6c, 16); 363 clk[esai] = imx_clk_gate2_shared("esai", "esai_podf", base + 0x6c, 16, &share_count_esai);
364 clk[esai_ahb] = imx_clk_gate2_shared("esai_ahb", "ahb", base + 0x6c, 16, &share_count_esai);
358 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20); 365 clk[gpt_ipg] = imx_clk_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
359 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22); 366 clk[gpt_ipg_per] = imx_clk_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
360 if (cpu_is_imx6dl()) 367 if (cpu_is_imx6dl())
@@ -489,10 +496,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
489 /* Set initial power mode */ 496 /* Set initial power mode */
490 imx6q_set_lpm(WAIT_CLOCKED); 497 imx6q_set_lpm(WAIT_CLOCKED);
491 498
492 np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"); 499 mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"));
493 base = of_iomap(np, 0);
494 WARN_ON(!base);
495 irq = irq_of_parse_and_map(np, 0);
496 mxc_timer_init(base, irq);
497} 500}
498CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init); 501CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index f7073c0782fb..21cf06cebade 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -169,7 +169,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
169{ 169{
170 struct device_node *np; 170 struct device_node *np;
171 void __iomem *base; 171 void __iomem *base;
172 int irq;
173 int i; 172 int i;
174 int ret; 173 int ret;
175 174
@@ -385,9 +384,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
385 imx6q_set_lpm(WAIT_CLOCKED); 384 imx6q_set_lpm(WAIT_CLOCKED);
386 385
387 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt"); 386 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
388 base = of_iomap(np, 0); 387 mxc_timer_init_dt(np);
389 WARN_ON(!base);
390 irq = irq_of_parse_and_map(np, 0);
391 mxc_timer_init(base, irq);
392} 388}
393CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init); 389CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
new file mode 100644
index 000000000000..72f8902235d1
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -0,0 +1,524 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/clock/imx6sx-clock.h>
13#include <linux/clk.h>
14#include <linux/clkdev.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_irq.h>
21#include <linux/types.h>
22
23#include "clk.h"
24#include "common.h"
25
26#define CCDR 0x4
27#define BM_CCM_CCDR_MMDC_CH0_MASK (0x2 << 16)
28
29static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
30static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
31static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
32static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
33static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", };
34static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
35static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
36static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
37static const char *ocram_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
38static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
39static const char *gpu_axi_sels[] = { "pll2_pfd2_396m", "pll3_pfd0_720m", "pll3_pfd1_540m", "pll2_bus", };
40static const char *gpu_core_sels[] = { "pll3_pfd1_540m", "pll3_pfd0_720m", "pll2_bus", "pll2_pfd2_396m", };
41static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
42static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
43static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
44static const char *ldb_di1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
45static const char *pcie_axi_sels[] = { "axi", "ahb", };
46static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", };
47static const char *qspi1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
48static const char *perclk_sels[] = { "ipg", "osc", };
49static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
50static const char *vid_sels[] = { "pll3_pfd1_540m", "pll3_usb_otg", "pll3_pfd3_454m", "pll4_audio_div", "pll5_video_div", };
51static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", "dummy", };
52static const char *uart_sels[] = { "pll3_80m", "osc", };
53static const char *qspi2_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
54static const char *enet_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
55static const char *enet_sels[] = { "enet_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
56static const char *m4_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "osc", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd3_454m", };
57static const char *m4_sels[] = { "m4_pre_sel", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
58static const char *eim_slow_sels[] = { "ocram", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
59static const char *ecspi_sels[] = { "pll3_60m", "osc", };
60static const char *lcdif1_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
61static const char *lcdif1_sels[] = { "lcdif1_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
62static const char *lcdif2_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd3_594m", "pll3_pfd1_540m", };
63static const char *lcdif2_sels[] = { "lcdif2_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
64static const char *display_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", };
65static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
66static const char *cko1_sels[] = {
67 "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
68 "dummy", "ocram", "dummy", "pxp_axi", "epdc_axi", "lcdif_pix",
69 "epdc_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
70};
71static const char *cko2_sels[] = {
72 "dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck",
73 "ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
74 "lcdif_axi", "dummy", "osc", "dummy", "gpu2d_ovg_core",
75 "usdhc2", "ssi1", "ssi2", "ssi3", "gpu2d_core", "dummy",
76 "dummy", "dummy", "dummy", "esai_extal", "eim_slow", "uart_serial",
77 "spdif", "asrc", "dummy",
78};
79static const char *cko_sels[] = { "cko1", "cko2", };
80static const char *lvds_sels[] = {
81 "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
82 "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
83};
84
85static struct clk *clks[IMX6SX_CLK_CLK_END];
86static struct clk_onecell_data clk_data;
87
88static int const clks_init_on[] __initconst = {
89 IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3,
90 IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3,
91 IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG,
92 IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM,
93 IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_M4,
94 IMX6SX_CLK_QSPI1, IMX6SX_CLK_QSPI2, IMX6SX_CLK_UART_IPG,
95 IMX6SX_CLK_UART_SERIAL, IMX6SX_CLK_I2C3, IMX6SX_CLK_ECSPI5,
96 IMX6SX_CLK_CAN1_IPG, IMX6SX_CLK_CAN1_SERIAL, IMX6SX_CLK_CAN2_IPG,
97 IMX6SX_CLK_CAN2_SERIAL, IMX6SX_CLK_CANFD, IMX6SX_CLK_EPIT1,
98 IMX6SX_CLK_EPIT2,
99};
100
101static struct clk_div_table clk_enet_ref_table[] = {
102 { .val = 0, .div = 20, },
103 { .val = 1, .div = 10, },
104 { .val = 2, .div = 5, },
105 { .val = 3, .div = 4, },
106 { }
107};
108
109static struct clk_div_table post_div_table[] = {
110 { .val = 2, .div = 1, },
111 { .val = 1, .div = 2, },
112 { .val = 0, .div = 4, },
113 { }
114};
115
116static struct clk_div_table video_div_table[] = {
117 { .val = 0, .div = 1, },
118 { .val = 1, .div = 2, },
119 { .val = 2, .div = 1, },
120 { .val = 3, .div = 4, },
121 { }
122};
123
124static u32 share_count_asrc;
125static u32 share_count_audio;
126static u32 share_count_esai;
127
128static void __init imx6sx_clocks_init(struct device_node *ccm_node)
129{
130 struct device_node *np;
131 void __iomem *base;
132 int i;
133
134 clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
135
136 clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
137 clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");
138
139 /* ipp_di clock is external input */
140 clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
141 clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
142
143 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
144 base = of_iomap(np, 0);
145 WARN_ON(!base);
146
147 /* type name parent_name base div_mask */
148 clks[IMX6SX_CLK_PLL1_SYS] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
149 clks[IMX6SX_CLK_PLL2_BUS] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
150 clks[IMX6SX_CLK_PLL3_USB_OTG] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
151 clks[IMX6SX_CLK_PLL4_AUDIO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
152 clks[IMX6SX_CLK_PLL5_VIDEO] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
153 clks[IMX6SX_CLK_PLL6_ENET] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
154 clks[IMX6SX_CLK_PLL7_USB_HOST] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host", "osc", base + 0x20, 0x3);
155
156 /*
157 * Bit 20 is the reserved and read-only bit, we do this only for:
158 * - Do nothing for usbphy clk_enable/disable
159 * - Keep refcount when do usbphy clk_enable/disable, in that case,
160 * the clk framework may need to enable/disable usbphy's parent
161 */
162 clks[IMX6SX_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
163 clks[IMX6SX_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
164
165 /*
166 * usbphy*_gate needs to be on after system boots up, and software
167 * never needs to control it anymore.
168 */
169 clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
170 clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
171
172 /* FIXME 100Mhz is used for pcie ref for all imx6 pcie, excepted imx6q */
173 clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
174 clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
175
176 clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10);
177
178 clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
179 base + 0xe0, 0, 2, 0, clk_enet_ref_table,
180 &imx_ccm_lock);
181 clks[IMX6SX_CLK_ENET2_REF] = clk_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
182 base + 0xe0, 2, 2, 0, clk_enet_ref_table,
183 &imx_ccm_lock);
184 clks[IMX6SX_CLK_ENET2_REF_125M] = imx_clk_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20);
185
186 clks[IMX6SX_CLK_ENET_PTP_REF] = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
187 clks[IMX6SX_CLK_ENET_PTP] = imx_clk_gate("enet_ptp_25m", "enet_ptp_ref", base + 0xe0, 21);
188
189 /* name parent_name reg idx */
190 clks[IMX6SX_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
191 clks[IMX6SX_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
192 clks[IMX6SX_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
193 clks[IMX6SX_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus", base + 0x100, 3);
194 clks[IMX6SX_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
195 clks[IMX6SX_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
196 clks[IMX6SX_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
197 clks[IMX6SX_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
198
199 /* name parent_name mult div */
200 clks[IMX6SX_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
201 clks[IMX6SX_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
202 clks[IMX6SX_CLK_PLL3_80M] = imx_clk_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
203 clks[IMX6SX_CLK_PLL3_60M] = imx_clk_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
204 clks[IMX6SX_CLK_TWD] = imx_clk_fixed_factor("twd", "arm", 1, 2);
205 clks[IMX6SX_CLK_GPT_3M] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
206
207 clks[IMX6SX_CLK_PLL4_POST_DIV] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
208 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
209 clks[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
210 CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
211 clks[IMX6SX_CLK_PLL5_POST_DIV] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",
212 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
213 clks[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
214 CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
215
216 /* name reg shift width parent_names num_parents */
217 clks[IMX6SX_CLK_LVDS1_SEL] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
218
219 np = ccm_node;
220 base = of_iomap(np, 0);
221 WARN_ON(!base);
222
223 imx6q_pm_set_ccm_base(base);
224
225 /* name reg shift width parent_names num_parents */
226 clks[IMX6SX_CLK_STEP] = imx_clk_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
227 clks[IMX6SX_CLK_PLL1_SW] = imx_clk_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
228 clks[IMX6SX_CLK_OCRAM_SEL] = imx_clk_mux("ocram_sel", base + 0x14, 6, 2, ocram_sels, ARRAY_SIZE(ocram_sels));
229 clks[IMX6SX_CLK_PERIPH_PRE] = imx_clk_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
230 clks[IMX6SX_CLK_PERIPH2_PRE] = imx_clk_mux("periph2_pre", base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
231 clks[IMX6SX_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
232 clks[IMX6SX_CLK_PERIPH2_CLK2_SEL] = imx_clk_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
233 clks[IMX6SX_CLK_PCIE_AXI_SEL] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
234 clks[IMX6SX_CLK_GPU_AXI_SEL] = imx_clk_mux("gpu_axi_sel", base + 0x18, 8, 2, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
235 clks[IMX6SX_CLK_GPU_CORE_SEL] = imx_clk_mux("gpu_core_sel", base + 0x18, 4, 2, gpu_core_sels, ARRAY_SIZE(gpu_core_sels));
236 clks[IMX6SX_CLK_EIM_SLOW_SEL] = imx_clk_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
237 clks[IMX6SX_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
238 clks[IMX6SX_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
239 clks[IMX6SX_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
240 clks[IMX6SX_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
241 clks[IMX6SX_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
242 clks[IMX6SX_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
243 clks[IMX6SX_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
244 clks[IMX6SX_CLK_QSPI1_SEL] = imx_clk_mux_flags("qspi1_sel", base + 0x1c, 7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels), CLK_SET_RATE_PARENT);
245 clks[IMX6SX_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels));
246 clks[IMX6SX_CLK_VID_SEL] = imx_clk_mux("vid_sel", base + 0x20, 21, 3, vid_sels, ARRAY_SIZE(vid_sels));
247 clks[IMX6SX_CLK_ESAI_SEL] = imx_clk_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
248 clks[IMX6SX_CLK_CAN_SEL] = imx_clk_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
249 clks[IMX6SX_CLK_UART_SEL] = imx_clk_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
250 clks[IMX6SX_CLK_QSPI2_SEL] = imx_clk_mux_flags("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT);
251 clks[IMX6SX_CLK_SPDIF_SEL] = imx_clk_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
252 clks[IMX6SX_CLK_AUDIO_SEL] = imx_clk_mux("audio_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
253 clks[IMX6SX_CLK_ENET_PRE_SEL] = imx_clk_mux("enet_pre_sel", base + 0x34, 15, 3, enet_pre_sels, ARRAY_SIZE(enet_pre_sels));
254 clks[IMX6SX_CLK_ENET_SEL] = imx_clk_mux("enet_sel", base + 0x34, 9, 3, enet_sels, ARRAY_SIZE(enet_sels));
255 clks[IMX6SX_CLK_M4_PRE_SEL] = imx_clk_mux("m4_pre_sel", base + 0x34, 6, 3, m4_pre_sels, ARRAY_SIZE(m4_pre_sels));
256 clks[IMX6SX_CLK_M4_SEL] = imx_clk_mux("m4_sel", base + 0x34, 0, 3, m4_sels, ARRAY_SIZE(m4_sels));
257 clks[IMX6SX_CLK_ECSPI_SEL] = imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
258 clks[IMX6SX_CLK_LCDIF2_PRE_SEL] = imx_clk_mux("lcdif2_pre_sel", base + 0x38, 6, 3, lcdif2_pre_sels, ARRAY_SIZE(lcdif2_pre_sels));
259 clks[IMX6SX_CLK_LCDIF2_SEL] = imx_clk_mux("lcdif2_sel", base + 0x38, 0, 3, lcdif2_sels, ARRAY_SIZE(lcdif2_sels));
260 clks[IMX6SX_CLK_DISPLAY_SEL] = imx_clk_mux("display_sel", base + 0x3c, 14, 2, display_sels, ARRAY_SIZE(display_sels));
261 clks[IMX6SX_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
262 clks[IMX6SX_CLK_CKO1_SEL] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
263 clks[IMX6SX_CLK_CKO2_SEL] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
264 clks[IMX6SX_CLK_CKO] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
265
266 clks[IMX6SX_CLK_LDB_DI1_DIV_SEL] = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
267 clks[IMX6SX_CLK_LDB_DI0_DIV_SEL] = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
268 clks[IMX6SX_CLK_LDB_DI1_SEL] = imx_clk_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di1_sels, ARRAY_SIZE(ldb_di1_sels), CLK_SET_RATE_PARENT);
269 clks[IMX6SX_CLK_LDB_DI0_SEL] = imx_clk_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels), CLK_SET_RATE_PARENT);
270 clks[IMX6SX_CLK_LCDIF1_PRE_SEL] = imx_clk_mux_flags("lcdif1_pre_sel", base + 0x38, 15, 3, lcdif1_pre_sels, ARRAY_SIZE(lcdif1_pre_sels), CLK_SET_RATE_PARENT);
271 clks[IMX6SX_CLK_LCDIF1_SEL] = imx_clk_mux_flags("lcdif1_sel", base + 0x38, 9, 3, lcdif1_sels, ARRAY_SIZE(lcdif1_sels), CLK_SET_RATE_PARENT);
272
273 /* name parent_name reg shift width */
274 clks[IMX6SX_CLK_PERIPH_CLK2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
275 clks[IMX6SX_CLK_PERIPH2_CLK2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
276 clks[IMX6SX_CLK_IPG] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
277 clks[IMX6SX_CLK_GPU_CORE_PODF] = imx_clk_divider("gpu_core_podf", "gpu_core_sel", base + 0x18, 29, 3);
278 clks[IMX6SX_CLK_GPU_AXI_PODF] = imx_clk_divider("gpu_axi_podf", "gpu_axi_sel", base + 0x18, 26, 3);
279 clks[IMX6SX_CLK_LCDIF1_PODF] = imx_clk_divider("lcdif1_podf", "lcdif1_pred", base + 0x18, 23, 3);
280 clks[IMX6SX_CLK_QSPI1_PODF] = imx_clk_divider("qspi1_podf", "qspi1_sel", base + 0x1c, 26, 3);
281 clks[IMX6SX_CLK_EIM_SLOW_PODF] = imx_clk_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
282 clks[IMX6SX_CLK_LCDIF2_PODF] = imx_clk_divider("lcdif2_podf", "lcdif2_pred", base + 0x1c, 20, 3);
283 clks[IMX6SX_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6);
284 clks[IMX6SX_CLK_VID_PODF] = imx_clk_divider("vid_podf", "vid_sel", base + 0x20, 24, 2);
285 clks[IMX6SX_CLK_CAN_PODF] = imx_clk_divider("can_podf", "can_sel", base + 0x20, 2, 6);
286 clks[IMX6SX_CLK_USDHC4_PODF] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
287 clks[IMX6SX_CLK_USDHC3_PODF] = imx_clk_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
288 clks[IMX6SX_CLK_USDHC2_PODF] = imx_clk_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
289 clks[IMX6SX_CLK_USDHC1_PODF] = imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
290 clks[IMX6SX_CLK_UART_PODF] = imx_clk_divider("uart_podf", "uart_sel", base + 0x24, 0, 6);
291 clks[IMX6SX_CLK_ESAI_PRED] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
292 clks[IMX6SX_CLK_ESAI_PODF] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
293 clks[IMX6SX_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
294 clks[IMX6SX_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
295 clks[IMX6SX_CLK_SSI1_PRED] = imx_clk_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
296 clks[IMX6SX_CLK_SSI1_PODF] = imx_clk_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
297 clks[IMX6SX_CLK_QSPI2_PRED] = imx_clk_divider("qspi2_pred", "qspi2_sel", base + 0x2c, 18, 3);
298 clks[IMX6SX_CLK_QSPI2_PODF] = imx_clk_divider("qspi2_podf", "qspi2_pred", base + 0x2c, 21, 6);
299 clks[IMX6SX_CLK_SSI2_PRED] = imx_clk_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
300 clks[IMX6SX_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
301 clks[IMX6SX_CLK_SPDIF_PRED] = imx_clk_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
302 clks[IMX6SX_CLK_SPDIF_PODF] = imx_clk_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
303 clks[IMX6SX_CLK_AUDIO_PRED] = imx_clk_divider("audio_pred", "audio_sel", base + 0x30, 12, 3);
304 clks[IMX6SX_CLK_AUDIO_PODF] = imx_clk_divider("audio_podf", "audio_pred", base + 0x30, 9, 3);
305 clks[IMX6SX_CLK_ENET_PODF] = imx_clk_divider("enet_podf", "enet_pre_sel", base + 0x34, 12, 3);
306 clks[IMX6SX_CLK_M4_PODF] = imx_clk_divider("m4_podf", "m4_sel", base + 0x34, 3, 3);
307 clks[IMX6SX_CLK_ECSPI_PODF] = imx_clk_divider("ecspi_podf", "ecspi_sel", base + 0x38, 19, 6);
308 clks[IMX6SX_CLK_LCDIF1_PRED] = imx_clk_divider("lcdif1_pred", "lcdif1_pre_sel", base + 0x38, 12, 3);
309 clks[IMX6SX_CLK_LCDIF2_PRED] = imx_clk_divider("lcdif2_pred", "lcdif2_pre_sel", base + 0x38, 3, 3);
310 clks[IMX6SX_CLK_DISPLAY_PODF] = imx_clk_divider("display_podf", "display_sel", base + 0x3c, 16, 3);
311 clks[IMX6SX_CLK_CSI_PODF] = imx_clk_divider("csi_podf", "csi_sel", base + 0x3c, 11, 3);
312 clks[IMX6SX_CLK_CKO1_PODF] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
313 clks[IMX6SX_CLK_CKO2_PODF] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
314
315 clks[IMX6SX_CLK_LDB_DI0_DIV_3_5] = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
316 clks[IMX6SX_CLK_LDB_DI0_DIV_7] = imx_clk_fixed_factor("ldb_di0_div_7", "ldb_di0_sel", 1, 7);
317 clks[IMX6SX_CLK_LDB_DI1_DIV_3_5] = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
318 clks[IMX6SX_CLK_LDB_DI1_DIV_7] = imx_clk_fixed_factor("ldb_di1_div_7", "ldb_di1_sel", 1, 7);
319
320 /* name reg shift width busy: reg, shift parent_names num_parents */
321 clks[IMX6SX_CLK_PERIPH] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
322 clks[IMX6SX_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
323 /* name parent_name reg shift width busy: reg, shift */
324 clks[IMX6SX_CLK_OCRAM_PODF] = imx_clk_busy_divider("ocram_podf", "ocram_sel", base + 0x14, 16, 3, base + 0x48, 0);
325 clks[IMX6SX_CLK_AHB] = imx_clk_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
326 clks[IMX6SX_CLK_MMDC_PODF] = imx_clk_busy_divider("mmdc_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
327 clks[IMX6SX_CLK_ARM] = imx_clk_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
328
329 /* name parent_name reg shift */
330 /* CCGR0 */
331 clks[IMX6SX_CLK_AIPS_TZ1] = imx_clk_gate2("aips_tz1", "ahb", base + 0x68, 0);
332 clks[IMX6SX_CLK_AIPS_TZ2] = imx_clk_gate2("aips_tz2", "ahb", base + 0x68, 2);
333 clks[IMX6SX_CLK_APBH_DMA] = imx_clk_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
334 clks[IMX6SX_CLK_ASRC_MEM] = imx_clk_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
335 clks[IMX6SX_CLK_ASRC_IPG] = imx_clk_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
336 clks[IMX6SX_CLK_CAAM_MEM] = imx_clk_gate2("caam_mem", "ahb", base + 0x68, 8);
337 clks[IMX6SX_CLK_CAAM_ACLK] = imx_clk_gate2("caam_aclk", "ahb", base + 0x68, 10);
338 clks[IMX6SX_CLK_CAAM_IPG] = imx_clk_gate2("caam_ipg", "ipg", base + 0x68, 12);
339 clks[IMX6SX_CLK_CAN1_IPG] = imx_clk_gate2("can1_ipg", "ipg", base + 0x68, 14);
340 clks[IMX6SX_CLK_CAN1_SERIAL] = imx_clk_gate2("can1_serial", "can_podf", base + 0x68, 16);
341 clks[IMX6SX_CLK_CAN2_IPG] = imx_clk_gate2("can2_ipg", "ipg", base + 0x68, 18);
342 clks[IMX6SX_CLK_CAN2_SERIAL] = imx_clk_gate2("can2_serial", "can_podf", base + 0x68, 20);
343 clks[IMX6SX_CLK_DCIC1] = imx_clk_gate2("dcic1", "display_podf", base + 0x68, 24);
344 clks[IMX6SX_CLK_DCIC2] = imx_clk_gate2("dcic2", "display_podf", base + 0x68, 26);
345 clks[IMX6SX_CLK_AIPS_TZ3] = imx_clk_gate2("aips_tz3", "ahb", base + 0x68, 30);
346
347 /* CCGR1 */
348 clks[IMX6SX_CLK_ECSPI1] = imx_clk_gate2("ecspi1", "ecspi_podf", base + 0x6c, 0);
349 clks[IMX6SX_CLK_ECSPI2] = imx_clk_gate2("ecspi2", "ecspi_podf", base + 0x6c, 2);
350 clks[IMX6SX_CLK_ECSPI3] = imx_clk_gate2("ecspi3", "ecspi_podf", base + 0x6c, 4);
351 clks[IMX6SX_CLK_ECSPI4] = imx_clk_gate2("ecspi4", "ecspi_podf", base + 0x6c, 6);
352 clks[IMX6SX_CLK_ECSPI5] = imx_clk_gate2("ecspi5", "ecspi_podf", base + 0x6c, 8);
353 clks[IMX6SX_CLK_EPIT1] = imx_clk_gate2("epit1", "perclk", base + 0x6c, 12);
354 clks[IMX6SX_CLK_EPIT2] = imx_clk_gate2("epit2", "perclk", base + 0x6c, 14);
355 clks[IMX6SX_CLK_ESAI_EXTAL] = imx_clk_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
356 clks[IMX6SX_CLK_ESAI_IPG] = imx_clk_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
357 clks[IMX6SX_CLK_ESAI_MEM] = imx_clk_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
358 clks[IMX6SX_CLK_WAKEUP] = imx_clk_gate2("wakeup", "ipg", base + 0x6c, 18);
359 clks[IMX6SX_CLK_GPT_BUS] = imx_clk_gate2("gpt_bus", "perclk", base + 0x6c, 20);
360 clks[IMX6SX_CLK_GPT_SERIAL] = imx_clk_gate2("gpt_serial", "perclk", base + 0x6c, 22);
361 clks[IMX6SX_CLK_GPU] = imx_clk_gate2("gpu", "gpu_core_podf", base + 0x6c, 26);
362 clks[IMX6SX_CLK_CANFD] = imx_clk_gate2("canfd", "can_podf", base + 0x6c, 30);
363
364 /* CCGR2 */
365 clks[IMX6SX_CLK_CSI] = imx_clk_gate2("csi", "csi_podf", base + 0x70, 2);
366 clks[IMX6SX_CLK_I2C1] = imx_clk_gate2("i2c1", "perclk", base + 0x70, 6);
367 clks[IMX6SX_CLK_I2C2] = imx_clk_gate2("i2c2", "perclk", base + 0x70, 8);
368 clks[IMX6SX_CLK_I2C3] = imx_clk_gate2("i2c3", "perclk", base + 0x70, 10);
369 clks[IMX6SX_CLK_OCOTP] = imx_clk_gate2("ocotp", "ipg", base + 0x70, 12);
370 clks[IMX6SX_CLK_IOMUXC] = imx_clk_gate2("iomuxc", "lcdif1_podf", base + 0x70, 14);
371 clks[IMX6SX_CLK_IPMUX1] = imx_clk_gate2("ipmux1", "ahb", base + 0x70, 16);
372 clks[IMX6SX_CLK_IPMUX2] = imx_clk_gate2("ipmux2", "ahb", base + 0x70, 18);
373 clks[IMX6SX_CLK_IPMUX3] = imx_clk_gate2("ipmux3", "ahb", base + 0x70, 20);
374 clks[IMX6SX_CLK_TZASC1] = imx_clk_gate2("tzasc1", "mmdc_podf", base + 0x70, 22);
375 clks[IMX6SX_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb", "display_podf", base + 0x70, 28);
376 clks[IMX6SX_CLK_PXP_AXI] = imx_clk_gate2("pxp_axi", "display_podf", base + 0x70, 30);
377
378 /* CCGR3 */
379 clks[IMX6SX_CLK_M4] = imx_clk_gate2("m4", "m4_podf", base + 0x74, 2);
380 clks[IMX6SX_CLK_ENET] = imx_clk_gate2("enet", "ipg", base + 0x74, 4);
381 clks[IMX6SX_CLK_ENET_AHB] = imx_clk_gate2("enet_ahb", "enet_sel", base + 0x74, 4);
382 clks[IMX6SX_CLK_DISPLAY_AXI] = imx_clk_gate2("display_axi", "display_podf", base + 0x74, 6);
383 clks[IMX6SX_CLK_LCDIF2_PIX] = imx_clk_gate2("lcdif2_pix", "lcdif2_sel", base + 0x74, 8);
384 clks[IMX6SX_CLK_LCDIF1_PIX] = imx_clk_gate2("lcdif1_pix", "lcdif1_sel", base + 0x74, 10);
385 clks[IMX6SX_CLK_LDB_DI0] = imx_clk_gate2("ldb_di0", "ldb_di0_div_sel", base + 0x74, 12);
386 clks[IMX6SX_CLK_QSPI1] = imx_clk_gate2("qspi1", "qspi1_podf", base + 0x74, 14);
387 clks[IMX6SX_CLK_MLB] = imx_clk_gate2("mlb", "ahb", base + 0x74, 18);
388 clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2("mmdc_p0_fast", "mmdc_podf", base + 0x74, 20);
389 clks[IMX6SX_CLK_MMDC_P0_IPG] = imx_clk_gate2("mmdc_p0_ipg", "ipg", base + 0x74, 24);
390 clks[IMX6SX_CLK_OCRAM] = imx_clk_gate2("ocram", "ocram_podf", base + 0x74, 28);
391
392 /* CCGR4 */
393 clks[IMX6SX_CLK_PCIE_AXI] = imx_clk_gate2("pcie_axi", "display_podf", base + 0x78, 0);
394 clks[IMX6SX_CLK_QSPI2] = imx_clk_gate2("qspi2", "qspi2_podf", base + 0x78, 10);
395 clks[IMX6SX_CLK_PER1_BCH] = imx_clk_gate2("per1_bch", "usdhc3", base + 0x78, 12);
396 clks[IMX6SX_CLK_PER2_MAIN] = imx_clk_gate2("per2_main", "ahb", base + 0x78, 14);
397 clks[IMX6SX_CLK_PWM1] = imx_clk_gate2("pwm1", "perclk", base + 0x78, 16);
398 clks[IMX6SX_CLK_PWM2] = imx_clk_gate2("pwm2", "perclk", base + 0x78, 18);
399 clks[IMX6SX_CLK_PWM3] = imx_clk_gate2("pwm3", "perclk", base + 0x78, 20);
400 clks[IMX6SX_CLK_PWM4] = imx_clk_gate2("pwm4", "perclk", base + 0x78, 22);
401 clks[IMX6SX_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
402 clks[IMX6SX_CLK_GPMI_BCH] = imx_clk_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
403 clks[IMX6SX_CLK_GPMI_IO] = imx_clk_gate2("gpmi_io", "qspi2_podf", base + 0x78, 28);
404 clks[IMX6SX_CLK_GPMI_APB] = imx_clk_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
405
406 /* CCGR5 */
407 clks[IMX6SX_CLK_ROM] = imx_clk_gate2("rom", "ahb", base + 0x7c, 0);
408 clks[IMX6SX_CLK_SDMA] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
409 clks[IMX6SX_CLK_SPBA] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
410 clks[IMX6SX_CLK_AUDIO] = imx_clk_gate2_shared("audio", "audio_podf", base + 0x7c, 14, &share_count_audio);
411 clks[IMX6SX_CLK_SPDIF] = imx_clk_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_audio);
412 clks[IMX6SX_CLK_SSI1_IPG] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
413 clks[IMX6SX_CLK_SSI2_IPG] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
414 clks[IMX6SX_CLK_SSI3_IPG] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
415 clks[IMX6SX_CLK_SSI1] = imx_clk_gate2("ssi1", "ssi1_podf", base + 0x7c, 18);
416 clks[IMX6SX_CLK_SSI2] = imx_clk_gate2("ssi2", "ssi2_podf", base + 0x7c, 20);
417 clks[IMX6SX_CLK_SSI3] = imx_clk_gate2("ssi3", "ssi3_podf", base + 0x7c, 22);
418 clks[IMX6SX_CLK_UART_IPG] = imx_clk_gate2("uart_ipg", "ipg", base + 0x7c, 24);
419 clks[IMX6SX_CLK_UART_SERIAL] = imx_clk_gate2("uart_serial", "uart_podf", base + 0x7c, 26);
420 clks[IMX6SX_CLK_SAI1_IPG] = imx_clk_gate2("sai1_ipg", "ipg", base + 0x7c, 28);
421 clks[IMX6SX_CLK_SAI2_IPG] = imx_clk_gate2("sai2_ipg", "ipg", base + 0x7c, 30);
422 clks[IMX6SX_CLK_SAI1] = imx_clk_gate2("sai1", "ssi1_podf", base + 0x7c, 28);
423 clks[IMX6SX_CLK_SAI2] = imx_clk_gate2("sai2", "ssi2_podf", base + 0x7c, 30);
424
425 /* CCGR6 */
426 clks[IMX6SX_CLK_USBOH3] = imx_clk_gate2("usboh3", "ipg", base + 0x80, 0);
427 clks[IMX6SX_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
428 clks[IMX6SX_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
429 clks[IMX6SX_CLK_USDHC3] = imx_clk_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
430 clks[IMX6SX_CLK_USDHC4] = imx_clk_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
431 clks[IMX6SX_CLK_EIM_SLOW] = imx_clk_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
432 clks[IMX6SX_CLK_PWM8] = imx_clk_gate2("pwm8", "perclk", base + 0x80, 16);
433 clks[IMX6SX_CLK_VADC] = imx_clk_gate2("vadc", "vid_podf", base + 0x80, 20);
434 clks[IMX6SX_CLK_GIS] = imx_clk_gate2("gis", "display_podf", base + 0x80, 22);
435 clks[IMX6SX_CLK_I2C4] = imx_clk_gate2("i2c4", "perclk", base + 0x80, 24);
436 clks[IMX6SX_CLK_PWM5] = imx_clk_gate2("pwm5", "perclk", base + 0x80, 26);
437 clks[IMX6SX_CLK_PWM6] = imx_clk_gate2("pwm6", "perclk", base + 0x80, 28);
438 clks[IMX6SX_CLK_PWM7] = imx_clk_gate2("pwm7", "perclk", base + 0x80, 30);
439
440 clks[IMX6SX_CLK_CKO1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
441 clks[IMX6SX_CLK_CKO2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
442
443 /* mask handshake of mmdc */
444 writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
445
446 for (i = 0; i < ARRAY_SIZE(clks); i++)
447 if (IS_ERR(clks[i]))
448 pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
449
450 clk_data.clks = clks;
451 clk_data.clk_num = ARRAY_SIZE(clks);
452 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
453
454 clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0");
455 clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0");
456
457 for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
458 clk_prepare_enable(clks[clks_init_on[i]]);
459
460 if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
461 clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
462 clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
463 }
464
465 /* Set the default 132MHz for EIM module */
466 clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
467 clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
468
469 /* set parent clock for LCDIF1 pixel clock */
470 clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]);
471 clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]);
472
473 /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */
474 if (clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M]))
475 pr_err("Failed to set pcie bus parent clk.\n");
476 if (clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI]))
477 pr_err("Failed to set pcie parent clk.\n");
478
479 /*
480 * Init enet system AHB clock, set to 200Mhz
481 * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
482 */
483 clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
484 clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);
485 clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
486 clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
487 clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
488
489 /* Audio clocks */
490 clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);
491
492 clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
493 clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
494
495 clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
496 clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
497
498 clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
499 clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
500 clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
501 clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
502 clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
503 clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000);
504
505 clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
506 clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000);
507
508 /* Set parent clock for vadc */
509 clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
510
511 /* default parent of can_sel clock is invalid, manually set it here */
512 clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]);
513
514 /* Update gpu clock from default 528M to 720M */
515 clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
516 clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
517
518 /* Set initial power mode */
519 imx6q_set_lpm(WAIT_CLOCKED);
520
521 np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt");
522 mxc_timer_init_dt(np);
523}
524CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 048c5ad8a80b..e29f6ebe9f39 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -28,7 +28,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
28struct clk *clk_register_gate2(struct device *dev, const char *name, 28struct clk *clk_register_gate2(struct device *dev, const char *name,
29 const char *parent_name, unsigned long flags, 29 const char *parent_name, unsigned long flags,
30 void __iomem *reg, u8 bit_idx, 30 void __iomem *reg, u8 bit_idx,
31 u8 clk_gate_flags, spinlock_t *lock); 31 u8 clk_gate_flags, spinlock_t *lock,
32 unsigned int *share_count);
32 33
33struct clk * imx_obtain_fixed_clock( 34struct clk * imx_obtain_fixed_clock(
34 const char *name, unsigned long rate); 35 const char *name, unsigned long rate);
@@ -37,7 +38,15 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
37 void __iomem *reg, u8 shift) 38 void __iomem *reg, u8 shift)
38{ 39{
39 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg, 40 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
40 shift, 0, &imx_ccm_lock); 41 shift, 0, &imx_ccm_lock, NULL);
42}
43
44static inline struct clk *imx_clk_gate2_shared(const char *name,
45 const char *parent, void __iomem *reg, u8 shift,
46 unsigned int *share_count)
47{
48 return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
49 shift, 0, &imx_ccm_lock, share_count);
41} 50}
42 51
43struct clk *imx_clk_pfd(const char *name, const char *parent_name, 52struct clk *imx_clk_pfd(const char *name, const char *parent_name,
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index b5241ea76706..9ab785ce13e8 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -17,6 +17,7 @@ struct irq_data;
17struct platform_device; 17struct platform_device;
18struct pt_regs; 18struct pt_regs;
19struct clk; 19struct clk;
20struct device_node;
20enum mxc_cpu_pwr_mode; 21enum mxc_cpu_pwr_mode;
21 22
22void mx1_map_io(void); 23void mx1_map_io(void);
@@ -56,6 +57,7 @@ void imx51_init_late(void);
56void imx53_init_late(void); 57void imx53_init_late(void);
57void epit_timer_init(void __iomem *base, int irq); 58void epit_timer_init(void __iomem *base, int irq);
58void mxc_timer_init(void __iomem *, int); 59void mxc_timer_init(void __iomem *, int);
60void mxc_timer_init_dt(struct device_node *);
59int mx1_clocks_init(unsigned long fref); 61int mx1_clocks_init(unsigned long fref);
60int mx21_clocks_init(unsigned long lref, unsigned long fref); 62int mx21_clocks_init(unsigned long lref, unsigned long fref);
61int mx25_clocks_init(void); 63int mx25_clocks_init(void);
@@ -99,19 +101,6 @@ enum mx3_cpu_pwr_mode {
99void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode); 101void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
100void imx_print_silicon_rev(const char *cpu, int srev); 102void imx_print_silicon_rev(const char *cpu, int srev);
101 103
102void avic_handle_irq(struct pt_regs *);
103void tzic_handle_irq(struct pt_regs *);
104
105#define imx1_handle_irq avic_handle_irq
106#define imx21_handle_irq avic_handle_irq
107#define imx25_handle_irq avic_handle_irq
108#define imx27_handle_irq avic_handle_irq
109#define imx31_handle_irq avic_handle_irq
110#define imx35_handle_irq avic_handle_irq
111#define imx50_handle_irq tzic_handle_irq
112#define imx51_handle_irq tzic_handle_irq
113#define imx53_handle_irq tzic_handle_irq
114
115void imx_enable_cpu(int cpu, bool enable); 104void imx_enable_cpu(int cpu, bool enable);
116void imx_set_cpu_jump(int cpu, void *jump_addr); 105void imx_set_cpu_jump(int cpu, void *jump_addr);
117u32 imx_get_cpu_arg(int cpu); 106u32 imx_get_cpu_arg(int cpu);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index ba3b498a67ec..bbe8ff1f0412 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -111,6 +111,9 @@ struct device * __init imx_soc_device_init(void)
111 case MXC_CPU_IMX6DL: 111 case MXC_CPU_IMX6DL:
112 soc_id = "i.MX6DL"; 112 soc_id = "i.MX6DL";
113 break; 113 break;
114 case MXC_CPU_IMX6SX:
115 soc_id = "i.MX6SX";
116 break;
114 case MXC_CPU_IMX6Q: 117 case MXC_CPU_IMX6Q:
115 soc_id = "i.MX6Q"; 118 soc_id = "i.MX6Q";
116 break; 119 break;
diff --git a/arch/arm/mach-imx/devices/platform-mx2-emma.c b/arch/arm/mach-imx/devices/platform-mx2-emma.c
index 11bd01d402f2..0dc0651825b1 100644
--- a/arch/arm/mach-imx/devices/platform-mx2-emma.c
+++ b/arch/arm/mach-imx/devices/platform-mx2-emma.c
@@ -12,7 +12,7 @@
12#define imx_mx2_emmaprp_data_entry_single(soc) \ 12#define imx_mx2_emmaprp_data_entry_single(soc) \
13 { \ 13 { \
14 .iobase = soc ## _EMMAPRP_BASE_ADDR, \ 14 .iobase = soc ## _EMMAPRP_BASE_ADDR, \
15 .iosize = SZ_32, \ 15 .iosize = SZ_256, \
16 .irq = soc ## _INT_EMMAPRP, \ 16 .irq = soc ## _INT_EMMAPRP, \
17 } 17 }
18 18
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
deleted file mode 100644
index 9be6c1e69d68..000000000000
--- a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
+++ /dev/null
@@ -1,231 +0,0 @@
1/*
2 * Copyright (C) 2010 Eric Benard - eric@eukrea.com
3 *
4 * Based on pcm970-baseboard.c which is :
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/types.h>
23#include <linux/init.h>
24
25#include <linux/gpio.h>
26#include <linux/interrupt.h>
27#include <linux/leds.h>
28#include <linux/platform_device.h>
29#include <linux/input.h>
30#include <linux/i2c.h>
31#include <video/platform_lcd.h>
32#include <linux/backlight.h>
33
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37#include <asm/mach/map.h>
38
39#include "common.h"
40#include "devices-imx51.h"
41#include "hardware.h"
42#include "iomux-mx51.h"
43
44static iomux_v3_cfg_t eukrea_mbimxsd51_pads[] = {
45 /* LED */
46 MX51_PAD_NANDF_D10__GPIO3_30,
47 /* SWITCH */
48 NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP |
49 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
50 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
51 /* UART2 */
52 MX51_PAD_UART2_RXD__UART2_RXD,
53 MX51_PAD_UART2_TXD__UART2_TXD,
54 /* UART 3 */
55 MX51_PAD_UART3_RXD__UART3_RXD,
56 MX51_PAD_UART3_TXD__UART3_TXD,
57 MX51_PAD_KEY_COL4__UART3_RTS,
58 MX51_PAD_KEY_COL5__UART3_CTS,
59 /* SD */
60 MX51_PAD_SD1_CMD__SD1_CMD,
61 MX51_PAD_SD1_CLK__SD1_CLK,
62 MX51_PAD_SD1_DATA0__SD1_DATA0,
63 MX51_PAD_SD1_DATA1__SD1_DATA1,
64 MX51_PAD_SD1_DATA2__SD1_DATA2,
65 MX51_PAD_SD1_DATA3__SD1_DATA3,
66 /* SD1 CD */
67 NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
68 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
69 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
70 /* SSI */
71 MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
72 MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
73 MX51_PAD_AUD3_BB_CK__AUD3_TXC,
74 MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
75 /* LCD Backlight */
76 MX51_PAD_DI1_D1_CS__GPIO3_4,
77 /* LCD RST */
78 MX51_PAD_CSI1_D9__GPIO3_13,
79};
80
81#define GPIO_LED1 IMX_GPIO_NR(3, 30)
82#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31)
83#define GPIO_LCDRST IMX_GPIO_NR(3, 13)
84#define GPIO_LCDBL IMX_GPIO_NR(3, 4)
85
86static void eukrea_mbimxsd51_lcd_power_set(struct plat_lcd_data *pd,
87 unsigned int power)
88{
89 if (power)
90 gpio_direction_output(GPIO_LCDRST, 1);
91 else
92 gpio_direction_output(GPIO_LCDRST, 0);
93}
94
95static struct plat_lcd_data eukrea_mbimxsd51_lcd_power_data = {
96 .set_power = eukrea_mbimxsd51_lcd_power_set,
97};
98
99static struct platform_device eukrea_mbimxsd51_lcd_powerdev = {
100 .name = "platform-lcd",
101 .dev.platform_data = &eukrea_mbimxsd51_lcd_power_data,
102};
103
104static void eukrea_mbimxsd51_bl_set_intensity(int intensity)
105{
106 if (intensity)
107 gpio_direction_output(GPIO_LCDBL, 1);
108 else
109 gpio_direction_output(GPIO_LCDBL, 0);
110}
111
112static struct generic_bl_info eukrea_mbimxsd51_bl_info = {
113 .name = "eukrea_mbimxsd51-bl",
114 .max_intensity = 0xff,
115 .default_intensity = 0xff,
116 .set_bl_intensity = eukrea_mbimxsd51_bl_set_intensity,
117};
118
119static struct platform_device eukrea_mbimxsd51_bl_dev = {
120 .name = "generic-bl",
121 .id = 1,
122 .dev = {
123 .platform_data = &eukrea_mbimxsd51_bl_info,
124 },
125};
126
127static const struct gpio_led eukrea_mbimxsd51_leds[] __initconst = {
128 {
129 .name = "led1",
130 .default_trigger = "heartbeat",
131 .active_low = 1,
132 .gpio = GPIO_LED1,
133 },
134};
135
136static const struct gpio_led_platform_data
137 eukrea_mbimxsd51_led_info __initconst = {
138 .leds = eukrea_mbimxsd51_leds,
139 .num_leds = ARRAY_SIZE(eukrea_mbimxsd51_leds),
140};
141
142static struct gpio_keys_button eukrea_mbimxsd51_gpio_buttons[] = {
143 {
144 .gpio = GPIO_SWITCH1,
145 .code = BTN_0,
146 .desc = "BP1",
147 .active_low = 1,
148 .wakeup = 1,
149 },
150};
151
152static const struct gpio_keys_platform_data
153 eukrea_mbimxsd51_button_data __initconst = {
154 .buttons = eukrea_mbimxsd51_gpio_buttons,
155 .nbuttons = ARRAY_SIZE(eukrea_mbimxsd51_gpio_buttons),
156};
157
158static const struct imxuart_platform_data uart_pdata __initconst = {
159 .flags = IMXUART_HAVE_RTSCTS,
160};
161
162static struct i2c_board_info eukrea_mbimxsd51_i2c_devices[] = {
163 {
164 I2C_BOARD_INFO("tlv320aic23", 0x1a),
165 },
166};
167
168static const
169struct imx_ssi_platform_data eukrea_mbimxsd51_ssi_pdata __initconst = {
170 .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
171};
172
173static int screen_type;
174
175static int __init eukrea_mbimxsd51_screen_type(char *options)
176{
177 if (!strcmp(options, "dvi"))
178 screen_type = 1;
179 else if (!strcmp(options, "tft"))
180 screen_type = 0;
181
182 return 0;
183}
184__setup("screen_type=", eukrea_mbimxsd51_screen_type);
185
186/*
187 * system init for baseboard usage. Will be called by cpuimx51sd init.
188 *
189 * Add platform devices present on this baseboard and init
190 * them from CPU side as far as required to use them later on
191 */
192void __init eukrea_mbimxsd51_baseboard_init(void)
193{
194 if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd51_pads,
195 ARRAY_SIZE(eukrea_mbimxsd51_pads)))
196 printk(KERN_ERR "error setting mbimxsd pads !\n");
197
198 imx51_add_imx_uart(1, NULL);
199 imx51_add_imx_uart(2, &uart_pdata);
200
201 imx51_add_sdhci_esdhc_imx(0, NULL);
202
203 imx51_add_imx_ssi(0, &eukrea_mbimxsd51_ssi_pdata);
204
205 gpio_request(GPIO_LED1, "LED1");
206 gpio_direction_output(GPIO_LED1, 1);
207 gpio_free(GPIO_LED1);
208
209 gpio_request(GPIO_SWITCH1, "SWITCH1");
210 gpio_direction_input(GPIO_SWITCH1);
211 gpio_free(GPIO_SWITCH1);
212
213 gpio_request(GPIO_LCDRST, "LCDRST");
214 gpio_direction_output(GPIO_LCDRST, 0);
215 gpio_request(GPIO_LCDBL, "LCDBL");
216 gpio_direction_output(GPIO_LCDBL, 0);
217 if (!screen_type) {
218 platform_device_register(&eukrea_mbimxsd51_bl_dev);
219 platform_device_register(&eukrea_mbimxsd51_lcd_powerdev);
220 } else {
221 gpio_free(GPIO_LCDRST);
222 gpio_free(GPIO_LCDBL);
223 }
224
225 i2c_register_board_info(0, eukrea_mbimxsd51_i2c_devices,
226 ARRAY_SIZE(eukrea_mbimxsd51_i2c_devices));
227
228 gpio_led_register_device(-1, &eukrea_mbimxsd51_led_info);
229 imx_add_gpio_keys(&eukrea_mbimxsd51_button_data);
230 imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
231}
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index 3e1ec5ffe630..42a65e067443 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -38,7 +38,6 @@ DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
38 .map_io = mx25_map_io, 38 .map_io = mx25_map_io,
39 .init_early = imx25_init_early, 39 .init_early = imx25_init_early,
40 .init_irq = mx25_init_irq, 40 .init_irq = mx25_init_irq,
41 .handle_irq = imx25_handle_irq,
42 .init_time = imx25_timer_init, 41 .init_time = imx25_timer_init,
43 .init_machine = imx25_dt_init, 42 .init_machine = imx25_dt_init,
44 .dt_compat = imx25_dt_board_compat, 43 .dt_compat = imx25_dt_board_compat,
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 4e235ecb4021..17bd4058133d 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -43,7 +43,6 @@ DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
43 .map_io = mx27_map_io, 43 .map_io = mx27_map_io,
44 .init_early = imx27_init_early, 44 .init_early = imx27_init_early,
45 .init_irq = mx27_init_irq, 45 .init_irq = mx27_init_irq,
46 .handle_irq = imx27_handle_irq,
47 .init_time = imx27_timer_init, 46 .init_time = imx27_timer_init,
48 .init_machine = imx27_dt_init, 47 .init_machine = imx27_dt_init,
49 .dt_compat = imx27_dt_board_compat, 48 .dt_compat = imx27_dt_board_compat,
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index e1e70ef7bc2d..581f4d6c9b8a 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -39,7 +39,6 @@ DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
39 .map_io = mx31_map_io, 39 .map_io = mx31_map_io,
40 .init_early = imx31_init_early, 40 .init_early = imx31_init_early,
41 .init_irq = mx31_init_irq, 41 .init_irq = mx31_init_irq,
42 .handle_irq = imx31_handle_irq,
43 .init_time = imx31_dt_timer_init, 42 .init_time = imx31_dt_timer_init,
44 .init_machine = imx31_dt_init, 43 .init_machine = imx31_dt_init,
45 .dt_compat = imx31_dt_board_compat, 44 .dt_compat = imx31_dt_board_compat,
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
index 9d48e0065a63..a62854c59240 100644
--- a/arch/arm/mach-imx/imx35-dt.c
+++ b/arch/arm/mach-imx/imx35-dt.c
@@ -43,7 +43,6 @@ DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
43 .map_io = mx35_map_io, 43 .map_io = mx35_map_io,
44 .init_early = imx35_init_early, 44 .init_early = imx35_init_early,
45 .init_irq = imx35_irq_init, 45 .init_irq = imx35_irq_init,
46 .handle_irq = imx35_handle_irq,
47 .init_machine = imx35_dt_init, 46 .init_machine = imx35_dt_init,
48 .dt_compat = imx35_dt_board_compat, 47 .dt_compat = imx35_dt_board_compat,
49 .restart = mxc_restart, 48 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 0230d78d1413..b8cd968faa52 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -38,7 +38,6 @@ DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
38 .map_io = mx51_map_io, 38 .map_io = mx51_map_io,
39 .init_early = imx51_init_early, 39 .init_early = imx51_init_early,
40 .init_irq = mx51_init_irq, 40 .init_irq = mx51_init_irq,
41 .handle_irq = imx51_handle_irq,
42 .init_machine = imx51_dt_init, 41 .init_machine = imx51_dt_init,
43 .init_late = imx51_init_late, 42 .init_late = imx51_init_late,
44 .dt_compat = imx51_dt_board_compat, 43 .dt_compat = imx51_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 067580b2969b..ebbb5ab63529 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -142,7 +142,6 @@ MACHINE_START(APF9328, "Armadeus APF9328")
142 .map_io = mx1_map_io, 142 .map_io = mx1_map_io,
143 .init_early = imx1_init_early, 143 .init_early = imx1_init_early,
144 .init_irq = mx1_init_irq, 144 .init_irq = mx1_init_irq,
145 .handle_irq = imx1_handle_irq,
146 .init_time = apf9328_timer_init, 145 .init_time = apf9328_timer_init,
147 .init_machine = apf9328_init, 146 .init_machine = apf9328_init,
148 .restart = mxc_restart, 147 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 58b864a3fc20..39406b7e3228 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -562,7 +562,6 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
562 .map_io = mx31_map_io, 562 .map_io = mx31_map_io,
563 .init_early = imx31_init_early, 563 .init_early = imx31_init_early,
564 .init_irq = mx31_init_irq, 564 .init_irq = mx31_init_irq,
565 .handle_irq = imx31_handle_irq,
566 .init_time = armadillo5x0_timer_init, 565 .init_time = armadillo5x0_timer_init,
567 .init_machine = armadillo5x0_init, 566 .init_machine = armadillo5x0_init,
568 .restart = mxc_restart, 567 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index 2d00476f7d2c..c97d7cb39135 100644
--- a/arch/arm/mach-imx/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -57,7 +57,6 @@ MACHINE_START(BUG, "BugLabs BUGBase")
57 .map_io = mx31_map_io, 57 .map_io = mx31_map_io,
58 .init_early = imx31_init_early, 58 .init_early = imx31_init_early,
59 .init_irq = mx31_init_irq, 59 .init_irq = mx31_init_irq,
60 .handle_irq = imx31_handle_irq,
61 .init_time = bug_timer_init, 60 .init_time = bug_timer_init,
62 .init_machine = bug_board_init, 61 .init_machine = bug_board_init,
63 .restart = mxc_restart, 62 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index ea50870bda80..75b7b6aa2720 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -314,7 +314,6 @@ MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
314 .map_io = mx27_map_io, 314 .map_io = mx27_map_io,
315 .init_early = imx27_init_early, 315 .init_early = imx27_init_early,
316 .init_irq = mx27_init_irq, 316 .init_irq = mx27_init_irq,
317 .handle_irq = imx27_handle_irq,
318 .init_time = eukrea_cpuimx27_timer_init, 317 .init_time = eukrea_cpuimx27_timer_init,
319 .init_machine = eukrea_cpuimx27_init, 318 .init_machine = eukrea_cpuimx27_init,
320 .restart = mxc_restart, 319 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 65e4c53e1554..1ffa27169045 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -199,7 +199,6 @@ MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
199 .map_io = mx35_map_io, 199 .map_io = mx35_map_io,
200 .init_early = imx35_init_early, 200 .init_early = imx35_init_early,
201 .init_irq = mx35_init_irq, 201 .init_irq = mx35_init_irq,
202 .handle_irq = imx35_handle_irq,
203 .init_time = eukrea_cpuimx35_timer_init, 202 .init_time = eukrea_cpuimx35_timer_init,
204 .init_machine = eukrea_cpuimx35_init, 203 .init_machine = eukrea_cpuimx35_init,
205 .restart = mxc_restart, 204 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
deleted file mode 100644
index 1fba2b8e983f..000000000000
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ /dev/null
@@ -1,364 +0,0 @@
1/*
2 *
3 * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
4 *
5 * based on board-mx51_babbage.c which is
6 * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
7 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
8 *
9 * The code contained herein is licensed under the GNU General Public
10 * License. You may obtain a copy of the GNU General Public License
11 * Version 2 or later at the following locations:
12 *
13 * http://www.opensource.org/licenses/gpl-license.html
14 * http://www.gnu.org/copyleft/gpl.html
15 */
16
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/i2c.h>
20#include <linux/i2c/tsc2007.h>
21#include <linux/gpio.h>
22#include <linux/delay.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/i2c-gpio.h>
26#include <linux/spi/spi.h>
27#include <linux/can/platform/mcp251x.h>
28
29#include <asm/setup.h>
30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32#include <asm/mach/time.h>
33
34#include "common.h"
35#include "devices-imx51.h"
36#include "eukrea-baseboards.h"
37#include "hardware.h"
38#include "iomux-mx51.h"
39
40#define USBH1_RST IMX_GPIO_NR(2, 28)
41#define ETH_RST IMX_GPIO_NR(2, 31)
42#define TSC2007_IRQGPIO_REV2 IMX_GPIO_NR(3, 12)
43#define TSC2007_IRQGPIO_REV3 IMX_GPIO_NR(4, 0)
44#define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
45#define CAN_RST IMX_GPIO_NR(4, 15)
46#define CAN_NCS IMX_GPIO_NR(4, 24)
47#define CAN_RXOBF_REV2 IMX_GPIO_NR(1, 4)
48#define CAN_RXOBF_REV3 IMX_GPIO_NR(3, 12)
49#define CAN_RX1BF IMX_GPIO_NR(1, 6)
50#define CAN_TXORTS IMX_GPIO_NR(1, 7)
51#define CAN_TX1RTS IMX_GPIO_NR(1, 8)
52#define CAN_TX2RTS IMX_GPIO_NR(1, 9)
53#define I2C_SCL IMX_GPIO_NR(4, 16)
54#define I2C_SDA IMX_GPIO_NR(4, 17)
55
56/* USB_CTRL_1 */
57#define MX51_USB_CTRL_1_OFFSET 0x10
58#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
59
60#define MX51_USB_PLLDIV_12_MHZ 0x00
61#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
62#define MX51_USB_PLL_DIV_24_MHZ 0x02
63
64static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
65 /* UART1 */
66 MX51_PAD_UART1_RXD__UART1_RXD,
67 MX51_PAD_UART1_TXD__UART1_TXD,
68 MX51_PAD_UART1_RTS__UART1_RTS,
69 MX51_PAD_UART1_CTS__UART1_CTS,
70
71 /* USB HOST1 */
72 MX51_PAD_USBH1_CLK__USBH1_CLK,
73 MX51_PAD_USBH1_DIR__USBH1_DIR,
74 MX51_PAD_USBH1_NXT__USBH1_NXT,
75 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
76 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
77 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
78 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
79 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
80 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
81 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
82 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
83 MX51_PAD_USBH1_STP__USBH1_STP,
84 MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
85
86 /* FEC */
87 MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
88
89 /* HSI2C */
90 MX51_PAD_I2C1_CLK__GPIO4_16,
91 MX51_PAD_I2C1_DAT__GPIO4_17,
92
93 /* I2C1 */
94 MX51_PAD_SD2_CMD__I2C1_SCL,
95 MX51_PAD_SD2_CLK__I2C1_SDA,
96
97 /* CAN */
98 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
99 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
100 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
101 MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
102 MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
103 MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
104 MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
105 MX51_PAD_GPIO1_6__GPIO1_6,
106 MX51_PAD_GPIO1_7__GPIO1_7,
107 MX51_PAD_GPIO1_8__GPIO1_8,
108 MX51_PAD_GPIO1_9__GPIO1_9,
109
110 /* Touchscreen */
111 /* IRQ */
112 NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
113 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
114 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
115 NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP |
116 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
117 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
118};
119
120static const struct imxuart_platform_data uart_pdata __initconst = {
121 .flags = IMXUART_HAVE_RTSCTS,
122};
123
124static int tsc2007_get_pendown_state(struct device *dev)
125{
126 if (mx51_revision() < IMX_CHIP_REVISION_3_0)
127 return !gpio_get_value(TSC2007_IRQGPIO_REV2);
128 else
129 return !gpio_get_value(TSC2007_IRQGPIO_REV3);
130}
131
132static struct tsc2007_platform_data tsc2007_info = {
133 .model = 2007,
134 .x_plate_ohms = 180,
135 .get_pendown_state = tsc2007_get_pendown_state,
136};
137
138static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
139 {
140 I2C_BOARD_INFO("pcf8563", 0x51),
141 }, {
142 I2C_BOARD_INFO("tsc2007", 0x49),
143 .platform_data = &tsc2007_info,
144 },
145};
146
147static const struct mxc_nand_platform_data
148 eukrea_cpuimx51sd_nand_board_info __initconst = {
149 .width = 1,
150 .hw_ecc = 1,
151 .flash_bbt = 1,
152};
153
154/* This function is board specific as the bit mask for the plldiv will also
155be different for other Freescale SoCs, thus a common bitmask is not
156possible and cannot get place in /plat-mxc/ehci.c.*/
157static int initialize_otg_port(struct platform_device *pdev)
158{
159 u32 v;
160 void __iomem *usb_base;
161 void __iomem *usbother_base;
162
163 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
164 if (!usb_base)
165 return -ENOMEM;
166 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
167
168 /* Set the PHY clock to 19.2MHz */
169 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
170 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
171 v |= MX51_USB_PLL_DIV_19_2_MHZ;
172 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
173 iounmap(usb_base);
174
175 mdelay(10);
176
177 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
178}
179
180static int initialize_usbh1_port(struct platform_device *pdev)
181{
182 u32 v;
183 void __iomem *usb_base;
184 void __iomem *usbother_base;
185
186 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
187 if (!usb_base)
188 return -ENOMEM;
189 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
190
191 /* The clock for the USBH1 ULPI port will come from the PHY. */
192 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
193 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
194 usbother_base + MX51_USB_CTRL_1_OFFSET);
195 iounmap(usb_base);
196
197 mdelay(10);
198
199 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
200 MXC_EHCI_ITC_NO_THRESHOLD);
201}
202
203static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
204 .init = initialize_otg_port,
205 .portsc = MXC_EHCI_UTMI_16BIT,
206};
207
208static const struct fsl_usb2_platform_data usb_pdata __initconst = {
209 .operating_mode = FSL_USB2_DR_DEVICE,
210 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
211};
212
213static const struct mxc_usbh_platform_data usbh1_config __initconst = {
214 .init = initialize_usbh1_port,
215 .portsc = MXC_EHCI_MODE_ULPI,
216};
217
218static bool otg_mode_host __initdata;
219
220static int __init eukrea_cpuimx51sd_otg_mode(char *options)
221{
222 if (!strcmp(options, "host"))
223 otg_mode_host = true;
224 else if (!strcmp(options, "device"))
225 otg_mode_host = false;
226 else
227 pr_info("otg_mode neither \"host\" nor \"device\". "
228 "Defaulting to device\n");
229 return 1;
230}
231__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
232
233static struct i2c_gpio_platform_data pdata = {
234 .sda_pin = I2C_SDA,
235 .sda_is_open_drain = 0,
236 .scl_pin = I2C_SCL,
237 .scl_is_open_drain = 0,
238 .udelay = 2,
239};
240
241static struct platform_device hsi2c_gpio_device = {
242 .name = "i2c-gpio",
243 .id = 0,
244 .dev.platform_data = &pdata,
245};
246
247static struct mcp251x_platform_data mcp251x_info = {
248 .oscillator_frequency = 24E6,
249};
250
251static struct spi_board_info cpuimx51sd_spi_device[] = {
252 {
253 .modalias = "mcp2515",
254 .max_speed_hz = 10000000,
255 .bus_num = 0,
256 .mode = SPI_MODE_0,
257 .chip_select = 0,
258 .platform_data = &mcp251x_info,
259 /* irq number is run-time assigned */
260 },
261};
262
263static int cpuimx51sd_spi1_cs[] = {
264 CAN_NCS,
265};
266
267static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
268 .chipselect = cpuimx51sd_spi1_cs,
269 .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
270};
271
272static struct platform_device *rev2_platform_devices[] __initdata = {
273 &hsi2c_gpio_device,
274};
275
276static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
277 .bitrate = 100000,
278};
279
280static void __init eukrea_cpuimx51sd_init(void)
281{
282 imx51_soc_init();
283
284 mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
285 ARRAY_SIZE(eukrea_cpuimx51sd_pads));
286
287 imx51_add_imx_uart(0, &uart_pdata);
288 imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
289 imx51_add_imx2_wdt(0);
290
291 gpio_request(ETH_RST, "eth_rst");
292 gpio_set_value(ETH_RST, 1);
293 imx51_add_fec(NULL);
294
295 gpio_request(CAN_IRQGPIO, "can_irq");
296 gpio_direction_input(CAN_IRQGPIO);
297 gpio_free(CAN_IRQGPIO);
298 gpio_request(CAN_NCS, "can_ncs");
299 gpio_direction_output(CAN_NCS, 1);
300 gpio_free(CAN_NCS);
301 gpio_request(CAN_RST, "can_rst");
302 gpio_direction_output(CAN_RST, 0);
303 msleep(20);
304 gpio_set_value(CAN_RST, 1);
305 imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
306 cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
307 spi_register_board_info(cpuimx51sd_spi_device,
308 ARRAY_SIZE(cpuimx51sd_spi_device));
309
310 if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
311 eukrea_cpuimx51sd_i2c_devices[1].irq =
312 gpio_to_irq(TSC2007_IRQGPIO_REV2),
313 platform_add_devices(rev2_platform_devices,
314 ARRAY_SIZE(rev2_platform_devices));
315 gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
316 gpio_direction_input(TSC2007_IRQGPIO_REV2);
317 gpio_free(TSC2007_IRQGPIO_REV2);
318 } else {
319 eukrea_cpuimx51sd_i2c_devices[1].irq =
320 gpio_to_irq(TSC2007_IRQGPIO_REV3),
321 imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
322 gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
323 gpio_direction_input(TSC2007_IRQGPIO_REV3);
324 gpio_free(TSC2007_IRQGPIO_REV3);
325 }
326
327 i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
328 ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
329
330 if (otg_mode_host)
331 imx51_add_mxc_ehci_otg(&dr_utmi_config);
332 else {
333 initialize_otg_port(NULL);
334 imx51_add_fsl_usb2_udc(&usb_pdata);
335 }
336
337 gpio_request(USBH1_RST, "usb_rst");
338 gpio_direction_output(USBH1_RST, 0);
339 msleep(20);
340 gpio_set_value(USBH1_RST, 1);
341 imx51_add_mxc_ehci_hs(1, &usbh1_config);
342
343#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
344 eukrea_mbimxsd51_baseboard_init();
345#endif
346}
347
348static void __init eukrea_cpuimx51sd_timer_init(void)
349{
350 mx51_clocks_init(32768, 24000000, 22579200, 0);
351}
352
353MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
354 /* Maintainer: Eric Bénard <eric@eukrea.com> */
355 .atag_offset = 0x100,
356 .map_io = mx51_map_io,
357 .init_early = imx51_init_early,
358 .init_irq = mx51_init_irq,
359 .handle_irq = imx51_handle_irq,
360 .init_time = eukrea_cpuimx51sd_timer_init,
361 .init_machine = eukrea_cpuimx51sd_init,
362 .init_late = imx51_init_late,
363 .restart = mxc_restart,
364MACHINE_END
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 4bf454424249..e978dda1434c 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -165,7 +165,6 @@ MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
165 .map_io = mx25_map_io, 165 .map_io = mx25_map_io,
166 .init_early = imx25_init_early, 166 .init_early = imx25_init_early,
167 .init_irq = mx25_init_irq, 167 .init_irq = mx25_init_irq,
168 .handle_irq = imx25_handle_irq,
169 .init_time = eukrea_cpuimx25_timer_init, 168 .init_time = eukrea_cpuimx25_timer_init,
170 .init_machine = eukrea_cpuimx25_init, 169 .init_machine = eukrea_cpuimx25_init,
171 .restart = mxc_restart, 170 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 97f9c6297fcf..b61bd8ed5568 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -604,7 +604,6 @@ MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
604 .map_io = mx27_map_io, 604 .map_io = mx27_map_io,
605 .init_early = imx27_init_early, 605 .init_early = imx27_init_early,
606 .init_irq = mx27_init_irq, 606 .init_irq = mx27_init_irq,
607 .handle_irq = imx27_handle_irq,
608 .init_time = visstrim_m10_timer_init, 607 .init_time = visstrim_m10_timer_init,
609 .init_machine = visstrim_m10_board_init, 608 .init_machine = visstrim_m10_board_init,
610 .restart = mxc_restart, 609 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 1a851aea6832..bb3ca0429680 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -71,7 +71,6 @@ MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
71 .map_io = mx27_map_io, 71 .map_io = mx27_map_io,
72 .init_early = imx27_init_early, 72 .init_early = imx27_init_early,
73 .init_irq = mx27_init_irq, 73 .init_irq = mx27_init_irq,
74 .handle_irq = imx27_handle_irq,
75 .init_time = mx27ipcam_timer_init, 74 .init_time = mx27ipcam_timer_init,
76 .init_machine = mx27ipcam_init, 75 .init_machine = mx27ipcam_init,
77 .restart = mxc_restart, 76 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 3da2e3e44ce9..9992089d3ad1 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -77,7 +77,6 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
77 .map_io = mx27_map_io, 77 .map_io = mx27_map_io,
78 .init_early = imx27_init_early, 78 .init_early = imx27_init_early,
79 .init_irq = mx27_init_irq, 79 .init_irq = mx27_init_irq,
80 .handle_irq = imx27_handle_irq,
81 .init_time = mx27lite_timer_init, 80 .init_time = mx27lite_timer_init,
82 .init_machine = mx27lite_init, 81 .init_machine = mx27lite_init,
83 .restart = mxc_restart, 82 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
index 77b77a92bb5d..b899c0b59afd 100644
--- a/arch/arm/mach-imx/mach-imx50.c
+++ b/arch/arm/mach-imx/mach-imx50.c
@@ -31,7 +31,6 @@ static const char *imx50_dt_board_compat[] __initconst = {
31DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)") 31DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
32 .map_io = mx53_map_io, 32 .map_io = mx53_map_io,
33 .init_irq = mx53_init_irq, 33 .init_irq = mx53_init_irq,
34 .handle_irq = imx50_handle_irq,
35 .init_machine = imx50_dt_init, 34 .init_machine = imx50_dt_init,
36 .dt_compat = imx50_dt_board_compat, 35 .dt_compat = imx50_dt_board_compat,
37 .restart = mxc_restart, 36 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 65850908a4b4..2bad387956c0 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -40,7 +40,6 @@ DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
40 .map_io = mx53_map_io, 40 .map_io = mx53_map_io,
41 .init_early = imx53_init_early, 41 .init_early = imx53_init_early,
42 .init_irq = mx53_init_irq, 42 .init_irq = mx53_init_irq,
43 .handle_irq = imx53_handle_irq,
44 .init_machine = imx53_dt_init, 43 .init_machine = imx53_dt_init,
45 .init_late = imx53_init_late, 44 .init_late = imx53_init_late,
46 .dt_compat = imx53_dt_board_compat, 45 .dt_compat = imx53_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
new file mode 100644
index 000000000000..02fccf6033ac
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <linux/irqchip.h>
10#include <linux/of_platform.h>
11#include <asm/mach/arch.h>
12#include <asm/mach/map.h>
13
14#include "common.h"
15
16static void __init imx6sx_init_machine(void)
17{
18 struct device *parent;
19
20 mxc_arch_reset_init_dt();
21
22 parent = imx_soc_device_init();
23 if (parent == NULL)
24 pr_warn("failed to initialize soc device\n");
25
26 of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
27
28 imx_anatop_init();
29}
30
31static void __init imx6sx_init_irq(void)
32{
33 imx_init_revision_from_anatop();
34 imx_init_l2cache();
35 imx_src_init();
36 imx_gpc_init();
37 irqchip_init();
38}
39
40static const char *imx6sx_dt_compat[] __initconst = {
41 "fsl,imx6sx",
42 NULL,
43};
44
45DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
46 .map_io = debug_ll_io_init,
47 .init_irq = imx6sx_init_irq,
48 .init_machine = imx6sx_init_machine,
49 .dt_compat = imx6sx_dt_compat,
50 .restart = mxc_restart,
51MACHINE_END
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index c7bc41d6b468..31df4361996f 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -289,7 +289,6 @@ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
289 .map_io = kzm_map_io, 289 .map_io = kzm_map_io,
290 .init_early = imx31_init_early, 290 .init_early = imx31_init_early,
291 .init_irq = mx31_init_irq, 291 .init_irq = mx31_init_irq,
292 .handle_irq = imx31_handle_irq,
293 .init_time = kzm_timer_init, 292 .init_time = kzm_timer_init,
294 .init_machine = kzm_board_init, 293 .init_machine = kzm_board_init,
295 .restart = mxc_restart, 294 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 9f883e4d6fc9..77fda3de4290 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -138,7 +138,6 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
138 .map_io = mx1_map_io, 138 .map_io = mx1_map_io,
139 .init_early = imx1_init_early, 139 .init_early = imx1_init_early,
140 .init_irq = mx1_init_irq, 140 .init_irq = mx1_init_irq,
141 .handle_irq = imx1_handle_irq,
142 .init_time = mx1ads_timer_init, 141 .init_time = mx1ads_timer_init,
143 .init_machine = mx1ads_init, 142 .init_machine = mx1ads_init,
144 .restart = mxc_restart, 143 .restart = mxc_restart,
@@ -149,7 +148,6 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
149 .map_io = mx1_map_io, 148 .map_io = mx1_map_io,
150 .init_early = imx1_init_early, 149 .init_early = imx1_init_early,
151 .init_irq = mx1_init_irq, 150 .init_irq = mx1_init_irq,
152 .handle_irq = imx1_handle_irq,
153 .init_time = mx1ads_timer_init, 151 .init_time = mx1ads_timer_init,
154 .init_machine = mx1ads_init, 152 .init_machine = mx1ads_init,
155 .restart = mxc_restart, 153 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index a06aa4dc37fc..703ce31d7379 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -17,51 +17,46 @@
17#include <linux/platform_device.h> 17#include <linux/platform_device.h>
18#include <linux/mtd/mtd.h> 18#include <linux/mtd/mtd.h>
19#include <linux/mtd/physmap.h> 19#include <linux/mtd/physmap.h>
20#include <linux/basic_mmio_gpio.h>
20#include <linux/gpio.h> 21#include <linux/gpio.h>
22#include <linux/regulator/fixed.h>
23#include <linux/regulator/machine.h>
21#include <asm/mach-types.h> 24#include <asm/mach-types.h>
22#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
23#include <asm/mach/time.h>
24#include <asm/mach/map.h>
25 26
26#include "common.h" 27#include "common.h"
27#include "devices-imx21.h" 28#include "devices-imx21.h"
28#include "hardware.h" 29#include "hardware.h"
29#include "iomux-mx21.h" 30#include "iomux-mx21.h"
30 31
31/* 32#define MX21ADS_CS8900A_REG (MX21_CS1_BASE_ADDR + 0x000000)
32 * Memory-mapped I/O on MX21ADS base board 33#define MX21ADS_ST16C255_IOBASE_REG (MX21_CS1_BASE_ADDR + 0x200000)
33 */ 34#define MX21ADS_VERSION_REG (MX21_CS1_BASE_ADDR + 0x400000)
34#define MX21ADS_MMIO_BASE_ADDR 0xf5000000 35#define MX21ADS_IO_REG (MX21_CS1_BASE_ADDR + 0x800000)
35#define MX21ADS_MMIO_SIZE 0xc00000
36
37#define MX21ADS_REG_ADDR(offset) (void __force __iomem *) \
38 (MX21ADS_MMIO_BASE_ADDR + (offset))
39 36
40#define MX21ADS_CS8900A_MMIO_SIZE 0x200000 37#define MX21ADS_MMC_CD IMX_GPIO_NR(4, 25)
41#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11) 38#define MX21ADS_CS8900A_IRQ_GPIO IMX_GPIO_NR(5, 11)
42#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000) 39#define MX21ADS_MMGPIO_BASE (6 * 32)
43#define MX21ADS_VERSION_REG MX21ADS_REG_ADDR(0x400000)
44#define MX21ADS_IO_REG MX21ADS_REG_ADDR(0x800000)
45 40
46/* MX21ADS_IO_REG bit definitions */ 41/* MX21ADS_IO_REG bit definitions */
47#define MX21ADS_IO_SD_WP 0x0001 /* read */ 42#define MX21ADS_IO_SD_WP (MX21ADS_MMGPIO_BASE + 0)
48#define MX21ADS_IO_TP6 0x0001 /* write */ 43#define MX21ADS_IO_TP6 (MX21ADS_IO_SD_WP)
49#define MX21ADS_IO_SW_SEL 0x0002 /* read */ 44#define MX21ADS_IO_SW_SEL (MX21ADS_MMGPIO_BASE + 1)
50#define MX21ADS_IO_TP7 0x0002 /* write */ 45#define MX21ADS_IO_TP7 (MX21ADS_IO_SW_SEL)
51#define MX21ADS_IO_RESET_E_UART 0x0004 46#define MX21ADS_IO_RESET_E_UART (MX21ADS_MMGPIO_BASE + 2)
52#define MX21ADS_IO_RESET_BASE 0x0008 47#define MX21ADS_IO_RESET_BASE (MX21ADS_MMGPIO_BASE + 3)
53#define MX21ADS_IO_CSI_CTL2 0x0010 48#define MX21ADS_IO_CSI_CTL2 (MX21ADS_MMGPIO_BASE + 4)
54#define MX21ADS_IO_CSI_CTL1 0x0020 49#define MX21ADS_IO_CSI_CTL1 (MX21ADS_MMGPIO_BASE + 5)
55#define MX21ADS_IO_CSI_CTL0 0x0040 50#define MX21ADS_IO_CSI_CTL0 (MX21ADS_MMGPIO_BASE + 6)
56#define MX21ADS_IO_UART1_EN 0x0080 51#define MX21ADS_IO_UART1_EN (MX21ADS_MMGPIO_BASE + 7)
57#define MX21ADS_IO_UART4_EN 0x0100 52#define MX21ADS_IO_UART4_EN (MX21ADS_MMGPIO_BASE + 8)
58#define MX21ADS_IO_LCDON 0x0200 53#define MX21ADS_IO_LCDON (MX21ADS_MMGPIO_BASE + 9)
59#define MX21ADS_IO_IRDA_EN 0x0400 54#define MX21ADS_IO_IRDA_EN (MX21ADS_MMGPIO_BASE + 10)
60#define MX21ADS_IO_IRDA_FIR_SEL 0x0800 55#define MX21ADS_IO_IRDA_FIR_SEL (MX21ADS_MMGPIO_BASE + 11)
61#define MX21ADS_IO_IRDA_MD0_B 0x1000 56#define MX21ADS_IO_IRDA_MD0_B (MX21ADS_MMGPIO_BASE + 12)
62#define MX21ADS_IO_IRDA_MD1 0x2000 57#define MX21ADS_IO_IRDA_MD1 (MX21ADS_MMGPIO_BASE + 13)
63#define MX21ADS_IO_LED4_ON 0x4000 58#define MX21ADS_IO_LED4_ON (MX21ADS_MMGPIO_BASE + 14)
64#define MX21ADS_IO_LED3_ON 0x8000 59#define MX21ADS_IO_LED3_ON (MX21ADS_MMGPIO_BASE + 15)
65 60
66static const int mx21ads_pins[] __initconst = { 61static const int mx21ads_pins[] __initconst = {
67 62
@@ -143,11 +138,8 @@ static struct physmap_flash_data mx21ads_flash_data = {
143 .width = 4, 138 .width = 4,
144}; 139};
145 140
146static struct resource mx21ads_flash_resource = { 141static struct resource mx21ads_flash_resource =
147 .start = MX21_CS0_BASE_ADDR, 142 DEFINE_RES_MEM(MX21_CS0_BASE_ADDR, SZ_32M);
148 .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
149 .flags = IORESOURCE_MEM,
150};
151 143
152static struct platform_device mx21ads_nor_mtd_device = { 144static struct platform_device mx21ads_nor_mtd_device = {
153 .name = "physmap-flash", 145 .name = "physmap-flash",
@@ -160,7 +152,7 @@ static struct platform_device mx21ads_nor_mtd_device = {
160}; 152};
161 153
162static struct resource mx21ads_cs8900_resources[] __initdata = { 154static struct resource mx21ads_cs8900_resources[] __initdata = {
163 DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE), 155 DEFINE_RES_MEM(MX21ADS_CS8900A_REG, SZ_1K),
164 /* irq number is run-time assigned */ 156 /* irq number is run-time assigned */
165 DEFINE_RES_IRQ(-1), 157 DEFINE_RES_IRQ(-1),
166}; 158};
@@ -179,24 +171,50 @@ static const struct imxuart_platform_data uart_pdata_rts __initconst = {
179static const struct imxuart_platform_data uart_pdata_norts __initconst = { 171static const struct imxuart_platform_data uart_pdata_norts __initconst = {
180}; 172};
181 173
182static int mx21ads_fb_init(struct platform_device *pdev) 174static struct resource mx21ads_mmgpio_resource =
183{ 175 DEFINE_RES_MEM_NAMED(MX21ADS_IO_REG, SZ_2, "dat");
184 u16 tmp;
185 176
186 tmp = __raw_readw(MX21ADS_IO_REG); 177static struct bgpio_pdata mx21ads_mmgpio_pdata = {
187 tmp |= MX21ADS_IO_LCDON; 178 .base = MX21ADS_MMGPIO_BASE,
188 __raw_writew(tmp, MX21ADS_IO_REG); 179 .ngpio = 16,
189 return 0; 180};
190}
191 181
192static void mx21ads_fb_exit(struct platform_device *pdev) 182static struct platform_device mx21ads_mmgpio = {
193{ 183 .name = "basic-mmio-gpio",
194 u16 tmp; 184 .id = PLATFORM_DEVID_AUTO,
185 .resource = &mx21ads_mmgpio_resource,
186 .num_resources = 1,
187 .dev = {
188 .platform_data = &mx21ads_mmgpio_pdata,
189 },
190};
195 191
196 tmp = __raw_readw(MX21ADS_IO_REG); 192static struct regulator_consumer_supply mx21ads_lcd_regulator_consumer =
197 tmp &= ~MX21ADS_IO_LCDON; 193 REGULATOR_SUPPLY("lcd", "imx-fb.0");
198 __raw_writew(tmp, MX21ADS_IO_REG); 194
199} 195static struct regulator_init_data mx21ads_lcd_regulator_init_data = {
196 .constraints = {
197 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
198 },
199 .consumer_supplies = &mx21ads_lcd_regulator_consumer,
200 .num_consumer_supplies = 1,
201};
202
203static struct fixed_voltage_config mx21ads_lcd_regulator_pdata = {
204 .supply_name = "LCD",
205 .microvolts = 3300000,
206 .gpio = MX21ADS_IO_LCDON,
207 .enable_high = 1,
208 .init_data = &mx21ads_lcd_regulator_init_data,
209};
210
211static struct platform_device mx21ads_lcd_regulator = {
212 .name = "reg-fixed-voltage",
213 .id = PLATFORM_DEVID_AUTO,
214 .dev = {
215 .platform_data = &mx21ads_lcd_regulator_pdata,
216 },
217};
200 218
201/* 219/*
202 * Connected is a portrait Sharp-QVGA display 220 * Connected is a portrait Sharp-QVGA display
@@ -229,26 +247,30 @@ static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
229 .pwmr = 0x00a903ff, 247 .pwmr = 0x00a903ff,
230 .lscr1 = 0x00120300, 248 .lscr1 = 0x00120300,
231 .dmacr = 0x00020008, 249 .dmacr = 0x00020008,
232
233 .init = mx21ads_fb_init,
234 .exit = mx21ads_fb_exit,
235}; 250};
236 251
237static int mx21ads_sdhc_get_ro(struct device *dev) 252static int mx21ads_sdhc_get_ro(struct device *dev)
238{ 253{
239 return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0; 254 return gpio_get_value(MX21ADS_IO_SD_WP);
240} 255}
241 256
242static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, 257static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
243 void *data) 258 void *data)
244{ 259{
245 return request_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), detect_irq, 260 int ret;
246 IRQF_TRIGGER_FALLING, "mmc-detect", data); 261
262 ret = gpio_request(MX21ADS_IO_SD_WP, "mmc-ro");
263 if (ret)
264 return ret;
265
266 return request_irq(gpio_to_irq(MX21ADS_MMC_CD), detect_irq,
267 IRQF_TRIGGER_FALLING, "mmc-detect", data);
247} 268}
248 269
249static void mx21ads_sdhc_exit(struct device *dev, void *data) 270static void mx21ads_sdhc_exit(struct device *dev, void *data)
250{ 271{
251 free_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), data); 272 free_irq(gpio_to_irq(MX21ADS_MMC_CD), data);
273 gpio_free(MX21ADS_IO_SD_WP);
252} 274}
253 275
254static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = { 276static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
@@ -264,29 +286,9 @@ mx21ads_nand_board_info __initconst = {
264 .hw_ecc = 1, 286 .hw_ecc = 1,
265}; 287};
266 288
267static struct map_desc mx21ads_io_desc[] __initdata = {
268 /*
269 * Memory-mapped I/O on MX21ADS Base board:
270 * - CS8900A Ethernet controller
271 * - ST16C2552CJ UART
272 * - CPU and Base board version
273 * - Base board I/O register
274 */
275 {
276 .virtual = MX21ADS_MMIO_BASE_ADDR,
277 .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
278 .length = MX21ADS_MMIO_SIZE,
279 .type = MT_DEVICE,
280 },
281};
282
283static void __init mx21ads_map_io(void)
284{
285 mx21_map_io();
286 iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
287}
288
289static struct platform_device *platform_devices[] __initdata = { 289static struct platform_device *platform_devices[] __initdata = {
290 &mx21ads_mmgpio,
291 &mx21ads_lcd_regulator,
290 &mx21ads_nor_mtd_device, 292 &mx21ads_nor_mtd_device,
291}; 293};
292 294
@@ -300,12 +302,13 @@ static void __init mx21ads_board_init(void)
300 imx21_add_imx_uart0(&uart_pdata_rts); 302 imx21_add_imx_uart0(&uart_pdata_rts);
301 imx21_add_imx_uart2(&uart_pdata_norts); 303 imx21_add_imx_uart2(&uart_pdata_norts);
302 imx21_add_imx_uart3(&uart_pdata_rts); 304 imx21_add_imx_uart3(&uart_pdata_rts);
303 imx21_add_imx_fb(&mx21ads_fb_data);
304 imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata); 305 imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
305 imx21_add_mxc_nand(&mx21ads_nand_board_info); 306 imx21_add_mxc_nand(&mx21ads_nand_board_info);
306 307
307 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 308 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
308 309
310 imx21_add_imx_fb(&mx21ads_fb_data);
311
309 mx21ads_cs8900_resources[1].start = 312 mx21ads_cs8900_resources[1].start =
310 gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO); 313 gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
311 mx21ads_cs8900_resources[1].end = 314 mx21ads_cs8900_resources[1].end =
@@ -321,10 +324,9 @@ static void __init mx21ads_timer_init(void)
321MACHINE_START(MX21ADS, "Freescale i.MX21ADS") 324MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
322 /* maintainer: Freescale Semiconductor, Inc. */ 325 /* maintainer: Freescale Semiconductor, Inc. */
323 .atag_offset = 0x100, 326 .atag_offset = 0x100,
324 .map_io = mx21ads_map_io, 327 .map_io = mx21_map_io,
325 .init_early = imx21_init_early, 328 .init_early = imx21_init_early,
326 .init_irq = mx21_init_irq, 329 .init_irq = mx21_init_irq,
327 .handle_irq = imx21_handle_irq,
328 .init_time = mx21ads_timer_init, 330 .init_time = mx21ads_timer_init,
329 .init_machine = mx21ads_board_init, 331 .init_machine = mx21ads_board_init,
330 .restart = mxc_restart, 332 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 13490c203050..ea1fa199c148 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -263,7 +263,6 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
263 .map_io = mx25_map_io, 263 .map_io = mx25_map_io,
264 .init_early = imx25_init_early, 264 .init_early = imx25_init_early,
265 .init_irq = mx25_init_irq, 265 .init_irq = mx25_init_irq,
266 .handle_irq = imx25_handle_irq,
267 .init_time = mx25pdk_timer_init, 266 .init_time = mx25pdk_timer_init,
268 .init_machine = mx25pdk_init, 267 .init_machine = mx25pdk_init,
269 .restart = mxc_restart, 268 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 25b3e4c9bc0a..435a5428a678 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -544,7 +544,6 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
544 .map_io = mx27_map_io, 544 .map_io = mx27_map_io,
545 .init_early = imx27_init_early, 545 .init_early = imx27_init_early,
546 .init_irq = mx27_init_irq, 546 .init_irq = mx27_init_irq,
547 .handle_irq = imx27_handle_irq,
548 .init_time = mx27pdk_timer_init, 547 .init_time = mx27pdk_timer_init,
549 .init_machine = mx27pdk_init, 548 .init_machine = mx27pdk_init,
550 .restart = mxc_restart, 549 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index a7a4a9c67615..2f834ce8f39c 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -391,7 +391,6 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
391 .map_io = mx27ads_map_io, 391 .map_io = mx27ads_map_io,
392 .init_early = imx27_init_early, 392 .init_early = imx27_init_early,
393 .init_irq = mx27_init_irq, 393 .init_irq = mx27_init_irq,
394 .handle_irq = imx27_handle_irq,
395 .init_time = mx27ads_timer_init, 394 .init_time = mx27ads_timer_init,
396 .init_machine = mx27ads_board_init, 395 .init_machine = mx27ads_board_init,
397 .restart = mxc_restart, 396 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 50044a21b388..4217871a9653 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -775,7 +775,6 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
775 .map_io = mx31_map_io, 775 .map_io = mx31_map_io,
776 .init_early = imx31_init_early, 776 .init_early = imx31_init_early,
777 .init_irq = mx31_init_irq, 777 .init_irq = mx31_init_irq,
778 .handle_irq = imx31_handle_irq,
779 .init_time = mx31_3ds_timer_init, 778 .init_time = mx31_3ds_timer_init,
780 .init_machine = mx31_3ds_init, 779 .init_machine = mx31_3ds_init,
781 .reserve = mx31_3ds_reserve, 780 .reserve = mx31_3ds_reserve,
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index daf8889125cc..d08c37c696f6 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -582,7 +582,6 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
582 .map_io = mx31ads_map_io, 582 .map_io = mx31ads_map_io,
583 .init_early = imx31_init_early, 583 .init_early = imx31_init_early,
584 .init_irq = mx31ads_init_irq, 584 .init_irq = mx31ads_init_irq,
585 .handle_irq = imx31_handle_irq,
586 .init_time = mx31ads_timer_init, 585 .init_time = mx31ads_timer_init,
587 .init_machine = mx31ads_init, 586 .init_machine = mx31ads_init,
588 .restart = mxc_restart, 587 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 832b1e2f964e..eee042fa2768 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -308,7 +308,6 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
308 .map_io = mx31_map_io, 308 .map_io = mx31_map_io,
309 .init_early = imx31_init_early, 309 .init_early = imx31_init_early,
310 .init_irq = mx31_init_irq, 310 .init_irq = mx31_init_irq,
311 .handle_irq = imx31_handle_irq,
312 .init_time = mx31lilly_timer_init, 311 .init_time = mx31lilly_timer_init,
313 .init_machine = mx31lilly_board_init, 312 .init_machine = mx31lilly_board_init,
314 .restart = mxc_restart, 313 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index bea07299b61a..fa15d0b6118d 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -291,7 +291,6 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
291 .map_io = mx31lite_map_io, 291 .map_io = mx31lite_map_io,
292 .init_early = imx31_init_early, 292 .init_early = imx31_init_early,
293 .init_irq = mx31_init_irq, 293 .init_irq = mx31_init_irq,
294 .handle_irq = imx31_handle_irq,
295 .init_time = mx31lite_timer_init, 294 .init_time = mx31lite_timer_init,
296 .init_machine = mx31lite_init, 295 .init_machine = mx31lite_init,
297 .restart = mxc_restart, 296 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 8f45afe785f8..08730f238449 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -600,7 +600,6 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
600 .map_io = mx31_map_io, 600 .map_io = mx31_map_io,
601 .init_early = imx31_init_early, 601 .init_early = imx31_init_early,
602 .init_irq = mx31_init_irq, 602 .init_irq = mx31_init_irq,
603 .handle_irq = imx31_handle_irq,
604 .init_time = mx31moboard_timer_init, 603 .init_time = mx31moboard_timer_init,
605 .init_machine = mx31moboard_init, 604 .init_machine = mx31moboard_init,
606 .restart = mxc_restart, 605 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index a42f4f07051f..4e8b184d773b 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -615,7 +615,6 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
615 .map_io = mx35_map_io, 615 .map_io = mx35_map_io,
616 .init_early = imx35_init_early, 616 .init_early = imx35_init_early,
617 .init_irq = mx35_init_irq, 617 .init_irq = mx35_init_irq,
618 .handle_irq = imx35_handle_irq,
619 .init_time = mx35pdk_timer_init, 618 .init_time = mx35pdk_timer_init,
620 .init_machine = mx35_3ds_init, 619 .init_machine = mx35_3ds_init,
621 .reserve = mx35_3ds_reserve, 620 .reserve = mx35_3ds_reserve,
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
deleted file mode 100644
index f3d264a636fa..000000000000
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ /dev/null
@@ -1,428 +0,0 @@
1/*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/i2c.h>
16#include <linux/gpio.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/input.h>
20#include <linux/spi/flash.h>
21#include <linux/spi/spi.h>
22
23#include <asm/setup.h>
24#include <asm/mach-types.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/time.h>
27
28#include "common.h"
29#include "devices-imx51.h"
30#include "hardware.h"
31#include "iomux-mx51.h"
32
33#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
34#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
35#define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5)
36#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
37#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
38#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
39#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
40#define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6)
41#define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5)
42
43/* USB_CTRL_1 */
44#define MX51_USB_CTRL_1_OFFSET 0x10
45#define MX51_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
46
47#define MX51_USB_PLLDIV_12_MHZ 0x00
48#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
49#define MX51_USB_PLL_DIV_24_MHZ 0x02
50
51static struct gpio_keys_button babbage_buttons[] = {
52 {
53 .gpio = BABBAGE_POWER_KEY,
54 .code = BTN_0,
55 .desc = "PWR",
56 .active_low = 1,
57 .wakeup = 1,
58 },
59};
60
61static const struct gpio_keys_platform_data imx_button_data __initconst = {
62 .buttons = babbage_buttons,
63 .nbuttons = ARRAY_SIZE(babbage_buttons),
64};
65
66static iomux_v3_cfg_t mx51babbage_pads[] = {
67 /* UART1 */
68 MX51_PAD_UART1_RXD__UART1_RXD,
69 MX51_PAD_UART1_TXD__UART1_TXD,
70 MX51_PAD_UART1_RTS__UART1_RTS,
71 MX51_PAD_UART1_CTS__UART1_CTS,
72
73 /* UART2 */
74 MX51_PAD_UART2_RXD__UART2_RXD,
75 MX51_PAD_UART2_TXD__UART2_TXD,
76
77 /* UART3 */
78 MX51_PAD_EIM_D25__UART3_RXD,
79 MX51_PAD_EIM_D26__UART3_TXD,
80 MX51_PAD_EIM_D27__UART3_RTS,
81 MX51_PAD_EIM_D24__UART3_CTS,
82
83 /* I2C1 */
84 MX51_PAD_EIM_D16__I2C1_SDA,
85 MX51_PAD_EIM_D19__I2C1_SCL,
86
87 /* I2C2 */
88 MX51_PAD_KEY_COL4__I2C2_SCL,
89 MX51_PAD_KEY_COL5__I2C2_SDA,
90
91 /* HSI2C */
92 MX51_PAD_I2C1_CLK__I2C1_CLK,
93 MX51_PAD_I2C1_DAT__I2C1_DAT,
94
95 /* USB HOST1 */
96 MX51_PAD_USBH1_CLK__USBH1_CLK,
97 MX51_PAD_USBH1_DIR__USBH1_DIR,
98 MX51_PAD_USBH1_NXT__USBH1_NXT,
99 MX51_PAD_USBH1_DATA0__USBH1_DATA0,
100 MX51_PAD_USBH1_DATA1__USBH1_DATA1,
101 MX51_PAD_USBH1_DATA2__USBH1_DATA2,
102 MX51_PAD_USBH1_DATA3__USBH1_DATA3,
103 MX51_PAD_USBH1_DATA4__USBH1_DATA4,
104 MX51_PAD_USBH1_DATA5__USBH1_DATA5,
105 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
106 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
107
108 /* USB HUB reset line*/
109 MX51_PAD_GPIO1_7__GPIO1_7,
110
111 /* USB PHY reset line */
112 MX51_PAD_EIM_D21__GPIO2_5,
113
114 /* FEC */
115 MX51_PAD_EIM_EB2__FEC_MDIO,
116 MX51_PAD_EIM_EB3__FEC_RDATA1,
117 MX51_PAD_EIM_CS2__FEC_RDATA2,
118 MX51_PAD_EIM_CS3__FEC_RDATA3,
119 MX51_PAD_EIM_CS4__FEC_RX_ER,
120 MX51_PAD_EIM_CS5__FEC_CRS,
121 MX51_PAD_NANDF_RB2__FEC_COL,
122 MX51_PAD_NANDF_RB3__FEC_RX_CLK,
123 MX51_PAD_NANDF_D9__FEC_RDATA0,
124 MX51_PAD_NANDF_D8__FEC_TDATA0,
125 MX51_PAD_NANDF_CS2__FEC_TX_ER,
126 MX51_PAD_NANDF_CS3__FEC_MDC,
127 MX51_PAD_NANDF_CS4__FEC_TDATA1,
128 MX51_PAD_NANDF_CS5__FEC_TDATA2,
129 MX51_PAD_NANDF_CS6__FEC_TDATA3,
130 MX51_PAD_NANDF_CS7__FEC_TX_EN,
131 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
132
133 /* FEC PHY reset line */
134 MX51_PAD_EIM_A20__GPIO2_14,
135
136 /* SD 1 */
137 MX51_PAD_SD1_CMD__SD1_CMD,
138 MX51_PAD_SD1_CLK__SD1_CLK,
139 MX51_PAD_SD1_DATA0__SD1_DATA0,
140 MX51_PAD_SD1_DATA1__SD1_DATA1,
141 MX51_PAD_SD1_DATA2__SD1_DATA2,
142 MX51_PAD_SD1_DATA3__SD1_DATA3,
143 /* CD/WP from controller */
144 MX51_PAD_GPIO1_0__SD1_CD,
145 MX51_PAD_GPIO1_1__SD1_WP,
146
147 /* SD 2 */
148 MX51_PAD_SD2_CMD__SD2_CMD,
149 MX51_PAD_SD2_CLK__SD2_CLK,
150 MX51_PAD_SD2_DATA0__SD2_DATA0,
151 MX51_PAD_SD2_DATA1__SD2_DATA1,
152 MX51_PAD_SD2_DATA2__SD2_DATA2,
153 MX51_PAD_SD2_DATA3__SD2_DATA3,
154 /* CD/WP gpio */
155 MX51_PAD_GPIO1_6__GPIO1_6,
156 MX51_PAD_GPIO1_5__GPIO1_5,
157
158 /* eCSPI1 */
159 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
160 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
161 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
162 MX51_PAD_CSPI1_SS0__GPIO4_24,
163 MX51_PAD_CSPI1_SS1__GPIO4_25,
164
165 /* Audio */
166 MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
167 MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
168 MX51_PAD_AUD3_BB_CK__AUD3_TXC,
169 MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
170};
171
172/* Serial ports */
173static const struct imxuart_platform_data uart_pdata __initconst = {
174 .flags = IMXUART_HAVE_RTSCTS,
175};
176
177static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
178 .bitrate = 100000,
179};
180
181static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
182 .bitrate = 400000,
183};
184
185static struct gpio mx51_babbage_usbh1_gpios[] = {
186 { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
187 { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
188};
189
190static int gpio_usbh1_active(void)
191{
192 iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
193 int ret;
194
195 /* Set USBH1_STP to GPIO and toggle it */
196 mxc_iomux_v3_setup_pad(usbh1stp_gpio);
197 ret = gpio_request_array(mx51_babbage_usbh1_gpios,
198 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
199
200 if (ret) {
201 pr_debug("failed to get USBH1 pins: %d\n", ret);
202 return ret;
203 }
204
205 msleep(100);
206 gpio_set_value(BABBAGE_USBH1_STP, 1);
207 gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
208 gpio_free_array(mx51_babbage_usbh1_gpios,
209 ARRAY_SIZE(mx51_babbage_usbh1_gpios));
210 return 0;
211}
212
213static inline void babbage_usbhub_reset(void)
214{
215 int ret;
216
217 /* Reset USB hub */
218 ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
219 GPIOF_OUT_INIT_LOW, "GPIO1_7");
220 if (ret) {
221 printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
222 return;
223 }
224
225 msleep(2);
226 /* Deassert reset */
227 gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
228}
229
230static inline void babbage_fec_reset(void)
231{
232 int ret;
233
234 /* reset FEC PHY */
235 ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
236 GPIOF_OUT_INIT_LOW, "fec-phy-reset");
237 if (ret) {
238 printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
239 return;
240 }
241 msleep(1);
242 gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
243}
244
245/* This function is board specific as the bit mask for the plldiv will also
246be different for other Freescale SoCs, thus a common bitmask is not
247possible and cannot get place in /plat-mxc/ehci.c.*/
248static int initialize_otg_port(struct platform_device *pdev)
249{
250 u32 v;
251 void __iomem *usb_base;
252 void __iomem *usbother_base;
253
254 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
255 if (!usb_base)
256 return -ENOMEM;
257 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
258
259 /* Set the PHY clock to 19.2MHz */
260 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
261 v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
262 v |= MX51_USB_PLL_DIV_19_2_MHZ;
263 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
264 iounmap(usb_base);
265
266 mdelay(10);
267
268 return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
269}
270
271static int initialize_usbh1_port(struct platform_device *pdev)
272{
273 u32 v;
274 void __iomem *usb_base;
275 void __iomem *usbother_base;
276
277 usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
278 if (!usb_base)
279 return -ENOMEM;
280 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
281
282 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
283 v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
284 __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
285 iounmap(usb_base);
286
287 mdelay(10);
288
289 return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
290 MXC_EHCI_ITC_NO_THRESHOLD);
291}
292
293static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
294 .init = initialize_otg_port,
295 .portsc = MXC_EHCI_UTMI_16BIT,
296};
297
298static const struct fsl_usb2_platform_data usb_pdata __initconst = {
299 .operating_mode = FSL_USB2_DR_DEVICE,
300 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
301};
302
303static const struct mxc_usbh_platform_data usbh1_config __initconst = {
304 .init = initialize_usbh1_port,
305 .portsc = MXC_EHCI_MODE_ULPI,
306};
307
308static bool otg_mode_host __initdata;
309
310static int __init babbage_otg_mode(char *options)
311{
312 if (!strcmp(options, "host"))
313 otg_mode_host = true;
314 else if (!strcmp(options, "device"))
315 otg_mode_host = false;
316 else
317 pr_info("otg_mode neither \"host\" nor \"device\". "
318 "Defaulting to device\n");
319 return 1;
320}
321__setup("otg_mode=", babbage_otg_mode);
322
323static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
324 {
325 .modalias = "mtd_dataflash",
326 .max_speed_hz = 25000000,
327 .bus_num = 0,
328 .chip_select = 1,
329 .mode = SPI_MODE_0,
330 .platform_data = NULL,
331 },
332};
333
334static int mx51_babbage_spi_cs[] = {
335 BABBAGE_ECSPI1_CS0,
336 BABBAGE_ECSPI1_CS1,
337};
338
339static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
340 .chipselect = mx51_babbage_spi_cs,
341 .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
342};
343
344static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
345 .cd_type = ESDHC_CD_CONTROLLER,
346 .wp_type = ESDHC_WP_CONTROLLER,
347};
348
349static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
350 .cd_gpio = BABBAGE_SD2_CD,
351 .wp_gpio = BABBAGE_SD2_WP,
352 .cd_type = ESDHC_CD_GPIO,
353 .wp_type = ESDHC_WP_GPIO,
354};
355
356void __init imx51_babbage_common_init(void)
357{
358 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
359 ARRAY_SIZE(mx51babbage_pads));
360}
361
362/*
363 * Board specific initialization.
364 */
365static void __init mx51_babbage_init(void)
366{
367 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
368 iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
369 PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH);
370
371 imx51_soc_init();
372
373 imx51_babbage_common_init();
374
375 imx51_add_imx_uart(0, &uart_pdata);
376 imx51_add_imx_uart(1, NULL);
377 imx51_add_imx_uart(2, &uart_pdata);
378
379 babbage_fec_reset();
380 imx51_add_fec(NULL);
381
382 /* Set the PAD settings for the pwr key. */
383 mxc_iomux_v3_setup_pad(power_key);
384 imx_add_gpio_keys(&imx_button_data);
385
386 imx51_add_imx_i2c(0, &babbage_i2c_data);
387 imx51_add_imx_i2c(1, &babbage_i2c_data);
388 imx51_add_hsi2c(&babbage_hsi2c_data);
389
390 if (otg_mode_host)
391 imx51_add_mxc_ehci_otg(&dr_utmi_config);
392 else {
393 initialize_otg_port(NULL);
394 imx51_add_fsl_usb2_udc(&usb_pdata);
395 }
396
397 gpio_usbh1_active();
398 imx51_add_mxc_ehci_hs(1, &usbh1_config);
399 /* setback USBH1_STP to be function */
400 mxc_iomux_v3_setup_pad(usbh1stp);
401 babbage_usbhub_reset();
402
403 imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
404 imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
405
406 spi_register_board_info(mx51_babbage_spi_board_info,
407 ARRAY_SIZE(mx51_babbage_spi_board_info));
408 imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
409 imx51_add_imx2_wdt(0);
410}
411
412static void __init mx51_babbage_timer_init(void)
413{
414 mx51_clocks_init(32768, 24000000, 22579200, 0);
415}
416
417MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
418 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
419 .atag_offset = 0x100,
420 .map_io = mx51_map_io,
421 .init_early = imx51_init_early,
422 .init_irq = mx51_init_irq,
423 .handle_irq = imx51_handle_irq,
424 .init_time = mx51_babbage_timer_init,
425 .init_machine = mx51_babbage_init,
426 .init_late = imx51_init_late,
427 .restart = mxc_restart,
428MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index c91894003da9..0b5d1ca31b9f 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -267,7 +267,6 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
267 .map_io = mx27_map_io, 267 .map_io = mx27_map_io,
268 .init_early = imx27_init_early, 268 .init_early = imx27_init_early,
269 .init_irq = mx27_init_irq, 269 .init_irq = mx27_init_irq,
270 .handle_irq = imx27_handle_irq,
271 .init_time = mxt_td60_timer_init, 270 .init_time = mxt_td60_timer_init,
272 .init_machine = mxt_td60_board_init, 271 .init_machine = mxt_td60_board_init,
273 .restart = mxc_restart, 272 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index bf3ac51d5aca..12212378c672 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -245,8 +245,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
245 int ret; 245 int ret;
246 246
247 ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq, 247 ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
248 IRQF_DISABLED | IRQF_TRIGGER_FALLING, 248 IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
249 "imx-mmc-detect", data);
250 if (ret) 249 if (ret)
251 printk(KERN_ERR 250 printk(KERN_ERR
252 "pca100: Failed to request irq for sd/mmc detection\n"); 251 "pca100: Failed to request irq for sd/mmc detection\n");
@@ -421,7 +420,6 @@ MACHINE_START(PCA100, "phyCARD-i.MX27")
421 .map_io = mx27_map_io, 420 .map_io = mx27_map_io,
422 .init_early = imx27_init_early, 421 .init_early = imx27_init_early,
423 .init_irq = mx27_init_irq, 422 .init_irq = mx27_init_irq,
424 .handle_irq = imx27_handle_irq,
425 .init_machine = pca100_init, 423 .init_machine = pca100_init,
426 .init_time = pca100_timer_init, 424 .init_time = pca100_timer_init,
427 .restart = mxc_restart, 425 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 639a3dfb0092..81b8affb9448 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -703,7 +703,6 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
703 .map_io = mx31_map_io, 703 .map_io = mx31_map_io,
704 .init_early = imx31_init_early, 704 .init_early = imx31_init_early,
705 .init_irq = mx31_init_irq, 705 .init_irq = mx31_init_irq,
706 .handle_irq = imx31_handle_irq,
707 .init_time = pcm037_timer_init, 706 .init_time = pcm037_timer_init,
708 .init_machine = pcm037_init, 707 .init_machine = pcm037_init,
709 .init_late = pcm037_init_late, 708 .init_late = pcm037_init_late,
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 592ddbe031ac..6c56fb5553c7 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -351,7 +351,6 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
351 .map_io = mx27_map_io, 351 .map_io = mx27_map_io,
352 .init_early = imx27_init_early, 352 .init_early = imx27_init_early,
353 .init_irq = mx27_init_irq, 353 .init_irq = mx27_init_irq,
354 .handle_irq = imx27_handle_irq,
355 .init_time = pcm038_timer_init, 354 .init_time = pcm038_timer_init,
356 .init_machine = pcm038_init, 355 .init_machine = pcm038_init,
357 .restart = mxc_restart, 356 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index ac504b67326b..c62b5d261345 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -400,7 +400,6 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
400 .map_io = mx35_map_io, 400 .map_io = mx35_map_io,
401 .init_early = imx35_init_early, 401 .init_early = imx35_init_early,
402 .init_irq = mx35_init_irq, 402 .init_irq = mx35_init_irq,
403 .handle_irq = imx35_handle_irq,
404 .init_time = pcm043_timer_init, 403 .init_time = pcm043_timer_init,
405 .init_machine = pcm043_init, 404 .init_machine = pcm043_init,
406 .restart = mxc_restart, 405 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 22af27ed457e..a213e7b9cb1c 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -266,7 +266,6 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
266 .map_io = mx31_map_io, 266 .map_io = mx31_map_io,
267 .init_early = imx31_init_early, 267 .init_early = imx31_init_early,
268 .init_irq = mx31_init_irq, 268 .init_irq = mx31_init_irq,
269 .handle_irq = imx31_handle_irq,
270 .init_time = qong_timer_init, 269 .init_time = qong_timer_init,
271 .init_machine = qong_init, 270 .init_machine = qong_init,
272 .restart = mxc_restart, 271 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index b0fa10dd79fe..1f6bc3f7ae14 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -137,7 +137,6 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
137 .map_io = mx1_map_io, 137 .map_io = mx1_map_io,
138 .init_early = imx1_init_early, 138 .init_early = imx1_init_early,
139 .init_irq = mx1_init_irq, 139 .init_irq = mx1_init_irq,
140 .handle_irq = imx1_handle_irq,
141 .init_time = scb9328_timer_init, 140 .init_time = scb9328_timer_init,
142 .init_machine = scb9328_init, 141 .init_machine = scb9328_init,
143 .restart = mxc_restart, 142 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 8825d1217d18..872b3c6ba408 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -310,7 +310,6 @@ MACHINE_START(VPR200, "VPR200")
310 .map_io = mx35_map_io, 310 .map_io = mx35_map_io,
311 .init_early = imx35_init_early, 311 .init_early = imx35_init_early,
312 .init_irq = mx35_init_irq, 312 .init_irq = mx35_init_irq,
313 .handle_irq = imx35_handle_irq,
314 .init_time = vpr200_timer_init, 313 .init_time = vpr200_timer_init,
315 .init_machine = vpr200_board_init, 314 .init_machine = vpr200_board_init,
316 .restart = mxc_restart, 315 .restart = mxc_restart,
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index b08ab3ad4a6d..75d6a37e1ae4 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -36,6 +36,7 @@
36#define MXC_CPU_MX53 53 36#define MXC_CPU_MX53 53
37#define MXC_CPU_IMX6SL 0x60 37#define MXC_CPU_IMX6SL 0x60
38#define MXC_CPU_IMX6DL 0x61 38#define MXC_CPU_IMX6DL 0x61
39#define MXC_CPU_IMX6SX 0x62
39#define MXC_CPU_IMX6Q 0x63 40#define MXC_CPU_IMX6Q 0x63
40 41
41#define IMX_CHIP_REVISION_1_0 0x10 42#define IMX_CHIP_REVISION_1_0 0x10
@@ -163,6 +164,11 @@ static inline bool cpu_is_imx6dl(void)
163 return __mxc_cpu_type == MXC_CPU_IMX6DL; 164 return __mxc_cpu_type == MXC_CPU_IMX6DL;
164} 165}
165 166
167static inline bool cpu_is_imx6sx(void)
168{
169 return __mxc_cpu_type == MXC_CPU_IMX6SX;
170}
171
166static inline bool cpu_is_imx6q(void) 172static inline bool cpu_is_imx6q(void)
167{ 173{
168 return __mxc_cpu_type == MXC_CPU_IMX6Q; 174 return __mxc_cpu_type == MXC_CPU_IMX6Q;
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 65222ea0df6d..bed081e58262 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -28,6 +28,9 @@
28#include <linux/delay.h> 28#include <linux/delay.h>
29#include <linux/err.h> 29#include <linux/err.h>
30#include <linux/sched_clock.h> 30#include <linux/sched_clock.h>
31#include <linux/of.h>
32#include <linux/of_address.h>
33#include <linux/of_irq.h>
31 34
32#include <asm/mach/time.h> 35#include <asm/mach/time.h>
33 36
@@ -328,3 +331,15 @@ void __init mxc_timer_init(void __iomem *base, int irq)
328 /* Make irqs happen */ 331 /* Make irqs happen */
329 setup_irq(irq, &mxc_timer_irq); 332 setup_irq(irq, &mxc_timer_irq);
330} 333}
334
335void __init mxc_timer_init_dt(struct device_node *np)
336{
337 void __iomem *base;
338 int irq;
339
340 base = of_iomap(np, 0);
341 WARN_ON(!base);
342 irq = irq_of_parse_and_map(np, 0);
343
344 mxc_timer_init(base, irq);
345}
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
index 8183178d5aa3..7828af4b2022 100644
--- a/arch/arm/mach-imx/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -125,7 +125,7 @@ static __init void tzic_init_gc(int idx, unsigned int irq_start)
125 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0); 125 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
126} 126}
127 127
128asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs) 128static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
129{ 129{
130 u32 stat; 130 u32 stat;
131 int i, irqofs, handled; 131 int i, irqofs, handled;
@@ -189,6 +189,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
189 for (i = 0; i < 4; i++, irq_base += 32) 189 for (i = 0; i < 4; i++, irq_base += 32)
190 tzic_init_gc(i, irq_base); 190 tzic_init_gc(i, irq_base);
191 191
192 set_handle_irq(tzic_handle_irq);
193
192#ifdef CONFIG_FIQ 194#ifdef CONFIG_FIQ
193 /* Initialize FIQ */ 195 /* Initialize FIQ */
194 init_FIQ(FIQ_START); 196 init_FIQ(FIQ_START);
diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
new file mode 100644
index 000000000000..421d8bb76f2f
--- /dev/null
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -0,0 +1,256 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_IMX6SX_H
11#define __DT_BINDINGS_CLOCK_IMX6SX_H
12
13#define IMX6SX_CLK_DUMMY 0
14#define IMX6SX_CLK_CKIL 1
15#define IMX6SX_CLK_CKIH 2
16#define IMX6SX_CLK_OSC 3
17#define IMX6SX_CLK_PLL1_SYS 4
18#define IMX6SX_CLK_PLL2_BUS 5
19#define IMX6SX_CLK_PLL3_USB_OTG 6
20#define IMX6SX_CLK_PLL4_AUDIO 7
21#define IMX6SX_CLK_PLL5_VIDEO 8
22#define IMX6SX_CLK_PLL6_ENET 9
23#define IMX6SX_CLK_PLL7_USB_HOST 10
24#define IMX6SX_CLK_USBPHY1 11
25#define IMX6SX_CLK_USBPHY2 12
26#define IMX6SX_CLK_USBPHY1_GATE 13
27#define IMX6SX_CLK_USBPHY2_GATE 14
28#define IMX6SX_CLK_PCIE_REF 15
29#define IMX6SX_CLK_PCIE_REF_125M 16
30#define IMX6SX_CLK_ENET_REF 17
31#define IMX6SX_CLK_PLL2_PFD0 18
32#define IMX6SX_CLK_PLL2_PFD1 19
33#define IMX6SX_CLK_PLL2_PFD2 20
34#define IMX6SX_CLK_PLL2_PFD3 21
35#define IMX6SX_CLK_PLL3_PFD0 22
36#define IMX6SX_CLK_PLL3_PFD1 23
37#define IMX6SX_CLK_PLL3_PFD2 24
38#define IMX6SX_CLK_PLL3_PFD3 25
39#define IMX6SX_CLK_PLL2_198M 26
40#define IMX6SX_CLK_PLL3_120M 27
41#define IMX6SX_CLK_PLL3_80M 28
42#define IMX6SX_CLK_PLL3_60M 29
43#define IMX6SX_CLK_TWD 30
44#define IMX6SX_CLK_PLL4_POST_DIV 31
45#define IMX6SX_CLK_PLL4_AUDIO_DIV 32
46#define IMX6SX_CLK_PLL5_POST_DIV 33
47#define IMX6SX_CLK_PLL5_VIDEO_DIV 34
48#define IMX6SX_CLK_STEP 35
49#define IMX6SX_CLK_PLL1_SW 36
50#define IMX6SX_CLK_OCRAM_SEL 37
51#define IMX6SX_CLK_PERIPH_PRE 38
52#define IMX6SX_CLK_PERIPH2_PRE 39
53#define IMX6SX_CLK_PERIPH_CLK2_SEL 40
54#define IMX6SX_CLK_PERIPH2_CLK2_SEL 41
55#define IMX6SX_CLK_PCIE_AXI_SEL 42
56#define IMX6SX_CLK_GPU_AXI_SEL 43
57#define IMX6SX_CLK_GPU_CORE_SEL 44
58#define IMX6SX_CLK_EIM_SLOW_SEL 45
59#define IMX6SX_CLK_USDHC1_SEL 46
60#define IMX6SX_CLK_USDHC2_SEL 47
61#define IMX6SX_CLK_USDHC3_SEL 48
62#define IMX6SX_CLK_USDHC4_SEL 49
63#define IMX6SX_CLK_SSI1_SEL 50
64#define IMX6SX_CLK_SSI2_SEL 51
65#define IMX6SX_CLK_SSI3_SEL 52
66#define IMX6SX_CLK_QSPI1_SEL 53
67#define IMX6SX_CLK_PERCLK_SEL 54
68#define IMX6SX_CLK_VID_SEL 55
69#define IMX6SX_CLK_ESAI_SEL 56
70#define IMX6SX_CLK_LDB_DI0_DIV_SEL 57
71#define IMX6SX_CLK_LDB_DI1_DIV_SEL 58
72#define IMX6SX_CLK_CAN_SEL 59
73#define IMX6SX_CLK_UART_SEL 60
74#define IMX6SX_CLK_QSPI2_SEL 61
75#define IMX6SX_CLK_LDB_DI1_SEL 62
76#define IMX6SX_CLK_LDB_DI0_SEL 63
77#define IMX6SX_CLK_SPDIF_SEL 64
78#define IMX6SX_CLK_AUDIO_SEL 65
79#define IMX6SX_CLK_ENET_PRE_SEL 66
80#define IMX6SX_CLK_ENET_SEL 67
81#define IMX6SX_CLK_M4_PRE_SEL 68
82#define IMX6SX_CLK_M4_SEL 69
83#define IMX6SX_CLK_ECSPI_SEL 70
84#define IMX6SX_CLK_LCDIF1_PRE_SEL 71
85#define IMX6SX_CLK_LCDIF2_PRE_SEL 72
86#define IMX6SX_CLK_LCDIF1_SEL 73
87#define IMX6SX_CLK_LCDIF2_SEL 74
88#define IMX6SX_CLK_DISPLAY_SEL 75
89#define IMX6SX_CLK_CSI_SEL 76
90#define IMX6SX_CLK_CKO1_SEL 77
91#define IMX6SX_CLK_CKO2_SEL 78
92#define IMX6SX_CLK_CKO 79
93#define IMX6SX_CLK_PERIPH_CLK2 80
94#define IMX6SX_CLK_PERIPH2_CLK2 81
95#define IMX6SX_CLK_IPG 82
96#define IMX6SX_CLK_GPU_CORE_PODF 83
97#define IMX6SX_CLK_GPU_AXI_PODF 84
98#define IMX6SX_CLK_LCDIF1_PODF 85
99#define IMX6SX_CLK_QSPI1_PODF 86
100#define IMX6SX_CLK_EIM_SLOW_PODF 87
101#define IMX6SX_CLK_LCDIF2_PODF 88
102#define IMX6SX_CLK_PERCLK 89
103#define IMX6SX_CLK_VID_PODF 90
104#define IMX6SX_CLK_CAN_PODF 91
105#define IMX6SX_CLK_USDHC1_PODF 92
106#define IMX6SX_CLK_USDHC2_PODF 93
107#define IMX6SX_CLK_USDHC3_PODF 94
108#define IMX6SX_CLK_USDHC4_PODF 95
109#define IMX6SX_CLK_UART_PODF 96
110#define IMX6SX_CLK_ESAI_PRED 97
111#define IMX6SX_CLK_ESAI_PODF 98
112#define IMX6SX_CLK_SSI3_PRED 99
113#define IMX6SX_CLK_SSI3_PODF 100
114#define IMX6SX_CLK_SSI1_PRED 101
115#define IMX6SX_CLK_SSI1_PODF 102
116#define IMX6SX_CLK_QSPI2_PRED 103
117#define IMX6SX_CLK_QSPI2_PODF 104
118#define IMX6SX_CLK_SSI2_PRED 105
119#define IMX6SX_CLK_SSI2_PODF 106
120#define IMX6SX_CLK_SPDIF_PRED 107
121#define IMX6SX_CLK_SPDIF_PODF 108
122#define IMX6SX_CLK_AUDIO_PRED 109
123#define IMX6SX_CLK_AUDIO_PODF 110
124#define IMX6SX_CLK_ENET_PODF 111
125#define IMX6SX_CLK_M4_PODF 112
126#define IMX6SX_CLK_ECSPI_PODF 113
127#define IMX6SX_CLK_LCDIF1_PRED 114
128#define IMX6SX_CLK_LCDIF2_PRED 115
129#define IMX6SX_CLK_DISPLAY_PODF 116
130#define IMX6SX_CLK_CSI_PODF 117
131#define IMX6SX_CLK_LDB_DI0_DIV_3_5 118
132#define IMX6SX_CLK_LDB_DI0_DIV_7 119
133#define IMX6SX_CLK_LDB_DI1_DIV_3_5 120
134#define IMX6SX_CLK_LDB_DI1_DIV_7 121
135#define IMX6SX_CLK_CKO1_PODF 122
136#define IMX6SX_CLK_CKO2_PODF 123
137#define IMX6SX_CLK_PERIPH 124
138#define IMX6SX_CLK_PERIPH2 125
139#define IMX6SX_CLK_OCRAM 126
140#define IMX6SX_CLK_AHB 127
141#define IMX6SX_CLK_MMDC_PODF 128
142#define IMX6SX_CLK_ARM 129
143#define IMX6SX_CLK_AIPS_TZ1 130
144#define IMX6SX_CLK_AIPS_TZ2 131
145#define IMX6SX_CLK_APBH_DMA 132
146#define IMX6SX_CLK_ASRC_GATE 133
147#define IMX6SX_CLK_CAAM_MEM 134
148#define IMX6SX_CLK_CAAM_ACLK 135
149#define IMX6SX_CLK_CAAM_IPG 136
150#define IMX6SX_CLK_CAN1_IPG 137
151#define IMX6SX_CLK_CAN1_SERIAL 138
152#define IMX6SX_CLK_CAN2_IPG 139
153#define IMX6SX_CLK_CAN2_SERIAL 140
154#define IMX6SX_CLK_CPU_DEBUG 141
155#define IMX6SX_CLK_DCIC1 142
156#define IMX6SX_CLK_DCIC2 143
157#define IMX6SX_CLK_AIPS_TZ3 144
158#define IMX6SX_CLK_ECSPI1 145
159#define IMX6SX_CLK_ECSPI2 146
160#define IMX6SX_CLK_ECSPI3 147
161#define IMX6SX_CLK_ECSPI4 148
162#define IMX6SX_CLK_ECSPI5 149
163#define IMX6SX_CLK_EPIT1 150
164#define IMX6SX_CLK_EPIT2 151
165#define IMX6SX_CLK_ESAI_EXTAL 152
166#define IMX6SX_CLK_WAKEUP 153
167#define IMX6SX_CLK_GPT_BUS 154
168#define IMX6SX_CLK_GPT_SERIAL 155
169#define IMX6SX_CLK_GPU 156
170#define IMX6SX_CLK_OCRAM_S 157
171#define IMX6SX_CLK_CANFD 158
172#define IMX6SX_CLK_CSI 159
173#define IMX6SX_CLK_I2C1 160
174#define IMX6SX_CLK_I2C2 161
175#define IMX6SX_CLK_I2C3 162
176#define IMX6SX_CLK_OCOTP 163
177#define IMX6SX_CLK_IOMUXC 164
178#define IMX6SX_CLK_IPMUX1 165
179#define IMX6SX_CLK_IPMUX2 166
180#define IMX6SX_CLK_IPMUX3 167
181#define IMX6SX_CLK_TZASC1 168
182#define IMX6SX_CLK_LCDIF_APB 169
183#define IMX6SX_CLK_PXP_AXI 170
184#define IMX6SX_CLK_M4 171
185#define IMX6SX_CLK_ENET 172
186#define IMX6SX_CLK_DISPLAY_AXI 173
187#define IMX6SX_CLK_LCDIF2_PIX 174
188#define IMX6SX_CLK_LCDIF1_PIX 175
189#define IMX6SX_CLK_LDB_DI0 176
190#define IMX6SX_CLK_QSPI1 177
191#define IMX6SX_CLK_MLB 178
192#define IMX6SX_CLK_MMDC_P0_FAST 179
193#define IMX6SX_CLK_MMDC_P0_IPG 180
194#define IMX6SX_CLK_AXI 181
195#define IMX6SX_CLK_PCIE_AXI 182
196#define IMX6SX_CLK_QSPI2 183
197#define IMX6SX_CLK_PER1_BCH 184
198#define IMX6SX_CLK_PER2_MAIN 185
199#define IMX6SX_CLK_PWM1 186
200#define IMX6SX_CLK_PWM2 187
201#define IMX6SX_CLK_PWM3 188
202#define IMX6SX_CLK_PWM4 189
203#define IMX6SX_CLK_GPMI_BCH_APB 190
204#define IMX6SX_CLK_GPMI_BCH 191
205#define IMX6SX_CLK_GPMI_IO 192
206#define IMX6SX_CLK_GPMI_APB 193
207#define IMX6SX_CLK_ROM 194
208#define IMX6SX_CLK_SDMA 195
209#define IMX6SX_CLK_SPBA 196
210#define IMX6SX_CLK_SPDIF 197
211#define IMX6SX_CLK_SSI1_IPG 198
212#define IMX6SX_CLK_SSI2_IPG 199
213#define IMX6SX_CLK_SSI3_IPG 200
214#define IMX6SX_CLK_SSI1 201
215#define IMX6SX_CLK_SSI2 202
216#define IMX6SX_CLK_SSI3 203
217#define IMX6SX_CLK_UART_IPG 204
218#define IMX6SX_CLK_UART_SERIAL 205
219#define IMX6SX_CLK_SAI1 206
220#define IMX6SX_CLK_SAI2 207
221#define IMX6SX_CLK_USBOH3 208
222#define IMX6SX_CLK_USDHC1 209
223#define IMX6SX_CLK_USDHC2 210
224#define IMX6SX_CLK_USDHC3 211
225#define IMX6SX_CLK_USDHC4 212
226#define IMX6SX_CLK_EIM_SLOW 213
227#define IMX6SX_CLK_PWM8 214
228#define IMX6SX_CLK_VADC 215
229#define IMX6SX_CLK_GIS 216
230#define IMX6SX_CLK_I2C4 217
231#define IMX6SX_CLK_PWM5 218
232#define IMX6SX_CLK_PWM6 219
233#define IMX6SX_CLK_PWM7 220
234#define IMX6SX_CLK_CKO1 221
235#define IMX6SX_CLK_CKO2 222
236#define IMX6SX_CLK_IPP_DI0 223
237#define IMX6SX_CLK_IPP_DI1 224
238#define IMX6SX_CLK_ENET_AHB 225
239#define IMX6SX_CLK_OCRAM_PODF 226
240#define IMX6SX_CLK_GPT_3M 227
241#define IMX6SX_CLK_ENET_PTP 228
242#define IMX6SX_CLK_ENET_PTP_REF 229
243#define IMX6SX_CLK_ENET2_REF 230
244#define IMX6SX_CLK_ENET2_REF_125M 231
245#define IMX6SX_CLK_AUDIO 232
246#define IMX6SX_CLK_LVDS1_SEL 233
247#define IMX6SX_CLK_LVDS1_OUT 234
248#define IMX6SX_CLK_ASRC_IPG 235
249#define IMX6SX_CLK_ASRC_MEM 236
250#define IMX6SX_CLK_SAI1_IPG 237
251#define IMX6SX_CLK_SAI2_IPG 238
252#define IMX6SX_CLK_ESAI_IPG 239
253#define IMX6SX_CLK_ESAI_MEM 240
254#define IMX6SX_CLK_CLK_END 241
255
256#endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-29 21:35:06 -0400