diff options
author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-05-23 05:30:55 -0400 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-05-24 11:54:14 -0400 |
commit | 0af78a2bb4296839cfe7a855cd128e8687e77bc1 (patch) | |
tree | 0f77a0d0a2fc06d6afb10e6bf01ba8690ddfaefe | |
parent | 9589919fb3d269d4202a112b197468c7db1f97a3 (diff) |
drm/i915: reject doubleclocked cea modes on dp
These are ultra-low-res modes used to upscale SDTV content and we
don't know how to support these on dp on intel hw:
- It's unclear whether we can send avi infoframes over dp ports.
- And the pixel repeat setting that work for hdmi/sdvo explicitly
don't work for dp.
So don't bother and just reject these modes. These modes have been
introduced in
commit 54ac76f851a1789b047b74a8e14980f2dd1ac749
Author: Christian Schmidt <schmidt@digadd.de>
Date: Mon Dec 19 14:53:16 2011 +0000
drm/edid: support CEA video modes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45729
Tested-by: Yuang Guang <guang.a.yang@intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 3bbd7540bcd8..eb57ec7b36f4 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c | |||
@@ -266,6 +266,9 @@ intel_dp_mode_valid(struct drm_connector *connector, | |||
266 | if (mode->clock < 10000) | 266 | if (mode->clock < 10000) |
267 | return MODE_CLOCK_LOW; | 267 | return MODE_CLOCK_LOW; |
268 | 268 | ||
269 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | ||
270 | return MODE_H_ILLEGAL; | ||
271 | |||
269 | return MODE_OK; | 272 | return MODE_OK; |
270 | } | 273 | } |
271 | 274 | ||
@@ -702,6 +705,9 @@ intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, | |||
702 | mode->clock = intel_dp->panel_fixed_mode->clock; | 705 | mode->clock = intel_dp->panel_fixed_mode->clock; |
703 | } | 706 | } |
704 | 707 | ||
708 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) | ||
709 | return false; | ||
710 | |||
705 | DRM_DEBUG_KMS("DP link computation with max lane count %i " | 711 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
706 | "max bw %02x pixel clock %iKHz\n", | 712 | "max bw %02x pixel clock %iKHz\n", |
707 | max_lane_count, bws[max_clock], mode->clock); | 713 | max_lane_count, bws[max_clock], mode->clock); |