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authorDave Airlie <airlied@redhat.com>2013-04-23 20:09:23 -0400
committerDave Airlie <airlied@redhat.com>2013-04-23 20:09:23 -0400
commit0a397154e2240c928ebc2167d18c0b8ab7a7ac56 (patch)
tree6c369544dc2ce75a2b323bd66284f598f65b21a2
parentf9df7ea33c87291365d943828bec852874f15c2f (diff)
parent03708b05297b7f4782c2de51560ceb8d9f8bad68 (diff)
Merge branch 'drm-next-3.10-2' of git://people.freedesktop.org/~agd5f/linux into drm-next
Alex writes: A few more updates for 3.10. Nothing too major here. Mostly bug fixes. The big changes are adding golden register init for 7xx and newer asics and some audio cleanups. * 'drm-next-3.10-2' of git://people.freedesktop.org/~agd5f/linux: (32 commits) drm/radeon: disable UVD advanced semaphore mode drm/radeon: fix endian bugs in radeon_atom_get_clock_dividers() (v3) drm/radeon: fix up audio dto programming for DCE2 drm/radeon/evergreen: set SAD registers drm: add drm_edid_to_eld helper extracting SADs from EDID (v2) drm/radeon/si: add support for golden register init drm/radeon/cayman,TN: add support for golden register init (v2) drm/radeon/evergreen: add support for golden register init drm/radeon/7xx: add support for golden register init drm/radeon: add helper function to support golden registers drm/radeon: fix typo in si_select_se_sh() drm/radeon: switch audio handling to use callbacks drm/radeon: clean up audio dto programming drm/radeon: clean up audio supported check drm/radeon: raise UVD clocks on init v3 drm/radeon: raise UVD clocks only on demand drm/radeon: put UVD PLLs in bypass mode drm/radeon: disable audio format interrupts on Evergreen drm/radeon: fix hdmi mode enable on RS600/RS690/RS740 drm/radeon/evergreen: write default channel numbers ...
Diffstat
-rw-r--r--drivers/gpu/drm/drm_edid.c59
-rw-r--r--drivers/gpu/drm/radeon/atombios.h2
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c17
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c986
-rw-r--r--drivers/gpu/drm/radeon/evergreen_hdmi.c169
-rw-r--r--drivers/gpu/drm/radeon/evergreen_reg.h2
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h1
-rw-r--r--drivers/gpu/drm/radeon/ni.c281
-rw-r--r--drivers/gpu/drm/radeon/r100.c77
-rw-r--r--drivers/gpu/drm/radeon/r500_reg.h2
-rw-r--r--drivers/gpu/drm/radeon/r600.c34
-rw-r--r--drivers/gpu/drm/radeon/r600_audio.c64
-rw-r--r--drivers/gpu/drm/radeon/r600_hdmi.c150
-rw-r--r--drivers/gpu/drm/radeon/r600d.h7
-rw-r--r--drivers/gpu/drm/radeon/radeon.h17
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c18
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h5
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c6
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c36
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c7
-rw-r--r--drivers/gpu/drm/radeon/radeon_uvd.c58
-rw-r--r--drivers/gpu/drm/radeon/rs600.c52
-rw-r--r--drivers/gpu/drm/radeon/rv515.c54
-rw-r--r--drivers/gpu/drm/radeon/rv770.c672
-rw-r--r--drivers/gpu/drm/radeon/si.c817
-rw-r--r--include/drm/drm_edid.h9
27 files changed, 3332 insertions, 274 deletions
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index e2acfdbf7d3c..b6807e881a60 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -2511,6 +2511,65 @@ void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
2511EXPORT_SYMBOL(drm_edid_to_eld); 2511EXPORT_SYMBOL(drm_edid_to_eld);
2512 2512
2513/** 2513/**
2514 * drm_edid_to_sad - extracts SADs from EDID
2515 * @edid: EDID to parse
2516 * @sads: pointer that will be set to the extracted SADs
2517 *
2518 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it.
2519 * Note: returned pointer needs to be kfreed
2520 *
2521 * Return number of found SADs or negative number on error.
2522 */
2523int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads)
2524{
2525 int count = 0;
2526 int i, start, end, dbl;
2527 u8 *cea;
2528
2529 cea = drm_find_cea_extension(edid);
2530 if (!cea) {
2531 DRM_DEBUG_KMS("SAD: no CEA Extension found\n");
2532 return -ENOENT;
2533 }
2534
2535 if (cea_revision(cea) < 3) {
2536 DRM_DEBUG_KMS("SAD: wrong CEA revision\n");
2537 return -ENOTSUPP;
2538 }
2539
2540 if (cea_db_offsets(cea, &start, &end)) {
2541 DRM_DEBUG_KMS("SAD: invalid data block offsets\n");
2542 return -EPROTO;
2543 }
2544
2545 for_each_cea_db(cea, i, start, end) {
2546 u8 *db = &cea[i];
2547
2548 if (cea_db_tag(db) == AUDIO_BLOCK) {
2549 int j;
2550 dbl = cea_db_payload_len(db);
2551
2552 count = dbl / 3; /* SAD is 3B */
2553 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL);
2554 if (!*sads)
2555 return -ENOMEM;
2556 for (j = 0; j < count; j++) {
2557 u8 *sad = &db[1 + j * 3];
2558
2559 (*sads)[j].format = (sad[0] & 0x78) >> 3;
2560 (*sads)[j].channels = sad[0] & 0x7;
2561 (*sads)[j].freq = sad[1] & 0x7F;
2562 (*sads)[j].byte2 = sad[2];
2563 }
2564 break;
2565 }
2566 }
2567
2568 return count;
2569}
2570EXPORT_SYMBOL(drm_edid_to_sad);
2571
2572/**
2514 * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond 2573 * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond
2515 * @connector: connector associated with the HDMI/DP sink 2574 * @connector: connector associated with the HDMI/DP sink
2516 * @mode: the display mode 2575 * @mode: the display mode
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 4b04ba3828e8..0ee573743de9 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -458,6 +458,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
458 union 458 union
459 { 459 {
460 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 460 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
461 ULONG ulClockParams; //ULONG access for BE
461 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 462 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
462 }; 463 };
463 UCHAR ucRefDiv; //Output Parameter 464 UCHAR ucRefDiv; //Output Parameter
@@ -490,6 +491,7 @@ typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
490 union 491 union
491 { 492 {
492 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 493 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
494 ULONG ulClockParams; //ULONG access for BE
493 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 495 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
494 }; 496 };
495 UCHAR ucRefDiv; //Output Parameter 497 UCHAR ucRefDiv; //Output Parameter
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 4552d4aff317..44a7da66e081 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -2150,13 +2150,10 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2150 atombios_apply_encoder_quirks(encoder, adjusted_mode); 2150 atombios_apply_encoder_quirks(encoder, adjusted_mode);
2151 2151
2152 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) { 2152 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2153 r600_hdmi_enable(encoder); 2153 if (rdev->asic->display.hdmi_enable)
2154 if (ASIC_IS_DCE6(rdev)) 2154 radeon_hdmi_enable(rdev, encoder, true);
2155 ; /* TODO (use pointers instead of if-s?) */ 2155 if (rdev->asic->display.hdmi_setmode)
2156 else if (ASIC_IS_DCE4(rdev)) 2156 radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2157 evergreen_hdmi_setmode(encoder, adjusted_mode);
2158 else
2159 r600_hdmi_setmode(encoder, adjusted_mode);
2160 } 2157 }
2161} 2158}
2162 2159
@@ -2413,8 +2410,10 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2413 2410
2414disable_done: 2411disable_done:
2415 if (radeon_encoder_is_digital(encoder)) { 2412 if (radeon_encoder_is_digital(encoder)) {
2416 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) 2413 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2417 r600_hdmi_disable(encoder); 2414 if (rdev->asic->display.hdmi_enable)
2415 radeon_hdmi_enable(rdev, encoder, false);
2416 }
2418 dig = radeon_encoder->enc_priv; 2417 dig = radeon_encoder->enc_priv;
2419 dig->dig_encoder = -1; 2418 dig->dig_encoder = -1;
2420 } 2419 }
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 124c19365392..1531f167d152 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -53,6 +53,864 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
53extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev, 53extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
54 int ring, u32 cp_int_cntl); 54 int ring, u32 cp_int_cntl);
55 55
56static const u32 evergreen_golden_registers[] =
57{
58 0x3f90, 0xffff0000, 0xff000000,
59 0x9148, 0xffff0000, 0xff000000,
60 0x3f94, 0xffff0000, 0xff000000,
61 0x914c, 0xffff0000, 0xff000000,
62 0x9b7c, 0xffffffff, 0x00000000,
63 0x8a14, 0xffffffff, 0x00000007,
64 0x8b10, 0xffffffff, 0x00000000,
65 0x960c, 0xffffffff, 0x54763210,
66 0x88c4, 0xffffffff, 0x000000c2,
67 0x88d4, 0xffffffff, 0x00000010,
68 0x8974, 0xffffffff, 0x00000000,
69 0xc78, 0x00000080, 0x00000080,
70 0x5eb4, 0xffffffff, 0x00000002,
71 0x5e78, 0xffffffff, 0x001000f0,
72 0x6104, 0x01000300, 0x00000000,
73 0x5bc0, 0x00300000, 0x00000000,
74 0x7030, 0xffffffff, 0x00000011,
75 0x7c30, 0xffffffff, 0x00000011,
76 0x10830, 0xffffffff, 0x00000011,
77 0x11430, 0xffffffff, 0x00000011,
78 0x12030, 0xffffffff, 0x00000011,
79 0x12c30, 0xffffffff, 0x00000011,
80 0xd02c, 0xffffffff, 0x08421000,
81 0x240c, 0xffffffff, 0x00000380,
82 0x8b24, 0xffffffff, 0x00ff0fff,
83 0x28a4c, 0x06000000, 0x06000000,
84 0x10c, 0x00000001, 0x00000001,
85 0x8d00, 0xffffffff, 0x100e4848,
86 0x8d04, 0xffffffff, 0x00164745,
87 0x8c00, 0xffffffff, 0xe4000003,
88 0x8c04, 0xffffffff, 0x40600060,
89 0x8c08, 0xffffffff, 0x001c001c,
90 0x8cf0, 0xffffffff, 0x08e00620,
91 0x8c20, 0xffffffff, 0x00800080,
92 0x8c24, 0xffffffff, 0x00800080,
93 0x8c18, 0xffffffff, 0x20202078,
94 0x8c1c, 0xffffffff, 0x00001010,
95 0x28350, 0xffffffff, 0x00000000,
96 0xa008, 0xffffffff, 0x00010000,
97 0x5cc, 0xffffffff, 0x00000001,
98 0x9508, 0xffffffff, 0x00000002,
99 0x913c, 0x0000000f, 0x0000000a
100};
101
102static const u32 evergreen_golden_registers2[] =
103{
104 0x2f4c, 0xffffffff, 0x00000000,
105 0x54f4, 0xffffffff, 0x00000000,
106 0x54f0, 0xffffffff, 0x00000000,
107 0x5498, 0xffffffff, 0x00000000,
108 0x549c, 0xffffffff, 0x00000000,
109 0x5494, 0xffffffff, 0x00000000,
110 0x53cc, 0xffffffff, 0x00000000,
111 0x53c8, 0xffffffff, 0x00000000,
112 0x53c4, 0xffffffff, 0x00000000,
113 0x53c0, 0xffffffff, 0x00000000,
114 0x53bc, 0xffffffff, 0x00000000,
115 0x53b8, 0xffffffff, 0x00000000,
116 0x53b4, 0xffffffff, 0x00000000,
117 0x53b0, 0xffffffff, 0x00000000
118};
119
120static const u32 cypress_mgcg_init[] =
121{
122 0x802c, 0xffffffff, 0xc0000000,
123 0x5448, 0xffffffff, 0x00000100,
124 0x55e4, 0xffffffff, 0x00000100,
125 0x160c, 0xffffffff, 0x00000100,
126 0x5644, 0xffffffff, 0x00000100,
127 0xc164, 0xffffffff, 0x00000100,
128 0x8a18, 0xffffffff, 0x00000100,
129 0x897c, 0xffffffff, 0x06000100,
130 0x8b28, 0xffffffff, 0x00000100,
131 0x9144, 0xffffffff, 0x00000100,
132 0x9a60, 0xffffffff, 0x00000100,
133 0x9868, 0xffffffff, 0x00000100,
134 0x8d58, 0xffffffff, 0x00000100,
135 0x9510, 0xffffffff, 0x00000100,
136 0x949c, 0xffffffff, 0x00000100,
137 0x9654, 0xffffffff, 0x00000100,
138 0x9030, 0xffffffff, 0x00000100,
139 0x9034, 0xffffffff, 0x00000100,
140 0x9038, 0xffffffff, 0x00000100,
141 0x903c, 0xffffffff, 0x00000100,
142 0x9040, 0xffffffff, 0x00000100,
143 0xa200, 0xffffffff, 0x00000100,
144 0xa204, 0xffffffff, 0x00000100,
145 0xa208, 0xffffffff, 0x00000100,
146 0xa20c, 0xffffffff, 0x00000100,
147 0x971c, 0xffffffff, 0x00000100,
148 0x977c, 0xffffffff, 0x00000100,
149 0x3f80, 0xffffffff, 0x00000100,
150 0xa210, 0xffffffff, 0x00000100,
151 0xa214, 0xffffffff, 0x00000100,
152 0x4d8, 0xffffffff, 0x00000100,
153 0x9784, 0xffffffff, 0x00000100,
154 0x9698, 0xffffffff, 0x00000100,
155 0x4d4, 0xffffffff, 0x00000200,
156 0x30cc, 0xffffffff, 0x00000100,
157 0xd0c0, 0xffffffff, 0xff000100,
158 0x802c, 0xffffffff, 0x40000000,
159 0x915c, 0xffffffff, 0x00010000,
160 0x9160, 0xffffffff, 0x00030002,
161 0x9178, 0xffffffff, 0x00070000,
162 0x917c, 0xffffffff, 0x00030002,
163 0x9180, 0xffffffff, 0x00050004,
164 0x918c, 0xffffffff, 0x00010006,
165 0x9190, 0xffffffff, 0x00090008,
166 0x9194, 0xffffffff, 0x00070000,
167 0x9198, 0xffffffff, 0x00030002,
168 0x919c, 0xffffffff, 0x00050004,
169 0x91a8, 0xffffffff, 0x00010006,
170 0x91ac, 0xffffffff, 0x00090008,
171 0x91b0, 0xffffffff, 0x00070000,
172 0x91b4, 0xffffffff, 0x00030002,
173 0x91b8, 0xffffffff, 0x00050004,
174 0x91c4, 0xffffffff, 0x00010006,
175 0x91c8, 0xffffffff, 0x00090008,
176 0x91cc, 0xffffffff, 0x00070000,
177 0x91d0, 0xffffffff, 0x00030002,
178 0x91d4, 0xffffffff, 0x00050004,
179 0x91e0, 0xffffffff, 0x00010006,
180 0x91e4, 0xffffffff, 0x00090008,
181 0x91e8, 0xffffffff, 0x00000000,
182 0x91ec, 0xffffffff, 0x00070000,
183 0x91f0, 0xffffffff, 0x00030002,
184 0x91f4, 0xffffffff, 0x00050004,
185 0x9200, 0xffffffff, 0x00010006,
186 0x9204, 0xffffffff, 0x00090008,
187 0x9208, 0xffffffff, 0x00070000,
188 0x920c, 0xffffffff, 0x00030002,
189 0x9210, 0xffffffff, 0x00050004,
190 0x921c, 0xffffffff, 0x00010006,
191 0x9220, 0xffffffff, 0x00090008,
192 0x9224, 0xffffffff, 0x00070000,
193 0x9228, 0xffffffff, 0x00030002,
194 0x922c, 0xffffffff, 0x00050004,
195 0x9238, 0xffffffff, 0x00010006,
196 0x923c, 0xffffffff, 0x00090008,
197 0x9240, 0xffffffff, 0x00070000,
198 0x9244, 0xffffffff, 0x00030002,
199 0x9248, 0xffffffff, 0x00050004,
200 0x9254, 0xffffffff, 0x00010006,
201 0x9258, 0xffffffff, 0x00090008,
202 0x925c, 0xffffffff, 0x00070000,
203 0x9260, 0xffffffff, 0x00030002,
204 0x9264, 0xffffffff, 0x00050004,
205 0x9270, 0xffffffff, 0x00010006,
206 0x9274, 0xffffffff, 0x00090008,
207 0x9278, 0xffffffff, 0x00070000,
208 0x927c, 0xffffffff, 0x00030002,
209 0x9280, 0xffffffff, 0x00050004,
210 0x928c, 0xffffffff, 0x00010006,
211 0x9290, 0xffffffff, 0x00090008,
212 0x9294, 0xffffffff, 0x00000000,
213 0x929c, 0xffffffff, 0x00000001,
214 0x802c, 0xffffffff, 0x40010000,
215 0x915c, 0xffffffff, 0x00010000,
216 0x9160, 0xffffffff, 0x00030002,
217 0x9178, 0xffffffff, 0x00070000,
218 0x917c, 0xffffffff, 0x00030002,
219 0x9180, 0xffffffff, 0x00050004,
220 0x918c, 0xffffffff, 0x00010006,
221 0x9190, 0xffffffff, 0x00090008,
222 0x9194, 0xffffffff, 0x00070000,
223 0x9198, 0xffffffff, 0x00030002,
224 0x919c, 0xffffffff, 0x00050004,
225 0x91a8, 0xffffffff, 0x00010006,
226 0x91ac, 0xffffffff, 0x00090008,
227 0x91b0, 0xffffffff, 0x00070000,
228 0x91b4, 0xffffffff, 0x00030002,
229 0x91b8, 0xffffffff, 0x00050004,
230 0x91c4, 0xffffffff, 0x00010006,
231 0x91c8, 0xffffffff, 0x00090008,
232 0x91cc, 0xffffffff, 0x00070000,
233 0x91d0, 0xffffffff, 0x00030002,
234 0x91d4, 0xffffffff, 0x00050004,
235 0x91e0, 0xffffffff, 0x00010006,
236 0x91e4, 0xffffffff, 0x00090008,
237 0x91e8, 0xffffffff, 0x00000000,
238 0x91ec, 0xffffffff, 0x00070000,
239 0x91f0, 0xffffffff, 0x00030002,
240 0x91f4, 0xffffffff, 0x00050004,
241 0x9200, 0xffffffff, 0x00010006,
242 0x9204, 0xffffffff, 0x00090008,
243 0x9208, 0xffffffff, 0x00070000,
244 0x920c, 0xffffffff, 0x00030002,
245 0x9210, 0xffffffff, 0x00050004,
246 0x921c, 0xffffffff, 0x00010006,
247 0x9220, 0xffffffff, 0x00090008,
248 0x9224, 0xffffffff, 0x00070000,
249 0x9228, 0xffffffff, 0x00030002,
250 0x922c, 0xffffffff, 0x00050004,
251 0x9238, 0xffffffff, 0x00010006,
252 0x923c, 0xffffffff, 0x00090008,
253 0x9240, 0xffffffff, 0x00070000,
254 0x9244, 0xffffffff, 0x00030002,
255 0x9248, 0xffffffff, 0x00050004,
256 0x9254, 0xffffffff, 0x00010006,
257 0x9258, 0xffffffff, 0x00090008,
258 0x925c, 0xffffffff, 0x00070000,
259 0x9260, 0xffffffff, 0x00030002,
260 0x9264, 0xffffffff, 0x00050004,
261 0x9270, 0xffffffff, 0x00010006,
262 0x9274, 0xffffffff, 0x00090008,
263 0x9278, 0xffffffff, 0x00070000,
264 0x927c, 0xffffffff, 0x00030002,
265 0x9280, 0xffffffff, 0x00050004,
266 0x928c, 0xffffffff, 0x00010006,
267 0x9290, 0xffffffff, 0x00090008,
268 0x9294, 0xffffffff, 0x00000000,
269 0x929c, 0xffffffff, 0x00000001,
270 0x802c, 0xffffffff, 0xc0000000
271};
272
273static const u32 redwood_mgcg_init[] =
274{
275 0x802c, 0xffffffff, 0xc0000000,
276 0x5448, 0xffffffff, 0x00000100,
277 0x55e4, 0xffffffff, 0x00000100,
278 0x160c, 0xffffffff, 0x00000100,
279 0x5644, 0xffffffff, 0x00000100,
280 0xc164, 0xffffffff, 0x00000100,
281 0x8a18, 0xffffffff, 0x00000100,
282 0x897c, 0xffffffff, 0x06000100,
283 0x8b28, 0xffffffff, 0x00000100,
284 0x9144, 0xffffffff, 0x00000100,
285 0x9a60, 0xffffffff, 0x00000100,
286 0x9868, 0xffffffff, 0x00000100,
287 0x8d58, 0xffffffff, 0x00000100,
288 0x9510, 0xffffffff, 0x00000100,
289 0x949c, 0xffffffff, 0x00000100,
290 0x9654, 0xffffffff, 0x00000100,
291 0x9030, 0xffffffff, 0x00000100,
292 0x9034, 0xffffffff, 0x00000100,
293 0x9038, 0xffffffff, 0x00000100,
294 0x903c, 0xffffffff, 0x00000100,
295 0x9040, 0xffffffff, 0x00000100,
296 0xa200, 0xffffffff, 0x00000100,
297 0xa204, 0xffffffff, 0x00000100,
298 0xa208, 0xffffffff, 0x00000100,
299 0xa20c, 0xffffffff, 0x00000100,
300 0x971c, 0xffffffff, 0x00000100,
301 0x977c, 0xffffffff, 0x00000100,
302 0x3f80, 0xffffffff, 0x00000100,
303 0xa210, 0xffffffff, 0x00000100,
304 0xa214, 0xffffffff, 0x00000100,
305 0x4d8, 0xffffffff, 0x00000100,
306 0x9784, 0xffffffff, 0x00000100,
307 0x9698, 0xffffffff, 0x00000100,
308 0x4d4, 0xffffffff, 0x00000200,
309 0x30cc, 0xffffffff, 0x00000100,
310 0xd0c0, 0xffffffff, 0xff000100,
311 0x802c, 0xffffffff, 0x40000000,
312 0x915c, 0xffffffff, 0x00010000,
313 0x9160, 0xffffffff, 0x00030002,
314 0x9178, 0xffffffff, 0x00070000,
315 0x917c, 0xffffffff, 0x00030002,
316 0x9180, 0xffffffff, 0x00050004,
317 0x918c, 0xffffffff, 0x00010006,
318 0x9190, 0xffffffff, 0x00090008,
319 0x9194, 0xffffffff, 0x00070000,
320 0x9198, 0xffffffff, 0x00030002,
321 0x919c, 0xffffffff, 0x00050004,
322 0x91a8, 0xffffffff, 0x00010006,
323 0x91ac, 0xffffffff, 0x00090008,
324 0x91b0, 0xffffffff, 0x00070000,
325 0x91b4, 0xffffffff, 0x00030002,
326 0x91b8, 0xffffffff, 0x00050004,
327 0x91c4, 0xffffffff, 0x00010006,
328 0x91c8, 0xffffffff, 0x00090008,
329 0x91cc, 0xffffffff, 0x00070000,
330 0x91d0, 0xffffffff, 0x00030002,
331 0x91d4, 0xffffffff, 0x00050004,
332 0x91e0, 0xffffffff, 0x00010006,
333 0x91e4, 0xffffffff, 0x00090008,
334 0x91e8, 0xffffffff, 0x00000000,
335 0x91ec, 0xffffffff, 0x00070000,
336 0x91f0, 0xffffffff, 0x00030002,
337 0x91f4, 0xffffffff, 0x00050004,
338 0x9200, 0xffffffff, 0x00010006,
339 0x9204, 0xffffffff, 0x00090008,
340 0x9294, 0xffffffff, 0x00000000,
341 0x929c, 0xffffffff, 0x00000001,
342 0x802c, 0xffffffff, 0xc0000000
343};
344
345static const u32 cedar_golden_registers[] =
346{
347 0x3f90, 0xffff0000, 0xff000000,
348 0x9148, 0xffff0000, 0xff000000,
349 0x3f94, 0xffff0000, 0xff000000,
350 0x914c, 0xffff0000, 0xff000000,
351 0x9b7c, 0xffffffff, 0x00000000,
352 0x8a14, 0xffffffff, 0x00000007,
353 0x8b10, 0xffffffff, 0x00000000,
354 0x960c, 0xffffffff, 0x54763210,
355 0x88c4, 0xffffffff, 0x000000c2,
356 0x88d4, 0xffffffff, 0x00000000,
357 0x8974, 0xffffffff, 0x00000000,
358 0xc78, 0x00000080, 0x00000080,
359 0x5eb4, 0xffffffff, 0x00000002,
360 0x5e78, 0xffffffff, 0x001000f0,
361 0x6104, 0x01000300, 0x00000000,
362 0x5bc0, 0x00300000, 0x00000000,
363 0x7030, 0xffffffff, 0x00000011,
364 0x7c30, 0xffffffff, 0x00000011,
365 0x10830, 0xffffffff, 0x00000011,
366 0x11430, 0xffffffff, 0x00000011,
367 0xd02c, 0xffffffff, 0x08421000,
368 0x240c, 0xffffffff, 0x00000380,
369 0x8b24, 0xffffffff, 0x00ff0fff,
370 0x28a4c, 0x06000000, 0x06000000,
371 0x10c, 0x00000001, 0x00000001,
372 0x8d00, 0xffffffff, 0x100e4848,
373 0x8d04, 0xffffffff, 0x00164745,
374 0x8c00, 0xffffffff, 0xe4000003,
375 0x8c04, 0xffffffff, 0x40600060,
376 0x8c08, 0xffffffff, 0x001c001c,
377 0x8cf0, 0xffffffff, 0x08e00410,
378 0x8c20, 0xffffffff, 0x00800080,
379 0x8c24, 0xffffffff, 0x00800080,
380 0x8c18, 0xffffffff, 0x20202078,
381 0x8c1c, 0xffffffff, 0x00001010,
382 0x28350, 0xffffffff, 0x00000000,
383 0xa008, 0xffffffff, 0x00010000,
384 0x5cc, 0xffffffff, 0x00000001,
385 0x9508, 0xffffffff, 0x00000002
386};
387
388static const u32 cedar_mgcg_init[] =
389{
390 0x802c, 0xffffffff, 0xc0000000,
391 0x5448, 0xffffffff, 0x00000100,
392 0x55e4, 0xffffffff, 0x00000100,
393 0x160c, 0xffffffff, 0x00000100,
394 0x5644, 0xffffffff, 0x00000100,
395 0xc164, 0xffffffff, 0x00000100,
396 0x8a18, 0xffffffff, 0x00000100,
397 0x897c, 0xffffffff, 0x06000100,
398 0x8b28, 0xffffffff, 0x00000100,
399 0x9144, 0xffffffff, 0x00000100,
400 0x9a60, 0xffffffff, 0x00000100,
401 0x9868, 0xffffffff, 0x00000100,
402 0x8d58, 0xffffffff, 0x00000100,
403 0x9510, 0xffffffff, 0x00000100,
404 0x949c, 0xffffffff, 0x00000100,
405 0x9654, 0xffffffff, 0x00000100,
406 0x9030, 0xffffffff, 0x00000100,
407 0x9034, 0xffffffff, 0x00000100,
408 0x9038, 0xffffffff, 0x00000100,
409 0x903c, 0xffffffff, 0x00000100,
410 0x9040, 0xffffffff, 0x00000100,
411 0xa200, 0xffffffff, 0x00000100,
412 0xa204, 0xffffffff, 0x00000100,
413 0xa208, 0xffffffff, 0x00000100,
414 0xa20c, 0xffffffff, 0x00000100,
415 0x971c, 0xffffffff, 0x00000100,
416 0x977c, 0xffffffff, 0x00000100,
417 0x3f80, 0xffffffff, 0x00000100,
418 0xa210, 0xffffffff, 0x00000100,
419 0xa214, 0xffffffff, 0x00000100,
420 0x4d8, 0xffffffff, 0x00000100,
421 0x9784, 0xffffffff, 0x00000100,
422 0x9698, 0xffffffff, 0x00000100,
423 0x4d4, 0xffffffff, 0x00000200,
424 0x30cc, 0xffffffff, 0x00000100,
425 0xd0c0, 0xffffffff, 0xff000100,
426 0x802c, 0xffffffff, 0x40000000,
427 0x915c, 0xffffffff, 0x00010000,
428 0x9178, 0xffffffff, 0x00050000,
429 0x917c, 0xffffffff, 0x00030002,
430 0x918c, 0xffffffff, 0x00010004,
431 0x9190, 0xffffffff, 0x00070006,
432 0x9194, 0xffffffff, 0x00050000,
433 0x9198, 0xffffffff, 0x00030002,
434 0x91a8, 0xffffffff, 0x00010004,
435 0x91ac, 0xffffffff, 0x00070006,
436 0x91e8, 0xffffffff, 0x00000000,
437 0x9294, 0xffffffff, 0x00000000,
438 0x929c, 0xffffffff, 0x00000001,
439 0x802c, 0xffffffff, 0xc0000000
440};
441
442static const u32 juniper_mgcg_init[] =
443{
444 0x802c, 0xffffffff, 0xc0000000,
445 0x5448, 0xffffffff, 0x00000100,
446 0x55e4, 0xffffffff, 0x00000100,
447 0x160c, 0xffffffff, 0x00000100,
448 0x5644, 0xffffffff, 0x00000100,
449 0xc164, 0xffffffff, 0x00000100,
450 0x8a18, 0xffffffff, 0x00000100,
451 0x897c, 0xffffffff, 0x06000100,
452 0x8b28, 0xffffffff, 0x00000100,
453 0x9144, 0xffffffff, 0x00000100,
454 0x9a60, 0xffffffff, 0x00000100,
455 0x9868, 0xffffffff, 0x00000100,
456 0x8d58, 0xffffffff, 0x00000100,
457 0x9510, 0xffffffff, 0x00000100,
458 0x949c, 0xffffffff, 0x00000100,
459 0x9654, 0xffffffff, 0x00000100,
460 0x9030, 0xffffffff, 0x00000100,
461 0x9034, 0xffffffff, 0x00000100,
462 0x9038, 0xffffffff, 0x00000100,
463 0x903c, 0xffffffff, 0x00000100,
464 0x9040, 0xffffffff, 0x00000100,
465 0xa200, 0xffffffff, 0x00000100,
466 0xa204, 0xffffffff, 0x00000100,
467 0xa208, 0xffffffff, 0x00000100,
468 0xa20c, 0xffffffff, 0x00000100,
469 0x971c, 0xffffffff, 0x00000100,
470 0xd0c0, 0xffffffff, 0xff000100,
471 0x802c, 0xffffffff, 0x40000000,
472 0x915c, 0xffffffff, 0x00010000,
473 0x9160, 0xffffffff, 0x00030002,
474 0x9178, 0xffffffff, 0x00070000,
475 0x917c, 0xffffffff, 0x00030002,
476 0x9180, 0xffffffff, 0x00050004,
477 0x918c, 0xffffffff, 0x00010006,
478 0x9190, 0xffffffff, 0x00090008,
479 0x9194, 0xffffffff, 0x00070000,
480 0x9198, 0xffffffff, 0x00030002,
481 0x919c, 0xffffffff, 0x00050004,
482 0x91a8, 0xffffffff, 0x00010006,
483 0x91ac, 0xffffffff, 0x00090008,
484 0x91b0, 0xffffffff, 0x00070000,
485 0x91b4, 0xffffffff, 0x00030002,
486 0x91b8, 0xffffffff, 0x00050004,
487 0x91c4, 0xffffffff, 0x00010006,
488 0x91c8, 0xffffffff, 0x00090008,
489 0x91cc, 0xffffffff, 0x00070000,
490 0x91d0, 0xffffffff, 0x00030002,
491 0x91d4, 0xffffffff, 0x00050004,
492 0x91e0, 0xffffffff, 0x00010006,
493 0x91e4, 0xffffffff, 0x00090008,
494 0x91e8, 0xffffffff, 0x00000000,
495 0x91ec, 0xffffffff, 0x00070000,
496 0x91f0, 0xffffffff, 0x00030002,
497 0x91f4, 0xffffffff, 0x00050004,
498 0x9200, 0xffffffff, 0x00010006,
499 0x9204, 0xffffffff, 0x00090008,
500 0x9208, 0xffffffff, 0x00070000,
501 0x920c, 0xffffffff, 0x00030002,
502 0x9210, 0xffffffff, 0x00050004,
503 0x921c, 0xffffffff, 0x00010006,
504 0x9220, 0xffffffff, 0x00090008,
505 0x9224, 0xffffffff, 0x00070000,
506 0x9228, 0xffffffff, 0x00030002,
507 0x922c, 0xffffffff, 0x00050004,
508 0x9238, 0xffffffff, 0x00010006,
509 0x923c, 0xffffffff, 0x00090008,
510 0x9240, 0xffffffff, 0x00070000,
511 0x9244, 0xffffffff, 0x00030002,
512 0x9248, 0xffffffff, 0x00050004,
513 0x9254, 0xffffffff, 0x00010006,
514 0x9258, 0xffffffff, 0x00090008,
515 0x925c, 0xffffffff, 0x00070000,
516 0x9260, 0xffffffff, 0x00030002,
517 0x9264, 0xffffffff, 0x00050004,
518 0x9270, 0xffffffff, 0x00010006,
519 0x9274, 0xffffffff, 0x00090008,
520 0x9278, 0xffffffff, 0x00070000,
521 0x927c, 0xffffffff, 0x00030002,
522 0x9280, 0xffffffff, 0x00050004,
523 0x928c, 0xffffffff, 0x00010006,
524 0x9290, 0xffffffff, 0x00090008,
525 0x9294, 0xffffffff, 0x00000000,
526 0x929c, 0xffffffff, 0x00000001,
527 0x802c, 0xffffffff, 0xc0000000,
528 0x977c, 0xffffffff, 0x00000100,
529 0x3f80, 0xffffffff, 0x00000100,
530 0xa210, 0xffffffff, 0x00000100,
531 0xa214, 0xffffffff, 0x00000100,
532 0x4d8, 0xffffffff, 0x00000100,
533 0x9784, 0xffffffff, 0x00000100,
534 0x9698, 0xffffffff, 0x00000100,
535 0x4d4, 0xffffffff, 0x00000200,
536 0x30cc, 0xffffffff, 0x00000100,
537 0x802c, 0xffffffff, 0xc0000000
538};
539
540static const u32 supersumo_golden_registers[] =
541{
542 0x5eb4, 0xffffffff, 0x00000002,
543 0x5cc, 0xffffffff, 0x00000001,
544 0x7030, 0xffffffff, 0x00000011,
545 0x7c30, 0xffffffff, 0x00000011,
546 0x6104, 0x01000300, 0x00000000,
547 0x5bc0, 0x00300000, 0x00000000,
548 0x8c04, 0xffffffff, 0x40600060,
549 0x8c08, 0xffffffff, 0x001c001c,
550 0x8c20, 0xffffffff, 0x00800080,
551 0x8c24, 0xffffffff, 0x00800080,
552 0x8c18, 0xffffffff, 0x20202078,
553 0x8c1c, 0xffffffff, 0x00001010,
554 0x918c, 0xffffffff, 0x00010006,
555 0x91a8, 0xffffffff, 0x00010006,
556 0x91c4, 0xffffffff, 0x00010006,
557 0x91e0, 0xffffffff, 0x00010006,
558 0x9200, 0xffffffff, 0x00010006,
559 0x9150, 0xffffffff, 0x6e944040,
560 0x917c, 0xffffffff, 0x00030002,
561 0x9180, 0xffffffff, 0x00050004,
562 0x9198, 0xffffffff, 0x00030002,
563 0x919c, 0xffffffff, 0x00050004,
564 0x91b4, 0xffffffff, 0x00030002,
565 0x91b8, 0xffffffff, 0x00050004,
566 0x91d0, 0xffffffff, 0x00030002,
567 0x91d4, 0xffffffff, 0x00050004,
568 0x91f0, 0xffffffff, 0x00030002,
569 0x91f4, 0xffffffff, 0x00050004,
570 0x915c, 0xffffffff, 0x00010000,
571 0x9160, 0xffffffff, 0x00030002,
572 0x3f90, 0xffff0000, 0xff000000,
573 0x9178, 0xffffffff, 0x00070000,
574 0x9194, 0xffffffff, 0x00070000,
575 0x91b0, 0xffffffff, 0x00070000,
576 0x91cc, 0xffffffff, 0x00070000,
577 0x91ec, 0xffffffff, 0x00070000,
578 0x9148, 0xffff0000, 0xff000000,
579 0x9190, 0xffffffff, 0x00090008,
580 0x91ac, 0xffffffff, 0x00090008,
581 0x91c8, 0xffffffff, 0x00090008,
582 0x91e4, 0xffffffff, 0x00090008,
583 0x9204, 0xffffffff, 0x00090008,
584 0x3f94, 0xffff0000, 0xff000000,
585 0x914c, 0xffff0000, 0xff000000,
586 0x929c, 0xffffffff, 0x00000001,
587 0x8a18, 0xffffffff, 0x00000100,
588 0x8b28, 0xffffffff, 0x00000100,
589 0x9144, 0xffffffff, 0x00000100,
590 0x5644, 0xffffffff, 0x00000100,
591 0x9b7c, 0xffffffff, 0x00000000,
592 0x8030, 0xffffffff, 0x0000100a,
593 0x8a14, 0xffffffff, 0x00000007,
594 0x8b24, 0xffffffff, 0x00ff0fff,
595 0x8b10, 0xffffffff, 0x00000000,
596 0x28a4c, 0x06000000, 0x06000000,
597 0x4d8, 0xffffffff, 0x00000100,
598 0x913c, 0xffff000f, 0x0100000a,
599 0x960c, 0xffffffff, 0x54763210,
600 0x88c4, 0xffffffff, 0x000000c2,
601 0x88d4, 0xffffffff, 0x00000010,
602 0x8974, 0xffffffff, 0x00000000,
603 0xc78, 0x00000080, 0x00000080,
604 0x5e78, 0xffffffff, 0x001000f0,
605 0xd02c, 0xffffffff, 0x08421000,
606 0xa008, 0xffffffff, 0x00010000,
607 0x8d00, 0xffffffff, 0x100e4848,
608 0x8d04, 0xffffffff, 0x00164745,
609 0x8c00, 0xffffffff, 0xe4000003,
610 0x8cf0, 0x1fffffff, 0x08e00620,
611 0x28350, 0xffffffff, 0x00000000,
612 0x9508, 0xffffffff, 0x00000002
613};
614
615static const u32 sumo_golden_registers[] =
616{
617 0x900c, 0x00ffffff, 0x0017071f,
618 0x8c18, 0xffffffff, 0x10101060,
619 0x8c1c, 0xffffffff, 0x00001010,
620 0x8c30, 0x0000000f, 0x00000005,
621 0x9688, 0x0000000f, 0x00000007
622};
623
624static const u32 wrestler_golden_registers[] =
625{
626 0x5eb4, 0xffffffff, 0x00000002,
627 0x5cc, 0xffffffff, 0x00000001,
628 0x7030, 0xffffffff, 0x00000011,
629 0x7c30, 0xffffffff, 0x00000011,
630 0x6104, 0x01000300, 0x00000000,
631 0x5bc0, 0x00300000, 0x00000000,
632 0x918c, 0xffffffff, 0x00010006,
633 0x91a8, 0xffffffff, 0x00010006,
634 0x9150, 0xffffffff, 0x6e944040,
635 0x917c, 0xffffffff, 0x00030002,
636 0x9198, 0xffffffff, 0x00030002,
637 0x915c, 0xffffffff, 0x00010000,
638 0x3f90, 0xffff0000, 0xff000000,
639 0x9178, 0xffffffff, 0x00070000,
640 0x9194, 0xffffffff, 0x00070000,
641 0x9148, 0xffff0000, 0xff000000,
642 0x9190, 0xffffffff, 0x00090008,
643 0x91ac, 0xffffffff, 0x00090008,
644 0x3f94, 0xffff0000, 0xff000000,
645 0x914c, 0xffff0000, 0xff000000,
646 0x929c, 0xffffffff, 0x00000001,
647 0x8a18, 0xffffffff, 0x00000100,
648 0x8b28, 0xffffffff, 0x00000100,
649 0x9144, 0xffffffff, 0x00000100,
650 0x9b7c, 0xffffffff, 0x00000000,
651 0x8030, 0xffffffff, 0x0000100a,
652 0x8a14, 0xffffffff, 0x00000001,
653 0x8b24, 0xffffffff, 0x00ff0fff,
654 0x8b10, 0xffffffff, 0x00000000,
655 0x28a4c, 0x06000000, 0x06000000,
656 0x4d8, 0xffffffff, 0x00000100,
657 0x913c, 0xffff000f, 0x0100000a,
658 0x960c, 0xffffffff, 0x54763210,
659 0x88c4, 0xffffffff, 0x000000c2,
660 0x88d4, 0xffffffff, 0x00000010,
661 0x8974, 0xffffffff, 0x00000000,
662 0xc78, 0x00000080, 0x00000080,
663 0x5e78, 0xffffffff, 0x001000f0,
664 0xd02c, 0xffffffff, 0x08421000,
665 0xa008, 0xffffffff, 0x00010000,
666 0x8d00, 0xffffffff, 0x100e4848,
667 0x8d04, 0xffffffff, 0x00164745,
668 0x8c00, 0xffffffff, 0xe4000003,
669 0x8cf0, 0x1fffffff, 0x08e00410,
670 0x28350, 0xffffffff, 0x00000000,
671 0x9508, 0xffffffff, 0x00000002,
672 0x900c, 0xffffffff, 0x0017071f,
673 0x8c18, 0xffffffff, 0x10101060,
674 0x8c1c, 0xffffffff, 0x00001010
675};
676
677static const u32 barts_golden_registers[] =
678{
679 0x5eb4, 0xffffffff, 0x00000002,
680 0x5e78, 0x8f311ff1, 0x001000f0,
681 0x3f90, 0xffff0000, 0xff000000,
682 0x9148, 0xffff0000, 0xff000000,
683 0x3f94, 0xffff0000, 0xff000000,
684 0x914c, 0xffff0000, 0xff000000,
685 0xc78, 0x00000080, 0x00000080,
686 0xbd4, 0x70073777, 0x00010001,
687 0xd02c, 0xbfffff1f, 0x08421000,
688 0xd0b8, 0x03773777, 0x02011003,
689 0x5bc0, 0x00200000, 0x50100000,
690 0x98f8, 0x33773777, 0x02011003,
691 0x98fc, 0xffffffff, 0x76543210,
692 0x7030, 0x31000311, 0x00000011,
693 0x2f48, 0x00000007, 0x02011003,
694 0x6b28, 0x00000010, 0x00000012,
695 0x7728, 0x00000010, 0x00000012,
696 0x10328, 0x00000010, 0x00000012,
697 0x10f28, 0x00000010, 0x00000012,
698 0x11b28, 0x00000010, 0x00000012,
699 0x12728, 0x00000010, 0x00000012,
700 0x240c, 0x000007ff, 0x00000380,
701 0x8a14, 0xf000001f, 0x00000007,
702 0x8b24, 0x3fff3fff, 0x00ff0fff,
703 0x8b10, 0x0000ff0f, 0x00000000,
704 0x28a4c, 0x07ffffff, 0x06000000,
705 0x10c, 0x00000001, 0x00010003,
706 0xa02c, 0xffffffff, 0x0000009b,
707 0x913c, 0x0000000f, 0x0100000a,
708 0x8d00, 0xffff7f7f, 0x100e4848,
709 0x8d04, 0x00ffffff, 0x00164745,
710 0x8c00, 0xfffc0003, 0xe4000003,
711 0x8c04, 0xf8ff00ff, 0x40600060,
712 0x8c08, 0x00ff00ff, 0x001c001c,
713 0x8cf0, 0x1fff1fff, 0x08e00620,
714 0x8c20, 0x0fff0fff, 0x00800080,
715 0x8c24, 0x0fff0fff, 0x00800080,
716 0x8c18, 0xffffffff, 0x20202078,
717 0x8c1c, 0x0000ffff, 0x00001010,
718 0x28350, 0x00000f01, 0x00000000,
719 0x9508, 0x3700001f, 0x00000002,
720 0x960c, 0xffffffff, 0x54763210,
721 0x88c4, 0x001f3ae3, 0x000000c2,
722 0x88d4, 0x0000001f, 0x00000010,
723 0x8974, 0xffffffff, 0x00000000
724};
725
726static const u32 turks_golden_registers[] =
727{
728 0x5eb4, 0xffffffff, 0x00000002,
729 0x5e78, 0x8f311ff1, 0x001000f0,
730 0x8c8, 0x00003000, 0x00001070,
731 0x8cc, 0x000fffff, 0x00040035,
732 0x3f90, 0xffff0000, 0xfff00000,
733 0x9148, 0xffff0000, 0xfff00000,
734 0x3f94, 0xffff0000, 0xfff00000,
735 0x914c, 0xffff0000, 0xfff00000,
736 0xc78, 0x00000080, 0x00000080,
737 0xbd4, 0x00073007, 0x00010002,
738 0xd02c, 0xbfffff1f, 0x08421000,
739 0xd0b8, 0x03773777, 0x02010002,
740 0x5bc0, 0x00200000, 0x50100000,
741 0x98f8, 0x33773777, 0x00010002,
742 0x98fc, 0xffffffff, 0x33221100,
743 0x7030, 0x31000311, 0x00000011,
744 0x2f48, 0x33773777, 0x00010002,
745 0x6b28, 0x00000010, 0x00000012,
746 0x7728, 0x00000010, 0x00000012,
747 0x10328, 0x00000010, 0x00000012,
748 0x10f28, 0x00000010, 0x00000012,
749 0x11b28, 0x00000010, 0x00000012,
750 0x12728, 0x00000010, 0x00000012,
751 0x240c, 0x000007ff, 0x00000380,
752 0x8a14, 0xf000001f, 0x00000007,
753 0x8b24, 0x3fff3fff, 0x00ff0fff,
754 0x8b10, 0x0000ff0f, 0x00000000,
755 0x28a4c, 0x07ffffff, 0x06000000,
756 0x10c, 0x00000001, 0x00010003,
757 0xa02c, 0xffffffff, 0x0000009b,
758 0x913c, 0x0000000f, 0x0100000a,
759 0x8d00, 0xffff7f7f, 0x100e4848,
760 0x8d04, 0x00ffffff, 0x00164745,
761 0x8c00, 0xfffc0003, 0xe4000003,
762 0x8c04, 0xf8ff00ff, 0x40600060,
763 0x8c08, 0x00ff00ff, 0x001c001c,
764 0x8cf0, 0x1fff1fff, 0x08e00410,
765 0x8c20, 0x0fff0fff, 0x00800080,
766 0x8c24, 0x0fff0fff, 0x00800080,
767 0x8c18, 0xffffffff, 0x20202078,
768 0x8c1c, 0x0000ffff, 0x00001010,
769 0x28350, 0x00000f01, 0x00000000,
770 0x9508, 0x3700001f, 0x00000002,
771 0x960c, 0xffffffff, 0x54763210,
772 0x88c4, 0x001f3ae3, 0x000000c2,
773 0x88d4, 0x0000001f, 0x00000010,
774 0x8974, 0xffffffff, 0x00000000
775};
776
777static const u32 caicos_golden_registers[] =
778{
779 0x5eb4, 0xffffffff, 0x00000002,
780 0x5e78, 0x8f311ff1, 0x001000f0,
781 0x8c8, 0x00003420, 0x00001450,
782 0x8cc, 0x000fffff, 0x00040035,
783 0x3f90, 0xffff0000, 0xfffc0000,
784 0x9148, 0xffff0000, 0xfffc0000,
785 0x3f94, 0xffff0000, 0xfffc0000,
786 0x914c, 0xffff0000, 0xfffc0000,
787 0xc78, 0x00000080, 0x00000080,
788 0xbd4, 0x00073007, 0x00010001,
789 0xd02c, 0xbfffff1f, 0x08421000,
790 0xd0b8, 0x03773777, 0x02010001,
791 0x5bc0, 0x00200000, 0x50100000,
792 0x98f8, 0x33773777, 0x02010001,
793 0x98fc, 0xffffffff, 0x33221100,
794 0x7030, 0x31000311, 0x00000011,
795 0x2f48, 0x33773777, 0x02010001,
796 0x6b28, 0x00000010, 0x00000012,
797 0x7728, 0x00000010, 0x00000012,
798 0x10328, 0x00000010, 0x00000012,
799 0x10f28, 0x00000010, 0x00000012,
800 0x11b28, 0x00000010, 0x00000012,
801 0x12728, 0x00000010, 0x00000012,
802 0x240c, 0x000007ff, 0x00000380,
803 0x8a14, 0xf000001f, 0x00000001,
804 0x8b24, 0x3fff3fff, 0x00ff0fff,
805 0x8b10, 0x0000ff0f, 0x00000000,
806 0x28a4c, 0x07ffffff, 0x06000000,
807 0x10c, 0x00000001, 0x00010003,
808 0xa02c, 0xffffffff, 0x0000009b,
809 0x913c, 0x0000000f, 0x0100000a,
810 0x8d00, 0xffff7f7f, 0x100e4848,
811 0x8d04, 0x00ffffff, 0x00164745,
812 0x8c00, 0xfffc0003, 0xe4000003,
813 0x8c04, 0xf8ff00ff, 0x40600060,
814 0x8c08, 0x00ff00ff, 0x001c001c,
815 0x8cf0, 0x1fff1fff, 0x08e00410,
816 0x8c20, 0x0fff0fff, 0x00800080,
817 0x8c24, 0x0fff0fff, 0x00800080,
818 0x8c18, 0xffffffff, 0x20202078,
819 0x8c1c, 0x0000ffff, 0x00001010,
820 0x28350, 0x00000f01, 0x00000000,
821 0x9508, 0x3700001f, 0x00000002,
822 0x960c, 0xffffffff, 0x54763210,
823 0x88c4, 0x001f3ae3, 0x000000c2,
824 0x88d4, 0x0000001f, 0x00000010,
825 0x8974, 0xffffffff, 0x00000000
826};
827
828static void evergreen_init_golden_registers(struct radeon_device *rdev)
829{
830 switch (rdev->family) {
831 case CHIP_CYPRESS:
832 case CHIP_HEMLOCK:
833 radeon_program_register_sequence(rdev,
834 evergreen_golden_registers,
835 (const u32)ARRAY_SIZE(evergreen_golden_registers));
836 radeon_program_register_sequence(rdev,
837 evergreen_golden_registers2,
838 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
839 radeon_program_register_sequence(rdev,
840 cypress_mgcg_init,
841 (const u32)ARRAY_SIZE(cypress_mgcg_init));
842 break;
843 case CHIP_JUNIPER:
844 radeon_program_register_sequence(rdev,
845 evergreen_golden_registers,
846 (const u32)ARRAY_SIZE(evergreen_golden_registers));
847 radeon_program_register_sequence(rdev,
848 evergreen_golden_registers2,
849 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
850 radeon_program_register_sequence(rdev,
851 juniper_mgcg_init,
852 (const u32)ARRAY_SIZE(juniper_mgcg_init));
853 break;
854 case CHIP_REDWOOD:
855 radeon_program_register_sequence(rdev,
856 evergreen_golden_registers,
857 (const u32)ARRAY_SIZE(evergreen_golden_registers));
858 radeon_program_register_sequence(rdev,
859 evergreen_golden_registers2,
860 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
861 radeon_program_register_sequence(rdev,
862 redwood_mgcg_init,
863 (const u32)ARRAY_SIZE(redwood_mgcg_init));
864 break;
865 case CHIP_CEDAR:
866 radeon_program_register_sequence(rdev,
867 cedar_golden_registers,
868 (const u32)ARRAY_SIZE(cedar_golden_registers));
869 radeon_program_register_sequence(rdev,
870 evergreen_golden_registers2,
871 (const u32)ARRAY_SIZE(evergreen_golden_registers2));
872 radeon_program_register_sequence(rdev,
873 cedar_mgcg_init,
874 (const u32)ARRAY_SIZE(cedar_mgcg_init));
875 break;
876 case CHIP_PALM:
877 radeon_program_register_sequence(rdev,
878 wrestler_golden_registers,
879 (const u32)ARRAY_SIZE(wrestler_golden_registers));
880 break;
881 case CHIP_SUMO:
882 radeon_program_register_sequence(rdev,
883 supersumo_golden_registers,
884 (const u32)ARRAY_SIZE(supersumo_golden_registers));
885 break;
886 case CHIP_SUMO2:
887 radeon_program_register_sequence(rdev,
888 supersumo_golden_registers,
889 (const u32)ARRAY_SIZE(supersumo_golden_registers));
890 radeon_program_register_sequence(rdev,
891 sumo_golden_registers,
892 (const u32)ARRAY_SIZE(sumo_golden_registers));
893 break;
894 case CHIP_BARTS:
895 radeon_program_register_sequence(rdev,
896 barts_golden_registers,
897 (const u32)ARRAY_SIZE(barts_golden_registers));
898 break;
899 case CHIP_TURKS:
900 radeon_program_register_sequence(rdev,
901 turks_golden_registers,
902 (const u32)ARRAY_SIZE(turks_golden_registers));
903 break;
904 case CHIP_CAICOS:
905 radeon_program_register_sequence(rdev,
906 caicos_golden_registers,
907 (const u32)ARRAY_SIZE(caicos_golden_registers));
908 break;
909 default:
910 break;
911 }
912}
913
56void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, 914void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
57 unsigned *bankh, unsigned *mtaspect, 915 unsigned *bankh, unsigned *mtaspect,
58 unsigned *tile_split) 916 unsigned *tile_split)
@@ -189,6 +1047,20 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
189 unsigned vco_freq; 1047 unsigned vco_freq;
190 int r; 1048 int r;
191 1049
1050 /* bypass vclk and dclk with bclk */
1051 WREG32_P(CG_UPLL_FUNC_CNTL_2,
1052 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
1053 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
1054
1055 /* put PLL in bypass mode */
1056 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
1057
1058 if (!vclk || !dclk) {
1059 /* keep the Bypass mode, put PLL to sleep */
1060 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
1061 return 0;
1062 }
1063
192 /* loop through vco from low to high */ 1064 /* loop through vco from low to high */
193 for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) { 1065 for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {
194 unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384; 1066 unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;
@@ -236,14 +1108,6 @@ int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
236 1108
237 mdelay(1); 1109 mdelay(1);
238 1110
239 /* bypass vclk and dclk with bclk */
240 WREG32_P(CG_UPLL_FUNC_CNTL_2,
241 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
242 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
243
244 /* put PLL in bypass mode */
245 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
246
247 r = evergreen_uvd_send_upll_ctlreq(rdev); 1111 r = evergreen_uvd_send_upll_ctlreq(rdev);
248 if (r) 1112 if (r)
249 return r; 1113 return r;
@@ -316,6 +1180,27 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
316 } 1180 }
317} 1181}
318 1182
1183static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
1184{
1185 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
1186 return true;
1187 else
1188 return false;
1189}
1190
1191static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc)
1192{
1193 u32 pos1, pos2;
1194
1195 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
1196 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]);
1197
1198 if (pos1 != pos2)
1199 return true;
1200 else
1201 return false;
1202}
1203
319/** 1204/**
320 * dce4_wait_for_vblank - vblank wait asic callback. 1205 * dce4_wait_for_vblank - vblank wait asic callback.
321 * 1206 *
@@ -326,21 +1211,28 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
326 */ 1211 */
327void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) 1212void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
328{ 1213{
329 int i; 1214 unsigned i = 0;
330 1215
331 if (crtc >= rdev->num_crtc) 1216 if (crtc >= rdev->num_crtc)
332 return; 1217 return;
333 1218
334 if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) { 1219 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN))
335 for (i = 0; i < rdev->usec_timeout; i++) { 1220 return;
336 if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)) 1221
1222 /* depending on when we hit vblank, we may be close to active; if so,
1223 * wait for another frame.
1224 */
1225 while (dce4_is_in_vblank(rdev, crtc)) {
1226 if (i++ % 100 == 0) {
1227 if (!dce4_is_counter_moving(rdev, crtc))
337 break; 1228 break;
338 udelay(1);
339 } 1229 }
340 for (i = 0; i < rdev->usec_timeout; i++) { 1230 }
341 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) 1231
1232 while (!dce4_is_in_vblank(rdev, crtc)) {
1233 if (i++ % 100 == 0) {
1234 if (!dce4_is_counter_moving(rdev, crtc))
342 break; 1235 break;
343 udelay(1);
344 } 1236 }
345 } 1237 }
346} 1238}
@@ -1546,17 +2438,16 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
1546 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); 2438 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1547 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) { 2439 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1548 radeon_wait_for_vblank(rdev, i); 2440 radeon_wait_for_vblank(rdev, i);
1549 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1550 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 2441 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2442 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1551 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); 2443 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1552 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1553 } 2444 }
1554 } else { 2445 } else {
1555 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); 2446 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1556 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) { 2447 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1557 radeon_wait_for_vblank(rdev, i); 2448 radeon_wait_for_vblank(rdev, i);
1558 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1559 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); 2449 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2450 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1560 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp); 2451 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1561 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0); 2452 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1562 } 2453 }
@@ -1568,6 +2459,15 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
1568 break; 2459 break;
1569 udelay(1); 2460 udelay(1);
1570 } 2461 }
2462
2463 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
2464 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
2465 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
2466 tmp &= ~EVERGREEN_CRTC_MASTER_EN;
2467 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
2468 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
2469 save->crtc_enabled[i] = false;
2470 /* ***** */
1571 } else { 2471 } else {
1572 save->crtc_enabled[i] = false; 2472 save->crtc_enabled[i] = false;
1573 } 2473 }
@@ -1585,6 +2485,22 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
1585 } 2485 }
1586 /* wait for the MC to settle */ 2486 /* wait for the MC to settle */
1587 udelay(100); 2487 udelay(100);
2488
2489 /* lock double buffered regs */
2490 for (i = 0; i < rdev->num_crtc; i++) {
2491 if (save->crtc_enabled[i]) {
2492 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2493 if (!(tmp & EVERGREEN_GRPH_UPDATE_LOCK)) {
2494 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
2495 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
2496 }
2497 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
2498 if (!(tmp & 1)) {
2499 tmp |= 1;
2500 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
2501 }
2502 }
2503 }
1588} 2504}
1589 2505
1590void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) 2506void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
@@ -1606,6 +2522,33 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1606 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); 2522 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1607 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 2523 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1608 2524
2525 /* unlock regs and wait for update */
2526 for (i = 0; i < rdev->num_crtc; i++) {
2527 if (save->crtc_enabled[i]) {
2528 tmp = RREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i]);
2529 if ((tmp & 0x3) != 0) {
2530 tmp &= ~0x3;
2531 WREG32(EVERGREEN_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
2532 }
2533 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2534 if (tmp & EVERGREEN_GRPH_UPDATE_LOCK) {
2535 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
2536 WREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i], tmp);
2537 }
2538 tmp = RREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i]);
2539 if (tmp & 1) {
2540 tmp &= ~1;
2541 WREG32(EVERGREEN_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
2542 }
2543 for (j = 0; j < rdev->usec_timeout; j++) {
2544 tmp = RREG32(EVERGREEN_GRPH_UPDATE + crtc_offsets[i]);
2545 if ((tmp & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING) == 0)
2546 break;
2547 udelay(1);
2548 }
2549 }
2550 }
2551
1609 /* unblackout the MC */ 2552 /* unblackout the MC */
1610 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); 2553 tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1611 tmp &= ~BLACKOUT_MODE_MASK; 2554 tmp &= ~BLACKOUT_MODE_MASK;
@@ -3961,6 +4904,9 @@ int evergreen_resume(struct radeon_device *rdev)
3961 /* post card */ 4904 /* post card */
3962 atom_asic_init(rdev->mode_info.atom_context); 4905 atom_asic_init(rdev->mode_info.atom_context);
3963 4906
4907 /* init golden registers */
4908 evergreen_init_golden_registers(rdev);
4909
3964 rdev->accel_working = true; 4910 rdev->accel_working = true;
3965 r = evergreen_startup(rdev); 4911 r = evergreen_startup(rdev);
3966 if (r) { 4912 if (r) {
@@ -4024,6 +4970,8 @@ int evergreen_init(struct radeon_device *rdev)
4024 DRM_INFO("GPU not posted. posting now...\n"); 4970 DRM_INFO("GPU not posted. posting now...\n");
4025 atom_asic_init(rdev->mode_info.atom_context); 4971 atom_asic_init(rdev->mode_info.atom_context);
4026 } 4972 }
4973 /* init golden registers */
4974 evergreen_init_golden_registers(rdev);
4027 /* Initialize scratch registers */ 4975 /* Initialize scratch registers */
4028 r600_scratch_init(rdev); 4976 r600_scratch_init(rdev);
4029 /* Initialize surface registers */ 4977 /* Initialize surface registers */
diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
index 4fdecc2b4040..b4ab8ceb1654 100644
--- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
+++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
@@ -54,6 +54,68 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t cloc
54 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz); 54 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
55} 55}
56 56
57static void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder)
58{
59 struct radeon_device *rdev = encoder->dev->dev_private;
60 struct drm_connector *connector;
61 struct radeon_connector *radeon_connector = NULL;
62 struct cea_sad *sads;
63 int i, sad_count;
64
65 static const u16 eld_reg_to_type[][2] = {
66 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
67 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
68 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
69 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
70 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
71 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
72 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
73 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
74 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
75 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
76 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
77 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
78 };
79
80 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
81 if (connector->encoder == encoder)
82 radeon_connector = to_radeon_connector(connector);
83 }
84
85 if (!radeon_connector) {
86 DRM_ERROR("Couldn't find encoder's connector\n");
87 return;
88 }
89
90 sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
91 if (sad_count < 0) {
92 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
93 return;
94 }
95 BUG_ON(!sads);
96
97 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
98 u32 value = 0;
99 int j;
100
101 for (j = 0; j < sad_count; j++) {
102 struct cea_sad *sad = &sads[j];
103
104 if (sad->format == eld_reg_to_type[i][1]) {
105 value = MAX_CHANNELS(sad->channels) |
106 DESCRIPTOR_BYTE_2(sad->byte2) |
107 SUPPORTED_FREQUENCIES(sad->freq);
108 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
109 value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
110 break;
111 }
112 }
113 WREG32(eld_reg_to_type[i][0], value);
114 }
115
116 kfree(sads);
117}
118
57/* 119/*
58 * build a HDMI Video Info Frame 120 * build a HDMI Video Info Frame
59 */ 121 */
@@ -85,6 +147,30 @@ static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
85 frame[0xC] | (frame[0xD] << 8)); 147 frame[0xC] | (frame[0xD] << 8));
86} 148}
87 149
150static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
151{
152 struct drm_device *dev = encoder->dev;
153 struct radeon_device *rdev = dev->dev_private;
154 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
155 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
157 u32 base_rate = 48000;
158
159 if (!dig || !dig->afmt)
160 return;
161
162 /* XXX: properly calculate this */
163 /* XXX two dtos; generally use dto0 for hdmi */
164 /* Express [24MHz / target pixel clock] as an exact rational
165 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
166 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
167 */
168 WREG32(DCCG_AUDIO_DTO0_PHASE, (base_rate*50) & 0xffffff);
169 WREG32(DCCG_AUDIO_DTO0_MODULE, (clock*100) & 0xffffff);
170 WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
171}
172
173
88/* 174/*
89 * update the info frames with the data from the current display mode 175 * update the info frames with the data from the current display mode
90 */ 176 */
@@ -104,33 +190,19 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
104 return; 190 return;
105 offset = dig->afmt->offset; 191 offset = dig->afmt->offset;
106 192
107 r600_audio_set_clock(encoder, mode->clock); 193 evergreen_audio_set_dto(encoder, mode->clock);
108 194
109 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 195 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
110 HDMI_NULL_SEND); /* send null packets when required */ 196 HDMI_NULL_SEND); /* send null packets when required */
111 197
112 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000); 198 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
113 199
114 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
115 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
116 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
117
118 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
119 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
120 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
121
122 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
123 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
124 HDMI_ACR_SOURCE); /* select SW CTS value */
125
126 WREG32(HDMI_VBI_PACKET_CONTROL + offset, 200 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
127 HDMI_NULL_SEND | /* send null packets when required */ 201 HDMI_NULL_SEND | /* send null packets when required */
128 HDMI_GC_SEND | /* send general control packets */ 202 HDMI_GC_SEND | /* send general control packets */
129 HDMI_GC_CONT); /* send general control packets every frame */ 203 HDMI_GC_CONT); /* send general control packets every frame */
130 204
131 WREG32(HDMI_INFOFRAME_CONTROL0 + offset, 205 WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
132 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
133 HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */
134 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */ 206 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
135 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */ 207 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
136 208
@@ -138,11 +210,47 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
138 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */ 210 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
139 211
140 WREG32(HDMI_INFOFRAME_CONTROL1 + offset, 212 WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
141 HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */
142 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */ 213 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
143 214
144 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */ 215 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
145 216
217 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
218 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
219 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
220
221 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
222 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
223
224 /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
225
226 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
227 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
228 HDMI_ACR_SOURCE); /* select SW CTS value */
229
230 evergreen_hdmi_update_ACR(encoder, mode->clock);
231
232 WREG32(AFMT_60958_0 + offset,
233 AFMT_60958_CS_CHANNEL_NUMBER_L(1));
234
235 WREG32(AFMT_60958_1 + offset,
236 AFMT_60958_CS_CHANNEL_NUMBER_R(2));
237
238 WREG32(AFMT_60958_2 + offset,
239 AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
240 AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
241 AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
242 AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
243 AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
244 AFMT_60958_CS_CHANNEL_NUMBER_7(8));
245
246 /* fglrx sets 0x0001005f | (x & 0x00fc0000) in 0x5f78 here */
247
248 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
249 AFMT_AUDIO_CHANNEL_ENABLE(0xff));
250
251 /* fglrx sets 0x40 in 0x5f80 here */
252 evergreen_hdmi_write_sad_regs(encoder);
253
146 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 254 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
147 if (err < 0) { 255 if (err < 0) {
148 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); 256 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
@@ -156,7 +264,17 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
156 } 264 }
157 265
158 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer)); 266 evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
159 evergreen_hdmi_update_ACR(encoder, mode->clock); 267
268 WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
269 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
270 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
271
272 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
273 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
274 ~HDMI_AVI_INFO_LINE_MASK);
275
276 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
277 AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
160 278
161 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */ 279 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
162 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF); 280 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
@@ -164,3 +282,20 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
164 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001); 282 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
165 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001); 283 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
166} 284}
285
286void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
287{
288 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
289 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
290
291 /* Silent, r600_hdmi_enable will raise WARN for us */
292 if (enable && dig->afmt->enabled)
293 return;
294 if (!enable && !dig->afmt->enabled)
295 return;
296
297 dig->afmt->enabled = enable;
298
299 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
300 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
301}
diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h
index f585be16e2d5..881aba23c477 100644
--- a/drivers/gpu/drm/radeon/evergreen_reg.h
+++ b/drivers/gpu/drm/radeon/evergreen_reg.h
@@ -226,6 +226,8 @@
226#define EVERGREEN_CRTC_STATUS_HV_COUNT 0x6ea0 226#define EVERGREEN_CRTC_STATUS_HV_COUNT 0x6ea0
227#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8 227#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
228#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 228#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4
229#define EVERGREEN_MASTER_UPDATE_LOCK 0x6ef4
230#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
229 231
230#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0 232#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0
231#define EVERGREEN_DC_GPIO_HPD_A 0x64b4 233#define EVERGREEN_DC_GPIO_HPD_A 0x64b4
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index eabf92af84e5..d9a005431087 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -234,6 +234,7 @@
234# define HDMI_MPEG_INFO_CONT (1 << 9) 234# define HDMI_MPEG_INFO_CONT (1 << 9)
235#define HDMI_INFOFRAME_CONTROL1 0x7048 235#define HDMI_INFOFRAME_CONTROL1 0x7048
236# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 236# define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
237# define HDMI_AVI_INFO_LINE_MASK (0x3f << 0)
237# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 238# define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
238# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 239# define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
239#define HDMI_GENERIC_PACKET_CONTROL 0x704c 240#define HDMI_GENERIC_PACKET_CONTROL 0x704c
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index fd03f318cc1c..7436b91699d0 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -78,6 +78,282 @@ MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
78MODULE_FIRMWARE("radeon/ARUBA_me.bin"); 78MODULE_FIRMWARE("radeon/ARUBA_me.bin");
79MODULE_FIRMWARE("radeon/ARUBA_rlc.bin"); 79MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
80 80
81
82static const u32 cayman_golden_registers2[] =
83{
84 0x3e5c, 0xffffffff, 0x00000000,
85 0x3e48, 0xffffffff, 0x00000000,
86 0x3e4c, 0xffffffff, 0x00000000,
87 0x3e64, 0xffffffff, 0x00000000,
88 0x3e50, 0xffffffff, 0x00000000,
89 0x3e60, 0xffffffff, 0x00000000
90};
91
92static const u32 cayman_golden_registers[] =
93{
94 0x5eb4, 0xffffffff, 0x00000002,
95 0x5e78, 0x8f311ff1, 0x001000f0,
96 0x3f90, 0xffff0000, 0xff000000,
97 0x9148, 0xffff0000, 0xff000000,
98 0x3f94, 0xffff0000, 0xff000000,
99 0x914c, 0xffff0000, 0xff000000,
100 0xc78, 0x00000080, 0x00000080,
101 0xbd4, 0x70073777, 0x00011003,
102 0xd02c, 0xbfffff1f, 0x08421000,
103 0xd0b8, 0x73773777, 0x02011003,
104 0x5bc0, 0x00200000, 0x50100000,
105 0x98f8, 0x33773777, 0x02011003,
106 0x98fc, 0xffffffff, 0x76541032,
107 0x7030, 0x31000311, 0x00000011,
108 0x2f48, 0x33773777, 0x42010001,
109 0x6b28, 0x00000010, 0x00000012,
110 0x7728, 0x00000010, 0x00000012,
111 0x10328, 0x00000010, 0x00000012,
112 0x10f28, 0x00000010, 0x00000012,
113 0x11b28, 0x00000010, 0x00000012,
114 0x12728, 0x00000010, 0x00000012,
115 0x240c, 0x000007ff, 0x00000000,
116 0x8a14, 0xf000001f, 0x00000007,
117 0x8b24, 0x3fff3fff, 0x00ff0fff,
118 0x8b10, 0x0000ff0f, 0x00000000,
119 0x28a4c, 0x07ffffff, 0x06000000,
120 0x10c, 0x00000001, 0x00010003,
121 0xa02c, 0xffffffff, 0x0000009b,
122 0x913c, 0x0000010f, 0x01000100,
123 0x8c04, 0xf8ff00ff, 0x40600060,
124 0x28350, 0x00000f01, 0x00000000,
125 0x9508, 0x3700001f, 0x00000002,
126 0x960c, 0xffffffff, 0x54763210,
127 0x88c4, 0x001f3ae3, 0x00000082,
128 0x88d0, 0xffffffff, 0x0f40df40,
129 0x88d4, 0x0000001f, 0x00000010,
130 0x8974, 0xffffffff, 0x00000000
131};
132
133static const u32 dvst_golden_registers2[] =
134{
135 0x8f8, 0xffffffff, 0,
136 0x8fc, 0x00380000, 0,
137 0x8f8, 0xffffffff, 1,
138 0x8fc, 0x0e000000, 0
139};
140
141static const u32 dvst_golden_registers[] =
142{
143 0x690, 0x3fff3fff, 0x20c00033,
144 0x918c, 0x0fff0fff, 0x00010006,
145 0x91a8, 0x0fff0fff, 0x00010006,
146 0x9150, 0xffffdfff, 0x6e944040,
147 0x917c, 0x0fff0fff, 0x00030002,
148 0x9198, 0x0fff0fff, 0x00030002,
149 0x915c, 0x0fff0fff, 0x00010000,
150 0x3f90, 0xffff0001, 0xff000000,
151 0x9178, 0x0fff0fff, 0x00070000,
152 0x9194, 0x0fff0fff, 0x00070000,
153 0x9148, 0xffff0001, 0xff000000,
154 0x9190, 0x0fff0fff, 0x00090008,
155 0x91ac, 0x0fff0fff, 0x00090008,
156 0x3f94, 0xffff0000, 0xff000000,
157 0x914c, 0xffff0000, 0xff000000,
158 0x929c, 0x00000fff, 0x00000001,
159 0x55e4, 0xff607fff, 0xfc000100,
160 0x8a18, 0xff000fff, 0x00000100,
161 0x8b28, 0xff000fff, 0x00000100,
162 0x9144, 0xfffc0fff, 0x00000100,
163 0x6ed8, 0x00010101, 0x00010000,
164 0x9830, 0xffffffff, 0x00000000,
165 0x9834, 0xf00fffff, 0x00000400,
166 0x9838, 0xfffffffe, 0x00000000,
167 0xd0c0, 0xff000fff, 0x00000100,
168 0xd02c, 0xbfffff1f, 0x08421000,
169 0xd0b8, 0x73773777, 0x12010001,
170 0x5bb0, 0x000000f0, 0x00000070,
171 0x98f8, 0x73773777, 0x12010001,
172 0x98fc, 0xffffffff, 0x00000010,
173 0x9b7c, 0x00ff0000, 0x00fc0000,
174 0x8030, 0x00001f0f, 0x0000100a,
175 0x2f48, 0x73773777, 0x12010001,
176 0x2408, 0x00030000, 0x000c007f,
177 0x8a14, 0xf000003f, 0x00000007,
178 0x8b24, 0x3fff3fff, 0x00ff0fff,
179 0x8b10, 0x0000ff0f, 0x00000000,
180 0x28a4c, 0x07ffffff, 0x06000000,
181 0x4d8, 0x00000fff, 0x00000100,
182 0xa008, 0xffffffff, 0x00010000,
183 0x913c, 0xffff03ff, 0x01000100,
184 0x8c00, 0x000000ff, 0x00000003,
185 0x8c04, 0xf8ff00ff, 0x40600060,
186 0x8cf0, 0x1fff1fff, 0x08e00410,
187 0x28350, 0x00000f01, 0x00000000,
188 0x9508, 0xf700071f, 0x00000002,
189 0x960c, 0xffffffff, 0x54763210,
190 0x20ef8, 0x01ff01ff, 0x00000002,
191 0x20e98, 0xfffffbff, 0x00200000,
192 0x2015c, 0xffffffff, 0x00000f40,
193 0x88c4, 0x001f3ae3, 0x00000082,
194 0x8978, 0x3fffffff, 0x04050140,
195 0x88d4, 0x0000001f, 0x00000010,
196 0x8974, 0xffffffff, 0x00000000
197};
198
199static const u32 scrapper_golden_registers[] =
200{
201 0x690, 0x3fff3fff, 0x20c00033,
202 0x918c, 0x0fff0fff, 0x00010006,
203 0x918c, 0x0fff0fff, 0x00010006,
204 0x91a8, 0x0fff0fff, 0x00010006,
205 0x91a8, 0x0fff0fff, 0x00010006,
206 0x9150, 0xffffdfff, 0x6e944040,
207 0x9150, 0xffffdfff, 0x6e944040,
208 0x917c, 0x0fff0fff, 0x00030002,
209 0x917c, 0x0fff0fff, 0x00030002,
210 0x9198, 0x0fff0fff, 0x00030002,
211 0x9198, 0x0fff0fff, 0x00030002,
212 0x915c, 0x0fff0fff, 0x00010000,
213 0x915c, 0x0fff0fff, 0x00010000,
214 0x3f90, 0xffff0001, 0xff000000,
215 0x3f90, 0xffff0001, 0xff000000,
216 0x9178, 0x0fff0fff, 0x00070000,
217 0x9178, 0x0fff0fff, 0x00070000,
218 0x9194, 0x0fff0fff, 0x00070000,
219 0x9194, 0x0fff0fff, 0x00070000,
220 0x9148, 0xffff0001, 0xff000000,
221 0x9148, 0xffff0001, 0xff000000,
222 0x9190, 0x0fff0fff, 0x00090008,
223 0x9190, 0x0fff0fff, 0x00090008,
224 0x91ac, 0x0fff0fff, 0x00090008,
225 0x91ac, 0x0fff0fff, 0x00090008,
226 0x3f94, 0xffff0000, 0xff000000,
227 0x3f94, 0xffff0000, 0xff000000,
228 0x914c, 0xffff0000, 0xff000000,
229 0x914c, 0xffff0000, 0xff000000,
230 0x929c, 0x00000fff, 0x00000001,
231 0x929c, 0x00000fff, 0x00000001,
232 0x55e4, 0xff607fff, 0xfc000100,
233 0x8a18, 0xff000fff, 0x00000100,
234 0x8a18, 0xff000fff, 0x00000100,
235 0x8b28, 0xff000fff, 0x00000100,
236 0x8b28, 0xff000fff, 0x00000100,
237 0x9144, 0xfffc0fff, 0x00000100,
238 0x9144, 0xfffc0fff, 0x00000100,
239 0x6ed8, 0x00010101, 0x00010000,
240 0x9830, 0xffffffff, 0x00000000,
241 0x9830, 0xffffffff, 0x00000000,
242 0x9834, 0xf00fffff, 0x00000400,
243 0x9834, 0xf00fffff, 0x00000400,
244 0x9838, 0xfffffffe, 0x00000000,
245 0x9838, 0xfffffffe, 0x00000000,
246 0xd0c0, 0xff000fff, 0x00000100,
247 0xd02c, 0xbfffff1f, 0x08421000,
248 0xd02c, 0xbfffff1f, 0x08421000,
249 0xd0b8, 0x73773777, 0x12010001,
250 0xd0b8, 0x73773777, 0x12010001,
251 0x5bb0, 0x000000f0, 0x00000070,
252 0x98f8, 0x73773777, 0x12010001,
253 0x98f8, 0x73773777, 0x12010001,
254 0x98fc, 0xffffffff, 0x00000010,
255 0x98fc, 0xffffffff, 0x00000010,
256 0x9b7c, 0x00ff0000, 0x00fc0000,
257 0x9b7c, 0x00ff0000, 0x00fc0000,
258 0x8030, 0x00001f0f, 0x0000100a,
259 0x8030, 0x00001f0f, 0x0000100a,
260 0x2f48, 0x73773777, 0x12010001,
261 0x2f48, 0x73773777, 0x12010001,
262 0x2408, 0x00030000, 0x000c007f,
263 0x8a14, 0xf000003f, 0x00000007,
264 0x8a14, 0xf000003f, 0x00000007,
265 0x8b24, 0x3fff3fff, 0x00ff0fff,
266 0x8b24, 0x3fff3fff, 0x00ff0fff,
267 0x8b10, 0x0000ff0f, 0x00000000,
268 0x8b10, 0x0000ff0f, 0x00000000,
269 0x28a4c, 0x07ffffff, 0x06000000,
270 0x28a4c, 0x07ffffff, 0x06000000,
271 0x4d8, 0x00000fff, 0x00000100,
272 0x4d8, 0x00000fff, 0x00000100,
273 0xa008, 0xffffffff, 0x00010000,
274 0xa008, 0xffffffff, 0x00010000,
275 0x913c, 0xffff03ff, 0x01000100,
276 0x913c, 0xffff03ff, 0x01000100,
277 0x90e8, 0x001fffff, 0x010400c0,
278 0x8c00, 0x000000ff, 0x00000003,
279 0x8c00, 0x000000ff, 0x00000003,
280 0x8c04, 0xf8ff00ff, 0x40600060,
281 0x8c04, 0xf8ff00ff, 0x40600060,
282 0x8c30, 0x0000000f, 0x00040005,
283 0x8cf0, 0x1fff1fff, 0x08e00410,
284 0x8cf0, 0x1fff1fff, 0x08e00410,
285 0x900c, 0x00ffffff, 0x0017071f,
286 0x28350, 0x00000f01, 0x00000000,
287 0x28350, 0x00000f01, 0x00000000,
288 0x9508, 0xf700071f, 0x00000002,
289 0x9508, 0xf700071f, 0x00000002,
290 0x9688, 0x00300000, 0x0017000f,
291 0x960c, 0xffffffff, 0x54763210,
292 0x960c, 0xffffffff, 0x54763210,
293 0x20ef8, 0x01ff01ff, 0x00000002,
294 0x20e98, 0xfffffbff, 0x00200000,
295 0x2015c, 0xffffffff, 0x00000f40,
296 0x88c4, 0x001f3ae3, 0x00000082,
297 0x88c4, 0x001f3ae3, 0x00000082,
298 0x8978, 0x3fffffff, 0x04050140,
299 0x8978, 0x3fffffff, 0x04050140,
300 0x88d4, 0x0000001f, 0x00000010,
301 0x88d4, 0x0000001f, 0x00000010,
302 0x8974, 0xffffffff, 0x00000000,
303 0x8974, 0xffffffff, 0x00000000
304};
305
306static void ni_init_golden_registers(struct radeon_device *rdev)
307{
308 switch (rdev->family) {
309 case CHIP_CAYMAN:
310 radeon_program_register_sequence(rdev,
311 cayman_golden_registers,
312 (const u32)ARRAY_SIZE(cayman_golden_registers));
313 radeon_program_register_sequence(rdev,
314 cayman_golden_registers2,
315 (const u32)ARRAY_SIZE(cayman_golden_registers2));
316 break;
317 case CHIP_ARUBA:
318 if ((rdev->pdev->device == 0x9900) ||
319 (rdev->pdev->device == 0x9901) ||
320 (rdev->pdev->device == 0x9903) ||
321 (rdev->pdev->device == 0x9904) ||
322 (rdev->pdev->device == 0x9905) ||
323 (rdev->pdev->device == 0x9906) ||
324 (rdev->pdev->device == 0x9907) ||
325 (rdev->pdev->device == 0x9908) ||
326 (rdev->pdev->device == 0x9909) ||
327 (rdev->pdev->device == 0x990A) ||
328 (rdev->pdev->device == 0x990B) ||
329 (rdev->pdev->device == 0x990C) ||
330 (rdev->pdev->device == 0x990D) ||
331 (rdev->pdev->device == 0x990E) ||
332 (rdev->pdev->device == 0x990F) ||
333 (rdev->pdev->device == 0x9910) ||
334 (rdev->pdev->device == 0x9913) ||
335 (rdev->pdev->device == 0x9917) ||
336 (rdev->pdev->device == 0x9918)) {
337 radeon_program_register_sequence(rdev,
338 dvst_golden_registers,
339 (const u32)ARRAY_SIZE(dvst_golden_registers));
340 radeon_program_register_sequence(rdev,
341 dvst_golden_registers2,
342 (const u32)ARRAY_SIZE(dvst_golden_registers2));
343 } else {
344 radeon_program_register_sequence(rdev,
345 scrapper_golden_registers,
346 (const u32)ARRAY_SIZE(scrapper_golden_registers));
347 radeon_program_register_sequence(rdev,
348 dvst_golden_registers2,
349 (const u32)ARRAY_SIZE(dvst_golden_registers2));
350 }
351 break;
352 default:
353 break;
354 }
355}
356
81#define BTC_IO_MC_REGS_SIZE 29 357#define BTC_IO_MC_REGS_SIZE 29
82 358
83static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = { 359static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
@@ -1830,6 +2106,9 @@ int cayman_resume(struct radeon_device *rdev)
1830 /* post card */ 2106 /* post card */
1831 atom_asic_init(rdev->mode_info.atom_context); 2107 atom_asic_init(rdev->mode_info.atom_context);
1832 2108
2109 /* init golden registers */
2110 ni_init_golden_registers(rdev);
2111
1833 rdev->accel_working = true; 2112 rdev->accel_working = true;
1834 r = cayman_startup(rdev); 2113 r = cayman_startup(rdev);
1835 if (r) { 2114 if (r) {
@@ -1888,6 +2167,8 @@ int cayman_init(struct radeon_device *rdev)
1888 DRM_INFO("GPU not posted. posting now...\n"); 2167 DRM_INFO("GPU not posted. posting now...\n");
1889 atom_asic_init(rdev->mode_info.atom_context); 2168 atom_asic_init(rdev->mode_info.atom_context);
1890 } 2169 }
2170 /* init golden registers */
2171 ni_init_golden_registers(rdev);
1891 /* Initialize scratch registers */ 2172 /* Initialize scratch registers */
1892 r600_scratch_init(rdev); 2173 r600_scratch_init(rdev);
1893 /* Initialize surface registers */ 2174 /* Initialize surface registers */
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 9db58530be37..4973bff37fec 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -69,6 +69,38 @@ MODULE_FIRMWARE(FIRMWARE_R520);
69 * and others in some cases. 69 * and others in some cases.
70 */ 70 */
71 71
72static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
73{
74 if (crtc == 0) {
75 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
76 return true;
77 else
78 return false;
79 } else {
80 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
81 return true;
82 else
83 return false;
84 }
85}
86
87static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
88{
89 u32 vline1, vline2;
90
91 if (crtc == 0) {
92 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
93 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
94 } else {
95 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
96 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
97 }
98 if (vline1 != vline2)
99 return true;
100 else
101 return false;
102}
103
72/** 104/**
73 * r100_wait_for_vblank - vblank wait asic callback. 105 * r100_wait_for_vblank - vblank wait asic callback.
74 * 106 *
@@ -79,36 +111,33 @@ MODULE_FIRMWARE(FIRMWARE_R520);
79 */ 111 */
80void r100_wait_for_vblank(struct radeon_device *rdev, int crtc) 112void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
81{ 113{
82 int i; 114 unsigned i = 0;
83 115
84 if (crtc >= rdev->num_crtc) 116 if (crtc >= rdev->num_crtc)
85 return; 117 return;
86 118
87 if (crtc == 0) { 119 if (crtc == 0) {
88 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) { 120 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
89 for (i = 0; i < rdev->usec_timeout; i++) { 121 return;
90 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
91 break;
92 udelay(1);
93 }
94 for (i = 0; i < rdev->usec_timeout; i++) {
95 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
96 break;
97 udelay(1);
98 }
99 }
100 } else { 122 } else {
101 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) { 123 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
102 for (i = 0; i < rdev->usec_timeout; i++) { 124 return;
103 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)) 125 }
104 break; 126
105 udelay(1); 127 /* depending on when we hit vblank, we may be close to active; if so,
106 } 128 * wait for another frame.
107 for (i = 0; i < rdev->usec_timeout; i++) { 129 */
108 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR) 130 while (r100_is_in_vblank(rdev, crtc)) {
109 break; 131 if (i++ % 100 == 0) {
110 udelay(1); 132 if (!r100_is_counter_moving(rdev, crtc))
111 } 133 break;
134 }
135 }
136
137 while (!r100_is_in_vblank(rdev, crtc)) {
138 if (i++ % 100 == 0) {
139 if (!r100_is_counter_moving(rdev, crtc))
140 break;
112 } 141 }
113 } 142 }
114} 143}
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h
index c0dc8d3ba0bb..1dd0d32993d5 100644
--- a/drivers/gpu/drm/radeon/r500_reg.h
+++ b/drivers/gpu/drm/radeon/r500_reg.h
@@ -358,7 +358,9 @@
358#define AVIVO_D1CRTC_STATUS_HV_COUNT 0x60ac 358#define AVIVO_D1CRTC_STATUS_HV_COUNT 0x60ac
359#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4 359#define AVIVO_D1CRTC_STEREO_CONTROL 0x60c4
360 360
361#define AVIVO_D1MODE_MASTER_UPDATE_LOCK 0x60e0
361#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4 362#define AVIVO_D1MODE_MASTER_UPDATE_MODE 0x60e4
363#define AVIVO_D1CRTC_UPDATE_LOCK 0x60e8
362 364
363/* master controls */ 365/* master controls */
364#define AVIVO_DC_CRTC_MASTER_EN 0x60f8 366#define AVIVO_DC_CRTC_MASTER_EN 0x60f8
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 5fe9e74d6360..1a08008c978b 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2625,7 +2625,7 @@ int r600_uvd_rbc_start(struct radeon_device *rdev)
2625 radeon_ring_write(ring, 0x8); 2625 radeon_ring_write(ring, 0x8);
2626 2626
2627 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0)); 2627 radeon_ring_write(ring, PACKET0(UVD_SEMA_CNTL, 0));
2628 radeon_ring_write(ring, 1); 2628 radeon_ring_write(ring, 3);
2629 2629
2630 radeon_ring_unlock_commit(rdev, ring); 2630 radeon_ring_unlock_commit(rdev, ring);
2631 2631
@@ -2645,6 +2645,9 @@ int r600_uvd_init(struct radeon_device *rdev)
2645{ 2645{
2646 int i, j, r; 2646 int i, j, r;
2647 2647
2648 /* raise clocks while booting up the VCPU */
2649 radeon_set_uvd_clocks(rdev, 53300, 40000);
2650
2648 /* disable clock gating */ 2651 /* disable clock gating */
2649 WREG32(UVD_CGC_GATE, 0); 2652 WREG32(UVD_CGC_GATE, 0);
2650 2653
@@ -2715,19 +2718,24 @@ int r600_uvd_init(struct radeon_device *rdev)
2715 mdelay(10); 2718 mdelay(10);
2716 r = -1; 2719 r = -1;
2717 } 2720 }
2721
2718 if (r) { 2722 if (r) {
2719 DRM_ERROR("UVD not responding, giving up!!!\n"); 2723 DRM_ERROR("UVD not responding, giving up!!!\n");
2724 radeon_set_uvd_clocks(rdev, 0, 0);
2720 return r; 2725 return r;
2721 } 2726 }
2727
2722 /* enable interupt */ 2728 /* enable interupt */
2723 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1)); 2729 WREG32_P(UVD_MASTINT_EN, 3<<1, ~(3 << 1));
2724 2730
2725 r = r600_uvd_rbc_start(rdev); 2731 r = r600_uvd_rbc_start(rdev);
2726 if (r) 2732 if (!r)
2727 return r; 2733 DRM_INFO("UVD initialized successfully.\n");
2728 2734
2729 DRM_INFO("UVD initialized successfully.\n"); 2735 /* lower clocks again */
2730 return 0; 2736 radeon_set_uvd_clocks(rdev, 0, 0);
2737
2738 return r;
2731} 2739}
2732 2740
2733/* 2741/*
@@ -3566,28 +3574,36 @@ int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3566 3574
3567int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring) 3575int r600_uvd_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3568{ 3576{
3569 struct radeon_fence *fence; 3577 struct radeon_fence *fence = NULL;
3570 int r; 3578 int r;
3571 3579
3580 r = radeon_set_uvd_clocks(rdev, 53300, 40000);
3581 if (r) {
3582 DRM_ERROR("radeon: failed to raise UVD clocks (%d).\n", r);
3583 return r;
3584 }
3585
3572 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL); 3586 r = radeon_uvd_get_create_msg(rdev, ring->idx, 1, NULL);
3573 if (r) { 3587 if (r) {
3574 DRM_ERROR("radeon: failed to get create msg (%d).\n", r); 3588 DRM_ERROR("radeon: failed to get create msg (%d).\n", r);
3575 return r; 3589 goto error;
3576 } 3590 }
3577 3591
3578 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence); 3592 r = radeon_uvd_get_destroy_msg(rdev, ring->idx, 1, &fence);
3579 if (r) { 3593 if (r) {
3580 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r); 3594 DRM_ERROR("radeon: failed to get destroy ib (%d).\n", r);
3581 return r; 3595 goto error;
3582 } 3596 }
3583 3597
3584 r = radeon_fence_wait(fence, false); 3598 r = radeon_fence_wait(fence, false);
3585 if (r) { 3599 if (r) {
3586 DRM_ERROR("radeon: fence wait failed (%d).\n", r); 3600 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3587 return r; 3601 goto error;
3588 } 3602 }
3589 DRM_INFO("ib test on ring %d succeeded\n", ring->idx); 3603 DRM_INFO("ib test on ring %d succeeded\n", ring->idx);
3604error:
3590 radeon_fence_unref(&fence); 3605 radeon_fence_unref(&fence);
3606 radeon_set_uvd_clocks(rdev, 0, 0);
3591 return r; 3607 return r;
3592} 3608}
3593 3609
diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c
index cb03fe22b0ab..c92eb86a8e55 100644
--- a/drivers/gpu/drm/radeon/r600_audio.c
+++ b/drivers/gpu/drm/radeon/r600_audio.c
@@ -57,10 +57,7 @@ static bool radeon_dig_encoder(struct drm_encoder *encoder)
57 */ 57 */
58static int r600_audio_chipset_supported(struct radeon_device *rdev) 58static int r600_audio_chipset_supported(struct radeon_device *rdev)
59{ 59{
60 return (rdev->family >= CHIP_R600 && !ASIC_IS_DCE6(rdev)) 60 return ASIC_IS_DCE2(rdev) && !ASIC_IS_DCE6(rdev);
61 || rdev->family == CHIP_RS600
62 || rdev->family == CHIP_RS690
63 || rdev->family == CHIP_RS740;
64} 61}
65 62
66struct r600_audio r600_audio_status(struct radeon_device *rdev) 63struct r600_audio r600_audio_status(struct radeon_device *rdev)
@@ -184,65 +181,6 @@ int r600_audio_init(struct radeon_device *rdev)
184} 181}
185 182
186/* 183/*
187 * atach the audio codec to the clock source of the encoder
188 */
189void r600_audio_set_clock(struct drm_encoder *encoder, int clock)
190{
191 struct drm_device *dev = encoder->dev;
192 struct radeon_device *rdev = dev->dev_private;
193 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
194 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
195 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
196 int base_rate = 48000;
197
198 switch (radeon_encoder->encoder_id) {
199 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
200 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
201 WREG32_P(R600_AUDIO_TIMING, 0, ~0x301);
202 break;
203 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
204 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
205 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
206 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
207 WREG32_P(R600_AUDIO_TIMING, 0x100, ~0x301);
208 break;
209 default:
210 dev_err(rdev->dev, "Unsupported encoder type 0x%02X\n",
211 radeon_encoder->encoder_id);
212 return;
213 }
214
215 if (ASIC_IS_DCE4(rdev)) {
216 /* TODO: other PLLs? */
217 WREG32(EVERGREEN_AUDIO_PLL1_MUL, base_rate * 10);
218 WREG32(EVERGREEN_AUDIO_PLL1_DIV, clock * 10);
219 WREG32(EVERGREEN_AUDIO_PLL1_UNK, 0x00000071);
220
221 /* Select DTO source */
222 WREG32(0x5ac, radeon_crtc->crtc_id);
223 } else {
224 switch (dig->dig_encoder) {
225 case 0:
226 WREG32(R600_AUDIO_PLL1_MUL, base_rate * 50);
227 WREG32(R600_AUDIO_PLL1_DIV, clock * 100);
228 WREG32(R600_AUDIO_CLK_SRCSEL, 0);
229 break;
230
231 case 1:
232 WREG32(R600_AUDIO_PLL2_MUL, base_rate * 50);
233 WREG32(R600_AUDIO_PLL2_DIV, clock * 100);
234 WREG32(R600_AUDIO_CLK_SRCSEL, 1);
235 break;
236 default:
237 dev_err(rdev->dev,
238 "Unsupported DIG on encoder 0x%02X\n",
239 radeon_encoder->encoder_id);
240 return;
241 }
242 }
243}
244
245/*
246 * release the audio timer 184 * release the audio timer
247 * TODO: How to do this correctly on SMP systems? 185 * TODO: How to do this correctly on SMP systems?
248 */ 186 */
diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c
index 21ecc0e12dc4..47f180a79352 100644
--- a/drivers/gpu/drm/radeon/r600_hdmi.c
+++ b/drivers/gpu/drm/radeon/r600_hdmi.c
@@ -226,6 +226,39 @@ static void r600_hdmi_audio_workaround(struct drm_encoder *encoder)
226 value, ~HDMI0_AUDIO_TEST_EN); 226 value, ~HDMI0_AUDIO_TEST_EN);
227} 227}
228 228
229void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock)
230{
231 struct drm_device *dev = encoder->dev;
232 struct radeon_device *rdev = dev->dev_private;
233 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
234 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
235 u32 base_rate = 48000;
236
237 if (!dig || !dig->afmt)
238 return;
239
240 /* there are two DTOs selected by DCCG_AUDIO_DTO_SELECT.
241 * doesn't matter which one you use. Just use the first one.
242 */
243 /* XXX: properly calculate this */
244 /* XXX two dtos; generally use dto0 for hdmi */
245 /* Express [24MHz / target pixel clock] as an exact rational
246 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
247 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
248 */
249 if (ASIC_IS_DCE3(rdev)) {
250 /* according to the reg specs, this should DCE3.2 only, but in
251 * practice it seems to cover DCE3.0 as well.
252 */
253 WREG32(DCCG_AUDIO_DTO0_PHASE, base_rate * 50);
254 WREG32(DCCG_AUDIO_DTO0_MODULE, clock * 100);
255 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */
256 } else {
257 /* according to the reg specs, this should be DCE2.0 and DCE3.0 */
258 WREG32(AUDIO_DTO, AUDIO_DTO_PHASE(base_rate * 50) |
259 AUDIO_DTO_MODULE(clock * 100));
260 }
261}
229 262
230/* 263/*
231 * update the info frames with the data from the current display mode 264 * update the info frames with the data from the current display mode
@@ -246,7 +279,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
246 return; 279 return;
247 offset = dig->afmt->offset; 280 offset = dig->afmt->offset;
248 281
249 r600_audio_set_clock(encoder, mode->clock); 282 r600_audio_set_dto(encoder, mode->clock);
250 283
251 WREG32(HDMI0_VBI_PACKET_CONTROL + offset, 284 WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
252 HDMI0_NULL_SEND); /* send null packets when required */ 285 HDMI0_NULL_SEND); /* send null packets when required */
@@ -415,114 +448,73 @@ void r600_hdmi_update_audio_settings(struct drm_encoder *encoder)
415/* 448/*
416 * enable the HDMI engine 449 * enable the HDMI engine
417 */ 450 */
418void r600_hdmi_enable(struct drm_encoder *encoder) 451void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
419{ 452{
420 struct drm_device *dev = encoder->dev; 453 struct drm_device *dev = encoder->dev;
421 struct radeon_device *rdev = dev->dev_private; 454 struct radeon_device *rdev = dev->dev_private;
422 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 455 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
423 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 456 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
424 uint32_t offset; 457 u32 hdmi = HDMI0_ERROR_ACK;
425 u32 hdmi;
426
427 if (ASIC_IS_DCE6(rdev))
428 return;
429 458
430 /* Silent, r600_hdmi_enable will raise WARN for us */ 459 /* Silent, r600_hdmi_enable will raise WARN for us */
431 if (dig->afmt->enabled) 460 if (enable && dig->afmt->enabled)
461 return;
462 if (!enable && !dig->afmt->enabled)
432 return; 463 return;
433 offset = dig->afmt->offset;
434 464
435 /* Older chipsets require setting HDMI and routing manually */ 465 /* Older chipsets require setting HDMI and routing manually */
436 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) { 466 if (!ASIC_IS_DCE3(rdev)) {
437 hdmi = HDMI0_ERROR_ACK | HDMI0_ENABLE; 467 if (enable)
468 hdmi |= HDMI0_ENABLE;
438 switch (radeon_encoder->encoder_id) { 469 switch (radeon_encoder->encoder_id) {
439 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1: 470 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
440 WREG32_P(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN, 471 if (enable) {
441 ~AVIVO_TMDSA_CNTL_HDMI_EN); 472 WREG32_OR(AVIVO_TMDSA_CNTL, AVIVO_TMDSA_CNTL_HDMI_EN);
442 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA); 473 hdmi |= HDMI0_STREAM(HDMI0_STREAM_TMDSA);
474 } else {
475 WREG32_AND(AVIVO_TMDSA_CNTL, ~AVIVO_TMDSA_CNTL_HDMI_EN);
476 }
443 break; 477 break;
444 case ENCODER_OBJECT_ID_INTERNAL_LVTM1: 478 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
445 WREG32_P(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN, 479 if (enable) {
446 ~AVIVO_LVTMA_CNTL_HDMI_EN); 480 WREG32_OR(AVIVO_LVTMA_CNTL, AVIVO_LVTMA_CNTL_HDMI_EN);
447 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA); 481 hdmi |= HDMI0_STREAM(HDMI0_STREAM_LVTMA);
482 } else {
483 WREG32_AND(AVIVO_LVTMA_CNTL, ~AVIVO_LVTMA_CNTL_HDMI_EN);
484 }
448 break; 485 break;
449 case ENCODER_OBJECT_ID_INTERNAL_DDI: 486 case ENCODER_OBJECT_ID_INTERNAL_DDI:
450 WREG32_P(DDIA_CNTL, DDIA_HDMI_EN, ~DDIA_HDMI_EN); 487 if (enable) {
451 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA); 488 WREG32_OR(DDIA_CNTL, DDIA_HDMI_EN);
489 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DDIA);
490 } else {
491 WREG32_AND(DDIA_CNTL, ~DDIA_HDMI_EN);
492 }
452 break; 493 break;
453 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1: 494 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
454 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA); 495 if (enable)
496 hdmi |= HDMI0_STREAM(HDMI0_STREAM_DVOA);
455 break; 497 break;
456 default: 498 default:
457 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n", 499 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
458 radeon_encoder->encoder_id); 500 radeon_encoder->encoder_id);
459 break; 501 break;
460 } 502 }
461 WREG32(HDMI0_CONTROL + offset, hdmi); 503 WREG32(HDMI0_CONTROL + dig->afmt->offset, hdmi);
462 } 504 }
463 505
464 if (rdev->irq.installed) { 506 if (rdev->irq.installed) {
465 /* if irq is available use it */ 507 /* if irq is available use it */
466 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id); 508 /* XXX: shouldn't need this on any asics. Double check DCE2/3 */
509 if (enable)
510 radeon_irq_kms_enable_afmt(rdev, dig->afmt->id);
511 else
512 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
467 } 513 }
468 514
469 dig->afmt->enabled = true; 515 dig->afmt->enabled = enable;
470 516
471 DRM_DEBUG("Enabling HDMI interface @ 0x%04X for encoder 0x%x\n", 517 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
472 offset, radeon_encoder->encoder_id); 518 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
473} 519}
474 520
475/*
476 * disable the HDMI engine
477 */
478void r600_hdmi_disable(struct drm_encoder *encoder)
479{
480 struct drm_device *dev = encoder->dev;
481 struct radeon_device *rdev = dev->dev_private;
482 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
483 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
484 uint32_t offset;
485
486 if (ASIC_IS_DCE6(rdev))
487 return;
488
489 /* Called for ATOM_ENCODER_MODE_HDMI only */
490 if (!dig || !dig->afmt) {
491 return;
492 }
493 if (!dig->afmt->enabled)
494 return;
495 offset = dig->afmt->offset;
496
497 DRM_DEBUG("Disabling HDMI interface @ 0x%04X for encoder 0x%x\n",
498 offset, radeon_encoder->encoder_id);
499
500 /* disable irq */
501 radeon_irq_kms_disable_afmt(rdev, dig->afmt->id);
502
503 /* Older chipsets not handled by AtomBIOS */
504 if (rdev->family >= CHIP_R600 && !ASIC_IS_DCE3(rdev)) {
505 switch (radeon_encoder->encoder_id) {
506 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
507 WREG32_P(AVIVO_TMDSA_CNTL, 0,
508 ~AVIVO_TMDSA_CNTL_HDMI_EN);
509 break;
510 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
511 WREG32_P(AVIVO_LVTMA_CNTL, 0,
512 ~AVIVO_LVTMA_CNTL_HDMI_EN);
513 break;
514 case ENCODER_OBJECT_ID_INTERNAL_DDI:
515 WREG32_P(DDIA_CNTL, 0, ~DDIA_HDMI_EN);
516 break;
517 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
518 break;
519 default:
520 dev_err(rdev->dev, "Invalid encoder for HDMI: 0x%X\n",
521 radeon_encoder->encoder_id);
522 break;
523 }
524 WREG32(HDMI0_CONTROL + offset, HDMI0_ERROR_ACK);
525 }
526
527 dig->afmt->enabled = false;
528}
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index 441bdb809a0b..6105b25b18c3 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -910,7 +910,12 @@
910# define TARGET_LINK_SPEED_MASK (0xf << 0) 910# define TARGET_LINK_SPEED_MASK (0xf << 0)
911# define SELECTABLE_DEEMPHASIS (1 << 6) 911# define SELECTABLE_DEEMPHASIS (1 << 6)
912 912
913/* Audio clocks */ 913/* Audio clocks DCE 2.0/3.0 */
914#define AUDIO_DTO 0x7340
915# define AUDIO_DTO_PHASE(x) (((x) & 0xffff) << 0)
916# define AUDIO_DTO_MODULE(x) (((x) & 0xffff) << 16)
917
918/* Audio clocks DCE 3.2 */
914#define DCCG_AUDIO_DTO0_PHASE 0x0514 919#define DCCG_AUDIO_DTO0_PHASE 0x0514
915#define DCCG_AUDIO_DTO0_MODULE 0x0518 920#define DCCG_AUDIO_DTO0_MODULE 0x0518
916#define DCCG_AUDIO_DTO0_LOAD 0x051c 921#define DCCG_AUDIO_DTO0_LOAD 0x051c
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 18904fb83d3a..d6c8cbaa8693 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -1143,6 +1143,7 @@ struct radeon_uvd {
1143 uint64_t gpu_addr; 1143 uint64_t gpu_addr;
1144 atomic_t handles[RADEON_MAX_UVD_HANDLES]; 1144 atomic_t handles[RADEON_MAX_UVD_HANDLES];
1145 struct drm_file *filp[RADEON_MAX_UVD_HANDLES]; 1145 struct drm_file *filp[RADEON_MAX_UVD_HANDLES];
1146 struct delayed_work idle_work;
1146}; 1147};
1147 1148
1148int radeon_uvd_init(struct radeon_device *rdev); 1149int radeon_uvd_init(struct radeon_device *rdev);
@@ -1157,6 +1158,7 @@ void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo);
1157void radeon_uvd_free_handles(struct radeon_device *rdev, 1158void radeon_uvd_free_handles(struct radeon_device *rdev,
1158 struct drm_file *filp); 1159 struct drm_file *filp);
1159int radeon_uvd_cs_parse(struct radeon_cs_parser *parser); 1160int radeon_uvd_cs_parse(struct radeon_cs_parser *parser);
1161void radeon_uvd_note_usage(struct radeon_device *rdev);
1160 1162
1161struct r600_audio { 1163struct r600_audio {
1162 int channels; 1164 int channels;
@@ -1268,6 +1270,9 @@ struct radeon_asic {
1268 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); 1270 void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level);
1269 /* get backlight level */ 1271 /* get backlight level */
1270 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); 1272 u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder);
1273 /* audio callbacks */
1274 void (*hdmi_enable)(struct drm_encoder *encoder, bool enable);
1275 void (*hdmi_setmode)(struct drm_encoder *encoder, struct drm_display_mode *mode);
1271 } display; 1276 } display;
1272 /* copy functions for bo handling */ 1277 /* copy functions for bo handling */
1273 struct { 1278 struct {
@@ -1741,6 +1746,8 @@ void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1741 tmp_ |= ((val) & ~(mask)); \ 1746 tmp_ |= ((val) & ~(mask)); \
1742 WREG32(reg, tmp_); \ 1747 WREG32(reg, tmp_); \
1743 } while (0) 1748 } while (0)
1749#define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1750#define WREG32_OR(reg, or) WREG32_P(reg, or, ~or)
1744#define WREG32_PLL_P(reg, val, mask) \ 1751#define WREG32_PLL_P(reg, val, mask) \
1745 do { \ 1752 do { \
1746 uint32_t tmp_ = RREG32_PLL(reg); \ 1753 uint32_t tmp_ = RREG32_PLL(reg); \
@@ -1874,6 +1881,8 @@ void radeon_ring_write(struct radeon_ring *ring, uint32_t v);
1874#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) 1881#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc))
1875#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) 1882#define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l))
1876#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) 1883#define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e))
1884#define radeon_hdmi_enable(rdev, e, b) (rdev)->asic->display.hdmi_enable((e), (b))
1885#define radeon_hdmi_setmode(rdev, e, m) (rdev)->asic->display.hdmi_setmode((e), (m))
1877#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) 1886#define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence))
1878#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) 1887#define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait))
1879#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) 1888#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f))
@@ -1937,6 +1946,9 @@ extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc
1937extern int radeon_resume_kms(struct drm_device *dev); 1946extern int radeon_resume_kms(struct drm_device *dev);
1938extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); 1947extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1939extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); 1948extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1949extern void radeon_program_register_sequence(struct radeon_device *rdev,
1950 const u32 *registers,
1951 const u32 array_size);
1940 1952
1941/* 1953/*
1942 * vm 1954 * vm
@@ -2009,9 +2021,6 @@ struct radeon_hdmi_acr {
2009 2021
2010extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); 2022extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock);
2011 2023
2012extern void r600_hdmi_enable(struct drm_encoder *encoder);
2013extern void r600_hdmi_disable(struct drm_encoder *encoder);
2014extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
2015extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, 2024extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2016 u32 tiling_pipe_num, 2025 u32 tiling_pipe_num,
2017 u32 max_rb_num, 2026 u32 max_rb_num,
@@ -2022,8 +2031,6 @@ extern u32 r6xx_remap_render_backend(struct radeon_device *rdev,
2022 * evergreen functions used by radeon_encoder.c 2031 * evergreen functions used by radeon_encoder.c
2023 */ 2032 */
2024 2033
2025extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
2026
2027extern int ni_init_microcode(struct radeon_device *rdev); 2034extern int ni_init_microcode(struct radeon_device *rdev);
2028extern int ni_mc_load_microcode(struct radeon_device *rdev); 2035extern int ni_mc_load_microcode(struct radeon_device *rdev);
2029 2036
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 48d020057100..6417132c50cf 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -656,6 +656,8 @@ static struct radeon_asic rs600_asic = {
656 .wait_for_vblank = &avivo_wait_for_vblank, 656 .wait_for_vblank = &avivo_wait_for_vblank,
657 .set_backlight_level = &atombios_set_backlight_level, 657 .set_backlight_level = &atombios_set_backlight_level,
658 .get_backlight_level = &atombios_get_backlight_level, 658 .get_backlight_level = &atombios_get_backlight_level,
659 .hdmi_enable = &r600_hdmi_enable,
660 .hdmi_setmode = &r600_hdmi_setmode,
659 }, 661 },
660 .copy = { 662 .copy = {
661 .blit = &r100_copy_blit, 663 .blit = &r100_copy_blit,
@@ -732,6 +734,8 @@ static struct radeon_asic rs690_asic = {
732 .wait_for_vblank = &avivo_wait_for_vblank, 734 .wait_for_vblank = &avivo_wait_for_vblank,
733 .set_backlight_level = &atombios_set_backlight_level, 735 .set_backlight_level = &atombios_set_backlight_level,
734 .get_backlight_level = &atombios_get_backlight_level, 736 .get_backlight_level = &atombios_get_backlight_level,
737 .hdmi_enable = &r600_hdmi_enable,
738 .hdmi_setmode = &r600_hdmi_setmode,
735 }, 739 },
736 .copy = { 740 .copy = {
737 .blit = &r100_copy_blit, 741 .blit = &r100_copy_blit,
@@ -970,6 +974,8 @@ static struct radeon_asic r600_asic = {
970 .wait_for_vblank = &avivo_wait_for_vblank, 974 .wait_for_vblank = &avivo_wait_for_vblank,
971 .set_backlight_level = &atombios_set_backlight_level, 975 .set_backlight_level = &atombios_set_backlight_level,
972 .get_backlight_level = &atombios_get_backlight_level, 976 .get_backlight_level = &atombios_get_backlight_level,
977 .hdmi_enable = &r600_hdmi_enable,
978 .hdmi_setmode = &r600_hdmi_setmode,
973 }, 979 },
974 .copy = { 980 .copy = {
975 .blit = &r600_copy_blit, 981 .blit = &r600_copy_blit,
@@ -1056,6 +1062,8 @@ static struct radeon_asic rs780_asic = {
1056 .wait_for_vblank = &avivo_wait_for_vblank, 1062 .wait_for_vblank = &avivo_wait_for_vblank,
1057 .set_backlight_level = &atombios_set_backlight_level, 1063 .set_backlight_level = &atombios_set_backlight_level,
1058 .get_backlight_level = &atombios_get_backlight_level, 1064 .get_backlight_level = &atombios_get_backlight_level,
1065 .hdmi_enable = &r600_hdmi_enable,
1066 .hdmi_setmode = &r600_hdmi_setmode,
1059 }, 1067 },
1060 .copy = { 1068 .copy = {
1061 .blit = &r600_copy_blit, 1069 .blit = &r600_copy_blit,
@@ -1151,6 +1159,8 @@ static struct radeon_asic rv770_asic = {
1151 .wait_for_vblank = &avivo_wait_for_vblank, 1159 .wait_for_vblank = &avivo_wait_for_vblank,
1152 .set_backlight_level = &atombios_set_backlight_level, 1160 .set_backlight_level = &atombios_set_backlight_level,
1153 .get_backlight_level = &atombios_get_backlight_level, 1161 .get_backlight_level = &atombios_get_backlight_level,
1162 .hdmi_enable = &r600_hdmi_enable,
1163 .hdmi_setmode = &r600_hdmi_setmode,
1154 }, 1164 },
1155 .copy = { 1165 .copy = {
1156 .blit = &r600_copy_blit, 1166 .blit = &r600_copy_blit,
@@ -1247,6 +1257,8 @@ static struct radeon_asic evergreen_asic = {
1247 .wait_for_vblank = &dce4_wait_for_vblank, 1257 .wait_for_vblank = &dce4_wait_for_vblank,
1248 .set_backlight_level = &atombios_set_backlight_level, 1258 .set_backlight_level = &atombios_set_backlight_level,
1249 .get_backlight_level = &atombios_get_backlight_level, 1259 .get_backlight_level = &atombios_get_backlight_level,
1260 .hdmi_enable = &evergreen_hdmi_enable,
1261 .hdmi_setmode = &evergreen_hdmi_setmode,
1250 }, 1262 },
1251 .copy = { 1263 .copy = {
1252 .blit = &r600_copy_blit, 1264 .blit = &r600_copy_blit,
@@ -1343,6 +1355,8 @@ static struct radeon_asic sumo_asic = {
1343 .wait_for_vblank = &dce4_wait_for_vblank, 1355 .wait_for_vblank = &dce4_wait_for_vblank,
1344 .set_backlight_level = &atombios_set_backlight_level, 1356 .set_backlight_level = &atombios_set_backlight_level,
1345 .get_backlight_level = &atombios_get_backlight_level, 1357 .get_backlight_level = &atombios_get_backlight_level,
1358 .hdmi_enable = &evergreen_hdmi_enable,
1359 .hdmi_setmode = &evergreen_hdmi_setmode,
1346 }, 1360 },
1347 .copy = { 1361 .copy = {
1348 .blit = &r600_copy_blit, 1362 .blit = &r600_copy_blit,
@@ -1439,6 +1453,8 @@ static struct radeon_asic btc_asic = {
1439 .wait_for_vblank = &dce4_wait_for_vblank, 1453 .wait_for_vblank = &dce4_wait_for_vblank,
1440 .set_backlight_level = &atombios_set_backlight_level, 1454 .set_backlight_level = &atombios_set_backlight_level,
1441 .get_backlight_level = &atombios_get_backlight_level, 1455 .get_backlight_level = &atombios_get_backlight_level,
1456 .hdmi_enable = &evergreen_hdmi_enable,
1457 .hdmi_setmode = &evergreen_hdmi_setmode,
1442 }, 1458 },
1443 .copy = { 1459 .copy = {
1444 .blit = &r600_copy_blit, 1460 .blit = &r600_copy_blit,
@@ -1578,6 +1594,8 @@ static struct radeon_asic cayman_asic = {
1578 .wait_for_vblank = &dce4_wait_for_vblank, 1594 .wait_for_vblank = &dce4_wait_for_vblank,
1579 .set_backlight_level = &atombios_set_backlight_level, 1595 .set_backlight_level = &atombios_set_backlight_level,
1580 .get_backlight_level = &atombios_get_backlight_level, 1596 .get_backlight_level = &atombios_get_backlight_level,
1597 .hdmi_enable = &evergreen_hdmi_enable,
1598 .hdmi_setmode = &evergreen_hdmi_setmode,
1581 }, 1599 },
1582 .copy = { 1600 .copy = {
1583 .blit = &r600_copy_blit, 1601 .blit = &r600_copy_blit,
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 2add5268d280..2c87365d345f 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -374,11 +374,12 @@ void r600_disable_interrupts(struct radeon_device *rdev);
374void r600_rlc_stop(struct radeon_device *rdev); 374void r600_rlc_stop(struct radeon_device *rdev);
375/* r600 audio */ 375/* r600 audio */
376int r600_audio_init(struct radeon_device *rdev); 376int r600_audio_init(struct radeon_device *rdev);
377void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
378struct r600_audio r600_audio_status(struct radeon_device *rdev); 377struct r600_audio r600_audio_status(struct radeon_device *rdev);
379void r600_audio_fini(struct radeon_device *rdev); 378void r600_audio_fini(struct radeon_device *rdev);
380int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder); 379int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
381void r600_hdmi_update_audio_settings(struct drm_encoder *encoder); 380void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
381void r600_hdmi_enable(struct drm_encoder *encoder, bool enable);
382void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
382/* r600 blit */ 383/* r600 blit */
383int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages, 384int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
384 struct radeon_fence **fence, struct radeon_sa_bo **vb, 385 struct radeon_fence **fence, struct radeon_sa_bo **vb,
@@ -477,6 +478,8 @@ int evergreen_copy_dma(struct radeon_device *rdev,
477 uint64_t src_offset, uint64_t dst_offset, 478 uint64_t src_offset, uint64_t dst_offset,
478 unsigned num_gpu_pages, 479 unsigned num_gpu_pages,
479 struct radeon_fence **fence); 480 struct radeon_fence **fence);
481void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable);
482void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
480 483
481/* 484/*
482 * cayman 485 * cayman
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 8c1779cba1f3..0dd87c0e0fac 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -2710,8 +2710,7 @@ int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2710 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; 2710 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2711 } else { 2711 } else {
2712 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 2712 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2713 args.v3.ulClock.ulComputeClockFlag = clock_type; 2713 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2714 args.v3.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2715 2714
2716 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); 2715 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2717 2716
@@ -2726,8 +2725,7 @@ int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2726 dividers->vco_mode = (args.v3.ucCntlFlag & 2725 dividers->vco_mode = (args.v3.ucCntlFlag &
2727 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 2726 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2728 } else { 2727 } else {
2729 args.v5.ulClock.ulComputeClockFlag = clock_type; 2728 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2730 args.v5.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2731 if (strobe_mode) 2729 if (strobe_mode)
2732 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 2730 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2733 2731
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index c7407074c09b..7e265a58141f 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -549,6 +549,10 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
549 r = radeon_cs_handle_lockup(rdev, r); 549 r = radeon_cs_handle_lockup(rdev, r);
550 return r; 550 return r;
551 } 551 }
552
553 if (parser.ring == R600_RING_TYPE_UVD_INDEX)
554 radeon_uvd_note_usage(rdev);
555
552 r = radeon_cs_ib_chunk(rdev, &parser); 556 r = radeon_cs_ib_chunk(rdev, &parser);
553 if (r) { 557 if (r) {
554 goto out; 558 goto out;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 62d0ba338582..237b7a7549e6 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -98,6 +98,42 @@ static const char radeon_family_name[][16] = {
98}; 98};
99 99
100/** 100/**
101 * radeon_program_register_sequence - program an array of registers.
102 *
103 * @rdev: radeon_device pointer
104 * @registers: pointer to the register array
105 * @array_size: size of the register array
106 *
107 * Programs an array or registers with and and or masks.
108 * This is a helper for setting golden registers.
109 */
110void radeon_program_register_sequence(struct radeon_device *rdev,
111 const u32 *registers,
112 const u32 array_size)
113{
114 u32 tmp, reg, and_mask, or_mask;
115 int i;
116
117 if (array_size % 3)
118 return;
119
120 for (i = 0; i < array_size; i +=3) {
121 reg = registers[i + 0];
122 and_mask = registers[i + 1];
123 or_mask = registers[i + 2];
124
125 if (and_mask == 0xffffffff) {
126 tmp = or_mask;
127 } else {
128 tmp = RREG32(reg);
129 tmp &= ~and_mask;
130 tmp |= or_mask;
131 }
132 WREG32(reg, tmp);
133 }
134}
135
136/**
101 * radeon_surface_init - Clear GPU surface registers. 137 * radeon_surface_init - Clear GPU surface registers.
102 * 138 *
103 * @rdev: radeon_device pointer 139 * @rdev: radeon_device pointer
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 82fe1835ff8c..1a699cefaac7 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -776,10 +776,9 @@ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
776 776
777 } else { 777 } else {
778 /* put fence directly behind firmware */ 778 /* put fence directly behind firmware */
779 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + 779 index = ALIGN(rdev->uvd_fw->size, 8);
780 rdev->uvd_fw->size; 780 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
781 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + 781 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
782 rdev->uvd_fw->size;
783 } 782 }
784 783
785 } else { 784 } else {
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c
index 30a94609672a..0312a7f4d768 100644
--- a/drivers/gpu/drm/radeon/radeon_uvd.c
+++ b/drivers/gpu/drm/radeon/radeon_uvd.c
@@ -36,6 +36,9 @@
36#include "radeon.h" 36#include "radeon.h"
37#include "r600d.h" 37#include "r600d.h"
38 38
39/* 1 second timeout */
40#define UVD_IDLE_TIMEOUT_MS 1000
41
39/* Firmware Names */ 42/* Firmware Names */
40#define FIRMWARE_RV710 "radeon/RV710_uvd.bin" 43#define FIRMWARE_RV710 "radeon/RV710_uvd.bin"
41#define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin" 44#define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin"
@@ -47,6 +50,8 @@ MODULE_FIRMWARE(FIRMWARE_CYPRESS);
47MODULE_FIRMWARE(FIRMWARE_SUMO); 50MODULE_FIRMWARE(FIRMWARE_SUMO);
48MODULE_FIRMWARE(FIRMWARE_TAHITI); 51MODULE_FIRMWARE(FIRMWARE_TAHITI);
49 52
53static void radeon_uvd_idle_work_handler(struct work_struct *work);
54
50int radeon_uvd_init(struct radeon_device *rdev) 55int radeon_uvd_init(struct radeon_device *rdev)
51{ 56{
52 struct platform_device *pdev; 57 struct platform_device *pdev;
@@ -54,6 +59,8 @@ int radeon_uvd_init(struct radeon_device *rdev)
54 const char *fw_name; 59 const char *fw_name;
55 int i, r; 60 int i, r;
56 61
62 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler);
63
57 pdev = platform_device_register_simple("radeon_uvd", 0, NULL, 0); 64 pdev = platform_device_register_simple("radeon_uvd", 0, NULL, 0);
58 r = IS_ERR(pdev); 65 r = IS_ERR(pdev);
59 if (r) { 66 if (r) {
@@ -107,7 +114,7 @@ int radeon_uvd_init(struct radeon_device *rdev)
107 114
108 platform_device_unregister(pdev); 115 platform_device_unregister(pdev);
109 116
110 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) + 117 bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) +
111 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE; 118 RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE;
112 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true, 119 r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true,
113 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo); 120 RADEON_GEM_DOMAIN_VRAM, NULL, &rdev->uvd.vcpu_bo);
@@ -188,8 +195,6 @@ int radeon_uvd_resume(struct radeon_device *rdev)
188 195
189 radeon_bo_unreserve(rdev->uvd.vcpu_bo); 196 radeon_bo_unreserve(rdev->uvd.vcpu_bo);
190 197
191 radeon_set_uvd_clocks(rdev, 53300, 40000);
192
193 return 0; 198 return 0;
194} 199}
195 200
@@ -415,24 +420,26 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
415 return -EINVAL; 420 return -EINVAL;
416 } 421 }
417 422
418 if (cmd == 0) { 423 if ((start >> 28) != (end >> 28)) {
419 if (end & 0xFFFFFFFFF0000000) { 424 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n",
420 DRM_ERROR("msg buffer %LX-%LX out of 256MB segment!\n", 425 start, end);
421 start, end); 426 return -EINVAL;
422 return -EINVAL;
423 }
424
425 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
426 if (r)
427 return r;
428 } 427 }
429 428
430 if ((start & 0xFFFFFFFFF0000000) != (end & 0xFFFFFFFFF0000000)) { 429 /* TODO: is this still necessary on NI+ ? */
431 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 430 if ((cmd == 0 || cmd == 0x3) &&
431 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
432 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
432 start, end); 433 start, end);
433 return -EINVAL; 434 return -EINVAL;
434 } 435 }
435 436
437 if (cmd == 0) {
438 r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes);
439 if (r)
440 return r;
441 }
442
436 return 0; 443 return 0;
437} 444}
438 445
@@ -664,3 +671,24 @@ int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring,
664 671
665 return radeon_uvd_send_msg(rdev, ring, bo, fence); 672 return radeon_uvd_send_msg(rdev, ring, bo, fence);
666} 673}
674
675static void radeon_uvd_idle_work_handler(struct work_struct *work)
676{
677 struct radeon_device *rdev =
678 container_of(work, struct radeon_device, uvd.idle_work.work);
679
680 if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0)
681 radeon_set_uvd_clocks(rdev, 0, 0);
682 else
683 schedule_delayed_work(&rdev->uvd.idle_work,
684 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
685}
686
687void radeon_uvd_note_usage(struct radeon_device *rdev)
688{
689 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work);
690 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work,
691 msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS));
692 if (set_clocks)
693 radeon_set_uvd_clocks(rdev, 53300, 40000);
694}
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 5a0fc74c2ba6..46fa1b07c560 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -52,23 +52,59 @@ static const u32 crtc_offsets[2] =
52 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL 52 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
53}; 53};
54 54
55static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)
56{
57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)
58 return true;
59 else
60 return false;
61}
62
63static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)
64{
65 u32 pos1, pos2;
66
67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);
69
70 if (pos1 != pos2)
71 return true;
72 else
73 return false;
74}
75
76/**
77 * avivo_wait_for_vblank - vblank wait asic callback.
78 *
79 * @rdev: radeon_device pointer
80 * @crtc: crtc to wait for vblank on
81 *
82 * Wait for vblank on the requested crtc (r5xx-r7xx).
83 */
55void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) 84void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)
56{ 85{
57 int i; 86 unsigned i = 0;
58 87
59 if (crtc >= rdev->num_crtc) 88 if (crtc >= rdev->num_crtc)
60 return; 89 return;
61 90
62 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN) { 91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))
63 for (i = 0; i < rdev->usec_timeout; i++) { 92 return;
64 if (!(RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)) 93
94 /* depending on when we hit vblank, we may be close to active; if so,
95 * wait for another frame.
96 */
97 while (avivo_is_in_vblank(rdev, crtc)) {
98 if (i++ % 100 == 0) {
99 if (!avivo_is_counter_moving(rdev, crtc))
65 break; 100 break;
66 udelay(1);
67 } 101 }
68 for (i = 0; i < rdev->usec_timeout; i++) { 102 }
69 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) 103
104 while (!avivo_is_in_vblank(rdev, crtc)) {
105 if (i++ % 100 == 0) {
106 if (!avivo_is_counter_moving(rdev, crtc))
70 break; 107 break;
71 udelay(1);
72 } 108 }
73 } 109 }
74} 110}
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 5e1ba16c7a77..ffcba730c57c 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -303,8 +303,10 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
303 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); 303 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
304 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) { 304 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
305 radeon_wait_for_vblank(rdev, i); 305 radeon_wait_for_vblank(rdev, i);
306 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
306 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE; 307 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
307 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); 308 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
309 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
308 } 310 }
309 /* wait for the next frame */ 311 /* wait for the next frame */
310 frame_count = radeon_get_vblank_counter(rdev, i); 312 frame_count = radeon_get_vblank_counter(rdev, i);
@@ -313,6 +315,15 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
313 break; 315 break;
314 udelay(1); 316 udelay(1);
315 } 317 }
318
319 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
320 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
321 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
322 tmp &= ~AVIVO_CRTC_EN;
323 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
324 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
325 save->crtc_enabled[i] = false;
326 /* ***** */
316 } else { 327 } else {
317 save->crtc_enabled[i] = false; 328 save->crtc_enabled[i] = false;
318 } 329 }
@@ -338,6 +349,22 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
338 } 349 }
339 /* wait for the MC to settle */ 350 /* wait for the MC to settle */
340 udelay(100); 351 udelay(100);
352
353 /* lock double buffered regs */
354 for (i = 0; i < rdev->num_crtc; i++) {
355 if (save->crtc_enabled[i]) {
356 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
357 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
358 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
359 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
360 }
361 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
362 if (!(tmp & 1)) {
363 tmp |= 1;
364 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
365 }
366 }
367 }
341} 368}
342 369
343void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save) 370void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
@@ -367,6 +394,33 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
367 } 394 }
368 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 395 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
369 396
397 /* unlock regs and wait for update */
398 for (i = 0; i < rdev->num_crtc; i++) {
399 if (save->crtc_enabled[i]) {
400 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
401 if ((tmp & 0x3) != 0) {
402 tmp &= ~0x3;
403 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
404 }
405 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
406 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
407 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
408 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
409 }
410 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
411 if (tmp & 1) {
412 tmp &= ~1;
413 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
414 }
415 for (j = 0; j < rdev->usec_timeout; j++) {
416 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
417 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
418 break;
419 udelay(1);
420 }
421 }
422 }
423
370 if (rdev->family >= CHIP_R600) { 424 if (rdev->family >= CHIP_R600) {
371 /* unblackout the MC */ 425 /* unblackout the MC */
372 if (rdev->family >= CHIP_RV770) 426 if (rdev->family >= CHIP_RV770)
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 777f537a32c7..91530d4c11c4 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -100,6 +100,17 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
100 if (rdev->family == CHIP_RV740) 100 if (rdev->family == CHIP_RV740)
101 return evergreen_set_uvd_clocks(rdev, vclk, dclk); 101 return evergreen_set_uvd_clocks(rdev, vclk, dclk);
102 102
103 /* bypass vclk and dclk with bclk */
104 WREG32_P(CG_UPLL_FUNC_CNTL_2,
105 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
106 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
107
108 if (!vclk || !dclk) {
109 /* keep the Bypass mode, put PLL to sleep */
110 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
111 return 0;
112 }
113
103 /* loop through vco from low to high */ 114 /* loop through vco from low to high */
104 vco_min = max(max(vco_min, vclk), dclk); 115 vco_min = max(max(vco_min, vclk), dclk);
105 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 500) { 116 for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 500) {
@@ -139,16 +150,11 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
139 } 150 }
140 } 151 }
141 152
142 /* bypass vclk and dclk with bclk */
143 WREG32_P(CG_UPLL_FUNC_CNTL_2,
144 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
145 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
146
147 /* set UPLL_FB_DIV to 0x50000 */ 153 /* set UPLL_FB_DIV to 0x50000 */
148 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK); 154 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
149 155
150 /* deassert UPLL_RESET */ 156 /* deassert UPLL_RESET and UPLL_SLEEP */
151 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK); 157 WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
152 158
153 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */ 159 /* assert BYPASS EN and FB_DIV[0] <- ??? why? */
154 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK); 160 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
@@ -199,6 +205,653 @@ int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
199 return 0; 205 return 0;
200} 206}
201 207
208static const u32 r7xx_golden_registers[] =
209{
210 0x8d00, 0xffffffff, 0x0e0e0074,
211 0x8d04, 0xffffffff, 0x013a2b34,
212 0x9508, 0xffffffff, 0x00000002,
213 0x8b20, 0xffffffff, 0,
214 0x88c4, 0xffffffff, 0x000000c2,
215 0x28350, 0xffffffff, 0,
216 0x9058, 0xffffffff, 0x0fffc40f,
217 0x240c, 0xffffffff, 0x00000380,
218 0x733c, 0xffffffff, 0x00000002,
219 0x2650, 0x00040000, 0,
220 0x20bc, 0x00040000, 0,
221 0x7300, 0xffffffff, 0x001000f0
222};
223
224static const u32 r7xx_golden_dyn_gpr_registers[] =
225{
226 0x8db0, 0xffffffff, 0x98989898,
227 0x8db4, 0xffffffff, 0x98989898,
228 0x8db8, 0xffffffff, 0x98989898,
229 0x8dbc, 0xffffffff, 0x98989898,
230 0x8dc0, 0xffffffff, 0x98989898,
231 0x8dc4, 0xffffffff, 0x98989898,
232 0x8dc8, 0xffffffff, 0x98989898,
233 0x8dcc, 0xffffffff, 0x98989898,
234 0x88c4, 0xffffffff, 0x00000082
235};
236
237static const u32 rv770_golden_registers[] =
238{
239 0x562c, 0xffffffff, 0,
240 0x3f90, 0xffffffff, 0,
241 0x9148, 0xffffffff, 0,
242 0x3f94, 0xffffffff, 0,
243 0x914c, 0xffffffff, 0,
244 0x9698, 0x18000000, 0x18000000
245};
246
247static const u32 rv770ce_golden_registers[] =
248{
249 0x562c, 0xffffffff, 0,
250 0x3f90, 0xffffffff, 0x00cc0000,
251 0x9148, 0xffffffff, 0x00cc0000,
252 0x3f94, 0xffffffff, 0x00cc0000,
253 0x914c, 0xffffffff, 0x00cc0000,
254 0x9b7c, 0xffffffff, 0x00fa0000,
255 0x3f8c, 0xffffffff, 0x00fa0000,
256 0x9698, 0x18000000, 0x18000000
257};
258
259static const u32 rv770_mgcg_init[] =
260{
261 0x8bcc, 0xffffffff, 0x130300f9,
262 0x5448, 0xffffffff, 0x100,
263 0x55e4, 0xffffffff, 0x100,
264 0x160c, 0xffffffff, 0x100,
265 0x5644, 0xffffffff, 0x100,
266 0xc164, 0xffffffff, 0x100,
267 0x8a18, 0xffffffff, 0x100,
268 0x897c, 0xffffffff, 0x8000100,
269 0x8b28, 0xffffffff, 0x3c000100,
270 0x9144, 0xffffffff, 0x100,
271 0x9a1c, 0xffffffff, 0x10000,
272 0x9a50, 0xffffffff, 0x100,
273 0x9a1c, 0xffffffff, 0x10001,
274 0x9a50, 0xffffffff, 0x100,
275 0x9a1c, 0xffffffff, 0x10002,
276 0x9a50, 0xffffffff, 0x100,
277 0x9a1c, 0xffffffff, 0x10003,
278 0x9a50, 0xffffffff, 0x100,
279 0x9a1c, 0xffffffff, 0x0,
280 0x9870, 0xffffffff, 0x100,
281 0x8d58, 0xffffffff, 0x100,
282 0x9500, 0xffffffff, 0x0,
283 0x9510, 0xffffffff, 0x100,
284 0x9500, 0xffffffff, 0x1,
285 0x9510, 0xffffffff, 0x100,
286 0x9500, 0xffffffff, 0x2,
287 0x9510, 0xffffffff, 0x100,
288 0x9500, 0xffffffff, 0x3,
289 0x9510, 0xffffffff, 0x100,
290 0x9500, 0xffffffff, 0x4,
291 0x9510, 0xffffffff, 0x100,
292 0x9500, 0xffffffff, 0x5,
293 0x9510, 0xffffffff, 0x100,
294 0x9500, 0xffffffff, 0x6,
295 0x9510, 0xffffffff, 0x100,
296 0x9500, 0xffffffff, 0x7,
297 0x9510, 0xffffffff, 0x100,
298 0x9500, 0xffffffff, 0x8,
299 0x9510, 0xffffffff, 0x100,
300 0x9500, 0xffffffff, 0x9,
301 0x9510, 0xffffffff, 0x100,
302 0x9500, 0xffffffff, 0x8000,
303 0x9490, 0xffffffff, 0x0,
304 0x949c, 0xffffffff, 0x100,
305 0x9490, 0xffffffff, 0x1,
306 0x949c, 0xffffffff, 0x100,
307 0x9490, 0xffffffff, 0x2,
308 0x949c, 0xffffffff, 0x100,
309 0x9490, 0xffffffff, 0x3,
310 0x949c, 0xffffffff, 0x100,
311 0x9490, 0xffffffff, 0x4,
312 0x949c, 0xffffffff, 0x100,
313 0x9490, 0xffffffff, 0x5,
314 0x949c, 0xffffffff, 0x100,
315 0x9490, 0xffffffff, 0x6,
316 0x949c, 0xffffffff, 0x100,
317 0x9490, 0xffffffff, 0x7,
318 0x949c, 0xffffffff, 0x100,
319 0x9490, 0xffffffff, 0x8,
320 0x949c, 0xffffffff, 0x100,
321 0x9490, 0xffffffff, 0x9,
322 0x949c, 0xffffffff, 0x100,
323 0x9490, 0xffffffff, 0x8000,
324 0x9604, 0xffffffff, 0x0,
325 0x9654, 0xffffffff, 0x100,
326 0x9604, 0xffffffff, 0x1,
327 0x9654, 0xffffffff, 0x100,
328 0x9604, 0xffffffff, 0x2,
329 0x9654, 0xffffffff, 0x100,
330 0x9604, 0xffffffff, 0x3,
331 0x9654, 0xffffffff, 0x100,
332 0x9604, 0xffffffff, 0x4,
333 0x9654, 0xffffffff, 0x100,
334 0x9604, 0xffffffff, 0x5,
335 0x9654, 0xffffffff, 0x100,
336 0x9604, 0xffffffff, 0x6,
337 0x9654, 0xffffffff, 0x100,
338 0x9604, 0xffffffff, 0x7,
339 0x9654, 0xffffffff, 0x100,
340 0x9604, 0xffffffff, 0x8,
341 0x9654, 0xffffffff, 0x100,
342 0x9604, 0xffffffff, 0x9,
343 0x9654, 0xffffffff, 0x100,
344 0x9604, 0xffffffff, 0x80000000,
345 0x9030, 0xffffffff, 0x100,
346 0x9034, 0xffffffff, 0x100,
347 0x9038, 0xffffffff, 0x100,
348 0x903c, 0xffffffff, 0x100,
349 0x9040, 0xffffffff, 0x100,
350 0xa200, 0xffffffff, 0x100,
351 0xa204, 0xffffffff, 0x100,
352 0xa208, 0xffffffff, 0x100,
353 0xa20c, 0xffffffff, 0x100,
354 0x971c, 0xffffffff, 0x100,
355 0x915c, 0xffffffff, 0x00020001,
356 0x9160, 0xffffffff, 0x00040003,
357 0x916c, 0xffffffff, 0x00060005,
358 0x9170, 0xffffffff, 0x00080007,
359 0x9174, 0xffffffff, 0x000a0009,
360 0x9178, 0xffffffff, 0x000c000b,
361 0x917c, 0xffffffff, 0x000e000d,
362 0x9180, 0xffffffff, 0x0010000f,
363 0x918c, 0xffffffff, 0x00120011,
364 0x9190, 0xffffffff, 0x00140013,
365 0x9194, 0xffffffff, 0x00020001,
366 0x9198, 0xffffffff, 0x00040003,
367 0x919c, 0xffffffff, 0x00060005,
368 0x91a8, 0xffffffff, 0x00080007,
369 0x91ac, 0xffffffff, 0x000a0009,
370 0x91b0, 0xffffffff, 0x000c000b,
371 0x91b4, 0xffffffff, 0x000e000d,
372 0x91b8, 0xffffffff, 0x0010000f,
373 0x91c4, 0xffffffff, 0x00120011,
374 0x91c8, 0xffffffff, 0x00140013,
375 0x91cc, 0xffffffff, 0x00020001,
376 0x91d0, 0xffffffff, 0x00040003,
377 0x91d4, 0xffffffff, 0x00060005,
378 0x91e0, 0xffffffff, 0x00080007,
379 0x91e4, 0xffffffff, 0x000a0009,
380 0x91e8, 0xffffffff, 0x000c000b,
381 0x91ec, 0xffffffff, 0x00020001,
382 0x91f0, 0xffffffff, 0x00040003,
383 0x91f4, 0xffffffff, 0x00060005,
384 0x9200, 0xffffffff, 0x00080007,
385 0x9204, 0xffffffff, 0x000a0009,
386 0x9208, 0xffffffff, 0x000c000b,
387 0x920c, 0xffffffff, 0x000e000d,
388 0x9210, 0xffffffff, 0x0010000f,
389 0x921c, 0xffffffff, 0x00120011,
390 0x9220, 0xffffffff, 0x00140013,
391 0x9224, 0xffffffff, 0x00020001,
392 0x9228, 0xffffffff, 0x00040003,
393 0x922c, 0xffffffff, 0x00060005,
394 0x9238, 0xffffffff, 0x00080007,
395 0x923c, 0xffffffff, 0x000a0009,
396 0x9240, 0xffffffff, 0x000c000b,
397 0x9244, 0xffffffff, 0x000e000d,
398 0x9248, 0xffffffff, 0x0010000f,
399 0x9254, 0xffffffff, 0x00120011,
400 0x9258, 0xffffffff, 0x00140013,
401 0x925c, 0xffffffff, 0x00020001,
402 0x9260, 0xffffffff, 0x00040003,
403 0x9264, 0xffffffff, 0x00060005,
404 0x9270, 0xffffffff, 0x00080007,
405 0x9274, 0xffffffff, 0x000a0009,
406 0x9278, 0xffffffff, 0x000c000b,
407 0x927c, 0xffffffff, 0x000e000d,
408 0x9280, 0xffffffff, 0x0010000f,
409 0x928c, 0xffffffff, 0x00120011,
410 0x9290, 0xffffffff, 0x00140013,
411 0x9294, 0xffffffff, 0x00020001,
412 0x929c, 0xffffffff, 0x00040003,
413 0x92a0, 0xffffffff, 0x00060005,
414 0x92a4, 0xffffffff, 0x00080007
415};
416
417static const u32 rv710_golden_registers[] =
418{
419 0x3f90, 0x00ff0000, 0x00fc0000,
420 0x9148, 0x00ff0000, 0x00fc0000,
421 0x3f94, 0x00ff0000, 0x00fc0000,
422 0x914c, 0x00ff0000, 0x00fc0000,
423 0xb4c, 0x00000020, 0x00000020,
424 0xa180, 0xffffffff, 0x00003f3f
425};
426
427static const u32 rv710_mgcg_init[] =
428{
429 0x8bcc, 0xffffffff, 0x13030040,
430 0x5448, 0xffffffff, 0x100,
431 0x55e4, 0xffffffff, 0x100,
432 0x160c, 0xffffffff, 0x100,
433 0x5644, 0xffffffff, 0x100,
434 0xc164, 0xffffffff, 0x100,
435 0x8a18, 0xffffffff, 0x100,
436 0x897c, 0xffffffff, 0x8000100,
437 0x8b28, 0xffffffff, 0x3c000100,
438 0x9144, 0xffffffff, 0x100,
439 0x9a1c, 0xffffffff, 0x10000,
440 0x9a50, 0xffffffff, 0x100,
441 0x9a1c, 0xffffffff, 0x0,
442 0x9870, 0xffffffff, 0x100,
443 0x8d58, 0xffffffff, 0x100,
444 0x9500, 0xffffffff, 0x0,
445 0x9510, 0xffffffff, 0x100,
446 0x9500, 0xffffffff, 0x1,
447 0x9510, 0xffffffff, 0x100,
448 0x9500, 0xffffffff, 0x8000,
449 0x9490, 0xffffffff, 0x0,
450 0x949c, 0xffffffff, 0x100,
451 0x9490, 0xffffffff, 0x1,
452 0x949c, 0xffffffff, 0x100,
453 0x9490, 0xffffffff, 0x8000,
454 0x9604, 0xffffffff, 0x0,
455 0x9654, 0xffffffff, 0x100,
456 0x9604, 0xffffffff, 0x1,
457 0x9654, 0xffffffff, 0x100,
458 0x9604, 0xffffffff, 0x80000000,
459 0x9030, 0xffffffff, 0x100,
460 0x9034, 0xffffffff, 0x100,
461 0x9038, 0xffffffff, 0x100,
462 0x903c, 0xffffffff, 0x100,
463 0x9040, 0xffffffff, 0x100,
464 0xa200, 0xffffffff, 0x100,
465 0xa204, 0xffffffff, 0x100,
466 0xa208, 0xffffffff, 0x100,
467 0xa20c, 0xffffffff, 0x100,
468 0x971c, 0xffffffff, 0x100,
469 0x915c, 0xffffffff, 0x00020001,
470 0x9174, 0xffffffff, 0x00000003,
471 0x9178, 0xffffffff, 0x00050001,
472 0x917c, 0xffffffff, 0x00030002,
473 0x918c, 0xffffffff, 0x00000004,
474 0x9190, 0xffffffff, 0x00070006,
475 0x9194, 0xffffffff, 0x00050001,
476 0x9198, 0xffffffff, 0x00030002,
477 0x91a8, 0xffffffff, 0x00000004,
478 0x91ac, 0xffffffff, 0x00070006,
479 0x91e8, 0xffffffff, 0x00000001,
480 0x9294, 0xffffffff, 0x00000001,
481 0x929c, 0xffffffff, 0x00000002,
482 0x92a0, 0xffffffff, 0x00040003,
483 0x9150, 0xffffffff, 0x4d940000
484};
485
486static const u32 rv730_golden_registers[] =
487{
488 0x3f90, 0x00ff0000, 0x00f00000,
489 0x9148, 0x00ff0000, 0x00f00000,
490 0x3f94, 0x00ff0000, 0x00f00000,
491 0x914c, 0x00ff0000, 0x00f00000,
492 0x900c, 0xffffffff, 0x003b033f,
493 0xb4c, 0x00000020, 0x00000020,
494 0xa180, 0xffffffff, 0x00003f3f
495};
496
497static const u32 rv730_mgcg_init[] =
498{
499 0x8bcc, 0xffffffff, 0x130300f9,
500 0x5448, 0xffffffff, 0x100,
501 0x55e4, 0xffffffff, 0x100,
502 0x160c, 0xffffffff, 0x100,
503 0x5644, 0xffffffff, 0x100,
504 0xc164, 0xffffffff, 0x100,
505 0x8a18, 0xffffffff, 0x100,
506 0x897c, 0xffffffff, 0x8000100,
507 0x8b28, 0xffffffff, 0x3c000100,
508 0x9144, 0xffffffff, 0x100,
509 0x9a1c, 0xffffffff, 0x10000,
510 0x9a50, 0xffffffff, 0x100,
511 0x9a1c, 0xffffffff, 0x10001,
512 0x9a50, 0xffffffff, 0x100,
513 0x9a1c, 0xffffffff, 0x0,
514 0x9870, 0xffffffff, 0x100,
515 0x8d58, 0xffffffff, 0x100,
516 0x9500, 0xffffffff, 0x0,
517 0x9510, 0xffffffff, 0x100,
518 0x9500, 0xffffffff, 0x1,
519 0x9510, 0xffffffff, 0x100,
520 0x9500, 0xffffffff, 0x2,
521 0x9510, 0xffffffff, 0x100,
522 0x9500, 0xffffffff, 0x3,
523 0x9510, 0xffffffff, 0x100,
524 0x9500, 0xffffffff, 0x4,
525 0x9510, 0xffffffff, 0x100,
526 0x9500, 0xffffffff, 0x5,
527 0x9510, 0xffffffff, 0x100,
528 0x9500, 0xffffffff, 0x6,
529 0x9510, 0xffffffff, 0x100,
530 0x9500, 0xffffffff, 0x7,
531 0x9510, 0xffffffff, 0x100,
532 0x9500, 0xffffffff, 0x8000,
533 0x9490, 0xffffffff, 0x0,
534 0x949c, 0xffffffff, 0x100,
535 0x9490, 0xffffffff, 0x1,
536 0x949c, 0xffffffff, 0x100,
537 0x9490, 0xffffffff, 0x2,
538 0x949c, 0xffffffff, 0x100,
539 0x9490, 0xffffffff, 0x3,
540 0x949c, 0xffffffff, 0x100,
541 0x9490, 0xffffffff, 0x4,
542 0x949c, 0xffffffff, 0x100,
543 0x9490, 0xffffffff, 0x5,
544 0x949c, 0xffffffff, 0x100,
545 0x9490, 0xffffffff, 0x6,
546 0x949c, 0xffffffff, 0x100,
547 0x9490, 0xffffffff, 0x7,
548 0x949c, 0xffffffff, 0x100,
549 0x9490, 0xffffffff, 0x8000,
550 0x9604, 0xffffffff, 0x0,
551 0x9654, 0xffffffff, 0x100,
552 0x9604, 0xffffffff, 0x1,
553 0x9654, 0xffffffff, 0x100,
554 0x9604, 0xffffffff, 0x2,
555 0x9654, 0xffffffff, 0x100,
556 0x9604, 0xffffffff, 0x3,
557 0x9654, 0xffffffff, 0x100,
558 0x9604, 0xffffffff, 0x4,
559 0x9654, 0xffffffff, 0x100,
560 0x9604, 0xffffffff, 0x5,
561 0x9654, 0xffffffff, 0x100,
562 0x9604, 0xffffffff, 0x6,
563 0x9654, 0xffffffff, 0x100,
564 0x9604, 0xffffffff, 0x7,
565 0x9654, 0xffffffff, 0x100,
566 0x9604, 0xffffffff, 0x80000000,
567 0x9030, 0xffffffff, 0x100,
568 0x9034, 0xffffffff, 0x100,
569 0x9038, 0xffffffff, 0x100,
570 0x903c, 0xffffffff, 0x100,
571 0x9040, 0xffffffff, 0x100,
572 0xa200, 0xffffffff, 0x100,
573 0xa204, 0xffffffff, 0x100,
574 0xa208, 0xffffffff, 0x100,
575 0xa20c, 0xffffffff, 0x100,
576 0x971c, 0xffffffff, 0x100,
577 0x915c, 0xffffffff, 0x00020001,
578 0x916c, 0xffffffff, 0x00040003,
579 0x9170, 0xffffffff, 0x00000005,
580 0x9178, 0xffffffff, 0x00050001,
581 0x917c, 0xffffffff, 0x00030002,
582 0x918c, 0xffffffff, 0x00000004,
583 0x9190, 0xffffffff, 0x00070006,
584 0x9194, 0xffffffff, 0x00050001,
585 0x9198, 0xffffffff, 0x00030002,
586 0x91a8, 0xffffffff, 0x00000004,
587 0x91ac, 0xffffffff, 0x00070006,
588 0x91b0, 0xffffffff, 0x00050001,
589 0x91b4, 0xffffffff, 0x00030002,
590 0x91c4, 0xffffffff, 0x00000004,
591 0x91c8, 0xffffffff, 0x00070006,
592 0x91cc, 0xffffffff, 0x00050001,
593 0x91d0, 0xffffffff, 0x00030002,
594 0x91e0, 0xffffffff, 0x00000004,
595 0x91e4, 0xffffffff, 0x00070006,
596 0x91e8, 0xffffffff, 0x00000001,
597 0x91ec, 0xffffffff, 0x00050001,
598 0x91f0, 0xffffffff, 0x00030002,
599 0x9200, 0xffffffff, 0x00000004,
600 0x9204, 0xffffffff, 0x00070006,
601 0x9208, 0xffffffff, 0x00050001,
602 0x920c, 0xffffffff, 0x00030002,
603 0x921c, 0xffffffff, 0x00000004,
604 0x9220, 0xffffffff, 0x00070006,
605 0x9224, 0xffffffff, 0x00050001,
606 0x9228, 0xffffffff, 0x00030002,
607 0x9238, 0xffffffff, 0x00000004,
608 0x923c, 0xffffffff, 0x00070006,
609 0x9240, 0xffffffff, 0x00050001,
610 0x9244, 0xffffffff, 0x00030002,
611 0x9254, 0xffffffff, 0x00000004,
612 0x9258, 0xffffffff, 0x00070006,
613 0x9294, 0xffffffff, 0x00000001,
614 0x929c, 0xffffffff, 0x00000002,
615 0x92a0, 0xffffffff, 0x00040003,
616 0x92a4, 0xffffffff, 0x00000005
617};
618
619static const u32 rv740_golden_registers[] =
620{
621 0x88c4, 0xffffffff, 0x00000082,
622 0x28a50, 0xfffffffc, 0x00000004,
623 0x2650, 0x00040000, 0,
624 0x20bc, 0x00040000, 0,
625 0x733c, 0xffffffff, 0x00000002,
626 0x7300, 0xffffffff, 0x001000f0,
627 0x3f90, 0x00ff0000, 0,
628 0x9148, 0x00ff0000, 0,
629 0x3f94, 0x00ff0000, 0,
630 0x914c, 0x00ff0000, 0,
631 0x240c, 0xffffffff, 0x00000380,
632 0x8a14, 0x00000007, 0x00000007,
633 0x8b24, 0xffffffff, 0x00ff0fff,
634 0x28a4c, 0xffffffff, 0x00004000,
635 0xa180, 0xffffffff, 0x00003f3f,
636 0x8d00, 0xffffffff, 0x0e0e003a,
637 0x8d04, 0xffffffff, 0x013a0e2a,
638 0x8c00, 0xffffffff, 0xe400000f,
639 0x8db0, 0xffffffff, 0x98989898,
640 0x8db4, 0xffffffff, 0x98989898,
641 0x8db8, 0xffffffff, 0x98989898,
642 0x8dbc, 0xffffffff, 0x98989898,
643 0x8dc0, 0xffffffff, 0x98989898,
644 0x8dc4, 0xffffffff, 0x98989898,
645 0x8dc8, 0xffffffff, 0x98989898,
646 0x8dcc, 0xffffffff, 0x98989898,
647 0x9058, 0xffffffff, 0x0fffc40f,
648 0x900c, 0xffffffff, 0x003b033f,
649 0x28350, 0xffffffff, 0,
650 0x8cf0, 0x1fffffff, 0x08e00420,
651 0x9508, 0xffffffff, 0x00000002,
652 0x88c4, 0xffffffff, 0x000000c2,
653 0x9698, 0x18000000, 0x18000000
654};
655
656static const u32 rv740_mgcg_init[] =
657{
658 0x8bcc, 0xffffffff, 0x13030100,
659 0x5448, 0xffffffff, 0x100,
660 0x55e4, 0xffffffff, 0x100,
661 0x160c, 0xffffffff, 0x100,
662 0x5644, 0xffffffff, 0x100,
663 0xc164, 0xffffffff, 0x100,
664 0x8a18, 0xffffffff, 0x100,
665 0x897c, 0xffffffff, 0x100,
666 0x8b28, 0xffffffff, 0x100,
667 0x9144, 0xffffffff, 0x100,
668 0x9a1c, 0xffffffff, 0x10000,
669 0x9a50, 0xffffffff, 0x100,
670 0x9a1c, 0xffffffff, 0x10001,
671 0x9a50, 0xffffffff, 0x100,
672 0x9a1c, 0xffffffff, 0x10002,
673 0x9a50, 0xffffffff, 0x100,
674 0x9a1c, 0xffffffff, 0x10003,
675 0x9a50, 0xffffffff, 0x100,
676 0x9a1c, 0xffffffff, 0x0,
677 0x9870, 0xffffffff, 0x100,
678 0x8d58, 0xffffffff, 0x100,
679 0x9500, 0xffffffff, 0x0,
680 0x9510, 0xffffffff, 0x100,
681 0x9500, 0xffffffff, 0x1,
682 0x9510, 0xffffffff, 0x100,
683 0x9500, 0xffffffff, 0x2,
684 0x9510, 0xffffffff, 0x100,
685 0x9500, 0xffffffff, 0x3,
686 0x9510, 0xffffffff, 0x100,
687 0x9500, 0xffffffff, 0x4,
688 0x9510, 0xffffffff, 0x100,
689 0x9500, 0xffffffff, 0x5,
690 0x9510, 0xffffffff, 0x100,
691 0x9500, 0xffffffff, 0x6,
692 0x9510, 0xffffffff, 0x100,
693 0x9500, 0xffffffff, 0x7,
694 0x9510, 0xffffffff, 0x100,
695 0x9500, 0xffffffff, 0x8000,
696 0x9490, 0xffffffff, 0x0,
697 0x949c, 0xffffffff, 0x100,
698 0x9490, 0xffffffff, 0x1,
699 0x949c, 0xffffffff, 0x100,
700 0x9490, 0xffffffff, 0x2,
701 0x949c, 0xffffffff, 0x100,
702 0x9490, 0xffffffff, 0x3,
703 0x949c, 0xffffffff, 0x100,
704 0x9490, 0xffffffff, 0x4,
705 0x949c, 0xffffffff, 0x100,
706 0x9490, 0xffffffff, 0x5,
707 0x949c, 0xffffffff, 0x100,
708 0x9490, 0xffffffff, 0x6,
709 0x949c, 0xffffffff, 0x100,
710 0x9490, 0xffffffff, 0x7,
711 0x949c, 0xffffffff, 0x100,
712 0x9490, 0xffffffff, 0x8000,
713 0x9604, 0xffffffff, 0x0,
714 0x9654, 0xffffffff, 0x100,
715 0x9604, 0xffffffff, 0x1,
716 0x9654, 0xffffffff, 0x100,
717 0x9604, 0xffffffff, 0x2,
718 0x9654, 0xffffffff, 0x100,
719 0x9604, 0xffffffff, 0x3,
720 0x9654, 0xffffffff, 0x100,
721 0x9604, 0xffffffff, 0x4,
722 0x9654, 0xffffffff, 0x100,
723 0x9604, 0xffffffff, 0x5,
724 0x9654, 0xffffffff, 0x100,
725 0x9604, 0xffffffff, 0x6,
726 0x9654, 0xffffffff, 0x100,
727 0x9604, 0xffffffff, 0x7,
728 0x9654, 0xffffffff, 0x100,
729 0x9604, 0xffffffff, 0x80000000,
730 0x9030, 0xffffffff, 0x100,
731 0x9034, 0xffffffff, 0x100,
732 0x9038, 0xffffffff, 0x100,
733 0x903c, 0xffffffff, 0x100,
734 0x9040, 0xffffffff, 0x100,
735 0xa200, 0xffffffff, 0x100,
736 0xa204, 0xffffffff, 0x100,
737 0xa208, 0xffffffff, 0x100,
738 0xa20c, 0xffffffff, 0x100,
739 0x971c, 0xffffffff, 0x100,
740 0x915c, 0xffffffff, 0x00020001,
741 0x9160, 0xffffffff, 0x00040003,
742 0x916c, 0xffffffff, 0x00060005,
743 0x9170, 0xffffffff, 0x00080007,
744 0x9174, 0xffffffff, 0x000a0009,
745 0x9178, 0xffffffff, 0x000c000b,
746 0x917c, 0xffffffff, 0x000e000d,
747 0x9180, 0xffffffff, 0x0010000f,
748 0x918c, 0xffffffff, 0x00120011,
749 0x9190, 0xffffffff, 0x00140013,
750 0x9194, 0xffffffff, 0x00020001,
751 0x9198, 0xffffffff, 0x00040003,
752 0x919c, 0xffffffff, 0x00060005,
753 0x91a8, 0xffffffff, 0x00080007,
754 0x91ac, 0xffffffff, 0x000a0009,
755 0x91b0, 0xffffffff, 0x000c000b,
756 0x91b4, 0xffffffff, 0x000e000d,
757 0x91b8, 0xffffffff, 0x0010000f,
758 0x91c4, 0xffffffff, 0x00120011,
759 0x91c8, 0xffffffff, 0x00140013,
760 0x91cc, 0xffffffff, 0x00020001,
761 0x91d0, 0xffffffff, 0x00040003,
762 0x91d4, 0xffffffff, 0x00060005,
763 0x91e0, 0xffffffff, 0x00080007,
764 0x91e4, 0xffffffff, 0x000a0009,
765 0x91e8, 0xffffffff, 0x000c000b,
766 0x91ec, 0xffffffff, 0x00020001,
767 0x91f0, 0xffffffff, 0x00040003,
768 0x91f4, 0xffffffff, 0x00060005,
769 0x9200, 0xffffffff, 0x00080007,
770 0x9204, 0xffffffff, 0x000a0009,
771 0x9208, 0xffffffff, 0x000c000b,
772 0x920c, 0xffffffff, 0x000e000d,
773 0x9210, 0xffffffff, 0x0010000f,
774 0x921c, 0xffffffff, 0x00120011,
775 0x9220, 0xffffffff, 0x00140013,
776 0x9224, 0xffffffff, 0x00020001,
777 0x9228, 0xffffffff, 0x00040003,
778 0x922c, 0xffffffff, 0x00060005,
779 0x9238, 0xffffffff, 0x00080007,
780 0x923c, 0xffffffff, 0x000a0009,
781 0x9240, 0xffffffff, 0x000c000b,
782 0x9244, 0xffffffff, 0x000e000d,
783 0x9248, 0xffffffff, 0x0010000f,
784 0x9254, 0xffffffff, 0x00120011,
785 0x9258, 0xffffffff, 0x00140013,
786 0x9294, 0xffffffff, 0x00020001,
787 0x929c, 0xffffffff, 0x00040003,
788 0x92a0, 0xffffffff, 0x00060005,
789 0x92a4, 0xffffffff, 0x00080007
790};
791
792static void rv770_init_golden_registers(struct radeon_device *rdev)
793{
794 switch (rdev->family) {
795 case CHIP_RV770:
796 radeon_program_register_sequence(rdev,
797 r7xx_golden_registers,
798 (const u32)ARRAY_SIZE(r7xx_golden_registers));
799 radeon_program_register_sequence(rdev,
800 r7xx_golden_dyn_gpr_registers,
801 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
802 if (rdev->pdev->device == 0x994e)
803 radeon_program_register_sequence(rdev,
804 rv770ce_golden_registers,
805 (const u32)ARRAY_SIZE(rv770ce_golden_registers));
806 else
807 radeon_program_register_sequence(rdev,
808 rv770_golden_registers,
809 (const u32)ARRAY_SIZE(rv770_golden_registers));
810 radeon_program_register_sequence(rdev,
811 rv770_mgcg_init,
812 (const u32)ARRAY_SIZE(rv770_mgcg_init));
813 break;
814 case CHIP_RV730:
815 radeon_program_register_sequence(rdev,
816 r7xx_golden_registers,
817 (const u32)ARRAY_SIZE(r7xx_golden_registers));
818 radeon_program_register_sequence(rdev,
819 r7xx_golden_dyn_gpr_registers,
820 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
821 radeon_program_register_sequence(rdev,
822 rv730_golden_registers,
823 (const u32)ARRAY_SIZE(rv770_golden_registers));
824 radeon_program_register_sequence(rdev,
825 rv730_mgcg_init,
826 (const u32)ARRAY_SIZE(rv770_mgcg_init));
827 break;
828 case CHIP_RV710:
829 radeon_program_register_sequence(rdev,
830 r7xx_golden_registers,
831 (const u32)ARRAY_SIZE(r7xx_golden_registers));
832 radeon_program_register_sequence(rdev,
833 r7xx_golden_dyn_gpr_registers,
834 (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
835 radeon_program_register_sequence(rdev,
836 rv710_golden_registers,
837 (const u32)ARRAY_SIZE(rv770_golden_registers));
838 radeon_program_register_sequence(rdev,
839 rv710_mgcg_init,
840 (const u32)ARRAY_SIZE(rv770_mgcg_init));
841 break;
842 case CHIP_RV740:
843 radeon_program_register_sequence(rdev,
844 rv740_golden_registers,
845 (const u32)ARRAY_SIZE(rv770_golden_registers));
846 radeon_program_register_sequence(rdev,
847 rv740_mgcg_init,
848 (const u32)ARRAY_SIZE(rv770_mgcg_init));
849 break;
850 default:
851 break;
852 }
853}
854
202#define PCIE_BUS_CLK 10000 855#define PCIE_BUS_CLK 10000
203#define TCLK (PCIE_BUS_CLK / 10) 856#define TCLK (PCIE_BUS_CLK / 10)
204 857
@@ -1384,6 +2037,9 @@ int rv770_resume(struct radeon_device *rdev)
1384 /* post card */ 2037 /* post card */
1385 atom_asic_init(rdev->mode_info.atom_context); 2038 atom_asic_init(rdev->mode_info.atom_context);
1386 2039
2040 /* init golden registers */
2041 rv770_init_golden_registers(rdev);
2042
1387 rdev->accel_working = true; 2043 rdev->accel_working = true;
1388 r = rv770_startup(rdev); 2044 r = rv770_startup(rdev);
1389 if (r) { 2045 if (r) {
@@ -1441,6 +2097,8 @@ int rv770_init(struct radeon_device *rdev)
1441 DRM_INFO("GPU not posted. posting now...\n"); 2097 DRM_INFO("GPU not posted. posting now...\n");
1442 atom_asic_init(rdev->mode_info.atom_context); 2098 atom_asic_init(rdev->mode_info.atom_context);
1443 } 2099 }
2100 /* init golden registers */
2101 rv770_init_golden_registers(rdev);
1444 /* Initialize scratch registers */ 2102 /* Initialize scratch registers */
1445 r600_scratch_init(rdev); 2103 r600_scratch_init(rdev);
1446 /* Initialize surface registers */ 2104 /* Initialize surface registers */
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index aa2c555ba877..fe6b14e0021c 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -70,6 +70,794 @@ extern u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
70extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev); 70extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
71extern bool evergreen_is_display_hung(struct radeon_device *rdev); 71extern bool evergreen_is_display_hung(struct radeon_device *rdev);
72 72
73static const u32 tahiti_golden_rlc_registers[] =
74{
75 0xc424, 0xffffffff, 0x00601005,
76 0xc47c, 0xffffffff, 0x10104040,
77 0xc488, 0xffffffff, 0x0100000a,
78 0xc314, 0xffffffff, 0x00000800,
79 0xc30c, 0xffffffff, 0x800000f4,
80 0xf4a8, 0xffffffff, 0x00000000
81};
82
83static const u32 tahiti_golden_registers[] =
84{
85 0x9a10, 0x00010000, 0x00018208,
86 0x9830, 0xffffffff, 0x00000000,
87 0x9834, 0xf00fffff, 0x00000400,
88 0x9838, 0x0002021c, 0x00020200,
89 0xc78, 0x00000080, 0x00000000,
90 0xd030, 0x000300c0, 0x00800040,
91 0xd830, 0x000300c0, 0x00800040,
92 0x5bb0, 0x000000f0, 0x00000070,
93 0x5bc0, 0x00200000, 0x50100000,
94 0x7030, 0x31000311, 0x00000011,
95 0x277c, 0x00000003, 0x000007ff,
96 0x240c, 0x000007ff, 0x00000000,
97 0x8a14, 0xf000001f, 0x00000007,
98 0x8b24, 0xffffffff, 0x00ffffff,
99 0x8b10, 0x0000ff0f, 0x00000000,
100 0x28a4c, 0x07ffffff, 0x4e000000,
101 0x28350, 0x3f3f3fff, 0x2a00126a,
102 0x30, 0x000000ff, 0x0040,
103 0x34, 0x00000040, 0x00004040,
104 0x9100, 0x07ffffff, 0x03000000,
105 0x8e88, 0x01ff1f3f, 0x00000000,
106 0x8e84, 0x01ff1f3f, 0x00000000,
107 0x9060, 0x0000007f, 0x00000020,
108 0x9508, 0x00010000, 0x00010000,
109 0xac14, 0x00000200, 0x000002fb,
110 0xac10, 0xffffffff, 0x0000543b,
111 0xac0c, 0xffffffff, 0xa9210876,
112 0x88d0, 0xffffffff, 0x000fff40,
113 0x88d4, 0x0000001f, 0x00000010,
114 0x1410, 0x20000000, 0x20fffed8,
115 0x15c0, 0x000c0fc0, 0x000c0400
116};
117
118static const u32 tahiti_golden_registers2[] =
119{
120 0xc64, 0x00000001, 0x00000001
121};
122
123static const u32 pitcairn_golden_rlc_registers[] =
124{
125 0xc424, 0xffffffff, 0x00601004,
126 0xc47c, 0xffffffff, 0x10102020,
127 0xc488, 0xffffffff, 0x01000020,
128 0xc314, 0xffffffff, 0x00000800,
129 0xc30c, 0xffffffff, 0x800000a4
130};
131
132static const u32 pitcairn_golden_registers[] =
133{
134 0x9a10, 0x00010000, 0x00018208,
135 0x9830, 0xffffffff, 0x00000000,
136 0x9834, 0xf00fffff, 0x00000400,
137 0x9838, 0x0002021c, 0x00020200,
138 0xc78, 0x00000080, 0x00000000,
139 0xd030, 0x000300c0, 0x00800040,
140 0xd830, 0x000300c0, 0x00800040,
141 0x5bb0, 0x000000f0, 0x00000070,
142 0x5bc0, 0x00200000, 0x50100000,
143 0x7030, 0x31000311, 0x00000011,
144 0x2ae4, 0x00073ffe, 0x000022a2,
145 0x240c, 0x000007ff, 0x00000000,
146 0x8a14, 0xf000001f, 0x00000007,
147 0x8b24, 0xffffffff, 0x00ffffff,
148 0x8b10, 0x0000ff0f, 0x00000000,
149 0x28a4c, 0x07ffffff, 0x4e000000,
150 0x28350, 0x3f3f3fff, 0x2a00126a,
151 0x30, 0x000000ff, 0x0040,
152 0x34, 0x00000040, 0x00004040,
153 0x9100, 0x07ffffff, 0x03000000,
154 0x9060, 0x0000007f, 0x00000020,
155 0x9508, 0x00010000, 0x00010000,
156 0xac14, 0x000003ff, 0x000000f7,
157 0xac10, 0xffffffff, 0x00000000,
158 0xac0c, 0xffffffff, 0x32761054,
159 0x88d4, 0x0000001f, 0x00000010,
160 0x15c0, 0x000c0fc0, 0x000c0400
161};
162
163static const u32 verde_golden_rlc_registers[] =
164{
165 0xc424, 0xffffffff, 0x033f1005,
166 0xc47c, 0xffffffff, 0x10808020,
167 0xc488, 0xffffffff, 0x00800008,
168 0xc314, 0xffffffff, 0x00001000,
169 0xc30c, 0xffffffff, 0x80010014
170};
171
172static const u32 verde_golden_registers[] =
173{
174 0x9a10, 0x00010000, 0x00018208,
175 0x9830, 0xffffffff, 0x00000000,
176 0x9834, 0xf00fffff, 0x00000400,
177 0x9838, 0x0002021c, 0x00020200,
178 0xc78, 0x00000080, 0x00000000,
179 0xd030, 0x000300c0, 0x00800040,
180 0xd030, 0x000300c0, 0x00800040,
181 0xd830, 0x000300c0, 0x00800040,
182 0xd830, 0x000300c0, 0x00800040,
183 0x5bb0, 0x000000f0, 0x00000070,
184 0x5bc0, 0x00200000, 0x50100000,
185 0x7030, 0x31000311, 0x00000011,
186 0x2ae4, 0x00073ffe, 0x000022a2,
187 0x2ae4, 0x00073ffe, 0x000022a2,
188 0x2ae4, 0x00073ffe, 0x000022a2,
189 0x240c, 0x000007ff, 0x00000000,
190 0x240c, 0x000007ff, 0x00000000,
191 0x240c, 0x000007ff, 0x00000000,
192 0x8a14, 0xf000001f, 0x00000007,
193 0x8a14, 0xf000001f, 0x00000007,
194 0x8a14, 0xf000001f, 0x00000007,
195 0x8b24, 0xffffffff, 0x00ffffff,
196 0x8b10, 0x0000ff0f, 0x00000000,
197 0x28a4c, 0x07ffffff, 0x4e000000,
198 0x28350, 0x3f3f3fff, 0x0000124a,
199 0x28350, 0x3f3f3fff, 0x0000124a,
200 0x28350, 0x3f3f3fff, 0x0000124a,
201 0x30, 0x000000ff, 0x0040,
202 0x34, 0x00000040, 0x00004040,
203 0x9100, 0x07ffffff, 0x03000000,
204 0x9100, 0x07ffffff, 0x03000000,
205 0x8e88, 0x01ff1f3f, 0x00000000,
206 0x8e88, 0x01ff1f3f, 0x00000000,
207 0x8e88, 0x01ff1f3f, 0x00000000,
208 0x8e84, 0x01ff1f3f, 0x00000000,
209 0x8e84, 0x01ff1f3f, 0x00000000,
210 0x8e84, 0x01ff1f3f, 0x00000000,
211 0x9060, 0x0000007f, 0x00000020,
212 0x9508, 0x00010000, 0x00010000,
213 0xac14, 0x000003ff, 0x00000003,
214 0xac14, 0x000003ff, 0x00000003,
215 0xac14, 0x000003ff, 0x00000003,
216 0xac10, 0xffffffff, 0x00000000,
217 0xac10, 0xffffffff, 0x00000000,
218 0xac10, 0xffffffff, 0x00000000,
219 0xac0c, 0xffffffff, 0x00001032,
220 0xac0c, 0xffffffff, 0x00001032,
221 0xac0c, 0xffffffff, 0x00001032,
222 0x88d4, 0x0000001f, 0x00000010,
223 0x88d4, 0x0000001f, 0x00000010,
224 0x88d4, 0x0000001f, 0x00000010,
225 0x15c0, 0x000c0fc0, 0x000c0400
226};
227
228static const u32 oland_golden_rlc_registers[] =
229{
230 0xc424, 0xffffffff, 0x00601005,
231 0xc47c, 0xffffffff, 0x10104040,
232 0xc488, 0xffffffff, 0x0100000a,
233 0xc314, 0xffffffff, 0x00000800,
234 0xc30c, 0xffffffff, 0x800000f4
235};
236
237static const u32 oland_golden_registers[] =
238{
239 0x9a10, 0x00010000, 0x00018208,
240 0x9830, 0xffffffff, 0x00000000,
241 0x9834, 0xf00fffff, 0x00000400,
242 0x9838, 0x0002021c, 0x00020200,
243 0xc78, 0x00000080, 0x00000000,
244 0xd030, 0x000300c0, 0x00800040,
245 0xd830, 0x000300c0, 0x00800040,
246 0x5bb0, 0x000000f0, 0x00000070,
247 0x5bc0, 0x00200000, 0x50100000,
248 0x7030, 0x31000311, 0x00000011,
249 0x2ae4, 0x00073ffe, 0x000022a2,
250 0x240c, 0x000007ff, 0x00000000,
251 0x8a14, 0xf000001f, 0x00000007,
252 0x8b24, 0xffffffff, 0x00ffffff,
253 0x8b10, 0x0000ff0f, 0x00000000,
254 0x28a4c, 0x07ffffff, 0x4e000000,
255 0x28350, 0x3f3f3fff, 0x00000082,
256 0x30, 0x000000ff, 0x0040,
257 0x34, 0x00000040, 0x00004040,
258 0x9100, 0x07ffffff, 0x03000000,
259 0x9060, 0x0000007f, 0x00000020,
260 0x9508, 0x00010000, 0x00010000,
261 0xac14, 0x000003ff, 0x000000f3,
262 0xac10, 0xffffffff, 0x00000000,
263 0xac0c, 0xffffffff, 0x00003210,
264 0x88d4, 0x0000001f, 0x00000010,
265 0x15c0, 0x000c0fc0, 0x000c0400
266};
267
268static const u32 tahiti_mgcg_cgcg_init[] =
269{
270 0xc400, 0xffffffff, 0xfffffffc,
271 0x802c, 0xffffffff, 0xe0000000,
272 0x9a60, 0xffffffff, 0x00000100,
273 0x92a4, 0xffffffff, 0x00000100,
274 0xc164, 0xffffffff, 0x00000100,
275 0x9774, 0xffffffff, 0x00000100,
276 0x8984, 0xffffffff, 0x06000100,
277 0x8a18, 0xffffffff, 0x00000100,
278 0x92a0, 0xffffffff, 0x00000100,
279 0xc380, 0xffffffff, 0x00000100,
280 0x8b28, 0xffffffff, 0x00000100,
281 0x9144, 0xffffffff, 0x00000100,
282 0x8d88, 0xffffffff, 0x00000100,
283 0x8d8c, 0xffffffff, 0x00000100,
284 0x9030, 0xffffffff, 0x00000100,
285 0x9034, 0xffffffff, 0x00000100,
286 0x9038, 0xffffffff, 0x00000100,
287 0x903c, 0xffffffff, 0x00000100,
288 0xad80, 0xffffffff, 0x00000100,
289 0xac54, 0xffffffff, 0x00000100,
290 0x897c, 0xffffffff, 0x06000100,
291 0x9868, 0xffffffff, 0x00000100,
292 0x9510, 0xffffffff, 0x00000100,
293 0xaf04, 0xffffffff, 0x00000100,
294 0xae04, 0xffffffff, 0x00000100,
295 0x949c, 0xffffffff, 0x00000100,
296 0x802c, 0xffffffff, 0xe0000000,
297 0x9160, 0xffffffff, 0x00010000,
298 0x9164, 0xffffffff, 0x00030002,
299 0x9168, 0xffffffff, 0x00040007,
300 0x916c, 0xffffffff, 0x00060005,
301 0x9170, 0xffffffff, 0x00090008,
302 0x9174, 0xffffffff, 0x00020001,
303 0x9178, 0xffffffff, 0x00040003,
304 0x917c, 0xffffffff, 0x00000007,
305 0x9180, 0xffffffff, 0x00060005,
306 0x9184, 0xffffffff, 0x00090008,
307 0x9188, 0xffffffff, 0x00030002,
308 0x918c, 0xffffffff, 0x00050004,
309 0x9190, 0xffffffff, 0x00000008,
310 0x9194, 0xffffffff, 0x00070006,
311 0x9198, 0xffffffff, 0x000a0009,
312 0x919c, 0xffffffff, 0x00040003,
313 0x91a0, 0xffffffff, 0x00060005,
314 0x91a4, 0xffffffff, 0x00000009,
315 0x91a8, 0xffffffff, 0x00080007,
316 0x91ac, 0xffffffff, 0x000b000a,
317 0x91b0, 0xffffffff, 0x00050004,
318 0x91b4, 0xffffffff, 0x00070006,
319 0x91b8, 0xffffffff, 0x0008000b,
320 0x91bc, 0xffffffff, 0x000a0009,
321 0x91c0, 0xffffffff, 0x000d000c,
322 0x91c4, 0xffffffff, 0x00060005,
323 0x91c8, 0xffffffff, 0x00080007,
324 0x91cc, 0xffffffff, 0x0000000b,
325 0x91d0, 0xffffffff, 0x000a0009,
326 0x91d4, 0xffffffff, 0x000d000c,
327 0x91d8, 0xffffffff, 0x00070006,
328 0x91dc, 0xffffffff, 0x00090008,
329 0x91e0, 0xffffffff, 0x0000000c,
330 0x91e4, 0xffffffff, 0x000b000a,
331 0x91e8, 0xffffffff, 0x000e000d,
332 0x91ec, 0xffffffff, 0x00080007,
333 0x91f0, 0xffffffff, 0x000a0009,
334 0x91f4, 0xffffffff, 0x0000000d,
335 0x91f8, 0xffffffff, 0x000c000b,
336 0x91fc, 0xffffffff, 0x000f000e,
337 0x9200, 0xffffffff, 0x00090008,
338 0x9204, 0xffffffff, 0x000b000a,
339 0x9208, 0xffffffff, 0x000c000f,
340 0x920c, 0xffffffff, 0x000e000d,
341 0x9210, 0xffffffff, 0x00110010,
342 0x9214, 0xffffffff, 0x000a0009,
343 0x9218, 0xffffffff, 0x000c000b,
344 0x921c, 0xffffffff, 0x0000000f,
345 0x9220, 0xffffffff, 0x000e000d,
346 0x9224, 0xffffffff, 0x00110010,
347 0x9228, 0xffffffff, 0x000b000a,
348 0x922c, 0xffffffff, 0x000d000c,
349 0x9230, 0xffffffff, 0x00000010,
350 0x9234, 0xffffffff, 0x000f000e,
351 0x9238, 0xffffffff, 0x00120011,
352 0x923c, 0xffffffff, 0x000c000b,
353 0x9240, 0xffffffff, 0x000e000d,
354 0x9244, 0xffffffff, 0x00000011,
355 0x9248, 0xffffffff, 0x0010000f,
356 0x924c, 0xffffffff, 0x00130012,
357 0x9250, 0xffffffff, 0x000d000c,
358 0x9254, 0xffffffff, 0x000f000e,
359 0x9258, 0xffffffff, 0x00100013,
360 0x925c, 0xffffffff, 0x00120011,
361 0x9260, 0xffffffff, 0x00150014,
362 0x9264, 0xffffffff, 0x000e000d,
363 0x9268, 0xffffffff, 0x0010000f,
364 0x926c, 0xffffffff, 0x00000013,
365 0x9270, 0xffffffff, 0x00120011,
366 0x9274, 0xffffffff, 0x00150014,
367 0x9278, 0xffffffff, 0x000f000e,
368 0x927c, 0xffffffff, 0x00110010,
369 0x9280, 0xffffffff, 0x00000014,
370 0x9284, 0xffffffff, 0x00130012,
371 0x9288, 0xffffffff, 0x00160015,
372 0x928c, 0xffffffff, 0x0010000f,
373 0x9290, 0xffffffff, 0x00120011,
374 0x9294, 0xffffffff, 0x00000015,
375 0x9298, 0xffffffff, 0x00140013,
376 0x929c, 0xffffffff, 0x00170016,
377 0x9150, 0xffffffff, 0x96940200,
378 0x8708, 0xffffffff, 0x00900100,
379 0xc478, 0xffffffff, 0x00000080,
380 0xc404, 0xffffffff, 0x0020003f,
381 0x30, 0xffffffff, 0x0000001c,
382 0x34, 0x000f0000, 0x000f0000,
383 0x160c, 0xffffffff, 0x00000100,
384 0x1024, 0xffffffff, 0x00000100,
385 0x102c, 0x00000101, 0x00000000,
386 0x20a8, 0xffffffff, 0x00000104,
387 0x264c, 0x000c0000, 0x000c0000,
388 0x2648, 0x000c0000, 0x000c0000,
389 0x55e4, 0xff000fff, 0x00000100,
390 0x55e8, 0x00000001, 0x00000001,
391 0x2f50, 0x00000001, 0x00000001,
392 0x30cc, 0xc0000fff, 0x00000104,
393 0xc1e4, 0x00000001, 0x00000001,
394 0xd0c0, 0xfffffff0, 0x00000100,
395 0xd8c0, 0xfffffff0, 0x00000100
396};
397
398static const u32 pitcairn_mgcg_cgcg_init[] =
399{
400 0xc400, 0xffffffff, 0xfffffffc,
401 0x802c, 0xffffffff, 0xe0000000,
402 0x9a60, 0xffffffff, 0x00000100,
403 0x92a4, 0xffffffff, 0x00000100,
404 0xc164, 0xffffffff, 0x00000100,
405 0x9774, 0xffffffff, 0x00000100,
406 0x8984, 0xffffffff, 0x06000100,
407 0x8a18, 0xffffffff, 0x00000100,
408 0x92a0, 0xffffffff, 0x00000100,
409 0xc380, 0xffffffff, 0x00000100,
410 0x8b28, 0xffffffff, 0x00000100,
411 0x9144, 0xffffffff, 0x00000100,
412 0x8d88, 0xffffffff, 0x00000100,
413 0x8d8c, 0xffffffff, 0x00000100,
414 0x9030, 0xffffffff, 0x00000100,
415 0x9034, 0xffffffff, 0x00000100,
416 0x9038, 0xffffffff, 0x00000100,
417 0x903c, 0xffffffff, 0x00000100,
418 0xad80, 0xffffffff, 0x00000100,
419 0xac54, 0xffffffff, 0x00000100,
420 0x897c, 0xffffffff, 0x06000100,
421 0x9868, 0xffffffff, 0x00000100,
422 0x9510, 0xffffffff, 0x00000100,
423 0xaf04, 0xffffffff, 0x00000100,
424 0xae04, 0xffffffff, 0x00000100,
425 0x949c, 0xffffffff, 0x00000100,
426 0x802c, 0xffffffff, 0xe0000000,
427 0x9160, 0xffffffff, 0x00010000,
428 0x9164, 0xffffffff, 0x00030002,
429 0x9168, 0xffffffff, 0x00040007,
430 0x916c, 0xffffffff, 0x00060005,
431 0x9170, 0xffffffff, 0x00090008,
432 0x9174, 0xffffffff, 0x00020001,
433 0x9178, 0xffffffff, 0x00040003,
434 0x917c, 0xffffffff, 0x00000007,
435 0x9180, 0xffffffff, 0x00060005,
436 0x9184, 0xffffffff, 0x00090008,
437 0x9188, 0xffffffff, 0x00030002,
438 0x918c, 0xffffffff, 0x00050004,
439 0x9190, 0xffffffff, 0x00000008,
440 0x9194, 0xffffffff, 0x00070006,
441 0x9198, 0xffffffff, 0x000a0009,
442 0x919c, 0xffffffff, 0x00040003,
443 0x91a0, 0xffffffff, 0x00060005,
444 0x91a4, 0xffffffff, 0x00000009,
445 0x91a8, 0xffffffff, 0x00080007,
446 0x91ac, 0xffffffff, 0x000b000a,
447 0x91b0, 0xffffffff, 0x00050004,
448 0x91b4, 0xffffffff, 0x00070006,
449 0x91b8, 0xffffffff, 0x0008000b,
450 0x91bc, 0xffffffff, 0x000a0009,
451 0x91c0, 0xffffffff, 0x000d000c,
452 0x9200, 0xffffffff, 0x00090008,
453 0x9204, 0xffffffff, 0x000b000a,
454 0x9208, 0xffffffff, 0x000c000f,
455 0x920c, 0xffffffff, 0x000e000d,
456 0x9210, 0xffffffff, 0x00110010,
457 0x9214, 0xffffffff, 0x000a0009,
458 0x9218, 0xffffffff, 0x000c000b,
459 0x921c, 0xffffffff, 0x0000000f,
460 0x9220, 0xffffffff, 0x000e000d,
461 0x9224, 0xffffffff, 0x00110010,
462 0x9228, 0xffffffff, 0x000b000a,
463 0x922c, 0xffffffff, 0x000d000c,
464 0x9230, 0xffffffff, 0x00000010,
465 0x9234, 0xffffffff, 0x000f000e,
466 0x9238, 0xffffffff, 0x00120011,
467 0x923c, 0xffffffff, 0x000c000b,
468 0x9240, 0xffffffff, 0x000e000d,
469 0x9244, 0xffffffff, 0x00000011,
470 0x9248, 0xffffffff, 0x0010000f,
471 0x924c, 0xffffffff, 0x00130012,
472 0x9250, 0xffffffff, 0x000d000c,
473 0x9254, 0xffffffff, 0x000f000e,
474 0x9258, 0xffffffff, 0x00100013,
475 0x925c, 0xffffffff, 0x00120011,
476 0x9260, 0xffffffff, 0x00150014,
477 0x9150, 0xffffffff, 0x96940200,
478 0x8708, 0xffffffff, 0x00900100,
479 0xc478, 0xffffffff, 0x00000080,
480 0xc404, 0xffffffff, 0x0020003f,
481 0x30, 0xffffffff, 0x0000001c,
482 0x34, 0x000f0000, 0x000f0000,
483 0x160c, 0xffffffff, 0x00000100,
484 0x1024, 0xffffffff, 0x00000100,
485 0x102c, 0x00000101, 0x00000000,
486 0x20a8, 0xffffffff, 0x00000104,
487 0x55e4, 0xff000fff, 0x00000100,
488 0x55e8, 0x00000001, 0x00000001,
489 0x2f50, 0x00000001, 0x00000001,
490 0x30cc, 0xc0000fff, 0x00000104,
491 0xc1e4, 0x00000001, 0x00000001,
492 0xd0c0, 0xfffffff0, 0x00000100,
493 0xd8c0, 0xfffffff0, 0x00000100
494};
495
496static const u32 verde_mgcg_cgcg_init[] =
497{
498 0xc400, 0xffffffff, 0xfffffffc,
499 0x802c, 0xffffffff, 0xe0000000,
500 0x9a60, 0xffffffff, 0x00000100,
501 0x92a4, 0xffffffff, 0x00000100,
502 0xc164, 0xffffffff, 0x00000100,
503 0x9774, 0xffffffff, 0x00000100,
504 0x8984, 0xffffffff, 0x06000100,
505 0x8a18, 0xffffffff, 0x00000100,
506 0x92a0, 0xffffffff, 0x00000100,
507 0xc380, 0xffffffff, 0x00000100,
508 0x8b28, 0xffffffff, 0x00000100,
509 0x9144, 0xffffffff, 0x00000100,
510 0x8d88, 0xffffffff, 0x00000100,
511 0x8d8c, 0xffffffff, 0x00000100,
512 0x9030, 0xffffffff, 0x00000100,
513 0x9034, 0xffffffff, 0x00000100,
514 0x9038, 0xffffffff, 0x00000100,
515 0x903c, 0xffffffff, 0x00000100,
516 0xad80, 0xffffffff, 0x00000100,
517 0xac54, 0xffffffff, 0x00000100,
518 0x897c, 0xffffffff, 0x06000100,
519 0x9868, 0xffffffff, 0x00000100,
520 0x9510, 0xffffffff, 0x00000100,
521 0xaf04, 0xffffffff, 0x00000100,
522 0xae04, 0xffffffff, 0x00000100,
523 0x949c, 0xffffffff, 0x00000100,
524 0x802c, 0xffffffff, 0xe0000000,
525 0x9160, 0xffffffff, 0x00010000,
526 0x9164, 0xffffffff, 0x00030002,
527 0x9168, 0xffffffff, 0x00040007,
528 0x916c, 0xffffffff, 0x00060005,
529 0x9170, 0xffffffff, 0x00090008,
530 0x9174, 0xffffffff, 0x00020001,
531 0x9178, 0xffffffff, 0x00040003,
532 0x917c, 0xffffffff, 0x00000007,
533 0x9180, 0xffffffff, 0x00060005,
534 0x9184, 0xffffffff, 0x00090008,
535 0x9188, 0xffffffff, 0x00030002,
536 0x918c, 0xffffffff, 0x00050004,
537 0x9190, 0xffffffff, 0x00000008,
538 0x9194, 0xffffffff, 0x00070006,
539 0x9198, 0xffffffff, 0x000a0009,
540 0x919c, 0xffffffff, 0x00040003,
541 0x91a0, 0xffffffff, 0x00060005,
542 0x91a4, 0xffffffff, 0x00000009,
543 0x91a8, 0xffffffff, 0x00080007,
544 0x91ac, 0xffffffff, 0x000b000a,
545 0x91b0, 0xffffffff, 0x00050004,
546 0x91b4, 0xffffffff, 0x00070006,
547 0x91b8, 0xffffffff, 0x0008000b,
548 0x91bc, 0xffffffff, 0x000a0009,
549 0x91c0, 0xffffffff, 0x000d000c,
550 0x9200, 0xffffffff, 0x00090008,
551 0x9204, 0xffffffff, 0x000b000a,
552 0x9208, 0xffffffff, 0x000c000f,
553 0x920c, 0xffffffff, 0x000e000d,
554 0x9210, 0xffffffff, 0x00110010,
555 0x9214, 0xffffffff, 0x000a0009,
556 0x9218, 0xffffffff, 0x000c000b,
557 0x921c, 0xffffffff, 0x0000000f,
558 0x9220, 0xffffffff, 0x000e000d,
559 0x9224, 0xffffffff, 0x00110010,
560 0x9228, 0xffffffff, 0x000b000a,
561 0x922c, 0xffffffff, 0x000d000c,
562 0x9230, 0xffffffff, 0x00000010,
563 0x9234, 0xffffffff, 0x000f000e,
564 0x9238, 0xffffffff, 0x00120011,
565 0x923c, 0xffffffff, 0x000c000b,
566 0x9240, 0xffffffff, 0x000e000d,
567 0x9244, 0xffffffff, 0x00000011,
568 0x9248, 0xffffffff, 0x0010000f,
569 0x924c, 0xffffffff, 0x00130012,
570 0x9250, 0xffffffff, 0x000d000c,
571 0x9254, 0xffffffff, 0x000f000e,
572 0x9258, 0xffffffff, 0x00100013,
573 0x925c, 0xffffffff, 0x00120011,
574 0x9260, 0xffffffff, 0x00150014,
575 0x9150, 0xffffffff, 0x96940200,
576 0x8708, 0xffffffff, 0x00900100,
577 0xc478, 0xffffffff, 0x00000080,
578 0xc404, 0xffffffff, 0x0020003f,
579 0x30, 0xffffffff, 0x0000001c,
580 0x34, 0x000f0000, 0x000f0000,
581 0x160c, 0xffffffff, 0x00000100,
582 0x1024, 0xffffffff, 0x00000100,
583 0x102c, 0x00000101, 0x00000000,
584 0x20a8, 0xffffffff, 0x00000104,
585 0x264c, 0x000c0000, 0x000c0000,
586 0x2648, 0x000c0000, 0x000c0000,
587 0x55e4, 0xff000fff, 0x00000100,
588 0x55e8, 0x00000001, 0x00000001,
589 0x2f50, 0x00000001, 0x00000001,
590 0x30cc, 0xc0000fff, 0x00000104,
591 0xc1e4, 0x00000001, 0x00000001,
592 0xd0c0, 0xfffffff0, 0x00000100,
593 0xd8c0, 0xfffffff0, 0x00000100
594};
595
596static const u32 oland_mgcg_cgcg_init[] =
597{
598 0xc400, 0xffffffff, 0xfffffffc,
599 0x802c, 0xffffffff, 0xe0000000,
600 0x9a60, 0xffffffff, 0x00000100,
601 0x92a4, 0xffffffff, 0x00000100,
602 0xc164, 0xffffffff, 0x00000100,
603 0x9774, 0xffffffff, 0x00000100,
604 0x8984, 0xffffffff, 0x06000100,
605 0x8a18, 0xffffffff, 0x00000100,
606 0x92a0, 0xffffffff, 0x00000100,
607 0xc380, 0xffffffff, 0x00000100,
608 0x8b28, 0xffffffff, 0x00000100,
609 0x9144, 0xffffffff, 0x00000100,
610 0x8d88, 0xffffffff, 0x00000100,
611 0x8d8c, 0xffffffff, 0x00000100,
612 0x9030, 0xffffffff, 0x00000100,
613 0x9034, 0xffffffff, 0x00000100,
614 0x9038, 0xffffffff, 0x00000100,
615 0x903c, 0xffffffff, 0x00000100,
616 0xad80, 0xffffffff, 0x00000100,
617 0xac54, 0xffffffff, 0x00000100,
618 0x897c, 0xffffffff, 0x06000100,
619 0x9868, 0xffffffff, 0x00000100,
620 0x9510, 0xffffffff, 0x00000100,
621 0xaf04, 0xffffffff, 0x00000100,
622 0xae04, 0xffffffff, 0x00000100,
623 0x949c, 0xffffffff, 0x00000100,
624 0x802c, 0xffffffff, 0xe0000000,
625 0x9160, 0xffffffff, 0x00010000,
626 0x9164, 0xffffffff, 0x00030002,
627 0x9168, 0xffffffff, 0x00040007,
628 0x916c, 0xffffffff, 0x00060005,
629 0x9170, 0xffffffff, 0x00090008,
630 0x9174, 0xffffffff, 0x00020001,
631 0x9178, 0xffffffff, 0x00040003,
632 0x917c, 0xffffffff, 0x00000007,
633 0x9180, 0xffffffff, 0x00060005,
634 0x9184, 0xffffffff, 0x00090008,
635 0x9188, 0xffffffff, 0x00030002,
636 0x918c, 0xffffffff, 0x00050004,
637 0x9190, 0xffffffff, 0x00000008,
638 0x9194, 0xffffffff, 0x00070006,
639 0x9198, 0xffffffff, 0x000a0009,
640 0x919c, 0xffffffff, 0x00040003,
641 0x91a0, 0xffffffff, 0x00060005,
642 0x91a4, 0xffffffff, 0x00000009,
643 0x91a8, 0xffffffff, 0x00080007,
644 0x91ac, 0xffffffff, 0x000b000a,
645 0x91b0, 0xffffffff, 0x00050004,
646 0x91b4, 0xffffffff, 0x00070006,
647 0x91b8, 0xffffffff, 0x0008000b,
648 0x91bc, 0xffffffff, 0x000a0009,
649 0x91c0, 0xffffffff, 0x000d000c,
650 0x91c4, 0xffffffff, 0x00060005,
651 0x91c8, 0xffffffff, 0x00080007,
652 0x91cc, 0xffffffff, 0x0000000b,
653 0x91d0, 0xffffffff, 0x000a0009,
654 0x91d4, 0xffffffff, 0x000d000c,
655 0x9150, 0xffffffff, 0x96940200,
656 0x8708, 0xffffffff, 0x00900100,
657 0xc478, 0xffffffff, 0x00000080,
658 0xc404, 0xffffffff, 0x0020003f,
659 0x30, 0xffffffff, 0x0000001c,
660 0x34, 0x000f0000, 0x000f0000,
661 0x160c, 0xffffffff, 0x00000100,
662 0x1024, 0xffffffff, 0x00000100,
663 0x102c, 0x00000101, 0x00000000,
664 0x20a8, 0xffffffff, 0x00000104,
665 0x264c, 0x000c0000, 0x000c0000,
666 0x2648, 0x000c0000, 0x000c0000,
667 0x55e4, 0xff000fff, 0x00000100,
668 0x55e8, 0x00000001, 0x00000001,
669 0x2f50, 0x00000001, 0x00000001,
670 0x30cc, 0xc0000fff, 0x00000104,
671 0xc1e4, 0x00000001, 0x00000001,
672 0xd0c0, 0xfffffff0, 0x00000100,
673 0xd8c0, 0xfffffff0, 0x00000100
674};
675
676static u32 verde_pg_init[] =
677{
678 0x353c, 0xffffffff, 0x40000,
679 0x3538, 0xffffffff, 0x200010ff,
680 0x353c, 0xffffffff, 0x0,
681 0x353c, 0xffffffff, 0x0,
682 0x353c, 0xffffffff, 0x0,
683 0x353c, 0xffffffff, 0x0,
684 0x353c, 0xffffffff, 0x0,
685 0x353c, 0xffffffff, 0x7007,
686 0x3538, 0xffffffff, 0x300010ff,
687 0x353c, 0xffffffff, 0x0,
688 0x353c, 0xffffffff, 0x0,
689 0x353c, 0xffffffff, 0x0,
690 0x353c, 0xffffffff, 0x0,
691 0x353c, 0xffffffff, 0x0,
692 0x353c, 0xffffffff, 0x400000,
693 0x3538, 0xffffffff, 0x100010ff,
694 0x353c, 0xffffffff, 0x0,
695 0x353c, 0xffffffff, 0x0,
696 0x353c, 0xffffffff, 0x0,
697 0x353c, 0xffffffff, 0x0,
698 0x353c, 0xffffffff, 0x0,
699 0x353c, 0xffffffff, 0x120200,
700 0x3538, 0xffffffff, 0x500010ff,
701 0x353c, 0xffffffff, 0x0,
702 0x353c, 0xffffffff, 0x0,
703 0x353c, 0xffffffff, 0x0,
704 0x353c, 0xffffffff, 0x0,
705 0x353c, 0xffffffff, 0x0,
706 0x353c, 0xffffffff, 0x1e1e16,
707 0x3538, 0xffffffff, 0x600010ff,
708 0x353c, 0xffffffff, 0x0,
709 0x353c, 0xffffffff, 0x0,
710 0x353c, 0xffffffff, 0x0,
711 0x353c, 0xffffffff, 0x0,
712 0x353c, 0xffffffff, 0x0,
713 0x353c, 0xffffffff, 0x171f1e,
714 0x3538, 0xffffffff, 0x700010ff,
715 0x353c, 0xffffffff, 0x0,
716 0x353c, 0xffffffff, 0x0,
717 0x353c, 0xffffffff, 0x0,
718 0x353c, 0xffffffff, 0x0,
719 0x353c, 0xffffffff, 0x0,
720 0x353c, 0xffffffff, 0x0,
721 0x3538, 0xffffffff, 0x9ff,
722 0x3500, 0xffffffff, 0x0,
723 0x3504, 0xffffffff, 0x10000800,
724 0x3504, 0xffffffff, 0xf,
725 0x3504, 0xffffffff, 0xf,
726 0x3500, 0xffffffff, 0x4,
727 0x3504, 0xffffffff, 0x1000051e,
728 0x3504, 0xffffffff, 0xffff,
729 0x3504, 0xffffffff, 0xffff,
730 0x3500, 0xffffffff, 0x8,
731 0x3504, 0xffffffff, 0x80500,
732 0x3500, 0xffffffff, 0x12,
733 0x3504, 0xffffffff, 0x9050c,
734 0x3500, 0xffffffff, 0x1d,
735 0x3504, 0xffffffff, 0xb052c,
736 0x3500, 0xffffffff, 0x2a,
737 0x3504, 0xffffffff, 0x1053e,
738 0x3500, 0xffffffff, 0x2d,
739 0x3504, 0xffffffff, 0x10546,
740 0x3500, 0xffffffff, 0x30,
741 0x3504, 0xffffffff, 0xa054e,
742 0x3500, 0xffffffff, 0x3c,
743 0x3504, 0xffffffff, 0x1055f,
744 0x3500, 0xffffffff, 0x3f,
745 0x3504, 0xffffffff, 0x10567,
746 0x3500, 0xffffffff, 0x42,
747 0x3504, 0xffffffff, 0x1056f,
748 0x3500, 0xffffffff, 0x45,
749 0x3504, 0xffffffff, 0x10572,
750 0x3500, 0xffffffff, 0x48,
751 0x3504, 0xffffffff, 0x20575,
752 0x3500, 0xffffffff, 0x4c,
753 0x3504, 0xffffffff, 0x190801,
754 0x3500, 0xffffffff, 0x67,
755 0x3504, 0xffffffff, 0x1082a,
756 0x3500, 0xffffffff, 0x6a,
757 0x3504, 0xffffffff, 0x1b082d,
758 0x3500, 0xffffffff, 0x87,
759 0x3504, 0xffffffff, 0x310851,
760 0x3500, 0xffffffff, 0xba,
761 0x3504, 0xffffffff, 0x891,
762 0x3500, 0xffffffff, 0xbc,
763 0x3504, 0xffffffff, 0x893,
764 0x3500, 0xffffffff, 0xbe,
765 0x3504, 0xffffffff, 0x20895,
766 0x3500, 0xffffffff, 0xc2,
767 0x3504, 0xffffffff, 0x20899,
768 0x3500, 0xffffffff, 0xc6,
769 0x3504, 0xffffffff, 0x2089d,
770 0x3500, 0xffffffff, 0xca,
771 0x3504, 0xffffffff, 0x8a1,
772 0x3500, 0xffffffff, 0xcc,
773 0x3504, 0xffffffff, 0x8a3,
774 0x3500, 0xffffffff, 0xce,
775 0x3504, 0xffffffff, 0x308a5,
776 0x3500, 0xffffffff, 0xd3,
777 0x3504, 0xffffffff, 0x6d08cd,
778 0x3500, 0xffffffff, 0x142,
779 0x3504, 0xffffffff, 0x2000095a,
780 0x3504, 0xffffffff, 0x1,
781 0x3500, 0xffffffff, 0x144,
782 0x3504, 0xffffffff, 0x301f095b,
783 0x3500, 0xffffffff, 0x165,
784 0x3504, 0xffffffff, 0xc094d,
785 0x3500, 0xffffffff, 0x173,
786 0x3504, 0xffffffff, 0xf096d,
787 0x3500, 0xffffffff, 0x184,
788 0x3504, 0xffffffff, 0x15097f,
789 0x3500, 0xffffffff, 0x19b,
790 0x3504, 0xffffffff, 0xc0998,
791 0x3500, 0xffffffff, 0x1a9,
792 0x3504, 0xffffffff, 0x409a7,
793 0x3500, 0xffffffff, 0x1af,
794 0x3504, 0xffffffff, 0xcdc,
795 0x3500, 0xffffffff, 0x1b1,
796 0x3504, 0xffffffff, 0x800,
797 0x3508, 0xffffffff, 0x6c9b2000,
798 0x3510, 0xfc00, 0x2000,
799 0x3544, 0xffffffff, 0xfc0,
800 0x28d4, 0x00000100, 0x100
801};
802
803static void si_init_golden_registers(struct radeon_device *rdev)
804{
805 switch (rdev->family) {
806 case CHIP_TAHITI:
807 radeon_program_register_sequence(rdev,
808 tahiti_golden_registers,
809 (const u32)ARRAY_SIZE(tahiti_golden_registers));
810 radeon_program_register_sequence(rdev,
811 tahiti_golden_rlc_registers,
812 (const u32)ARRAY_SIZE(tahiti_golden_rlc_registers));
813 radeon_program_register_sequence(rdev,
814 tahiti_mgcg_cgcg_init,
815 (const u32)ARRAY_SIZE(tahiti_mgcg_cgcg_init));
816 radeon_program_register_sequence(rdev,
817 tahiti_golden_registers2,
818 (const u32)ARRAY_SIZE(tahiti_golden_registers2));
819 break;
820 case CHIP_PITCAIRN:
821 radeon_program_register_sequence(rdev,
822 pitcairn_golden_registers,
823 (const u32)ARRAY_SIZE(pitcairn_golden_registers));
824 radeon_program_register_sequence(rdev,
825 pitcairn_golden_rlc_registers,
826 (const u32)ARRAY_SIZE(pitcairn_golden_rlc_registers));
827 radeon_program_register_sequence(rdev,
828 pitcairn_mgcg_cgcg_init,
829 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
830 break;
831 case CHIP_VERDE:
832 radeon_program_register_sequence(rdev,
833 verde_golden_registers,
834 (const u32)ARRAY_SIZE(verde_golden_registers));
835 radeon_program_register_sequence(rdev,
836 verde_golden_rlc_registers,
837 (const u32)ARRAY_SIZE(verde_golden_rlc_registers));
838 radeon_program_register_sequence(rdev,
839 verde_mgcg_cgcg_init,
840 (const u32)ARRAY_SIZE(verde_mgcg_cgcg_init));
841 radeon_program_register_sequence(rdev,
842 verde_pg_init,
843 (const u32)ARRAY_SIZE(verde_pg_init));
844 break;
845 case CHIP_OLAND:
846 radeon_program_register_sequence(rdev,
847 oland_golden_registers,
848 (const u32)ARRAY_SIZE(oland_golden_registers));
849 radeon_program_register_sequence(rdev,
850 oland_golden_rlc_registers,
851 (const u32)ARRAY_SIZE(oland_golden_rlc_registers));
852 radeon_program_register_sequence(rdev,
853 oland_mgcg_cgcg_init,
854 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
855 break;
856 default:
857 break;
858 }
859}
860
73#define PCIE_BUS_CLK 10000 861#define PCIE_BUS_CLK 10000
74#define TCLK (PCIE_BUS_CLK / 10) 862#define TCLK (PCIE_BUS_CLK / 10)
75 863
@@ -1465,7 +2253,7 @@ static void si_select_se_sh(struct radeon_device *rdev,
1465 u32 data = INSTANCE_BROADCAST_WRITES; 2253 u32 data = INSTANCE_BROADCAST_WRITES;
1466 2254
1467 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff)) 2255 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1468 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES; 2256 data |= SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1469 else if (se_num == 0xffffffff) 2257 else if (se_num == 0xffffffff)
1470 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num); 2258 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1471 else if (sh_num == 0xffffffff) 2259 else if (sh_num == 0xffffffff)
@@ -4435,6 +5223,9 @@ int si_resume(struct radeon_device *rdev)
4435 /* post card */ 5223 /* post card */
4436 atom_asic_init(rdev->mode_info.atom_context); 5224 atom_asic_init(rdev->mode_info.atom_context);
4437 5225
5226 /* init golden registers */
5227 si_init_golden_registers(rdev);
5228
4438 rdev->accel_working = true; 5229 rdev->accel_working = true;
4439 r = si_startup(rdev); 5230 r = si_startup(rdev);
4440 if (r) { 5231 if (r) {
@@ -4494,6 +5285,8 @@ int si_init(struct radeon_device *rdev)
4494 DRM_INFO("GPU not posted. posting now...\n"); 5285 DRM_INFO("GPU not posted. posting now...\n");
4495 atom_asic_init(rdev->mode_info.atom_context); 5286 atom_asic_init(rdev->mode_info.atom_context);
4496 } 5287 }
5288 /* init golden registers */
5289 si_init_golden_registers(rdev);
4497 /* Initialize scratch registers */ 5290 /* Initialize scratch registers */
4498 si_scratch_init(rdev); 5291 si_scratch_init(rdev);
4499 /* Initialize surface registers */ 5292 /* Initialize surface registers */
@@ -4680,6 +5473,20 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
4680 unsigned vco_freq; 5473 unsigned vco_freq;
4681 int r; 5474 int r;
4682 5475
5476 /* bypass vclk and dclk with bclk */
5477 WREG32_P(CG_UPLL_FUNC_CNTL_2,
5478 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
5479 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
5480
5481 /* put PLL in bypass mode */
5482 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
5483
5484 if (!vclk || !dclk) {
5485 /* keep the Bypass mode, put PLL to sleep */
5486 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
5487 return 0;
5488 }
5489
4683 /* loop through vco from low to high */ 5490 /* loop through vco from low to high */
4684 for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) { 5491 for (vco_freq = 125000; vco_freq <= 250000; vco_freq += 100) {
4685 unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384; 5492 unsigned fb_div = vco_freq / rdev->clock.spll.reference_freq * 16384;
@@ -4730,14 +5537,6 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
4730 5537
4731 mdelay(1); 5538 mdelay(1);
4732 5539
4733 /* bypass vclk and dclk with bclk */
4734 WREG32_P(CG_UPLL_FUNC_CNTL_2,
4735 VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
4736 ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
4737
4738 /* put PLL in bypass mode */
4739 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
4740
4741 r = si_uvd_send_upll_ctlreq(rdev); 5540 r = si_uvd_send_upll_ctlreq(rdev);
4742 if (r) 5541 if (r)
4743 return r; 5542 return r;
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 5da1b4ae7d84..fc481fc17085 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -244,12 +244,21 @@ struct edid {
244 244
245#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 245#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
246 246
247/* Short Audio Descriptor */
248struct cea_sad {
249 u8 format;
250 u8 channels; /* max number of channels - 1 */
251 u8 freq;
252 u8 byte2; /* meaning depends on format */
253};
254
247struct drm_encoder; 255struct drm_encoder;
248struct drm_connector; 256struct drm_connector;
249struct drm_display_mode; 257struct drm_display_mode;
250struct hdmi_avi_infoframe; 258struct hdmi_avi_infoframe;
251 259
252void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); 260void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid);
261int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads);
253int drm_av_sync_delay(struct drm_connector *connector, 262int drm_av_sync_delay(struct drm_connector *connector,
254 struct drm_display_mode *mode); 263 struct drm_display_mode *mode);
255struct drm_connector *drm_select_eld(struct drm_encoder *encoder, 264struct drm_connector *drm_select_eld(struct drm_encoder *encoder,
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-16 11:38:39 -0400