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authorOlof Johansson <olof@lixom.net>2013-02-12 18:32:31 -0500
committerOlof Johansson <olof@lixom.net>2013-02-12 18:32:31 -0500
commit0a0db4a1e4c6dfd93411a4425b9f068f0da752c1 (patch)
tree69165abb6dd862c5dd7d2e4229a3799ebe1fc842
parent02ea21331e6e516b30eff563b98c742e9cadb373 (diff)
parent3ad4a33158b7a2589149bc5ab29a6723d755c4ba (diff)
Merge tag 'omap-for-v3.9/am33xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/omap
From Tony Lindgren: am33xx updates via Paul Walmsley <paul@pwsan.com>: Fixes and IP block support for the TI AM33xx family of SoCs. These are prerequisites for power management and some PWM driver changes. Basic test logs are available from: http://www.pwsan.com/omap/testlogs/am33xx_fixes_a_3.9/20130208084835/ although it must be noted that I am unable to test these patches on AM33xx due to an unknown problem with v3.8-rc kernels: http://www.mail-archive.com/linux-omap@vger.kernel.org/msg83525.html * tag 'omap-for-v3.9/am33xx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP2: am33xx-hwmod: Fix "register offset NULL check" bug ARM: OMAP2+: AM33xx: hwmod: add missing HWMOD_NO_IDLEST flags ARM: OMAP: AM33xx hwmod: Add parent-child relationship for PWM subsystem ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries ARM: DTS: AM33XX: Add nodes for OCMC RAM and WKUP-M3 ARM: OMAP2+: AM33XX: Update the hardreset API ARM: OMAP2+: AM33XX: hwmod: Update the WKUP-M3 hwmod with reset status bit ARM: OMAP2+: AM33XX: hwmod: Fixup cpgmac0 hwmod entry ARM: OMAP2+: AM33XX: hwmod: Update TPTC0 hwmod with the right flags ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod ARM: OMAP2+: AM33XX: CM/PRM: Use __ASSEMBLER__ macros in header files ARM: OMAP2+: AM33XX: CM: Get rid of unnecessary header inclusions
Diffstat
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi14
-rw-r--r--arch/arm/mach-omap2/cm33xx.c3
-rw-r--r--arch/arm/mach-omap2/cm33xx.h9
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c5
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c443
-rw-r--r--arch/arm/mach-omap2/prm33xx.c11
-rw-r--r--arch/arm/mach-omap2/prm33xx.h4
7 files changed, 306 insertions, 183 deletions
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index c2f14e875eb6..0957645b73af 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -385,5 +385,19 @@
385 mac-address = [ 00 00 00 00 00 00 ]; 385 mac-address = [ 00 00 00 00 00 00 ];
386 }; 386 };
387 }; 387 };
388
389 ocmcram: ocmcram@40300000 {
390 compatible = "ti,am3352-ocmcram";
391 reg = <0x40300000 0x10000>;
392 ti,hwmods = "ocmcram";
393 ti,no_idle_on_suspend;
394 };
395
396 wkup_m3: wkup_m3@44d00000 {
397 compatible = "ti,am3353-wkup-m3";
398 reg = <0x44d00000 0x4000 /* M3 UMEM */
399 0x44d80000 0x2000>; /* M3 DMEM */
400 ti,hwmods = "wkup_m3";
401 };
388 }; 402 };
389}; 403};
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 058ce3c0873e..325a51576576 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -241,9 +241,6 @@ int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
241{ 241{
242 int i = 0; 242 int i = 0;
243 243
244 if (!clkctrl_offs)
245 return 0;
246
247 omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs), 244 omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
248 MAX_MODULE_READY_TIME, i); 245 MAX_MODULE_READY_TIME, i);
249 246
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 5fa0b62e1a79..64f4bafe7bd9 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -17,16 +17,11 @@
17#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H 17#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
18#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H 18#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
19 19
20#include <linux/delay.h>
21#include <linux/errno.h>
22#include <linux/err.h>
23#include <linux/io.h>
24
25#include "common.h" 20#include "common.h"
26 21
27#include "cm.h" 22#include "cm.h"
28#include "cm-regbits-33xx.h" 23#include "cm-regbits-33xx.h"
29#include "cm33xx.h" 24#include "iomap.h"
30 25
31/* CM base address */ 26/* CM base address */
32#define AM33XX_CM_BASE 0x44e00000 27#define AM33XX_CM_BASE 0x44e00000
@@ -381,6 +376,7 @@
381#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020) 376#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
382 377
383 378
379#ifndef __ASSEMBLER__
384extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs); 380extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
385extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs); 381extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
386extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); 382extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
@@ -417,4 +413,5 @@ static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
417} 413}
418#endif 414#endif
419 415
416#endif /* ASSEMBLER */
420#endif 417#endif
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 4653efb87a27..6549439d8d5f 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3041,11 +3041,8 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
3041static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, 3041static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
3042 struct omap_hwmod_rst_info *ohri) 3042 struct omap_hwmod_rst_info *ohri)
3043{ 3043{
3044 if (ohri->st_shift)
3045 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
3046 oh->name, ohri->name);
3047
3048 return am33xx_prm_deassert_hardreset(ohri->rst_shift, 3044 return am33xx_prm_deassert_hardreset(ohri->rst_shift,
3045 ohri->st_shift,
3049 oh->clkdm->pwrdm.ptr->prcm_offs, 3046 oh->clkdm->pwrdm.ptr->prcm_offs,
3050 oh->prcm.omap4.rstctrl_offs, 3047 oh->prcm.omap4.rstctrl_offs,
3051 oh->prcm.omap4.rstst_offs); 3048 oh->prcm.omap4.rstst_offs);
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 646c14d9fdb9..26eee4a556ad 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -262,13 +262,15 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
262 .name = "wkup_m3", 262 .name = "wkup_m3",
263 .class = &am33xx_wkup_m3_hwmod_class, 263 .class = &am33xx_wkup_m3_hwmod_class,
264 .clkdm_name = "l4_wkup_aon_clkdm", 264 .clkdm_name = "l4_wkup_aon_clkdm",
265 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */ 265 /* Keep hardreset asserted */
266 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
266 .mpu_irqs = am33xx_wkup_m3_irqs, 267 .mpu_irqs = am33xx_wkup_m3_irqs,
267 .main_clk = "dpll_core_m4_div2_ck", 268 .main_clk = "dpll_core_m4_div2_ck",
268 .prcm = { 269 .prcm = {
269 .omap4 = { 270 .omap4 = {
270 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, 271 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
271 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, 272 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
273 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
272 .modulemode = MODULEMODE_SWCTRL, 274 .modulemode = MODULEMODE_SWCTRL,
273 }, 275 },
274 }, 276 },
@@ -414,7 +416,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
414 * - cEFUSE (doesn't fall under any ocp_if) 416 * - cEFUSE (doesn't fall under any ocp_if)
415 * - clkdiv32k 417 * - clkdiv32k
416 * - debugss 418 * - debugss
417 * - ocmc ram
418 * - ocp watch point 419 * - ocp watch point
419 * - aes0 420 * - aes0
420 * - sha0 421 * - sha0
@@ -481,25 +482,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
481 }, 482 },
482}; 483};
483 484
484/* ocmcram */
485static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
486 .name = "ocmcram",
487};
488
489static struct omap_hwmod am33xx_ocmcram_hwmod = {
490 .name = "ocmcram",
491 .class = &am33xx_ocmcram_hwmod_class,
492 .clkdm_name = "l3_clkdm",
493 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
494 .main_clk = "l3_gclk",
495 .prcm = {
496 .omap4 = {
497 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
498 .modulemode = MODULEMODE_SWCTRL,
499 },
500 },
501};
502
503/* ocpwp */ 485/* ocpwp */
504static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { 486static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
505 .name = "ocpwp", 487 .name = "ocpwp",
@@ -570,6 +552,25 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
570 552
571#endif 553#endif
572 554
555/* ocmcram */
556static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
557 .name = "ocmcram",
558};
559
560static struct omap_hwmod am33xx_ocmcram_hwmod = {
561 .name = "ocmcram",
562 .class = &am33xx_ocmcram_hwmod_class,
563 .clkdm_name = "l3_clkdm",
564 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
565 .main_clk = "l3_gclk",
566 .prcm = {
567 .omap4 = {
568 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
569 .modulemode = MODULEMODE_SWCTRL,
570 },
571 },
572};
573
573/* 'smartreflex' class */ 574/* 'smartreflex' class */
574static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { 575static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
575 .name = "smartreflex", 576 .name = "smartreflex",
@@ -783,9 +784,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
783 }, 784 },
784}; 785};
785 786
786/* 787/* pwmss */
787 * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
788 */
789static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { 788static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
790 .rev_offs = 0x0, 789 .rev_offs = 0x0,
791 .sysc_offs = 0x4, 790 .sysc_offs = 0x4,
@@ -801,18 +800,23 @@ static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
801 .sysc = &am33xx_epwmss_sysc, 800 .sysc = &am33xx_epwmss_sysc,
802}; 801};
803 802
804/* ehrpwm0 */ 803static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
805static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = { 804 .name = "ecap",
806 { .name = "int", .irq = 86 + OMAP_INTC_START, },
807 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
808 { .irq = -1 },
809}; 805};
810 806
811static struct omap_hwmod am33xx_ehrpwm0_hwmod = { 807static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
812 .name = "ehrpwm0", 808 .name = "eqep",
809};
810
811static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
812 .name = "ehrpwm",
813};
814
815/* epwmss0 */
816static struct omap_hwmod am33xx_epwmss0_hwmod = {
817 .name = "epwmss0",
813 .class = &am33xx_epwmss_hwmod_class, 818 .class = &am33xx_epwmss_hwmod_class,
814 .clkdm_name = "l4ls_clkdm", 819 .clkdm_name = "l4ls_clkdm",
815 .mpu_irqs = am33xx_ehrpwm0_irqs,
816 .main_clk = "l4ls_gclk", 820 .main_clk = "l4ls_gclk",
817 .prcm = { 821 .prcm = {
818 .omap4 = { 822 .omap4 = {
@@ -822,63 +826,58 @@ static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
822 }, 826 },
823}; 827};
824 828
825/* ehrpwm1 */ 829/* ecap0 */
826static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = { 830static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
827 { .name = "int", .irq = 87 + OMAP_INTC_START, }, 831 { .irq = 31 + OMAP_INTC_START, },
828 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
829 { .irq = -1 }, 832 { .irq = -1 },
830}; 833};
831 834
832static struct omap_hwmod am33xx_ehrpwm1_hwmod = { 835static struct omap_hwmod am33xx_ecap0_hwmod = {
833 .name = "ehrpwm1", 836 .name = "ecap0",
834 .class = &am33xx_epwmss_hwmod_class, 837 .class = &am33xx_ecap_hwmod_class,
835 .clkdm_name = "l4ls_clkdm", 838 .clkdm_name = "l4ls_clkdm",
836 .mpu_irqs = am33xx_ehrpwm1_irqs, 839 .mpu_irqs = am33xx_ecap0_irqs,
837 .main_clk = "l4ls_gclk", 840 .main_clk = "l4ls_gclk",
838 .prcm = {
839 .omap4 = {
840 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
841 .modulemode = MODULEMODE_SWCTRL,
842 },
843 },
844}; 841};
845 842
846/* ehrpwm2 */ 843/* eqep0 */
847static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = { 844static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
848 { .name = "int", .irq = 39 + OMAP_INTC_START, }, 845 { .irq = 79 + OMAP_INTC_START, },
849 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
850 { .irq = -1 }, 846 { .irq = -1 },
851}; 847};
852 848
853static struct omap_hwmod am33xx_ehrpwm2_hwmod = { 849static struct omap_hwmod am33xx_eqep0_hwmod = {
854 .name = "ehrpwm2", 850 .name = "eqep0",
855 .class = &am33xx_epwmss_hwmod_class, 851 .class = &am33xx_eqep_hwmod_class,
856 .clkdm_name = "l4ls_clkdm", 852 .clkdm_name = "l4ls_clkdm",
857 .mpu_irqs = am33xx_ehrpwm2_irqs, 853 .mpu_irqs = am33xx_eqep0_irqs,
858 .main_clk = "l4ls_gclk", 854 .main_clk = "l4ls_gclk",
859 .prcm = {
860 .omap4 = {
861 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
862 .modulemode = MODULEMODE_SWCTRL,
863 },
864 },
865}; 855};
866 856
867/* ecap0 */ 857/* ehrpwm0 */
868static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = { 858static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
869 { .irq = 31 + OMAP_INTC_START, }, 859 { .name = "int", .irq = 86 + OMAP_INTC_START, },
860 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
870 { .irq = -1 }, 861 { .irq = -1 },
871}; 862};
872 863
873static struct omap_hwmod am33xx_ecap0_hwmod = { 864static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
874 .name = "ecap0", 865 .name = "ehrpwm0",
866 .class = &am33xx_ehrpwm_hwmod_class,
867 .clkdm_name = "l4ls_clkdm",
868 .mpu_irqs = am33xx_ehrpwm0_irqs,
869 .main_clk = "l4ls_gclk",
870};
871
872/* epwmss1 */
873static struct omap_hwmod am33xx_epwmss1_hwmod = {
874 .name = "epwmss1",
875 .class = &am33xx_epwmss_hwmod_class, 875 .class = &am33xx_epwmss_hwmod_class,
876 .clkdm_name = "l4ls_clkdm", 876 .clkdm_name = "l4ls_clkdm",
877 .mpu_irqs = am33xx_ecap0_irqs,
878 .main_clk = "l4ls_gclk", 877 .main_clk = "l4ls_gclk",
879 .prcm = { 878 .prcm = {
880 .omap4 = { 879 .omap4 = {
881 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, 880 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
882 .modulemode = MODULEMODE_SWCTRL, 881 .modulemode = MODULEMODE_SWCTRL,
883 }, 882 },
884 }, 883 },
@@ -892,13 +891,50 @@ static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
892 891
893static struct omap_hwmod am33xx_ecap1_hwmod = { 892static struct omap_hwmod am33xx_ecap1_hwmod = {
894 .name = "ecap1", 893 .name = "ecap1",
895 .class = &am33xx_epwmss_hwmod_class, 894 .class = &am33xx_ecap_hwmod_class,
896 .clkdm_name = "l4ls_clkdm", 895 .clkdm_name = "l4ls_clkdm",
897 .mpu_irqs = am33xx_ecap1_irqs, 896 .mpu_irqs = am33xx_ecap1_irqs,
898 .main_clk = "l4ls_gclk", 897 .main_clk = "l4ls_gclk",
898};
899
900/* eqep1 */
901static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
902 { .irq = 88 + OMAP_INTC_START, },
903 { .irq = -1 },
904};
905
906static struct omap_hwmod am33xx_eqep1_hwmod = {
907 .name = "eqep1",
908 .class = &am33xx_eqep_hwmod_class,
909 .clkdm_name = "l4ls_clkdm",
910 .mpu_irqs = am33xx_eqep1_irqs,
911 .main_clk = "l4ls_gclk",
912};
913
914/* ehrpwm1 */
915static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
916 { .name = "int", .irq = 87 + OMAP_INTC_START, },
917 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
918 { .irq = -1 },
919};
920
921static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
922 .name = "ehrpwm1",
923 .class = &am33xx_ehrpwm_hwmod_class,
924 .clkdm_name = "l4ls_clkdm",
925 .mpu_irqs = am33xx_ehrpwm1_irqs,
926 .main_clk = "l4ls_gclk",
927};
928
929/* epwmss2 */
930static struct omap_hwmod am33xx_epwmss2_hwmod = {
931 .name = "epwmss2",
932 .class = &am33xx_epwmss_hwmod_class,
933 .clkdm_name = "l4ls_clkdm",
934 .main_clk = "l4ls_gclk",
899 .prcm = { 935 .prcm = {
900 .omap4 = { 936 .omap4 = {
901 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, 937 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
902 .modulemode = MODULEMODE_SWCTRL, 938 .modulemode = MODULEMODE_SWCTRL,
903 }, 939 },
904 }, 940 },
@@ -912,16 +948,39 @@ static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
912 948
913static struct omap_hwmod am33xx_ecap2_hwmod = { 949static struct omap_hwmod am33xx_ecap2_hwmod = {
914 .name = "ecap2", 950 .name = "ecap2",
951 .class = &am33xx_ecap_hwmod_class,
952 .clkdm_name = "l4ls_clkdm",
915 .mpu_irqs = am33xx_ecap2_irqs, 953 .mpu_irqs = am33xx_ecap2_irqs,
916 .class = &am33xx_epwmss_hwmod_class, 954 .main_clk = "l4ls_gclk",
955};
956
957/* eqep2 */
958static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
959 { .irq = 89 + OMAP_INTC_START, },
960 { .irq = -1 },
961};
962
963static struct omap_hwmod am33xx_eqep2_hwmod = {
964 .name = "eqep2",
965 .class = &am33xx_eqep_hwmod_class,
917 .clkdm_name = "l4ls_clkdm", 966 .clkdm_name = "l4ls_clkdm",
967 .mpu_irqs = am33xx_eqep2_irqs,
968 .main_clk = "l4ls_gclk",
969};
970
971/* ehrpwm2 */
972static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
973 { .name = "int", .irq = 39 + OMAP_INTC_START, },
974 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
975 { .irq = -1 },
976};
977
978static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
979 .name = "ehrpwm2",
980 .class = &am33xx_ehrpwm_hwmod_class,
981 .clkdm_name = "l4ls_clkdm",
982 .mpu_irqs = am33xx_ehrpwm2_irqs,
918 .main_clk = "l4ls_gclk", 983 .main_clk = "l4ls_gclk",
919 .prcm = {
920 .omap4 = {
921 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
922 .modulemode = MODULEMODE_SWCTRL,
923 },
924 },
925}; 984};
926 985
927/* 986/*
@@ -1824,6 +1883,7 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
1824 .class = &am33xx_tptc_hwmod_class, 1883 .class = &am33xx_tptc_hwmod_class,
1825 .clkdm_name = "l3_clkdm", 1884 .clkdm_name = "l3_clkdm",
1826 .mpu_irqs = am33xx_tptc0_irqs, 1885 .mpu_irqs = am33xx_tptc0_irqs,
1886 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1827 .main_clk = "l3_gclk", 1887 .main_clk = "l3_gclk",
1828 .prcm = { 1888 .prcm = {
1829 .omap4 = { 1889 .omap4 = {
@@ -2496,7 +2556,6 @@ static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2496 { 2556 {
2497 .pa_start = 0x4a100000, 2557 .pa_start = 0x4a100000,
2498 .pa_end = 0x4a100000 + SZ_2K - 1, 2558 .pa_end = 0x4a100000 + SZ_2K - 1,
2499 .flags = ADDR_TYPE_RT,
2500 }, 2559 },
2501 /* cpsw wr */ 2560 /* cpsw wr */
2502 { 2561 {
@@ -2547,162 +2606,202 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2547 .user = OCP_USER_MPU, 2606 .user = OCP_USER_MPU,
2548}; 2607};
2549 2608
2550/* 2609static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
2551 * Splitting the resources to handle access of PWMSS config space
2552 * and module specific part independently
2553 */
2554static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2555 { 2610 {
2556 .pa_start = 0x48300000, 2611 .pa_start = 0x48300000,
2557 .pa_end = 0x48300000 + SZ_16 - 1, 2612 .pa_end = 0x48300000 + SZ_16 - 1,
2558 .flags = ADDR_TYPE_RT 2613 .flags = ADDR_TYPE_RT
2559 }, 2614 },
2560 {
2561 .pa_start = 0x48300200,
2562 .pa_end = 0x48300200 + SZ_256 - 1,
2563 .flags = ADDR_TYPE_RT
2564 },
2565 { } 2615 { }
2566}; 2616};
2567 2617
2568static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = { 2618static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
2569 .master = &am33xx_l4_ls_hwmod, 2619 .master = &am33xx_l4_ls_hwmod,
2570 .slave = &am33xx_ehrpwm0_hwmod, 2620 .slave = &am33xx_epwmss0_hwmod,
2571 .clk = "l4ls_gclk", 2621 .clk = "l4ls_gclk",
2572 .addr = am33xx_ehrpwm0_addr_space, 2622 .addr = am33xx_epwmss0_addr_space,
2573 .user = OCP_USER_MPU, 2623 .user = OCP_USER_MPU,
2574}; 2624};
2575 2625
2576/* 2626static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2577 * Splitting the resources to handle access of PWMSS config space
2578 * and module specific part independently
2579 */
2580static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2581 {
2582 .pa_start = 0x48302000,
2583 .pa_end = 0x48302000 + SZ_16 - 1,
2584 .flags = ADDR_TYPE_RT
2585 },
2586 { 2627 {
2587 .pa_start = 0x48302200, 2628 .pa_start = 0x48300100,
2588 .pa_end = 0x48302200 + SZ_256 - 1, 2629 .pa_end = 0x48300100 + SZ_128 - 1,
2589 .flags = ADDR_TYPE_RT
2590 }, 2630 },
2591 { } 2631 { }
2592}; 2632};
2593 2633
2594static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = { 2634static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
2595 .master = &am33xx_l4_ls_hwmod, 2635 .master = &am33xx_epwmss0_hwmod,
2596 .slave = &am33xx_ehrpwm1_hwmod, 2636 .slave = &am33xx_ecap0_hwmod,
2597 .clk = "l4ls_gclk", 2637 .clk = "l4ls_gclk",
2598 .addr = am33xx_ehrpwm1_addr_space, 2638 .addr = am33xx_ecap0_addr_space,
2599 .user = OCP_USER_MPU, 2639 .user = OCP_USER_MPU,
2600}; 2640};
2601 2641
2602/* 2642static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2603 * Splitting the resources to handle access of PWMSS config space
2604 * and module specific part independently
2605 */
2606static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2607 { 2643 {
2608 .pa_start = 0x48304000, 2644 .pa_start = 0x48300180,
2609 .pa_end = 0x48304000 + SZ_16 - 1, 2645 .pa_end = 0x48300180 + SZ_128 - 1,
2610 .flags = ADDR_TYPE_RT
2611 },
2612 {
2613 .pa_start = 0x48304200,
2614 .pa_end = 0x48304200 + SZ_256 - 1,
2615 .flags = ADDR_TYPE_RT
2616 }, 2646 },
2617 { } 2647 { }
2618}; 2648};
2619 2649
2620static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = { 2650static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
2621 .master = &am33xx_l4_ls_hwmod, 2651 .master = &am33xx_epwmss0_hwmod,
2622 .slave = &am33xx_ehrpwm2_hwmod, 2652 .slave = &am33xx_eqep0_hwmod,
2623 .clk = "l4ls_gclk", 2653 .clk = "l4ls_gclk",
2624 .addr = am33xx_ehrpwm2_addr_space, 2654 .addr = am33xx_eqep0_addr_space,
2625 .user = OCP_USER_MPU, 2655 .user = OCP_USER_MPU,
2626}; 2656};
2627 2657
2628/* 2658static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2629 * Splitting the resources to handle access of PWMSS config space
2630 * and module specific part independently
2631 */
2632static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2633 {
2634 .pa_start = 0x48300000,
2635 .pa_end = 0x48300000 + SZ_16 - 1,
2636 .flags = ADDR_TYPE_RT
2637 },
2638 { 2659 {
2639 .pa_start = 0x48300100, 2660 .pa_start = 0x48300200,
2640 .pa_end = 0x48300100 + SZ_256 - 1, 2661 .pa_end = 0x48300200 + SZ_128 - 1,
2641 .flags = ADDR_TYPE_RT
2642 }, 2662 },
2643 { } 2663 { }
2644}; 2664};
2645 2665
2646static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = { 2666static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2647 .master = &am33xx_l4_ls_hwmod, 2667 .master = &am33xx_epwmss0_hwmod,
2648 .slave = &am33xx_ecap0_hwmod, 2668 .slave = &am33xx_ehrpwm0_hwmod,
2649 .clk = "l4ls_gclk", 2669 .clk = "l4ls_gclk",
2650 .addr = am33xx_ecap0_addr_space, 2670 .addr = am33xx_ehrpwm0_addr_space,
2651 .user = OCP_USER_MPU, 2671 .user = OCP_USER_MPU,
2652}; 2672};
2653 2673
2654/* 2674
2655 * Splitting the resources to handle access of PWMSS config space 2675static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
2656 * and module specific part independently
2657 */
2658static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2659 { 2676 {
2660 .pa_start = 0x48302000, 2677 .pa_start = 0x48302000,
2661 .pa_end = 0x48302000 + SZ_16 - 1, 2678 .pa_end = 0x48302000 + SZ_16 - 1,
2662 .flags = ADDR_TYPE_RT 2679 .flags = ADDR_TYPE_RT
2663 }, 2680 },
2681 { }
2682};
2683
2684static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2685 .master = &am33xx_l4_ls_hwmod,
2686 .slave = &am33xx_epwmss1_hwmod,
2687 .clk = "l4ls_gclk",
2688 .addr = am33xx_epwmss1_addr_space,
2689 .user = OCP_USER_MPU,
2690};
2691
2692static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2664 { 2693 {
2665 .pa_start = 0x48302100, 2694 .pa_start = 0x48302100,
2666 .pa_end = 0x48302100 + SZ_256 - 1, 2695 .pa_end = 0x48302100 + SZ_128 - 1,
2667 .flags = ADDR_TYPE_RT
2668 }, 2696 },
2669 { } 2697 { }
2670}; 2698};
2671 2699
2672static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = { 2700static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2673 .master = &am33xx_l4_ls_hwmod, 2701 .master = &am33xx_epwmss1_hwmod,
2674 .slave = &am33xx_ecap1_hwmod, 2702 .slave = &am33xx_ecap1_hwmod,
2675 .clk = "l4ls_gclk", 2703 .clk = "l4ls_gclk",
2676 .addr = am33xx_ecap1_addr_space, 2704 .addr = am33xx_ecap1_addr_space,
2677 .user = OCP_USER_MPU, 2705 .user = OCP_USER_MPU,
2678}; 2706};
2679 2707
2680/* 2708static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2681 * Splitting the resources to handle access of PWMSS config space 2709 {
2682 * and module specific part independently 2710 .pa_start = 0x48302180,
2683 */ 2711 .pa_end = 0x48302180 + SZ_128 - 1,
2684static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = { 2712 },
2713 { }
2714};
2715
2716static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2717 .master = &am33xx_epwmss1_hwmod,
2718 .slave = &am33xx_eqep1_hwmod,
2719 .clk = "l4ls_gclk",
2720 .addr = am33xx_eqep1_addr_space,
2721 .user = OCP_USER_MPU,
2722};
2723
2724static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2725 {
2726 .pa_start = 0x48302200,
2727 .pa_end = 0x48302200 + SZ_128 - 1,
2728 },
2729 { }
2730};
2731
2732static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2733 .master = &am33xx_epwmss1_hwmod,
2734 .slave = &am33xx_ehrpwm1_hwmod,
2735 .clk = "l4ls_gclk",
2736 .addr = am33xx_ehrpwm1_addr_space,
2737 .user = OCP_USER_MPU,
2738};
2739
2740static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
2685 { 2741 {
2686 .pa_start = 0x48304000, 2742 .pa_start = 0x48304000,
2687 .pa_end = 0x48304000 + SZ_16 - 1, 2743 .pa_end = 0x48304000 + SZ_16 - 1,
2688 .flags = ADDR_TYPE_RT 2744 .flags = ADDR_TYPE_RT
2689 }, 2745 },
2746 { }
2747};
2748
2749static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2750 .master = &am33xx_l4_ls_hwmod,
2751 .slave = &am33xx_epwmss2_hwmod,
2752 .clk = "l4ls_gclk",
2753 .addr = am33xx_epwmss2_addr_space,
2754 .user = OCP_USER_MPU,
2755};
2756
2757static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2690 { 2758 {
2691 .pa_start = 0x48304100, 2759 .pa_start = 0x48304100,
2692 .pa_end = 0x48304100 + SZ_256 - 1, 2760 .pa_end = 0x48304100 + SZ_128 - 1,
2693 .flags = ADDR_TYPE_RT
2694 }, 2761 },
2695 { } 2762 { }
2696}; 2763};
2697 2764
2698static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = { 2765static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2699 .master = &am33xx_l4_ls_hwmod, 2766 .master = &am33xx_epwmss2_hwmod,
2700 .slave = &am33xx_ecap2_hwmod, 2767 .slave = &am33xx_ecap2_hwmod,
2701 .clk = "l4ls_gclk", 2768 .clk = "l4ls_gclk",
2702 .addr = am33xx_ecap2_addr_space, 2769 .addr = am33xx_ecap2_addr_space,
2703 .user = OCP_USER_MPU, 2770 .user = OCP_USER_MPU,
2704}; 2771};
2705 2772
2773static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2774 {
2775 .pa_start = 0x48304180,
2776 .pa_end = 0x48304180 + SZ_128 - 1,
2777 },
2778 { }
2779};
2780
2781static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2782 .master = &am33xx_epwmss2_hwmod,
2783 .slave = &am33xx_eqep2_hwmod,
2784 .clk = "l4ls_gclk",
2785 .addr = am33xx_eqep2_addr_space,
2786 .user = OCP_USER_MPU,
2787};
2788
2789static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2790 {
2791 .pa_start = 0x48304200,
2792 .pa_end = 0x48304200 + SZ_128 - 1,
2793 },
2794 { }
2795};
2796
2797static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2798 .master = &am33xx_epwmss2_hwmod,
2799 .slave = &am33xx_ehrpwm2_hwmod,
2800 .clk = "l4ls_gclk",
2801 .addr = am33xx_ehrpwm2_addr_space,
2802 .user = OCP_USER_MPU,
2803};
2804
2706/* l3s cfg -> gpmc */ 2805/* l3s cfg -> gpmc */
2707static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { 2806static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2708 { 2807 {
@@ -3328,6 +3427,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3328 .flags = OCPIF_SWSUP_IDLE, 3427 .flags = OCPIF_SWSUP_IDLE,
3329}; 3428};
3330 3429
3430/* l3 main -> ocmc */
3431static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
3432 .master = &am33xx_l3_main_hwmod,
3433 .slave = &am33xx_ocmcram_hwmod,
3434 .user = OCP_USER_MPU | OCP_USER_SDMA,
3435};
3436
3331static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { 3437static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3332 &am33xx_l4_fw__emif_fw, 3438 &am33xx_l4_fw__emif_fw,
3333 &am33xx_l3_main__emif, 3439 &am33xx_l3_main__emif,
@@ -3385,12 +3491,18 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3385 &am33xx_l4_ls__uart6, 3491 &am33xx_l4_ls__uart6,
3386 &am33xx_l4_ls__spinlock, 3492 &am33xx_l4_ls__spinlock,
3387 &am33xx_l4_ls__elm, 3493 &am33xx_l4_ls__elm,
3388 &am33xx_l4_ls__ehrpwm0, 3494 &am33xx_l4_ls__epwmss0,
3389 &am33xx_l4_ls__ehrpwm1, 3495 &am33xx_epwmss0__ecap0,
3390 &am33xx_l4_ls__ehrpwm2, 3496 &am33xx_epwmss0__eqep0,
3391 &am33xx_l4_ls__ecap0, 3497 &am33xx_epwmss0__ehrpwm0,
3392 &am33xx_l4_ls__ecap1, 3498 &am33xx_l4_ls__epwmss1,
3393 &am33xx_l4_ls__ecap2, 3499 &am33xx_epwmss1__ecap1,
3500 &am33xx_epwmss1__eqep1,
3501 &am33xx_epwmss1__ehrpwm1,
3502 &am33xx_l4_ls__epwmss2,
3503 &am33xx_epwmss2__ecap2,
3504 &am33xx_epwmss2__eqep2,
3505 &am33xx_epwmss2__ehrpwm2,
3394 &am33xx_l3_s__gpmc, 3506 &am33xx_l3_s__gpmc,
3395 &am33xx_l3_main__lcdc, 3507 &am33xx_l3_main__lcdc,
3396 &am33xx_l4_ls__mcspi0, 3508 &am33xx_l4_ls__mcspi0,
@@ -3398,6 +3510,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3398 &am33xx_l3_main__tptc0, 3510 &am33xx_l3_main__tptc0,
3399 &am33xx_l3_main__tptc1, 3511 &am33xx_l3_main__tptc1,
3400 &am33xx_l3_main__tptc2, 3512 &am33xx_l3_main__tptc2,
3513 &am33xx_l3_main__ocmc,
3401 &am33xx_l3_s__usbss, 3514 &am33xx_l3_s__usbss,
3402 &am33xx_l4_hs__cpgmac0, 3515 &am33xx_l4_hs__cpgmac0,
3403 &am33xx_cpgmac0__mdio, 3516 &am33xx_cpgmac0__mdio,
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 1ac73883f891..44c0d7216aa7 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -110,11 +110,11 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
110 * -EINVAL upon an argument error, -EEXIST if the submodule was already out 110 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
111 * of reset, or -EBUSY if the submodule did not exit reset promptly. 111 * of reset, or -EBUSY if the submodule did not exit reset promptly.
112 */ 112 */
113int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, 113int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
114 u16 rstctrl_offs, u16 rstst_offs) 114 u16 rstctrl_offs, u16 rstst_offs)
115{ 115{
116 int c; 116 int c;
117 u32 mask = 1 << shift; 117 u32 mask = 1 << st_shift;
118 118
119 /* Check the current status to avoid de-asserting the line twice */ 119 /* Check the current status to avoid de-asserting the line twice */
120 if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0) 120 if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
@@ -122,11 +122,14 @@ int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
122 122
123 /* Clear the reset status by writing 1 to the status bit */ 123 /* Clear the reset status by writing 1 to the status bit */
124 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs); 124 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
125
125 /* de-assert the reset control line */ 126 /* de-assert the reset control line */
127 mask = 1 << shift;
128
126 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs); 129 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
127 /* wait the status to be set */
128 130
129 omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst, 131 /* wait the status to be set */
132 omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, inst,
130 rstst_offs), 133 rstst_offs),
131 MAX_MODULE_HARDRESET_WAIT, c); 134 MAX_MODULE_HARDRESET_WAIT, c);
132 135
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 3f25c563a821..9b9918dfb119 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -117,6 +117,7 @@
117#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004 117#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004
118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) 118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
119 119
120#ifndef __ASSEMBLER__
120extern u32 am33xx_prm_read_reg(s16 inst, u16 idx); 121extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
121extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx); 122extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
122extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); 123extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
@@ -124,6 +125,7 @@ extern void am33xx_prm_global_warm_sw_reset(void);
124extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, 125extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
125 u16 rstctrl_offs); 126 u16 rstctrl_offs);
126extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs); 127extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
127extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, 128extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
128 u16 rstctrl_offs, u16 rstst_offs); 129 u16 rstctrl_offs, u16 rstst_offs);
130#endif /* ASSEMBLER */
129#endif 131#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-02-27 06:41:47 -0500