diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2013-05-22 11:22:51 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-05-29 11:35:05 -0400 |
| commit | 09fb8bd1a63b0f9f15e655c4fe8d047e5d2bf67a (patch) | |
| tree | 0244eb117d9ee073c32ea4a50251e1dfe6c4225d | |
| parent | 468ef1a58c9268ac9709350bf95eaf1c22a69f29 (diff) | |
drm/radeon: fix card_posted check for newer asics
Newer asics have variable numbers of crtcs. Use that
rather than the asic family to determine which crtcs
to check. This avoids checking non-existent crtcs or
missing crtcs on certain asics.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_device.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c index c2c59fb1ea01..89cc8166db94 100644 --- a/drivers/gpu/drm/radeon/radeon_device.c +++ b/drivers/gpu/drm/radeon/radeon_device.c | |||
| @@ -472,18 +472,17 @@ bool radeon_card_posted(struct radeon_device *rdev) | |||
| 472 | return false; | 472 | return false; |
| 473 | 473 | ||
| 474 | /* first check CRTCs */ | 474 | /* first check CRTCs */ |
| 475 | if (ASIC_IS_DCE41(rdev)) { | 475 | if (ASIC_IS_DCE4(rdev)) { |
| 476 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | | 476 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
| 477 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); | 477 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
| 478 | if (reg & EVERGREEN_CRTC_MASTER_EN) | 478 | if (rdev->num_crtc >= 4) { |
| 479 | return true; | 479 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
| 480 | } else if (ASIC_IS_DCE4(rdev)) { | 480 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); |
| 481 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | | 481 | } |
| 482 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | | 482 | if (rdev->num_crtc >= 6) { |
| 483 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | | 483 | reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
| 484 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | | 484 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
| 485 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | | 485 | } |
| 486 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); | ||
| 487 | if (reg & EVERGREEN_CRTC_MASTER_EN) | 486 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
| 488 | return true; | 487 | return true; |
| 489 | } else if (ASIC_IS_AVIVO(rdev)) { | 488 | } else if (ASIC_IS_AVIVO(rdev)) { |