diff options
author | Sean Paul <seanpaul@chromium.org> | 2013-01-14 17:03:20 -0500 |
---|---|---|
committer | Inki Dae <inki.dae@samsung.com> | 2013-01-25 00:38:45 -0500 |
commit | 09760ea34965a48d39e58607945e5e69edba01e6 (patch) | |
tree | d39a843936674acec721770328247a2169f316e6 | |
parent | 0bc4a0aa377ec5e6e3bd2b8ac963a008d8e1401b (diff) |
drm/exynos: Replace mdelay with usleep_range
Replace the unnecessary atomic mdelay calls with usleep_range calls.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_hdmi.c | 14 | ||||
-rw-r--r-- | drivers/gpu/drm/exynos/exynos_mixer.c | 2 |
2 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c index 24dbb7f7c290..b490afa781dc 100644 --- a/drivers/gpu/drm/exynos/exynos_hdmi.c +++ b/drivers/gpu/drm/exynos/exynos_hdmi.c | |||
@@ -1647,9 +1647,9 @@ static void hdmi_conf_reset(struct hdmi_context *hdata) | |||
1647 | 1647 | ||
1648 | /* resetting HDMI core */ | 1648 | /* resetting HDMI core */ |
1649 | hdmi_reg_writemask(hdata, reg, 0, HDMI_CORE_SW_RSTOUT); | 1649 | hdmi_reg_writemask(hdata, reg, 0, HDMI_CORE_SW_RSTOUT); |
1650 | mdelay(10); | 1650 | usleep_range(10000, 12000); |
1651 | hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT); | 1651 | hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT); |
1652 | mdelay(10); | 1652 | usleep_range(10000, 12000); |
1653 | } | 1653 | } |
1654 | 1654 | ||
1655 | static void hdmi_conf_init(struct hdmi_context *hdata) | 1655 | static void hdmi_conf_init(struct hdmi_context *hdata) |
@@ -1774,7 +1774,7 @@ static void hdmi_v13_timing_apply(struct hdmi_context *hdata) | |||
1774 | u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS); | 1774 | u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS); |
1775 | if (val & HDMI_PHY_STATUS_READY) | 1775 | if (val & HDMI_PHY_STATUS_READY) |
1776 | break; | 1776 | break; |
1777 | mdelay(1); | 1777 | usleep_range(1000, 2000); |
1778 | } | 1778 | } |
1779 | /* steady state not achieved */ | 1779 | /* steady state not achieved */ |
1780 | if (tries == 0) { | 1780 | if (tries == 0) { |
@@ -1941,7 +1941,7 @@ static void hdmi_v14_timing_apply(struct hdmi_context *hdata) | |||
1941 | u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0); | 1941 | u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0); |
1942 | if (val & HDMI_PHY_STATUS_READY) | 1942 | if (val & HDMI_PHY_STATUS_READY) |
1943 | break; | 1943 | break; |
1944 | mdelay(1); | 1944 | usleep_range(1000, 2000); |
1945 | } | 1945 | } |
1946 | /* steady state not achieved */ | 1946 | /* steady state not achieved */ |
1947 | if (tries == 0) { | 1947 | if (tries == 0) { |
@@ -1993,9 +1993,9 @@ static void hdmiphy_conf_reset(struct hdmi_context *hdata) | |||
1993 | 1993 | ||
1994 | /* reset hdmiphy */ | 1994 | /* reset hdmiphy */ |
1995 | hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT); | 1995 | hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT); |
1996 | mdelay(10); | 1996 | usleep_range(10000, 12000); |
1997 | hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT); | 1997 | hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT); |
1998 | mdelay(10); | 1998 | usleep_range(10000, 12000); |
1999 | } | 1999 | } |
2000 | 2000 | ||
2001 | static void hdmiphy_poweron(struct hdmi_context *hdata) | 2001 | static void hdmiphy_poweron(struct hdmi_context *hdata) |
@@ -2043,7 +2043,7 @@ static void hdmiphy_conf_apply(struct hdmi_context *hdata) | |||
2043 | return; | 2043 | return; |
2044 | } | 2044 | } |
2045 | 2045 | ||
2046 | mdelay(10); | 2046 | usleep_range(10000, 12000); |
2047 | 2047 | ||
2048 | /* operation mode */ | 2048 | /* operation mode */ |
2049 | operation[0] = 0x1f; | 2049 | operation[0] = 0x1f; |
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c index c187ea33b748..1ff2d7a045b5 100644 --- a/drivers/gpu/drm/exynos/exynos_mixer.c +++ b/drivers/gpu/drm/exynos/exynos_mixer.c | |||
@@ -600,7 +600,7 @@ static void vp_win_reset(struct mixer_context *ctx) | |||
600 | /* waiting until VP_SRESET_PROCESSING is 0 */ | 600 | /* waiting until VP_SRESET_PROCESSING is 0 */ |
601 | if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING) | 601 | if (~vp_reg_read(res, VP_SRESET) & VP_SRESET_PROCESSING) |
602 | break; | 602 | break; |
603 | mdelay(10); | 603 | usleep_range(10000, 12000); |
604 | } | 604 | } |
605 | WARN(tries == 0, "failed to reset Video Processor\n"); | 605 | WARN(tries == 0, "failed to reset Video Processor\n"); |
606 | } | 606 | } |