diff options
author | Alexander Shiyan <shc_work@mail.ru> | 2013-12-31 11:49:42 -0500 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-01-07 20:06:18 -0500 |
commit | 093a9e2a20ebc414f8ca0d31709dab1040fa2886 (patch) | |
tree | 8403b0108980e2e14d01fdf08b76d99e7008c685 | |
parent | 71b9e8c6694f5cfe6cd37d53d6c24a33f1f59abd (diff) |
serial: clps711x: Enable driver compilation with COMPILE_TEST
This helps increasing build testing coverage.
To do this, read{write}_relaxed() functions was be replaced with
simple read{write}() variants. Potential "uninitialized variable"
warnings was be fixed if driver compiled without MFD_SYSCON.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r-- | drivers/tty/serial/Kconfig | 3 | ||||
-rw-r--r-- | drivers/tty/serial/clps711x.c | 40 |
2 files changed, 23 insertions, 20 deletions
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 7fbbbadea2dd..441ada489874 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig | |||
@@ -181,9 +181,8 @@ config SERIAL_KS8695_CONSOLE | |||
181 | 181 | ||
182 | config SERIAL_CLPS711X | 182 | config SERIAL_CLPS711X |
183 | tristate "CLPS711X serial port support" | 183 | tristate "CLPS711X serial port support" |
184 | depends on ARCH_CLPS711X | 184 | depends on ARCH_CLPS711X || COMPILE_TEST |
185 | select SERIAL_CORE | 185 | select SERIAL_CORE |
186 | default y | ||
187 | help | 186 | help |
188 | This enables the driver for the on-chip UARTs of the Cirrus | 187 | This enables the driver for the on-chip UARTs of the Cirrus |
189 | Logic EP711x/EP721x/EP731x processors. | 188 | Logic EP711x/EP721x/EP731x processors. |
diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c index 5a931f97aa7c..b0eacb83f831 100644 --- a/drivers/tty/serial/clps711x.c +++ b/drivers/tty/serial/clps711x.c | |||
@@ -99,15 +99,16 @@ static irqreturn_t uart_clps711x_int_rx(int irq, void *dev_id) | |||
99 | struct uart_port *port = dev_id; | 99 | struct uart_port *port = dev_id; |
100 | struct clps711x_port *s = dev_get_drvdata(port->dev); | 100 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
101 | unsigned int status, flg; | 101 | unsigned int status, flg; |
102 | u32 sysflg; | ||
103 | u16 ch; | 102 | u16 ch; |
104 | 103 | ||
105 | for (;;) { | 104 | for (;;) { |
105 | u32 sysflg = 0; | ||
106 | |||
106 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); | 107 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); |
107 | if (sysflg & SYSFLG_URXFE) | 108 | if (sysflg & SYSFLG_URXFE) |
108 | break; | 109 | break; |
109 | 110 | ||
110 | ch = readw_relaxed(port->membase + UARTDR_OFFSET); | 111 | ch = readw(port->membase + UARTDR_OFFSET); |
111 | status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR); | 112 | status = ch & (UARTDR_FRMERR | UARTDR_PARERR | UARTDR_OVERR); |
112 | ch &= 0xff; | 113 | ch &= 0xff; |
113 | 114 | ||
@@ -151,10 +152,9 @@ static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id) | |||
151 | struct uart_port *port = dev_id; | 152 | struct uart_port *port = dev_id; |
152 | struct clps711x_port *s = dev_get_drvdata(port->dev); | 153 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
153 | struct circ_buf *xmit = &port->state->xmit; | 154 | struct circ_buf *xmit = &port->state->xmit; |
154 | u32 sysflg; | ||
155 | 155 | ||
156 | if (port->x_char) { | 156 | if (port->x_char) { |
157 | writew_relaxed(port->x_char, port->membase + UARTDR_OFFSET); | 157 | writew(port->x_char, port->membase + UARTDR_OFFSET); |
158 | port->icount.tx++; | 158 | port->icount.tx++; |
159 | port->x_char = 0; | 159 | port->x_char = 0; |
160 | return IRQ_HANDLED; | 160 | return IRQ_HANDLED; |
@@ -169,8 +169,9 @@ static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id) | |||
169 | } | 169 | } |
170 | 170 | ||
171 | while (!uart_circ_empty(xmit)) { | 171 | while (!uart_circ_empty(xmit)) { |
172 | writew_relaxed(xmit->buf[xmit->tail], | 172 | u32 sysflg = 0; |
173 | port->membase + UARTDR_OFFSET); | 173 | |
174 | writew(xmit->buf[xmit->tail], port->membase + UARTDR_OFFSET); | ||
174 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | 175 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); |
175 | port->icount.tx++; | 176 | port->icount.tx++; |
176 | 177 | ||
@@ -188,7 +189,7 @@ static irqreturn_t uart_clps711x_int_tx(int irq, void *dev_id) | |||
188 | static unsigned int uart_clps711x_tx_empty(struct uart_port *port) | 189 | static unsigned int uart_clps711x_tx_empty(struct uart_port *port) |
189 | { | 190 | { |
190 | struct clps711x_port *s = dev_get_drvdata(port->dev); | 191 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
191 | u32 sysflg; | 192 | u32 sysflg = 0; |
192 | 193 | ||
193 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); | 194 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); |
194 | 195 | ||
@@ -199,9 +200,10 @@ static unsigned int uart_clps711x_get_mctrl(struct uart_port *port) | |||
199 | { | 200 | { |
200 | struct clps711x_port *s = dev_get_drvdata(port->dev); | 201 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
201 | unsigned int result = 0; | 202 | unsigned int result = 0; |
202 | u32 sysflg; | ||
203 | 203 | ||
204 | if (s->use_ms) { | 204 | if (s->use_ms) { |
205 | u32 sysflg = 0; | ||
206 | |||
205 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); | 207 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); |
206 | if (sysflg & SYSFLG1_DCD) | 208 | if (sysflg & SYSFLG1_DCD) |
207 | result |= TIOCM_CAR; | 209 | result |= TIOCM_CAR; |
@@ -224,12 +226,12 @@ static void uart_clps711x_break_ctl(struct uart_port *port, int break_state) | |||
224 | { | 226 | { |
225 | unsigned int ubrlcr; | 227 | unsigned int ubrlcr; |
226 | 228 | ||
227 | ubrlcr = readl_relaxed(port->membase + UBRLCR_OFFSET); | 229 | ubrlcr = readl(port->membase + UBRLCR_OFFSET); |
228 | if (break_state) | 230 | if (break_state) |
229 | ubrlcr |= UBRLCR_BREAK; | 231 | ubrlcr |= UBRLCR_BREAK; |
230 | else | 232 | else |
231 | ubrlcr &= ~UBRLCR_BREAK; | 233 | ubrlcr &= ~UBRLCR_BREAK; |
232 | writel_relaxed(ubrlcr, port->membase + UBRLCR_OFFSET); | 234 | writel(ubrlcr, port->membase + UBRLCR_OFFSET); |
233 | } | 235 | } |
234 | 236 | ||
235 | static void uart_clps711x_set_ldisc(struct uart_port *port, int ld) | 237 | static void uart_clps711x_set_ldisc(struct uart_port *port, int ld) |
@@ -247,8 +249,8 @@ static int uart_clps711x_startup(struct uart_port *port) | |||
247 | struct clps711x_port *s = dev_get_drvdata(port->dev); | 249 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
248 | 250 | ||
249 | /* Disable break */ | 251 | /* Disable break */ |
250 | writel_relaxed(readl_relaxed(port->membase + UBRLCR_OFFSET) & | 252 | writel(readl(port->membase + UBRLCR_OFFSET) & ~UBRLCR_BREAK, |
251 | ~UBRLCR_BREAK, port->membase + UBRLCR_OFFSET); | 253 | port->membase + UBRLCR_OFFSET); |
252 | 254 | ||
253 | /* Enable the port */ | 255 | /* Enable the port */ |
254 | return regmap_update_bits(s->syscon, SYSCON_OFFSET, | 256 | return regmap_update_bits(s->syscon, SYSCON_OFFSET, |
@@ -320,7 +322,7 @@ static void uart_clps711x_set_termios(struct uart_port *port, | |||
320 | 322 | ||
321 | uart_update_timeout(port, termios->c_cflag, baud); | 323 | uart_update_timeout(port, termios->c_cflag, baud); |
322 | 324 | ||
323 | writel_relaxed(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET); | 325 | writel(ubrlcr | (quot - 1), port->membase + UBRLCR_OFFSET); |
324 | } | 326 | } |
325 | 327 | ||
326 | static const char *uart_clps711x_type(struct uart_port *port) | 328 | static const char *uart_clps711x_type(struct uart_port *port) |
@@ -366,13 +368,13 @@ static const struct uart_ops uart_clps711x_ops = { | |||
366 | static void uart_clps711x_console_putchar(struct uart_port *port, int ch) | 368 | static void uart_clps711x_console_putchar(struct uart_port *port, int ch) |
367 | { | 369 | { |
368 | struct clps711x_port *s = dev_get_drvdata(port->dev); | 370 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
369 | u32 sysflg; | 371 | u32 sysflg = 0; |
370 | 372 | ||
371 | do { | 373 | do { |
372 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); | 374 | regmap_read(s->syscon, SYSFLG_OFFSET, &sysflg); |
373 | } while (sysflg & SYSFLG_UTXFF); | 375 | } while (sysflg & SYSFLG_UTXFF); |
374 | 376 | ||
375 | writew_relaxed(ch, port->membase + UARTDR_OFFSET); | 377 | writew(ch, port->membase + UARTDR_OFFSET); |
376 | } | 378 | } |
377 | 379 | ||
378 | static void uart_clps711x_console_write(struct console *co, const char *c, | 380 | static void uart_clps711x_console_write(struct console *co, const char *c, |
@@ -380,7 +382,7 @@ static void uart_clps711x_console_write(struct console *co, const char *c, | |||
380 | { | 382 | { |
381 | struct uart_port *port = clps711x_uart.state[co->index].uart_port; | 383 | struct uart_port *port = clps711x_uart.state[co->index].uart_port; |
382 | struct clps711x_port *s = dev_get_drvdata(port->dev); | 384 | struct clps711x_port *s = dev_get_drvdata(port->dev); |
383 | u32 sysflg; | 385 | u32 sysflg = 0; |
384 | 386 | ||
385 | uart_console_write(port, c, n, uart_clps711x_console_putchar); | 387 | uart_console_write(port, c, n, uart_clps711x_console_putchar); |
386 | 388 | ||
@@ -396,8 +398,8 @@ static int uart_clps711x_console_setup(struct console *co, char *options) | |||
396 | int ret, index = co->index; | 398 | int ret, index = co->index; |
397 | struct clps711x_port *s; | 399 | struct clps711x_port *s; |
398 | struct uart_port *port; | 400 | struct uart_port *port; |
399 | u32 ubrlcr, syscon; | ||
400 | unsigned int quot; | 401 | unsigned int quot; |
402 | u32 ubrlcr; | ||
401 | 403 | ||
402 | if (index < 0 || index >= UART_CLPS711X_NR) | 404 | if (index < 0 || index >= UART_CLPS711X_NR) |
403 | return -EINVAL; | 405 | return -EINVAL; |
@@ -409,9 +411,11 @@ static int uart_clps711x_console_setup(struct console *co, char *options) | |||
409 | s = dev_get_drvdata(port->dev); | 411 | s = dev_get_drvdata(port->dev); |
410 | 412 | ||
411 | if (!options) { | 413 | if (!options) { |
414 | u32 syscon = 0; | ||
415 | |||
412 | regmap_read(s->syscon, SYSCON_OFFSET, &syscon); | 416 | regmap_read(s->syscon, SYSCON_OFFSET, &syscon); |
413 | if (syscon & SYSCON_UARTEN) { | 417 | if (syscon & SYSCON_UARTEN) { |
414 | ubrlcr = readl_relaxed(port->membase + UBRLCR_OFFSET); | 418 | ubrlcr = readl(port->membase + UBRLCR_OFFSET); |
415 | 419 | ||
416 | if (ubrlcr & UBRLCR_PRTEN) { | 420 | if (ubrlcr & UBRLCR_PRTEN) { |
417 | if (ubrlcr & UBRLCR_EVENPRT) | 421 | if (ubrlcr & UBRLCR_EVENPRT) |