I/OAT: Add watchdog/reset functionality to ioatdma

Due to occasional DMA channel hangs observed for I/OAT versions 1.2 and 2.0
a watchdog has been introduced to check every 2 seconds
if all channels progress normally.
If stuck channel is detected, driver resets it.
The reset is done in two parts. The second part is scheduled
by the first one to reinitialize the channel after the restart.

Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

2 files changed, 271 insertions, 6 deletions

diff --git a/drivers/dma/ioat_dma.c b/drivers/dma/ioat_dma.c
index 171cad69f318..da572968a7db 100644
--- a/drivers/dma/ioat_dma.c
+++ b/drivers/dma/ioat_dma.c
@@ -32,6 +32,7 @@
 #include <linux/dmaengine.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
+#include <linux/workqueue.h>
 #include "ioatdma.h"
 #include "ioatdma_registers.h"
 #include "ioatdma_hw.h"
@@ -41,11 +42,17 @@
 #define to_ioat_desc(lh) container_of(lh, struct ioat_desc_sw, node)
 #define tx_to_ioat_desc(tx) container_of(tx, struct ioat_desc_sw, async_tx)
 
+#define chan_num(ch) ((int)((ch)->reg_base - (ch)->device->reg_base) / 0x80)
 static int ioat_pending_level = 4;
 module_param(ioat_pending_level, int, 0644);
 MODULE_PARM_DESC(ioat_pending_level,
                  "high-water mark for pushing ioat descriptors (default: 4)");
 
+#define RESET_DELAY  msecs_to_jiffies(100)
+#define WATCHDOG_DELAY  round_jiffies(msecs_to_jiffies(2000))
+static void ioat_dma_chan_reset_part2(struct work_struct *work);
+static void ioat_dma_chan_watchdog(struct work_struct *work);
+
 /* internal functions */
 static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan);
 static void ioat_dma_memcpy_cleanup(struct ioat_dma_chan *ioat_chan);
@@ -137,6 +144,7 @@ static int ioat_dma_enumerate_channels(struct ioatdma_device *device)
                 ioat_chan->reg_base = device->reg_base + (0x80 * (i + 1));
                 ioat_chan->xfercap = xfercap;
                 ioat_chan->desccount = 0;
+                INIT_DELAYED_WORK(&ioat_chan->work, ioat_dma_chan_reset_part2);
                 if (ioat_chan->device->version != IOAT_VER_1_2) {
                         writel(IOAT_DCACTRL_CMPL_WRITE_ENABLE
                                         | IOAT_DMA_DCA_ANY_CPU,
@@ -175,7 +183,7 @@ static void ioat1_dma_memcpy_issue_pending(struct dma_chan *chan)
 {
         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 
-        if (ioat_chan->pending != 0) {
+        if (ioat_chan->pending > 0) {
                 spin_lock_bh(&ioat_chan->desc_lock);
                 __ioat1_dma_memcpy_issue_pending(ioat_chan);
                 spin_unlock_bh(&ioat_chan->desc_lock);
@@ -194,13 +202,228 @@ static void ioat2_dma_memcpy_issue_pending(struct dma_chan *chan)
 {
         struct ioat_dma_chan *ioat_chan = to_ioat_chan(chan);
 
-        if (ioat_chan->pending != 0) {
+        if (ioat_chan->pending > 0) {
                 spin_lock_bh(&ioat_chan->desc_lock);
                 __ioat2_dma_memcpy_issue_pending(ioat_chan);
                 spin_unlock_bh(&ioat_chan->desc_lock);
         }
 }
 
+
+/**
+ * ioat_dma_chan_reset_part2 - reinit the channel after a reset
+ */
+static void ioat_dma_chan_reset_part2(struct work_struct *work)
+{
+        struct ioat_dma_chan *ioat_chan =
+                container_of(work, struct ioat_dma_chan, work.work);
+        struct ioat_desc_sw *desc;
+
+        spin_lock_bh(&ioat_chan->cleanup_lock);
+        spin_lock_bh(&ioat_chan->desc_lock);
+
+        ioat_chan->completion_virt->low = 0;
+        ioat_chan->completion_virt->high = 0;
+        ioat_chan->pending = 0;
+
+        /*
+         * count the descriptors waiting, and be sure to do it
+         * right for both the CB1 line and the CB2 ring
+         */
+        ioat_chan->dmacount = 0;
+        if (ioat_chan->used_desc.prev) {
+                desc = to_ioat_desc(ioat_chan->used_desc.prev);
+                do {
+                        ioat_chan->dmacount++;
+                        desc = to_ioat_desc(desc->node.next);
+                } while (&desc->node != ioat_chan->used_desc.next);
+        }
+
+        /*
+         * write the new starting descriptor address
+         * this puts channel engine into ARMED state
+         */
+        desc = to_ioat_desc(ioat_chan->used_desc.prev);
+        switch (ioat_chan->device->version) {
+        case IOAT_VER_1_2:
+                writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
+                       ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_LOW);
+                writel(((u64) desc->async_tx.phys) >> 32,
+                       ioat_chan->reg_base + IOAT1_CHAINADDR_OFFSET_HIGH);
+
+                writeb(IOAT_CHANCMD_START, ioat_chan->reg_base
+                        + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
+                break;
+        case IOAT_VER_2_0:
+                writel(((u64) desc->async_tx.phys) & 0x00000000FFFFFFFF,
+                       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
+                writel(((u64) desc->async_tx.phys) >> 32,
+                       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
+
+                /* tell the engine to go with what's left to be done */
+                writew(ioat_chan->dmacount,
+                       ioat_chan->reg_base + IOAT_CHAN_DMACOUNT_OFFSET);
+
+                break;
+        }
+        dev_err(&ioat_chan->device->pdev->dev,
+                "chan%d reset - %d descs waiting, %d total desc\n",
+                chan_num(ioat_chan), ioat_chan->dmacount, ioat_chan->desccount);
+
+        spin_unlock_bh(&ioat_chan->desc_lock);
+        spin_unlock_bh(&ioat_chan->cleanup_lock);
+}
+
+/**
+ * ioat_dma_reset_channel - restart a channel
+ * @ioat_chan: IOAT DMA channel handle
+ */
+static void ioat_dma_reset_channel(struct ioat_dma_chan *ioat_chan)
+{
+        u32 chansts, chanerr;
+
+        if (!ioat_chan->used_desc.prev)
+                return;
+
+        chanerr = readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
+        chansts = (ioat_chan->completion_virt->low
+                                        & IOAT_CHANSTS_DMA_TRANSFER_STATUS);
+        if (chanerr) {
+                dev_err(&ioat_chan->device->pdev->dev,
+                        "chan%d, CHANSTS = 0x%08x CHANERR = 0x%04x, clearing\n",
+                        chan_num(ioat_chan), chansts, chanerr);
+                writel(chanerr, ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
+        }
+
+        /*
+         * whack it upside the head with a reset
+         * and wait for things to settle out.
+         * force the pending count to a really big negative
+         * to make sure no one forces an issue_pending
+         * while we're waiting.
+         */
+
+        spin_lock_bh(&ioat_chan->desc_lock);
+        ioat_chan->pending = INT_MIN;
+        writeb(IOAT_CHANCMD_RESET,
+               ioat_chan->reg_base
+               + IOAT_CHANCMD_OFFSET(ioat_chan->device->version));
+        spin_unlock_bh(&ioat_chan->desc_lock);
+
+        /* schedule the 2nd half instead of sleeping a long time */
+        schedule_delayed_work(&ioat_chan->work, RESET_DELAY);
+}
+
+/**
+ * ioat_dma_chan_watchdog - watch for stuck channels
+ */
+static void ioat_dma_chan_watchdog(struct work_struct *work)
+{
+        struct ioatdma_device *device =
+                container_of(work, struct ioatdma_device, work.work);
+        struct ioat_dma_chan *ioat_chan;
+        int i;
+
+        union {
+                u64 full;
+                struct {
+                        u32 low;
+                        u32 high;