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authorBenoit Cousson <b-cousson@ti.com>2013-05-29 12:38:10 -0400
committerPaul Walmsley <paul@pwsan.com>2013-06-08 13:58:15 -0400
commit08e4830d71d422552f20a59627e9796f353b45e6 (patch)
tree0d0c6f3c7ce6bc574f95924385f45345affc58e3
parent411f968f1cd8c1e6262f794337c9cc49f67d687a (diff)
ARM: OMAP5: hwmod data: Create initial OMAP5 SOC hwmod data
Adding the hwmod data for OMAP54xx SOCs. Additional changes done on top of initial SOC data files. - The IO resource information like dma request lines, irq number and ocp address space can be populated via dt blob. So such data is stripped from OMAP5 SOC hwmod data file. - SDMA IO resource information is still kept since dmaengine work is till ongoing. Once the legacy dma platform driver becomes obsolete, SDMA io space information can be removed. - The devices like dss, aess, usb which are missing the device tree bindings, hwmod data is not added since OMAP5 is DT only build. When such devices add the dt bindings, respective hwmod data can be added along with it. With above update, we now need about ~2000 loc vs ~6000 loc with previous version of the patch for OMAP5 hwmod data file. Ofcourse with addition of few more drivers it can go upto ~2400 loc which is still better than the earlier version. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
Diffstat
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_54xx_data.c2151
2 files changed, 2152 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 0c898f58ac9b..aab33fd814c0 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -699,6 +699,7 @@ extern int omap2420_hwmod_init(void);
699extern int omap2430_hwmod_init(void); 699extern int omap2430_hwmod_init(void);
700extern int omap3xxx_hwmod_init(void); 700extern int omap3xxx_hwmod_init(void);
701extern int omap44xx_hwmod_init(void); 701extern int omap44xx_hwmod_init(void);
702extern int omap54xx_hwmod_init(void);
702extern int am33xx_hwmod_init(void); 703extern int am33xx_hwmod_init(void);
703 704
704extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); 705extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
new file mode 100644
index 000000000000..a538692a14cc
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -0,0 +1,2151 @@
1/*
2 * Hardware modules present on the OMAP54xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/power/smartreflex.h>
23#include <linux/platform_data/omap_ocp2scp.h>
24#include <linux/i2c-omap.h>
25
26#include <linux/omap-dma.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/asoc-ti-mcbsp.h>
29#include <plat/dmtimer.h>
30
31#include "omap_hwmod.h"
32#include "omap_hwmod_common_data.h"
33#include "cm1_54xx.h"
34#include "cm2_54xx.h"
35#include "prm54xx.h"
36#include "prm-regbits-54xx.h"
37#include "i2c.h"
38#include "mmc.h"
39#include "wd_timer.h"
40
41/* Base offset for all OMAP5 interrupts external to MPUSS */
42#define OMAP54XX_IRQ_GIC_START 32
43
44/* Base offset for all OMAP5 dma requests */
45#define OMAP54XX_DMA_REQ_START 1
46
47
48/*
49 * IP blocks
50 */
51
52/*
53 * 'dmm' class
54 * instance(s): dmm
55 */
56static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
57 .name = "dmm",
58};
59
60/* dmm */
61static struct omap_hwmod omap54xx_dmm_hwmod = {
62 .name = "dmm",
63 .class = &omap54xx_dmm_hwmod_class,
64 .clkdm_name = "emif_clkdm",
65 .prcm = {
66 .omap4 = {
67 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
68 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
69 },
70 },
71};
72
73/*
74 * 'l3' class
75 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
76 */
77static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
78 .name = "l3",
79};
80
81/* l3_instr */
82static struct omap_hwmod omap54xx_l3_instr_hwmod = {
83 .name = "l3_instr",
84 .class = &omap54xx_l3_hwmod_class,
85 .clkdm_name = "l3instr_clkdm",
86 .prcm = {
87 .omap4 = {
88 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
89 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
90 .modulemode = MODULEMODE_HWCTRL,
91 },
92 },
93};
94
95/* l3_main_1 */
96static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
97 .name = "l3_main_1",
98 .class = &omap54xx_l3_hwmod_class,
99 .clkdm_name = "l3main1_clkdm",
100 .prcm = {
101 .omap4 = {
102 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
103 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
104 },
105 },
106};
107
108/* l3_main_2 */
109static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
110 .name = "l3_main_2",
111 .class = &omap54xx_l3_hwmod_class,
112 .clkdm_name = "l3main2_clkdm",
113 .prcm = {
114 .omap4 = {
115 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
116 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
117 },
118 },
119};
120
121/* l3_main_3 */
122static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
123 .name = "l3_main_3",
124 .class = &omap54xx_l3_hwmod_class,
125 .clkdm_name = "l3instr_clkdm",
126 .prcm = {
127 .omap4 = {
128 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
129 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
130 .modulemode = MODULEMODE_HWCTRL,
131 },
132 },
133};
134
135/*
136 * 'l4' class
137 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
138 */
139static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
140 .name = "l4",
141};
142
143/* l4_abe */
144static struct omap_hwmod omap54xx_l4_abe_hwmod = {
145 .name = "l4_abe",
146 .class = &omap54xx_l4_hwmod_class,
147 .clkdm_name = "abe_clkdm",
148 .prcm = {
149 .omap4 = {
150 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
151 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
152 },
153 },
154};
155
156/* l4_cfg */
157static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
158 .name = "l4_cfg",
159 .class = &omap54xx_l4_hwmod_class,
160 .clkdm_name = "l4cfg_clkdm",
161 .prcm = {
162 .omap4 = {
163 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
164 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
165 },
166 },
167};
168
169/* l4_per */
170static struct omap_hwmod omap54xx_l4_per_hwmod = {
171 .name = "l4_per",
172 .class = &omap54xx_l4_hwmod_class,
173 .clkdm_name = "l4per_clkdm",
174 .prcm = {
175 .omap4 = {
176 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
177 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
178 },
179 },
180};
181
182/* l4_wkup */
183static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
184 .name = "l4_wkup",
185 .class = &omap54xx_l4_hwmod_class,
186 .clkdm_name = "wkupaon_clkdm",
187 .prcm = {
188 .omap4 = {
189 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
190 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
191 },
192 },
193};
194
195/*
196 * 'mpu_bus' class
197 * instance(s): mpu_private
198 */
199static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
200 .name = "mpu_bus",
201};
202
203/* mpu_private */
204static struct omap_hwmod omap54xx_mpu_private_hwmod = {
205 .name = "mpu_private",
206 .class = &omap54xx_mpu_bus_hwmod_class,
207 .clkdm_name = "mpu_clkdm",
208 .prcm = {
209 .omap4 = {
210 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
211 },
212 },
213};
214
215/*
216 * 'counter' class
217 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
218 */
219
220static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
221 .rev_offs = 0x0000,
222 .sysc_offs = 0x0010,
223 .sysc_flags = SYSC_HAS_SIDLEMODE,
224 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
225 .sysc_fields = &omap_hwmod_sysc_type1,
226};
227
228static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
229 .name = "counter",
230 .sysc = &omap54xx_counter_sysc,
231};
232
233/* counter_32k */
234static struct omap_hwmod omap54xx_counter_32k_hwmod = {
235 .name = "counter_32k",
236 .class = &omap54xx_counter_hwmod_class,
237 .clkdm_name = "wkupaon_clkdm",
238 .flags = HWMOD_SWSUP_SIDLE,
239 .main_clk = "wkupaon_iclk_mux",
240 .prcm = {
241 .omap4 = {
242 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
243 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
244 },
245 },
246};
247
248/*
249 * 'dma' class
250 * dma controller for data exchange between memory to memory (i.e. internal or
251 * external memory) and gp peripherals to memory or memory to gp peripherals
252 */
253
254static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
255 .rev_offs = 0x0000,
256 .sysc_offs = 0x002c,
257 .syss_offs = 0x0028,
258 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
259 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
260 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
261 SYSS_HAS_RESET_STATUS),
262 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
263 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
264 .sysc_fields = &omap_hwmod_sysc_type1,
265};
266
267static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
268 .name = "dma",
269 .sysc = &omap54xx_dma_sysc,
270};
271
272/* dma dev_attr */
273static struct omap_dma_dev_attr dma_dev_attr = {
274 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
275 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
276 .lch_count = 32,
277};
278
279/* dma_system */
280static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
281 { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
282 { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
283 { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
284 { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
285 { .irq = -1 }
286};
287
288static struct omap_hwmod omap54xx_dma_system_hwmod = {
289 .name = "dma_system",
290 .class = &omap54xx_dma_hwmod_class,
291 .clkdm_name = "dma_clkdm",
292 .mpu_irqs = omap54xx_dma_system_irqs,
293 .main_clk = "l3_iclk_div",
294 .prcm = {
295 .omap4 = {
296 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
297 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
298 },
299 },
300 .dev_attr = &dma_dev_attr,
301};
302
303/*
304 * 'dmic' class
305 * digital microphone controller
306 */
307
308static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
309 .rev_offs = 0x0000,
310 .sysc_offs = 0x0010,
311 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
312 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
313 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
314 SIDLE_SMART_WKUP),
315 .sysc_fields = &omap_hwmod_sysc_type2,
316};
317
318static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
319 .name = "dmic",
320 .sysc = &omap54xx_dmic_sysc,
321};
322
323/* dmic */
324static struct omap_hwmod omap54xx_dmic_hwmod = {
325 .name = "dmic",
326 .class = &omap54xx_dmic_hwmod_class,
327 .clkdm_name = "abe_clkdm",
328 .main_clk = "dmic_gfclk",
329 .prcm = {
330 .omap4 = {
331 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
332 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
333 .modulemode = MODULEMODE_SWCTRL,
334 },
335 },
336};
337
338/*
339 * 'emif' class
340 * external memory interface no1 (wrapper)
341 */
342
343static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
344 .rev_offs = 0x0000,
345};
346
347static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
348 .name = "emif",
349 .sysc = &omap54xx_emif_sysc,
350};
351
352/* emif1 */
353static struct omap_hwmod omap54xx_emif1_hwmod = {
354 .name = "emif1",
355 .class = &omap54xx_emif_hwmod_class,
356 .clkdm_name = "emif_clkdm",
357 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
358 .main_clk = "dpll_core_h11x2_ck",
359 .prcm = {
360 .omap4 = {
361 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
362 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
363 .modulemode = MODULEMODE_HWCTRL,
364 },
365 },
366};
367
368/* emif2 */
369static struct omap_hwmod omap54xx_emif2_hwmod = {
370 .name = "emif2",
371 .class = &omap54xx_emif_hwmod_class,
372 .clkdm_name = "emif_clkdm",
373 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
374 .main_clk = "dpll_core_h11x2_ck",
375 .prcm = {
376 .omap4 = {
377 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
378 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
379 .modulemode = MODULEMODE_HWCTRL,
380 },
381 },
382};
383
384/*
385 * 'gpio' class
386 * general purpose io module
387 */
388
389static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
390 .rev_offs = 0x0000,
391 .sysc_offs = 0x0010,
392 .syss_offs = 0x0114,
393 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
394 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
395 SYSS_HAS_RESET_STATUS),
396 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
397 SIDLE_SMART_WKUP),
398 .sysc_fields = &omap_hwmod_sysc_type1,
399};
400
401static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
402 .name = "gpio",
403 .sysc = &omap54xx_gpio_sysc,
404 .rev = 2,
405};
406
407/* gpio dev_attr */
408static struct omap_gpio_dev_attr gpio_dev_attr = {
409 .bank_width = 32,
410 .dbck_flag = true,
411};
412
413/* gpio1 */
414static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
415 { .role = "dbclk", .clk = "gpio1_dbclk" },
416};
417
418static struct omap_hwmod omap54xx_gpio1_hwmod = {
419 .name = "gpio1",
420 .class = &omap54xx_gpio_hwmod_class,
421 .clkdm_name = "wkupaon_clkdm",
422 .main_clk = "wkupaon_iclk_mux",
423 .prcm = {
424 .omap4 = {
425 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
426 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
427 .modulemode = MODULEMODE_HWCTRL,
428 },
429 },
430 .opt_clks = gpio1_opt_clks,
431 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
432 .dev_attr = &gpio_dev_attr,
433};
434
435/* gpio2 */
436static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
437 { .role = "dbclk", .clk = "gpio2_dbclk" },
438};
439
440static struct omap_hwmod omap54xx_gpio2_hwmod = {
441 .name = "gpio2",
442 .class = &omap54xx_gpio_hwmod_class,
443 .clkdm_name = "l4per_clkdm",
444 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
445 .main_clk = "l4_root_clk_div",
446 .prcm = {
447 .omap4 = {
448 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
449 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
450 .modulemode = MODULEMODE_HWCTRL,
451 },
452 },
453 .opt_clks = gpio2_opt_clks,
454 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
455 .dev_attr = &gpio_dev_attr,
456};
457
458/* gpio3 */
459static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
460 { .role = "dbclk", .clk = "gpio3_dbclk" },
461};
462
463static struct omap_hwmod omap54xx_gpio3_hwmod = {
464 .name = "gpio3",
465 .class = &omap54xx_gpio_hwmod_class,
466 .clkdm_name = "l4per_clkdm",
467 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
468 .main_clk = "l4_root_clk_div",
469 .prcm = {
470 .omap4 = {
471 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
472 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
473 .modulemode = MODULEMODE_HWCTRL,
474 },
475 },
476 .opt_clks = gpio3_opt_clks,
477 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
478 .dev_attr = &gpio_dev_attr,
479};
480
481/* gpio4 */
482static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
483 { .role = "dbclk", .clk = "gpio4_dbclk" },
484};
485
486static struct omap_hwmod omap54xx_gpio4_hwmod = {
487 .name = "gpio4",
488 .class = &omap54xx_gpio_hwmod_class,
489 .clkdm_name = "l4per_clkdm",
490 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
491 .main_clk = "l4_root_clk_div",
492 .prcm = {
493 .omap4 = {
494 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
495 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
496 .modulemode = MODULEMODE_HWCTRL,
497 },
498 },
499 .opt_clks = gpio4_opt_clks,
500 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
501 .dev_attr = &gpio_dev_attr,
502};
503
504/* gpio5 */
505static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
506 { .role = "dbclk", .clk = "gpio5_dbclk" },
507};
508
509static struct omap_hwmod omap54xx_gpio5_hwmod = {
510 .name = "gpio5",
511 .class = &omap54xx_gpio_hwmod_class,
512 .clkdm_name = "l4per_clkdm",
513 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
514 .main_clk = "l4_root_clk_div",
515 .prcm = {
516 .omap4 = {
517 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
518 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
519 .modulemode = MODULEMODE_HWCTRL,
520 },
521 },
522 .opt_clks = gpio5_opt_clks,
523 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
524 .dev_attr = &gpio_dev_attr,
525};
526
527/* gpio6 */
528static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
529 { .role = "dbclk", .clk = "gpio6_dbclk" },
530};
531
532static struct omap_hwmod omap54xx_gpio6_hwmod = {
533 .name = "gpio6",
534 .class = &omap54xx_gpio_hwmod_class,
535 .clkdm_name = "l4per_clkdm",
536 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
537 .main_clk = "l4_root_clk_div",
538 .prcm = {
539 .omap4 = {
540 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
541 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
542 .modulemode = MODULEMODE_HWCTRL,
543 },
544 },
545 .opt_clks = gpio6_opt_clks,
546 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
547 .dev_attr = &gpio_dev_attr,
548};
549
550/* gpio7 */
551static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
552 { .role = "dbclk", .clk = "gpio7_dbclk" },
553};
554
555static struct omap_hwmod omap54xx_gpio7_hwmod = {
556 .name = "gpio7",
557 .class = &omap54xx_gpio_hwmod_class,
558 .clkdm_name = "l4per_clkdm",
559 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
560 .main_clk = "l4_root_clk_div",
561 .prcm = {
562 .omap4 = {
563 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
564 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
565 .modulemode = MODULEMODE_HWCTRL,
566 },
567 },
568 .opt_clks = gpio7_opt_clks,
569 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
570 .dev_attr = &gpio_dev_attr,
571};
572
573/* gpio8 */
574static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
575 { .role = "dbclk", .clk = "gpio8_dbclk" },
576};
577
578static struct omap_hwmod omap54xx_gpio8_hwmod = {
579 .name = "gpio8",
580 .class = &omap54xx_gpio_hwmod_class,
581 .clkdm_name = "l4per_clkdm",
582 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
583 .main_clk = "l4_root_clk_div",
584 .prcm = {
585 .omap4 = {
586 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
587 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
588 .modulemode = MODULEMODE_HWCTRL,
589 },
590 },
591 .opt_clks = gpio8_opt_clks,
592 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
593 .dev_attr = &gpio_dev_attr,
594};
595
596/*
597 * 'i2c' class
598 * multimaster high-speed i2c controller
599 */
600
601static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
602 .sysc_offs = 0x0010,
603 .syss_offs = 0x0090,
604 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
605 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
606 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
607 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
608 SIDLE_SMART_WKUP),
609 .clockact = CLOCKACT_TEST_ICLK,
610 .sysc_fields = &omap_hwmod_sysc_type1,
611};
612
613static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
614 .name = "i2c",
615 .sysc = &omap54xx_i2c_sysc,
616 .reset = &omap_i2c_reset,
617 .rev = OMAP_I2C_IP_VERSION_2,
618};
619
620/* i2c dev_attr */
621static struct omap_i2c_dev_attr i2c_dev_attr = {
622 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
623};
624
625/* i2c1 */
626static struct omap_hwmod omap54xx_i2c1_hwmod = {
627 .name = "i2c1",
628 .class = &omap54xx_i2c_hwmod_class,
629 .clkdm_name = "l4per_clkdm",
630 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
631 .main_clk = "func_96m_fclk",
632 .prcm = {
633 .omap4 = {
634 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
635 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
636 .modulemode = MODULEMODE_SWCTRL,
637 },
638 },
639 .dev_attr = &i2c_dev_attr,
640};
641
642/* i2c2 */
643static struct omap_hwmod omap54xx_i2c2_hwmod = {
644 .name = "i2c2",
645 .class = &omap54xx_i2c_hwmod_class,
646 .clkdm_name = "l4per_clkdm",
647 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
648 .main_clk = "func_96m_fclk",
649 .prcm = {
650 .omap4 = {
651 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
652 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
653 .modulemode = MODULEMODE_SWCTRL,
654 },
655 },
656 .dev_attr = &i2c_dev_attr,
657};
658
659/* i2c3 */
660static struct omap_hwmod omap54xx_i2c3_hwmod = {
661 .name = "i2c3",
662 .class = &omap54xx_i2c_hwmod_class,
663 .clkdm_name = "l4per_clkdm",
664 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
665 .main_clk = "func_96m_fclk",
666 .prcm = {
667 .omap4 = {
668 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
669 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
670 .modulemode = MODULEMODE_SWCTRL,
671 },
672 },
673 .dev_attr = &i2c_dev_attr,
674};
675
676/* i2c4 */
677static struct omap_hwmod omap54xx_i2c4_hwmod = {
678 .name = "i2c4",
679 .class = &omap54xx_i2c_hwmod_class,
680 .clkdm_name = "l4per_clkdm",
681 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
682 .main_clk = "func_96m_fclk",
683 .prcm = {
684 .omap4 = {
685 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
686 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
687 .modulemode = MODULEMODE_SWCTRL,
688 },
689 },
690 .dev_attr = &i2c_dev_attr,
691};
692
693/* i2c5 */
694static struct omap_hwmod omap54xx_i2c5_hwmod = {
695 .name = "i2c5",
696 .class = &omap54xx_i2c_hwmod_class,
697 .clkdm_name = "l4per_clkdm",
698 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
699 .main_clk = "func_96m_fclk",
700 .prcm = {
701 .omap4 = {
702 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
703 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
704 .modulemode = MODULEMODE_SWCTRL,
705 },
706 },
707 .dev_attr = &i2c_dev_attr,
708};
709
710/*
711 * 'kbd' class
712 * keyboard controller
713 */
714
715static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
716 .rev_offs = 0x0000,
717 .sysc_offs = 0x0010,
718 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
719 SYSC_HAS_SOFTRESET),
720 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
721 .sysc_fields = &omap_hwmod_sysc_type1,
722};
723
724static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
725 .name = "kbd",
726 .sysc = &omap54xx_kbd_sysc,
727};
728
729/* kbd */
730static struct omap_hwmod omap54xx_kbd_hwmod = {
731 .name = "kbd",
732 .class = &omap54xx_kbd_hwmod_class,
733 .clkdm_name = "wkupaon_clkdm",
734 .main_clk = "sys_32k_ck",
735 .prcm = {
736 .omap4 = {
737 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
738 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
739 .modulemode = MODULEMODE_SWCTRL,
740 },
741 },
742};
743
744/*
745 * 'mcbsp' class
746 * multi channel buffered serial port controller
747 */
748
749static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
750 .sysc_offs = 0x008c,
751 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
752 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
753 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
754 .sysc_fields = &omap_hwmod_sysc_type1,
755};
756
757static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
758 .name = "mcbsp",
759 .sysc = &omap54xx_mcbsp_sysc,
760 .rev = MCBSP_CONFIG_TYPE4,
761};
762
763/* mcbsp1 */
764static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
765 { .role = "pad_fck", .clk = "pad_clks_ck" },
766 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
767};
768
769static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
770 .name = "mcbsp1",
771 .class = &omap54xx_mcbsp_hwmod_class,
772 .clkdm_name = "abe_clkdm",
773 .main_clk = "mcbsp1_gfclk",
774 .prcm = {
775 .omap4 = {
776 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
777 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
778 .modulemode = MODULEMODE_SWCTRL,
779 },
780 },
781 .opt_clks = mcbsp1_opt_clks,
782 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
783};
784
785/* mcbsp2 */
786static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
787 { .role = "pad_fck", .clk = "pad_clks_ck" },
788 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
789};
790
791static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
792 .name = "mcbsp2",
793 .class = &omap54xx_mcbsp_hwmod_class,
794 .clkdm_name = "abe_clkdm",
795 .main_clk = "mcbsp2_gfclk",
796 .prcm = {
797 .omap4 = {
798 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
799 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
800 .modulemode = MODULEMODE_SWCTRL,
801 },
802 },
803 .opt_clks = mcbsp2_opt_clks,
804 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
805};
806
807/* mcbsp3 */
808static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
809 { .role = "pad_fck", .clk = "pad_clks_ck" },
810 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
811};
812
813static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
814 .name = "mcbsp3",
815 .class = &omap54xx_mcbsp_hwmod_class,
816 .clkdm_name = "abe_clkdm",
817 .main_clk = "mcbsp3_gfclk",
818 .prcm = {
819 .omap4 = {
820 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
821 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
823 },
824 },
825 .opt_clks = mcbsp3_opt_clks,
826 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
827};
828
829/*
830 * 'mcpdm' class
831 * multi channel pdm controller (proprietary interface with phoenix power
832 * ic)
833 */
834
835static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
836 .rev_offs = 0x0000,
837 .sysc_offs = 0x0010,
838 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
839 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
840 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
841 SIDLE_SMART_WKUP),
842 .sysc_fields = &omap_hwmod_sysc_type2,
843};
844
845static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
846 .name = "mcpdm",
847 .sysc = &omap54xx_mcpdm_sysc,
848};
849
850/* mcpdm */
851static struct omap_hwmod omap54xx_mcpdm_hwmod = {
852 .name = "mcpdm",
853 .class = &omap54xx_mcpdm_hwmod_class,
854 .clkdm_name = "abe_clkdm",
855 /*
856 * It's suspected that the McPDM requires an off-chip main
857 * functional clock, controlled via I2C. This IP block is
858 * currently reset very early during boot, before I2C is
859 * available, so it doesn't seem that we have any choice in
860 * the kernel other than to avoid resetting it. XXX This is
861 * really a hardware issue workaround: every IP block should
862 * be able to source its main functional clock from either
863 * on-chip or off-chip sources. McPDM seems to be the only
864 * current exception.
865 */
866
867 .flags = HWMOD_EXT_OPT_MAIN_CLK,
868 .main_clk = "pad_clks_ck",
869 .prcm = {
870 .omap4 = {
871 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
872 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
873 .modulemode = MODULEMODE_SWCTRL,
874 },
875 },
876};
877
878/*
879 * 'mcspi' class
880 * multichannel serial port interface (mcspi) / master/slave synchronous serial
881 * bus
882 */
883
884static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
885 .rev_offs = 0x0000,
886 .sysc_offs = 0x0010,
887 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
888 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
889 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
890 SIDLE_SMART_WKUP),
891 .sysc_fields = &omap_hwmod_sysc_type2,
892};
893
894static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
895 .name = "mcspi",
896 .sysc = &omap54xx_mcspi_sysc,
897 .rev = OMAP4_MCSPI_REV,
898};
899
900/* mcspi1 */
901/* mcspi1 dev_attr */
902static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
903 .num_chipselect = 4,
904};
905
906static struct omap_hwmod omap54xx_mcspi1_hwmod = {
907 .name = "mcspi1",
908 .class = &omap54xx_mcspi_hwmod_class,
909 .clkdm_name = "l4per_clkdm",
910 .main_clk = "func_48m_fclk",
911 .prcm = {
912 .omap4 = {
913 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
914 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
915 .modulemode = MODULEMODE_SWCTRL,
916 },
917 },
918 .dev_attr = &mcspi1_dev_attr,
919};
920
921/* mcspi2 */
922/* mcspi2 dev_attr */
923static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
924 .num_chipselect = 2,
925};
926
927static struct omap_hwmod omap54xx_mcspi2_hwmod = {
928 .name = "mcspi2",
929 .class = &omap54xx_mcspi_hwmod_class,
930 .clkdm_name = "l4per_clkdm",
931 .main_clk = "func_48m_fclk",
932 .prcm = {
933 .omap4 = {
934 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
935 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
936 .modulemode = MODULEMODE_SWCTRL,
937 },
938 },
939 .dev_attr = &mcspi2_dev_attr,
940};
941
942/* mcspi3 */
943/* mcspi3 dev_attr */
944static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
945 .num_chipselect = 2,
946};
947
948static struct omap_hwmod omap54xx_mcspi3_hwmod = {
949 .name = "mcspi3",
950 .class = &omap54xx_mcspi_hwmod_class,
951 .clkdm_name = "l4per_clkdm",
952 .main_clk = "func_48m_fclk",
953 .prcm = {
954 .omap4 = {
955 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
956 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
957 .modulemode = MODULEMODE_SWCTRL,
958 },
959 },
960 .dev_attr = &mcspi3_dev_attr,
961};
962
963/* mcspi4 */
964/* mcspi4 dev_attr */
965static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
966 .num_chipselect = 1,
967};
968
969static struct omap_hwmod omap54xx_mcspi4_hwmod = {
970 .name = "mcspi4",
971 .class = &omap54xx_mcspi_hwmod_class,
972 .clkdm_name = "l4per_clkdm",
973 .main_clk = "func_48m_fclk",
974 .prcm = {
975 .omap4 = {
976 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
977 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
978 .modulemode = MODULEMODE_SWCTRL,
979 },
980 },
981 .dev_attr = &mcspi4_dev_attr,
982};
983
984/*
985 * 'mmc' class
986 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
987 */
988
989static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
990 .rev_offs = 0x0000,
991 .sysc_offs = 0x0010,
992 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
993 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
994 SYSC_HAS_SOFTRESET),
995 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
996 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
997 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
998 .sysc_fields = &omap_hwmod_sysc_type2,
999};
1000
1001static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1002 .name = "mmc",
1003 .sysc = &omap54xx_mmc_sysc,
1004};
1005
1006/* mmc1 */
1007static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1008 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1009};
1010
1011/* mmc1 dev_attr */
1012static struct omap_mmc_dev_attr mmc1_dev_attr = {
1013 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1014};
1015
1016static struct omap_hwmod omap54xx_mmc1_hwmod = {
1017 .name = "mmc1",
1018 .class = &omap54xx_mmc_hwmod_class,
1019 .clkdm_name = "l3init_clkdm",
1020 .main_clk = "mmc1_fclk",
1021 .prcm = {
1022 .omap4 = {
1023 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1024 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1025 .modulemode = MODULEMODE_SWCTRL,
1026 },
1027 },
1028 .opt_clks = mmc1_opt_clks,
1029 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1030 .dev_attr = &mmc1_dev_attr,
1031};
1032
1033/* mmc2 */
1034static struct omap_hwmod omap54xx_mmc2_hwmod = {
1035 .name = "mmc2",
1036 .class = &omap54xx_mmc_hwmod_class,
1037 .clkdm_name = "l3init_clkdm",
1038 .main_clk = "mmc2_fclk",
1039 .prcm = {
1040 .omap4 = {
1041 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1042 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1043 .modulemode = MODULEMODE_SWCTRL,
1044 },
1045 },
1046};
1047
1048/* mmc3 */
1049static struct omap_hwmod omap54xx_mmc3_hwmod = {
1050 .name = "mmc3",
1051 .class = &omap54xx_mmc_hwmod_class,
1052 .clkdm_name = "l4per_clkdm",
1053 .main_clk = "func_48m_fclk",
1054 .prcm = {
1055 .omap4 = {
1056 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1057 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1058 .modulemode = MODULEMODE_SWCTRL,
1059 },
1060 },
1061};
1062
1063/* mmc4 */
1064static struct omap_hwmod omap54xx_mmc4_hwmod = {
1065 .name = "mmc4",
1066 .class = &omap54xx_mmc_hwmod_class,
1067 .clkdm_name = "l4per_clkdm",
1068 .main_clk = "func_48m_fclk",
1069 .prcm = {
1070 .omap4 = {
1071 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1072 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1073 .modulemode = MODULEMODE_SWCTRL,
1074 },
1075 },
1076};
1077
1078/* mmc5 */
1079static struct omap_hwmod omap54xx_mmc5_hwmod = {
1080 .name = "mmc5",
1081 .class = &omap54xx_mmc_hwmod_class,
1082 .clkdm_name = "l4per_clkdm",
1083 .main_clk = "func_96m_fclk",
1084 .prcm = {
1085 .omap4 = {
1086 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1087 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1088 .modulemode = MODULEMODE_SWCTRL,
1089 },
1090 },
1091};
1092
1093/*
1094 * 'mpu' class
1095 * mpu sub-system
1096 */
1097
1098static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1099 .name = "mpu",
1100};
1101
1102/* mpu */
1103static struct omap_hwmod omap54xx_mpu_hwmod = {
1104 .name = "mpu",
1105 .class = &omap54xx_mpu_hwmod_class,
1106 .clkdm_name = "mpu_clkdm",
1107 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1108 .main_clk = "dpll_mpu_m2_ck",
1109 .prcm = {
1110 .omap4 = {
1111 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1112 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1113 },
1114 },
1115};
1116
1117/*
1118 * 'timer' class
1119 * general purpose timer module with accurate 1ms tick
1120 * This class contains several variants: ['timer_1ms', 'timer']
1121 */
1122
1123static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1124 .rev_offs = 0x0000,
1125 .sysc_offs = 0x0010,
1126 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1127 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1128 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1129 SIDLE_SMART_WKUP),
1130 .sysc_fields = &omap_hwmod_sysc_type2,
1131 .clockact = CLOCKACT_TEST_ICLK,
1132};
1133
1134static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1135 .name = "timer",
1136 .sysc = &omap54xx_timer_1ms_sysc,
1137};
1138
1139static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1140 .rev_offs = 0x0000,
1141 .sysc_offs = 0x0010,
1142 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1143 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1144 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1145 SIDLE_SMART_WKUP),
1146 .sysc_fields = &omap_hwmod_sysc_type2,
1147};
1148
1149static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1150 .name = "timer",
1151 .sysc = &omap54xx_timer_sysc,
1152};
1153
1154/* timer1 */
1155static struct omap_hwmod omap54xx_timer1_hwmod = {
1156 .name = "timer1",
1157 .class = &omap54xx_timer_1ms_hwmod_class,
1158 .clkdm_name = "wkupaon_clkdm",
1159 .main_clk = "timer1_gfclk_mux",
1160 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1161 .prcm = {
1162 .omap4 = {
1163 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1164 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1165 .modulemode = MODULEMODE_SWCTRL,
1166 },
1167 },
1168};
1169
1170/* timer2 */
1171static struct omap_hwmod omap54xx_timer2_hwmod = {
1172 .name = "timer2",
1173 .class = &omap54xx_timer_1ms_hwmod_class,
1174 .clkdm_name = "l4per_clkdm",
1175 .main_clk = "timer2_gfclk_mux",
1176 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1177 .prcm = {
1178 .omap4 = {
1179 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1180 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1181 .modulemode = MODULEMODE_SWCTRL,
1182 },
1183 },
1184};
1185
1186/* timer3 */
1187static struct omap_hwmod omap54xx_timer3_hwmod = {
1188 .name = "timer3",
1189 .class = &omap54xx_timer_hwmod_class,
1190 .clkdm_name = "l4per_clkdm",
1191 .main_clk = "timer3_gfclk_mux",
1192 .prcm = {
1193 .omap4 = {
1194 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1195 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1196 .modulemode = MODULEMODE_SWCTRL,
1197 },
1198 },
1199};
1200
1201/* timer4 */
1202static struct omap_hwmod omap54xx_timer4_hwmod = {
1203 .name = "timer4",
1204 .class = &omap54xx_timer_hwmod_class,
1205 .clkdm_name = "l4per_clkdm",
1206 .main_clk = "timer4_gfclk_mux",
1207 .prcm = {
1208 .omap4 = {
1209 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1210 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1211 .modulemode = MODULEMODE_SWCTRL,
1212 },
1213 },
1214};
1215
1216/* timer5 */
1217static struct omap_hwmod omap54xx_timer5_hwmod = {
1218 .name = "timer5",
1219 .class = &omap54xx_timer_hwmod_class,
1220 .clkdm_name = "abe_clkdm",
1221 .main_clk = "timer5_gfclk_mux",
1222 .prcm = {
1223 .omap4 = {
1224 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1225 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1226 .modulemode = MODULEMODE_SWCTRL,
1227 },
1228 },
1229};
1230
1231/* timer6 */
1232static struct omap_hwmod omap54xx_timer6_hwmod = {
1233 .name = "timer6",
1234 .class = &omap54xx_timer_hwmod_class,
1235 .clkdm_name = "abe_clkdm",
1236 .main_clk = "timer6_gfclk_mux",
1237 .prcm = {
1238 .omap4 = {
1239 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1240 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1241 .modulemode = MODULEMODE_SWCTRL,
1242 },
1243 },
1244};
1245
1246/* timer7 */
1247static struct omap_hwmod omap54xx_timer7_hwmod = {
1248 .name = "timer7",
1249 .class = &omap54xx_timer_hwmod_class,
1250 .clkdm_name = "abe_clkdm",
1251 .main_clk = "timer7_gfclk_mux",
1252 .prcm = {
1253 .omap4 = {
1254 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1255 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1256 .modulemode = MODULEMODE_SWCTRL,
1257 },
1258 },
1259};
1260
1261/* timer8 */
1262static struct omap_hwmod omap54xx_timer8_hwmod = {
1263 .name = "timer8",
1264 .class = &omap54xx_timer_hwmod_class,
1265 .clkdm_name = "abe_clkdm",
1266 .main_clk = "timer8_gfclk_mux",
1267 .prcm = {
1268 .omap4 = {
1269 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1270 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1271 .modulemode = MODULEMODE_SWCTRL,
1272 },
1273 },
1274};
1275
1276/* timer9 */
1277static struct omap_hwmod omap54xx_timer9_hwmod = {
1278 .name = "timer9",
1279 .class = &omap54xx_timer_hwmod_class,
1280 .clkdm_name = "l4per_clkdm",
1281 .main_clk = "timer9_gfclk_mux",
1282 .prcm = {
1283 .omap4 = {
1284 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1285 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1286 .modulemode = MODULEMODE_SWCTRL,
1287 },
1288 },
1289};
1290
1291/* timer10 */
1292static struct omap_hwmod omap54xx_timer10_hwmod = {
1293 .name = "timer10",
1294 .class = &omap54xx_timer_1ms_hwmod_class,
1295 .clkdm_name = "l4per_clkdm",
1296 .main_clk = "timer10_gfclk_mux",
1297 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1298 .prcm = {
1299 .omap4 = {
1300 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1301 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1302 .modulemode = MODULEMODE_SWCTRL,
1303 },
1304 },
1305};
1306
1307/* timer11 */
1308static struct omap_hwmod omap54xx_timer11_hwmod = {
1309 .name = "timer11",
1310 .class = &omap54xx_timer_hwmod_class,
1311 .clkdm_name = "l4per_clkdm",
1312 .main_clk = "timer11_gfclk_mux",
1313 .prcm = {
1314 .omap4 = {
1315 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1316 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1317 .modulemode = MODULEMODE_SWCTRL,
1318 },
1319 },
1320};
1321
1322/*
1323 * 'uart' class
1324 * universal asynchronous receiver/transmitter (uart)
1325 */
1326
1327static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1328 .rev_offs = 0x0050,
1329 .sysc_offs = 0x0054,
1330 .syss_offs = 0x0058,
1331 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1332 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1333 SYSS_HAS_RESET_STATUS),
1334 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1335 SIDLE_SMART_WKUP),
1336 .sysc_fields = &omap_hwmod_sysc_type1,
1337};
1338
1339static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1340 .name = "uart",
1341 .sysc = &omap54xx_uart_sysc,
1342};
1343
1344/* uart1 */
1345static struct omap_hwmod omap54xx_uart1_hwmod = {
1346 .name = "uart1",
1347 .class = &omap54xx_uart_hwmod_class,
1348 .clkdm_name = "l4per_clkdm",
1349 .main_clk = "func_48m_fclk",
1350 .prcm = {
1351 .omap4 = {
1352 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1353 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1354 .modulemode = MODULEMODE_SWCTRL,
1355 },
1356 },
1357};
1358
1359/* uart2 */
1360static struct omap_hwmod omap54xx_uart2_hwmod = {
1361 .name = "uart2",
1362 .class = &omap54xx_uart_hwmod_class,
1363 .clkdm_name = "l4per_clkdm",
1364 .main_clk = "func_48m_fclk",
1365 .prcm = {
1366 .omap4 = {
1367 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1368 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1369 .modulemode = MODULEMODE_SWCTRL,
1370 },
1371 },
1372};
1373
1374/* uart3 */
1375static struct omap_hwmod omap54xx_uart3_hwmod = {
1376 .name = "uart3",
1377 .class = &omap54xx_uart_hwmod_class,
1378 .clkdm_name = "l4per_clkdm",
1379 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1380 .main_clk = "func_48m_fclk",
1381 .prcm = {
1382 .omap4 = {
1383 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1384 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1385 .modulemode = MODULEMODE_SWCTRL,
1386 },
1387 },
1388};
1389
1390/* uart4 */
1391static struct omap_hwmod omap54xx_uart4_hwmod = {
1392 .name = "uart4",
1393 .class = &omap54xx_uart_hwmod_class,
1394 .clkdm_name = "l4per_clkdm",
1395 .main_clk = "func_48m_fclk",
1396 .prcm = {
1397 .omap4 = {
1398 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1399 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1400 .modulemode = MODULEMODE_SWCTRL,
1401 },
1402 },
1403};
1404
1405/* uart5 */
1406static struct omap_hwmod omap54xx_uart5_hwmod = {
1407 .name = "uart5",
1408 .class = &omap54xx_uart_hwmod_class,
1409 .clkdm_name = "l4per_clkdm",
1410 .main_clk = "func_48m_fclk",
1411 .prcm = {
1412 .omap4 = {
1413 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1414 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1415 .modulemode = MODULEMODE_SWCTRL,
1416 },
1417 },
1418};
1419
1420/* uart6 */
1421static struct omap_hwmod omap54xx_uart6_hwmod = {
1422 .name = "uart6",
1423 .class = &omap54xx_uart_hwmod_class,
1424 .clkdm_name = "l4per_clkdm",
1425 .main_clk = "func_48m_fclk",
1426 .prcm = {
1427 .omap4 = {
1428 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1429 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1430 .modulemode = MODULEMODE_SWCTRL,
1431 },
1432 },
1433};
1434
1435/*
1436 * 'usb_otg_ss' class
1437 * 2.0 super speed (usb_otg_ss) controller
1438 */
1439
1440static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1441 .rev_offs = 0x0000,
1442 .sysc_offs = 0x0010,
1443 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1444 SYSC_HAS_SIDLEMODE),
1445 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1446 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1447 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1448 .sysc_fields = &omap_hwmod_sysc_type2,
1449};
1450
1451static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1452 .name = "usb_otg_ss",
1453 .sysc = &omap54xx_usb_otg_ss_sysc,
1454};
1455
1456/* usb_otg_ss */
1457static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1458 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1459};
1460
1461static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1462 .name = "usb_otg_ss",
1463 .class = &omap54xx_usb_otg_ss_hwmod_class,
1464 .clkdm_name = "l3init_clkdm",
1465 .flags = HWMOD_SWSUP_SIDLE,
1466 .main_clk = "dpll_core_h13x2_ck",
1467 .prcm = {
1468 .omap4 = {
1469 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1470 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1471 .modulemode = MODULEMODE_HWCTRL,
1472 },
1473 },
1474 .opt_clks = usb_otg_ss_opt_clks,
1475 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1476};
1477
1478/*
1479 * 'wd_timer' class
1480 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1481 * overflow condition
1482 */
1483
1484static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1485 .rev_offs = 0x0000,
1486 .sysc_offs = 0x0010,
1487 .syss_offs = 0x0014,
1488 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1489 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1490 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1491 SIDLE_SMART_WKUP),
1492 .sysc_fields = &omap_hwmod_sysc_type1,
1493};
1494
1495static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1496 .name = "wd_timer",
1497 .sysc = &omap54xx_wd_timer_sysc,
1498 .pre_shutdown = &omap2_wd_timer_disable,
1499};
1500
1501/* wd_timer2 */
1502static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1503 .name = "wd_timer2",
1504 .class = &omap54xx_wd_timer_hwmod_class,
1505 .clkdm_name = "wkupaon_clkdm",
1506 .main_clk = "sys_32k_ck",
1507 .prcm = {
1508 .omap4 = {
1509 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1510 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1511 .modulemode = MODULEMODE_SWCTRL,
1512 },
1513 },
1514};
1515
1516
1517/*
1518 * Interfaces
1519 */
1520
1521/* l3_main_1 -> dmm */
1522static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1523 .master = &omap54xx_l3_main_1_hwmod,
1524 .slave = &omap54xx_dmm_hwmod,
1525 .clk = "l3_iclk_div",
1526 .user = OCP_USER_SDMA,
1527};
1528
1529/* l3_main_3 -> l3_instr */
1530static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1531 .master = &omap54xx_l3_main_3_hwmod,
1532 .slave = &omap54xx_l3_instr_hwmod,
1533 .clk = "l3_iclk_div",
1534 .user = OCP_USER_MPU | OCP_USER_SDMA,
1535};
1536
1537/* l3_main_2 -> l3_main_1 */
1538static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1539 .master = &omap54xx_l3_main_2_hwmod,
1540 .slave = &omap54xx_l3_main_1_hwmod,
1541 .clk = "l3_iclk_div",
1542 .user = OCP_USER_MPU | OCP_USER_SDMA,
1543};
1544
1545/* l4_cfg -> l3_main_1 */
1546static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1547 .master = &omap54xx_l4_cfg_hwmod,
1548 .slave = &omap54xx_l3_main_1_hwmod,
1549 .clk = "l3_iclk_div",
1550 .user = OCP_USER_MPU | OCP_USER_SDMA,
1551};
1552
1553/* mpu -> l3_main_1 */
1554static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1555 .master = &omap54xx_mpu_hwmod,
1556 .slave = &omap54xx_l3_main_1_hwmod,
1557 .clk = "l3_iclk_div",
1558 .user = OCP_USER_MPU,
1559};
1560
1561/* l3_main_1 -> l3_main_2 */
1562static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1563 .master = &omap54xx_l3_main_1_hwmod,
1564 .slave = &omap54xx_l3_main_2_hwmod,
1565 .clk = "l3_iclk_div",
1566 .user = OCP_USER_MPU,
1567};
1568
1569/* l4_cfg -> l3_main_2 */
1570static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1571 .master = &omap54xx_l4_cfg_hwmod,
1572 .slave = &omap54xx_l3_main_2_hwmod,
1573 .clk = "l3_iclk_div",
1574 .user = OCP_USER_MPU | OCP_USER_SDMA,
1575};
1576
1577/* l3_main_1 -> l3_main_3 */
1578static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1579 .master = &omap54xx_l3_main_1_hwmod,
1580 .slave = &omap54xx_l3_main_3_hwmod,
1581 .clk = "l3_iclk_div",
1582 .user = OCP_USER_MPU,
1583};
1584
1585/* l3_main_2 -> l3_main_3 */
1586static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1587 .master = &omap54xx_l3_main_2_hwmod,
1588 .slave = &omap54xx_l3_main_3_hwmod,
1589 .clk = "l3_iclk_div",
1590 .user = OCP_USER_MPU | OCP_USER_SDMA,
1591};
1592
1593/* l4_cfg -> l3_main_3 */
1594static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1595 .master = &omap54xx_l4_cfg_hwmod,
1596 .slave = &omap54xx_l3_main_3_hwmod,
1597 .clk = "l3_iclk_div",
1598 .user = OCP_USER_MPU | OCP_USER_SDMA,
1599};
1600
1601/* l3_main_1 -> l4_abe */
1602static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1603 .master = &omap54xx_l3_main_1_hwmod,
1604 .slave = &omap54xx_l4_abe_hwmod,
1605 .clk = "abe_iclk",
1606 .user = OCP_USER_MPU | OCP_USER_SDMA,
1607};
1608
1609/* mpu -> l4_abe */
1610static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1611 .master = &omap54xx_mpu_hwmod,
1612 .slave = &omap54xx_l4_abe_hwmod,
1613 .clk = "abe_iclk",
1614 .user = OCP_USER_MPU | OCP_USER_SDMA,
1615};
1616
1617/* l3_main_1 -> l4_cfg */
1618static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1619 .master = &omap54xx_l3_main_1_hwmod,
1620 .slave = &omap54xx_l4_cfg_hwmod,
1621 .clk = "l4_root_clk_div",
1622 .user = OCP_USER_MPU | OCP_USER_SDMA,
1623};
1624
1625/* l3_main_2 -> l4_per */
1626static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1627 .master = &omap54xx_l3_main_2_hwmod,
1628 .slave = &omap54xx_l4_per_hwmod,
1629 .clk = "l4_root_clk_div",
1630 .user = OCP_USER_MPU | OCP_USER_SDMA,
1631};
1632
1633/* l3_main_1 -> l4_wkup */
1634static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1635 .master = &omap54xx_l3_main_1_hwmod,
1636 .slave = &omap54xx_l4_wkup_hwmod,
1637 .clk = "wkupaon_iclk_mux",
1638 .user = OCP_USER_MPU | OCP_USER_SDMA,
1639};
1640
1641/* mpu -> mpu_private */
1642static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1643 .master = &omap54xx_mpu_hwmod,
1644 .slave = &omap54xx_mpu_private_hwmod,
1645 .clk = "l3_iclk_div",
1646 .user = OCP_USER_MPU | OCP_USER_SDMA,
1647};
1648
1649/* l4_wkup -> counter_32k */
1650static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1651 .master = &omap54xx_l4_wkup_hwmod,
1652 .slave = &omap54xx_counter_32k_hwmod,
1653 .clk = "wkupaon_iclk_mux",
1654 .user = OCP_USER_MPU | OCP_USER_SDMA,
1655};
1656
1657static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
1658 {
1659 .pa_start = 0x4a056000,
1660 .pa_end = 0x4a056fff,
1661 .flags = ADDR_TYPE_RT
1662 },
1663 { }
1664};
1665
1666/* l4_cfg -> dma_system */
1667static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1668 .master = &omap54xx_l4_cfg_hwmod,
1669 .slave = &omap54xx_dma_system_hwmod,
1670 .clk = "l4_root_clk_div",
1671 .addr = omap54xx_dma_system_addrs,
1672 .user = OCP_USER_MPU | OCP_USER_SDMA,
1673};
1674
1675/* l4_abe -> dmic */
1676static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1677 .master = &omap54xx_l4_abe_hwmod,
1678 .slave = &omap54xx_dmic_hwmod,
1679 .clk = "abe_iclk",
1680 .user = OCP_USER_MPU,
1681};
1682
1683/* mpu -> emif1 */
1684static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1685 .master = &omap54xx_mpu_hwmod,
1686 .slave = &omap54xx_emif1_hwmod,
1687 .clk = "dpll_core_h11x2_ck",
1688 .user = OCP_USER_MPU | OCP_USER_SDMA,
1689};
1690
1691/* mpu -> emif2 */
1692static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1693 .master = &omap54xx_mpu_hwmod,
1694 .slave = &omap54xx_emif2_hwmod,
1695 .clk = "dpll_core_h11x2_ck",
1696 .user = OCP_USER_MPU | OCP_USER_SDMA,
1697};
1698
1699/* l4_wkup -> gpio1 */
1700static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
1701 .master = &omap54xx_l4_wkup_hwmod,
1702 .slave = &omap54xx_gpio1_hwmod,
1703 .clk = "wkupaon_iclk_mux",
1704 .user = OCP_USER_MPU | OCP_USER_SDMA,
1705};
1706
1707/* l4_per -> gpio2 */
1708static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
1709 .master = &omap54xx_l4_per_hwmod,
1710 .slave = &omap54xx_gpio2_hwmod,
1711 .clk = "l4_root_clk_div",
1712 .user = OCP_USER_MPU | OCP_USER_SDMA,
1713};
1714
1715/* l4_per -> gpio3 */
1716static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
1717 .master = &omap54xx_l4_per_hwmod,
1718 .slave = &omap54xx_gpio3_hwmod,
1719 .clk = "l4_root_clk_div",
1720 .user = OCP_USER_MPU | OCP_USER_SDMA,
1721};
1722
1723/* l4_per -> gpio4 */
1724static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
1725 .master = &omap54xx_l4_per_hwmod,
1726 .slave = &omap54xx_gpio4_hwmod,
1727 .clk = "l4_root_clk_div",
1728 .user = OCP_USER_MPU | OCP_USER_SDMA,
1729};
1730
1731/* l4_per -> gpio5 */
1732static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
1733 .master = &omap54xx_l4_per_hwmod,
1734 .slave = &omap54xx_gpio5_hwmod,
1735 .clk = "l4_root_clk_div",
1736 .user = OCP_USER_MPU | OCP_USER_SDMA,
1737};
1738
1739/* l4_per -> gpio6 */
1740static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
1741 .master = &omap54xx_l4_per_hwmod,
1742 .slave = &omap54xx_gpio6_hwmod,
1743 .clk = "l4_root_clk_div",
1744 .user = OCP_USER_MPU | OCP_USER_SDMA,
1745};
1746
1747/* l4_per -> gpio7 */
1748static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
1749 .master = &omap54xx_l4_per_hwmod,
1750 .slave = &omap54xx_gpio7_hwmod,
1751 .clk = "l4_root_clk_div",
1752 .user = OCP_USER_MPU | OCP_USER_SDMA,
1753};
1754
1755/* l4_per -> gpio8 */
1756static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
1757 .master = &omap54xx_l4_per_hwmod,
1758 .slave = &omap54xx_gpio8_hwmod,
1759 .clk = "l4_root_clk_div",
1760 .user = OCP_USER_MPU | OCP_USER_SDMA,
1761};
1762
1763/* l4_per -> i2c1 */
1764static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
1765 .master = &omap54xx_l4_per_hwmod,
1766 .slave = &omap54xx_i2c1_hwmod,
1767 .clk = "l4_root_clk_div",
1768 .user = OCP_USER_MPU | OCP_USER_SDMA,
1769};
1770
1771/* l4_per -> i2c2 */
1772static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
1773 .master = &omap54xx_l4_per_hwmod,
1774 .slave = &omap54xx_i2c2_hwmod,
1775 .clk = "l4_root_clk_div",
1776 .user = OCP_USER_MPU | OCP_USER_SDMA,
1777};
1778
1779/* l4_per -> i2c3 */
1780static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
1781 .master = &omap54xx_l4_per_hwmod,
1782 .slave = &omap54xx_i2c3_hwmod,
1783 .clk = "l4_root_clk_div",
1784 .user = OCP_USER_MPU | OCP_USER_SDMA,
1785};
1786
1787/* l4_per -> i2c4 */
1788static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
1789 .master = &omap54xx_l4_per_hwmod,
1790 .slave = &omap54xx_i2c4_hwmod,
1791 .clk = "l4_root_clk_div",
1792 .user = OCP_USER_MPU | OCP_USER_SDMA,
1793};
1794
1795/* l4_per -> i2c5 */
1796static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
1797 .master = &omap54xx_l4_per_hwmod,
1798 .slave = &omap54xx_i2c5_hwmod,
1799 .clk = "l4_root_clk_div",
1800 .user = OCP_USER_MPU | OCP_USER_SDMA,
1801};
1802
1803/* l4_wkup -> kbd */
1804static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1805 .master = &omap54xx_l4_wkup_hwmod,
1806 .slave = &omap54xx_kbd_hwmod,
1807 .clk = "wkupaon_iclk_mux",
1808 .user = OCP_USER_MPU | OCP_USER_SDMA,
1809};
1810
1811/* l4_abe -> mcbsp1 */
1812static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
1813 .master = &omap54xx_l4_abe_hwmod,
1814 .slave = &omap54xx_mcbsp1_hwmod,
1815 .clk = "abe_iclk",
1816 .user = OCP_USER_MPU,
1817};
1818
1819/* l4_abe -> mcbsp2 */
1820static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
1821 .master = &omap54xx_l4_abe_hwmod,
1822 .slave = &omap54xx_mcbsp2_hwmod,
1823 .clk = "abe_iclk",
1824 .user = OCP_USER_MPU,
1825};
1826
1827/* l4_abe -> mcbsp3 */
1828static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
1829 .master = &omap54xx_l4_abe_hwmod,
1830 .slave = &omap54xx_mcbsp3_hwmod,
1831 .clk = "abe_iclk",
1832 .user = OCP_USER_MPU,
1833};
1834
1835/* l4_abe -> mcpdm */
1836static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
1837 .master = &omap54xx_l4_abe_hwmod,
1838 .slave = &omap54xx_mcpdm_hwmod,
1839 .clk = "abe_iclk",
1840 .user = OCP_USER_MPU,
1841};
1842
1843/* l4_per -> mcspi1 */
1844static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
1845 .master = &omap54xx_l4_per_hwmod,
1846 .slave = &omap54xx_mcspi1_hwmod,
1847 .clk = "l4_root_clk_div",
1848 .user = OCP_USER_MPU | OCP_USER_SDMA,
1849};
1850
1851/* l4_per -> mcspi2 */
1852static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
1853 .master = &omap54xx_l4_per_hwmod,
1854 .slave = &omap54xx_mcspi2_hwmod,
1855 .clk = "l4_root_clk_div",
1856 .user = OCP_USER_MPU | OCP_USER_SDMA,
1857};
1858
1859/* l4_per -> mcspi3 */
1860static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
1861 .master = &omap54xx_l4_per_hwmod,
1862 .slave = &omap54xx_mcspi3_hwmod,
1863 .clk = "l4_root_clk_div",
1864 .user = OCP_USER_MPU | OCP_USER_SDMA,
1865};
1866
1867/* l4_per -> mcspi4 */
1868static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
1869 .master = &omap54xx_l4_per_hwmod,
1870 .slave = &omap54xx_mcspi4_hwmod,
1871 .clk = "l4_root_clk_div",
1872 .user = OCP_USER_MPU | OCP_USER_SDMA,
1873};
1874
1875/* l4_per -> mmc1 */
1876static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
1877 .master = &omap54xx_l4_per_hwmod,
1878 .slave = &omap54xx_mmc1_hwmod,
1879 .clk = "l3_iclk_div",
1880 .user = OCP_USER_MPU | OCP_USER_SDMA,
1881};
1882
1883/* l4_per -> mmc2 */
1884static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
1885 .master = &omap54xx_l4_per_hwmod,
1886 .slave = &omap54xx_mmc2_hwmod,
1887 .clk = "l3_iclk_div",
1888 .user = OCP_USER_MPU | OCP_USER_SDMA,
1889};
1890
1891/* l4_per -> mmc3 */
1892static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
1893 .master = &omap54xx_l4_per_hwmod,
1894 .slave = &omap54xx_mmc3_hwmod,
1895 .clk = "l4_root_clk_div",
1896 .user = OCP_USER_MPU | OCP_USER_SDMA,
1897};
1898
1899/* l4_per -> mmc4 */
1900static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
1901 .master = &omap54xx_l4_per_hwmod,
1902 .slave = &omap54xx_mmc4_hwmod,
1903 .clk = "l4_root_clk_div",
1904 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905};
1906
1907/* l4_per -> mmc5 */
1908static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
1909 .master = &omap54xx_l4_per_hwmod,
1910 .slave = &omap54xx_mmc5_hwmod,
1911 .clk = "l4_root_clk_div",
1912 .user = OCP_USER_MPU | OCP_USER_SDMA,
1913};
1914
1915/* l4_cfg -> mpu */
1916static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
1917 .master = &omap54xx_l4_cfg_hwmod,
1918 .slave = &omap54xx_mpu_hwmod,
1919 .clk = "l4_root_clk_div",
1920 .user = OCP_USER_MPU | OCP_USER_SDMA,
1921};
1922
1923/* l4_wkup -> timer1 */
1924static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
1925 .master = &omap54xx_l4_wkup_hwmod,
1926 .slave = &omap54xx_timer1_hwmod,
1927 .clk = "wkupaon_iclk_mux",
1928 .user = OCP_USER_MPU | OCP_USER_SDMA,
1929};
1930
1931/* l4_per -> timer2 */
1932static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
1933 .master = &omap54xx_l4_per_hwmod,
1934 .slave = &omap54xx_timer2_hwmod,
1935 .clk = "l4_root_clk_div",
1936 .user = OCP_USER_MPU | OCP_USER_SDMA,
1937};
1938
1939/* l4_per -> timer3 */
1940static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
1941 .master = &omap54xx_l4_per_hwmod,
1942 .slave = &omap54xx_timer3_hwmod,
1943 .clk = "l4_root_clk_div",
1944 .user = OCP_USER_MPU | OCP_USER_SDMA,
1945};
1946
1947/* l4_per -> timer4 */
1948static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
1949 .master = &omap54xx_l4_per_hwmod,
1950 .slave = &omap54xx_timer4_hwmod,
1951 .clk = "l4_root_clk_div",
1952 .user = OCP_USER_MPU | OCP_USER_SDMA,
1953};
1954
1955/* l4_abe -> timer5 */
1956static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
1957 .master = &omap54xx_l4_abe_hwmod,
1958 .slave = &omap54xx_timer5_hwmod,
1959 .clk = "abe_iclk",
1960 .user = OCP_USER_MPU,
1961};
1962
1963/* l4_abe -> timer6 */
1964static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
1965 .master = &omap54xx_l4_abe_hwmod,
1966 .slave = &omap54xx_timer6_hwmod,
1967 .clk = "abe_iclk",
1968 .user = OCP_USER_MPU,
1969};
1970
1971/* l4_abe -> timer7 */
1972static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
1973 .master = &omap54xx_l4_abe_hwmod,
1974 .slave = &omap54xx_timer7_hwmod,
1975 .clk = "abe_iclk",
1976 .user = OCP_USER_MPU,
1977};
1978
1979/* l4_abe -> timer8 */
1980static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
1981 .master = &omap54xx_l4_abe_hwmod,
1982 .slave = &omap54xx_timer8_hwmod,
1983 .clk = "abe_iclk",
1984 .user = OCP_USER_MPU,
1985};
1986
1987/* l4_per -> timer9 */
1988static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
1989 .master = &omap54xx_l4_per_hwmod,
1990 .slave = &omap54xx_timer9_hwmod,
1991 .clk = "l4_root_clk_div",
1992 .user = OCP_USER_MPU | OCP_USER_SDMA,
1993};
1994
1995/* l4_per -> timer10 */
1996static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
1997 .master = &omap54xx_l4_per_hwmod,
1998 .slave = &omap54xx_timer10_hwmod,
1999 .clk = "l4_root_clk_div",
2000 .user = OCP_USER_MPU | OCP_USER_SDMA,
2001};
2002
2003/* l4_per -> timer11 */
2004static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2005 .master = &omap54xx_l4_per_hwmod,
2006 .slave = &omap54xx_timer11_hwmod,
2007 .clk = "l4_root_clk_div",
2008 .user = OCP_USER_MPU | OCP_USER_SDMA,
2009};
2010
2011/* l4_per -> uart1 */
2012static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2013 .master = &omap54xx_l4_per_hwmod,
2014 .slave = &omap54xx_uart1_hwmod,
2015 .clk = "l4_root_clk_div",
2016 .user = OCP_USER_MPU | OCP_USER_SDMA,
2017};
2018
2019/* l4_per -> uart2 */
2020static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2021 .master = &omap54xx_l4_per_hwmod,
2022 .slave = &omap54xx_uart2_hwmod,
2023 .clk = "l4_root_clk_div",
2024 .user = OCP_USER_MPU | OCP_USER_SDMA,
2025};
2026
2027/* l4_per -> uart3 */
2028static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2029 .master = &omap54xx_l4_per_hwmod,
2030 .slave = &omap54xx_uart3_hwmod,
2031 .clk = "l4_root_clk_div",
2032 .user = OCP_USER_MPU | OCP_USER_SDMA,
2033};
2034
2035/* l4_per -> uart4 */
2036static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2037 .master = &omap54xx_l4_per_hwmod,
2038 .slave = &omap54xx_uart4_hwmod,
2039 .clk = "l4_root_clk_div",
2040 .user = OCP_USER_MPU | OCP_USER_SDMA,
2041};
2042
2043/* l4_per -> uart5 */
2044static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2045 .master = &omap54xx_l4_per_hwmod,
2046 .slave = &omap54xx_uart5_hwmod,
2047 .clk = "l4_root_clk_div",
2048 .user = OCP_USER_MPU | OCP_USER_SDMA,
2049};
2050
2051/* l4_per -> uart6 */
2052static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2053 .master = &omap54xx_l4_per_hwmod,
2054 .slave = &omap54xx_uart6_hwmod,
2055 .clk = "l4_root_clk_div",
2056 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057};
2058
2059/* l4_cfg -> usb_otg_ss */
2060static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2061 .master = &omap54xx_l4_cfg_hwmod,
2062 .slave = &omap54xx_usb_otg_ss_hwmod,
2063 .clk = "dpll_core_h13x2_ck",
2064 .user = OCP_USER_MPU | OCP_USER_SDMA,
2065};
2066
2067/* l4_wkup -> wd_timer2 */
2068static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2069 .master = &omap54xx_l4_wkup_hwmod,
2070 .slave = &omap54xx_wd_timer2_hwmod,
2071 .clk = "wkupaon_iclk_mux",
2072 .user = OCP_USER_MPU | OCP_USER_SDMA,
2073};
2074
2075static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2076 &omap54xx_l3_main_1__dmm,
2077 &omap54xx_l3_main_3__l3_instr,
2078 &omap54xx_l3_main_2__l3_main_1,
2079 &omap54xx_l4_cfg__l3_main_1,
2080 &omap54xx_mpu__l3_main_1,
2081 &omap54xx_l3_main_1__l3_main_2,
2082 &omap54xx_l4_cfg__l3_main_2,
2083 &omap54xx_l3_main_1__l3_main_3,
2084 &omap54xx_l3_main_2__l3_main_3,
2085 &omap54xx_l4_cfg__l3_main_3,
2086 &omap54xx_l3_main_1__l4_abe,
2087 &omap54xx_mpu__l4_abe,
2088 &omap54xx_l3_main_1__l4_cfg,
2089 &omap54xx_l3_main_2__l4_per,
2090 &omap54xx_l3_main_1__l4_wkup,
2091 &omap54xx_mpu__mpu_private,
2092 &omap54xx_l4_wkup__counter_32k,
2093 &omap54xx_l4_cfg__dma_system,
2094 &omap54xx_l4_abe__dmic,
2095 &omap54xx_mpu__emif1,
2096 &omap54xx_mpu__emif2,
2097 &omap54xx_l4_wkup__gpio1,
2098 &omap54xx_l4_per__gpio2,
2099 &omap54xx_l4_per__gpio3,
2100 &omap54xx_l4_per__gpio4,
2101 &omap54xx_l4_per__gpio5,
2102 &omap54xx_l4_per__gpio6,
2103 &omap54xx_l4_per__gpio7,
2104 &omap54xx_l4_per__gpio8,
2105 &omap54xx_l4_per__i2c1,
2106 &omap54xx_l4_per__i2c2,
2107 &omap54xx_l4_per__i2c3,
2108 &omap54xx_l4_per__i2c4,
2109 &omap54xx_l4_per__i2c5,
2110 &omap54xx_l4_wkup__kbd,
2111 &omap54xx_l4_abe__mcbsp1,
2112 &omap54xx_l4_abe__mcbsp2,
2113 &omap54xx_l4_abe__mcbsp3,
2114 &omap54xx_l4_abe__mcpdm,
2115 &omap54xx_l4_per__mcspi1,
2116 &omap54xx_l4_per__mcspi2,
2117 &omap54xx_l4_per__mcspi3,
2118 &omap54xx_l4_per__mcspi4,
2119 &omap54xx_l4_per__mmc1,
2120 &omap54xx_l4_per__mmc2,
2121 &omap54xx_l4_per__mmc3,
2122 &omap54xx_l4_per__mmc4,
2123 &omap54xx_l4_per__mmc5,
2124 &omap54xx_l4_cfg__mpu,
2125 &omap54xx_l4_wkup__timer1,
2126 &omap54xx_l4_per__timer2,
2127 &omap54xx_l4_per__timer3,
2128 &omap54xx_l4_per__timer4,
2129 &omap54xx_l4_abe__timer5,
2130 &omap54xx_l4_abe__timer6,
2131 &omap54xx_l4_abe__timer7,
2132 &omap54xx_l4_abe__timer8,
2133 &omap54xx_l4_per__timer9,
2134 &omap54xx_l4_per__timer10,
2135 &omap54xx_l4_per__timer11,
2136 &omap54xx_l4_per__uart1,
2137 &omap54xx_l4_per__uart2,
2138 &omap54xx_l4_per__uart3,
2139 &omap54xx_l4_per__uart4,
2140 &omap54xx_l4_per__uart5,
2141 &omap54xx_l4_per__uart6,
2142 &omap54xx_l4_cfg__usb_otg_ss,
2143 &omap54xx_l4_wkup__wd_timer2,
2144 NULL,
2145};
2146
2147int __init omap54xx_hwmod_init(void)
2148{
2149 omap_hwmod_init();
2150 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2151}
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-14 21:35:09 -0400