drm/i915: Move the SPLL enabling into hsw_crt_pre_enable

The call to intel_ddi_pll_enable in haswell_crtc_mode_set is the only
function that still touches the hardware state from the crtc mode_set
callback on hsw. Since the SPLL isn't ever shared we can easily take
it out into the hsw crt encoder functions.

Temporarily we'll loose a bit of WARN_ON coverage with this, but once
the WRPLLs are switched over that will be restored. For the SPLL
selection add a WARN in the hsw fdi link training code.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
[imre: rebased on patchset version w/o pch/crt/fdi refactoring]
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2 files changed, 14 insertions, 18 deletions

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 5a045d3bd77e..d312cf89c00a 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -137,6 +137,18 @@ static void hsw_crt_get_config(struct intel_encoder *encoder,
         pipe_config->adjusted_mode.flags |= intel_crt_get_flags(encoder);
 }
 
+static void hsw_crt_pre_enable(struct intel_encoder *encoder)
+{
+        struct drm_device *dev = encoder->base.dev;
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n");
+        I915_WRITE(SPLL_CTL,
+                   SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC);
+        POSTING_READ(SPLL_CTL);
+        udelay(20);
+}
+
 /* Note: The caller is required to filter out dpms modes not supported by the
  * platform. */
 static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode)
@@ -860,6 +872,7 @@ void intel_crt_init(struct drm_device *dev)
         if (HAS_DDI(dev)) {
                 crt->base.get_config = hsw_crt_get_config;
                 crt->base.get_hw_state = intel_ddi_get_hw_state;
+                crt->base.pre_enable = hsw_crt_pre_enable;
         } else {
                 crt->base.get_config = intel_crt_get_config;
                 crt->base.get_hw_state = intel_crt_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8c57f9a141db..991ad0b9859c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -278,6 +278,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
 
         /* Configure Port Clock Select */
         I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->ddi_pll_sel);
+        WARN_ON(intel_crtc->ddi_pll_sel != PORT_CLK_SEL_SPLL);
 
         /* Start the training iterating through available voltages and emphasis,
          * testing each value twice. */
@@ -848,23 +849,6 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
         BUILD_BUG_ON(enable_bit != WRPLL_PLL_ENABLE);
 
         switch (crtc->ddi_pll_sel) {
-        case PORT_CLK_SEL_LCPLL_2700:
-        case PORT_CLK_SEL_LCPLL_1350:
-        case PORT_CLK_SEL_LCPLL_810:
-                /*
-                 * LCPLL should always be enabled at this point of the mode set
-                 * sequence, so nothing to do.
-                 */
-                return;
-
-        case PORT_CLK_SEL_SPLL:
-                new_val = SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz |
-                          SPLL_PLL_SSC;
-                WARN(I915_READ(SPLL_CTL) & enable_bit, "SPLL already enabled\n");
-                I915_WRITE(SPLL_CTL, new_val);
-                POSTING_READ(SPLL_CTL);
-                udelay(20);
-                return;
         case PORT_CLK_SEL_WRPLL1:
         case PORT_CLK_SEL_WRPLL2:
                 if (crtc->ddi_pll_sel == PORT_CLK_SEL_WRPLL1) {
@@ -889,7 +873,6 @@ void intel_ddi_pll_enable(struct intel_crtc *crtc)
                 WARN(1, "Bad selected pll: PORT_CLK_SEL_NONE\n");
                 return;
         default:
-                WARN(1, "Bad selected pll: 0x%08x\n", crtc->ddi_pll_sel);
                 return;
         }