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authorPhilipp Zabel <p.zabel@pengutronix.de>2015-01-07 17:52:15 -0500
committerPhilipp Zabel <p.zabel@pengutronix.de>2015-02-23 11:19:00 -0500
commit081c80e85feabe9a0081f4db940fccb6443b81fb (patch)
tree54a32b59ec70b0d133595675266e208bdaeb8523
parent89ce4b0f4e7adda75ac7eec6aaa9b3516390cef2 (diff)
drm/imx: dw_hdmi-imx: add mode_valid callback prune unsupported modes
This patch limits the pixel clock to 13.4 MHz - 266 MHz for i.MX6Q and 13.5 MHz - 270 MHz for i.MX6DL, which is the range documented in the HDMI Transmitter chapter of the respective reference manuals. Without this patch, when connected to a monitor capable of 2160p60 modes, dw_hdmi will happily report this mode and the IPU code will cause a division by zero in ipu_di_config_clock when trying to figure out how to divide the 264 MHz HSP clock down to ~600 MHz. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
-rw-r--r--drivers/gpu/drm/imx/dw_hdmi-imx.c32
1 files changed, 28 insertions, 4 deletions
diff --git a/drivers/gpu/drm/imx/dw_hdmi-imx.c b/drivers/gpu/drm/imx/dw_hdmi-imx.c
index 121d30ca2d44..d25aaef3cba6 100644
--- a/drivers/gpu/drm/imx/dw_hdmi-imx.c
+++ b/drivers/gpu/drm/imx/dw_hdmi-imx.c
@@ -136,11 +136,34 @@ static struct drm_encoder_funcs dw_hdmi_imx_encoder_funcs = {
136 .destroy = drm_encoder_cleanup, 136 .destroy = drm_encoder_cleanup,
137}; 137};
138 138
139static enum drm_mode_status imx6q_hdmi_mode_valid(struct drm_connector *con,
140 struct drm_display_mode *mode)
141{
142 if (mode->clock < 13500)
143 return MODE_CLOCK_LOW;
144 if (mode->clock > 266000)
145 return MODE_CLOCK_HIGH;
146
147 return MODE_OK;
148}
149
150static enum drm_mode_status imx6dl_hdmi_mode_valid(struct drm_connector *con,
151 struct drm_display_mode *mode)
152{
153 if (mode->clock < 13500)
154 return MODE_CLOCK_LOW;
155 if (mode->clock > 270000)
156 return MODE_CLOCK_HIGH;
157
158 return MODE_OK;
159}
160
139static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = { 161static struct dw_hdmi_plat_data imx6q_hdmi_drv_data = {
140 .mpll_cfg = imx_mpll_cfg, 162 .mpll_cfg = imx_mpll_cfg,
141 .cur_ctr = imx_cur_ctr, 163 .cur_ctr = imx_cur_ctr,
142 .sym_term = imx_sym_term, 164 .sym_term = imx_sym_term,
143 .dev_type = IMX6Q_HDMI, 165 .dev_type = IMX6Q_HDMI,
166 .mode_valid = imx6q_hdmi_mode_valid,
144}; 167};
145 168
146static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = { 169static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
@@ -148,6 +171,7 @@ static struct dw_hdmi_plat_data imx6dl_hdmi_drv_data = {
148 .cur_ctr = imx_cur_ctr, 171 .cur_ctr = imx_cur_ctr,
149 .sym_term = imx_sym_term, 172 .sym_term = imx_sym_term,
150 .dev_type = IMX6DL_HDMI, 173 .dev_type = IMX6DL_HDMI,
174 .mode_valid = imx6dl_hdmi_mode_valid,
151}; 175};
152 176
153static const struct of_device_id dw_hdmi_imx_dt_ids[] = { 177static const struct of_device_id dw_hdmi_imx_dt_ids[] = {