Merge tag 'clk-mvebu-3xx-3.15-2' of git://git.infradead.org/linux-mvebu into clk-next-mvebu

clock: mvebu new SoC changes for v3.15 (incremental pull #2)

 - mvebu (Armada 375)
    - fix ratio register offest

 - mvebu (Armada 380)
    - expand core divider clock driver to support 380 SoC (enables nand support)

2 files changed, 28 insertions, 2 deletions

diff --git a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
index c62391fc0e39..520562a7dc2a 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt
@@ -4,7 +4,10 @@ The following is a list of provided IDs and clock names on Armada 370/XP:
  0 = nand (NAND clock)
 
 Required properties:
-- compatible : must be "marvell,armada-370-corediv-clock"
+- compatible : must be "marvell,armada-370-corediv-clock",
+                       "marvell,armada-375-corediv-clock",
+                       "marvell,armada-380-corediv-clock",
+
 - reg : must be the register address of Core Divider control register
 - #clock-cells : from common clock binding; shall be set to 1
 - clocks : must be set to the parent's phandle
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index 4da60760be10..d1e5863d3375 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -204,6 +204,22 @@ static const struct clk_corediv_soc_desc armada370_corediv_soc = {
         .ratio_offset = 0x8,
 };
 
+static const struct clk_corediv_soc_desc armada380_corediv_soc = {
+        .descs = mvebu_corediv_desc,
+        .ndescs = ARRAY_SIZE(mvebu_corediv_desc),
+        .ops = {
+                .enable = clk_corediv_enable,
+                .disable = clk_corediv_disable,
+                .is_enabled = clk_corediv_is_enabled,
+                .recalc_rate = clk_corediv_recalc_rate,
+                .round_rate = clk_corediv_round_rate,
+                .set_rate = clk_corediv_set_rate,
+        },
+        .ratio_reload = BIT(8),
+        .enable_bit_offset = 16,
+        .ratio_offset = 0x4,
+};
+
 static const struct clk_corediv_soc_desc armada375_corediv_soc = {
         .descs = mvebu_corediv_desc,
         .ndescs = ARRAY_SIZE(mvebu_corediv_desc),
@@ -213,7 +229,7 @@ static const struct clk_corediv_soc_desc armada375_corediv_soc = {
                 .set_rate = clk_corediv_set_rate,
         },
         .ratio_reload = BIT(8),
-        .ratio_offset = 0x8,
+        .ratio_offset = 0x4,
 };
 
 static void __init
@@ -290,3 +306,10 @@ static void __init armada375_corediv_clk_init(struct device_node *node)
 }
 CLK_OF_DECLARE(armada375_corediv_clk, "marvell,armada-375-corediv-clock",
                armada375_corediv_clk_init);
+
+static void __init armada380_corediv_clk_init(struct device_node *node)
+{
+        return mvebu_corediv_clk_init(node, &armada380_corediv_soc);
+}
+CLK_OF_DECLARE(armada380_corediv_clk, "marvell,armada-380-corediv-clock",
+               armada380_corediv_clk_init);