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authorSuman Anna <s-anna@ti.com>2014-07-11 17:44:39 -0400
committerTony Lindgren <tony@atomide.com>2014-07-15 08:08:56 -0400
commit067395d49c5149b7b50fa93e9cb691a184b24927 (patch)
tree7ab557e18dc087311adb42d1bda9963456c6ce4d
parent38baefb33f418991072d64b0c8d619def3c362d3 (diff)
ARM: DRA7: hwmod_data: Add mailbox hwmod data
Add the hwmod data for the 13 instances of the system mailbox IP in DRA7 SoC. The patch is needed for performing a soft-reset while configuring the respective mailbox instance, otherwise is a non-essential change for functionality. The modules are smart idled on reset, and the IP module mode is hardware controlled. Cc: Rajendra Nayak <rnayak@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c305
1 files changed, 305 insertions, 0 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 20b4398cec05..e35f5b18de6d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -939,6 +939,194 @@ static struct omap_hwmod dra7xx_i2c5_hwmod = {
939}; 939};
940 940
941/* 941/*
942 * 'mailbox' class
943 *
944 */
945
946static struct omap_hwmod_class_sysconfig dra7xx_mailbox_sysc = {
947 .rev_offs = 0x0000,
948 .sysc_offs = 0x0010,
949 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
950 SYSC_HAS_SOFTRESET),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
952 .sysc_fields = &omap_hwmod_sysc_type2,
953};
954
955static struct omap_hwmod_class dra7xx_mailbox_hwmod_class = {
956 .name = "mailbox",
957 .sysc = &dra7xx_mailbox_sysc,
958};
959
960/* mailbox1 */
961static struct omap_hwmod dra7xx_mailbox1_hwmod = {
962 .name = "mailbox1",
963 .class = &dra7xx_mailbox_hwmod_class,
964 .clkdm_name = "l4cfg_clkdm",
965 .prcm = {
966 .omap4 = {
967 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET,
968 .context_offs = DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET,
969 },
970 },
971};
972
973/* mailbox2 */
974static struct omap_hwmod dra7xx_mailbox2_hwmod = {
975 .name = "mailbox2",
976 .class = &dra7xx_mailbox_hwmod_class,
977 .clkdm_name = "l4cfg_clkdm",
978 .prcm = {
979 .omap4 = {
980 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET,
981 .context_offs = DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET,
982 },
983 },
984};
985
986/* mailbox3 */
987static struct omap_hwmod dra7xx_mailbox3_hwmod = {
988 .name = "mailbox3",
989 .class = &dra7xx_mailbox_hwmod_class,
990 .clkdm_name = "l4cfg_clkdm",
991 .prcm = {
992 .omap4 = {
993 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET,
994 .context_offs = DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET,
995 },
996 },
997};
998
999/* mailbox4 */
1000static struct omap_hwmod dra7xx_mailbox4_hwmod = {
1001 .name = "mailbox4",
1002 .class = &dra7xx_mailbox_hwmod_class,
1003 .clkdm_name = "l4cfg_clkdm",
1004 .prcm = {
1005 .omap4 = {
1006 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET,
1007 .context_offs = DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET,
1008 },
1009 },
1010};
1011
1012/* mailbox5 */
1013static struct omap_hwmod dra7xx_mailbox5_hwmod = {
1014 .name = "mailbox5",
1015 .class = &dra7xx_mailbox_hwmod_class,
1016 .clkdm_name = "l4cfg_clkdm",
1017 .prcm = {
1018 .omap4 = {
1019 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET,
1020 .context_offs = DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET,
1021 },
1022 },
1023};
1024
1025/* mailbox6 */
1026static struct omap_hwmod dra7xx_mailbox6_hwmod = {
1027 .name = "mailbox6",
1028 .class = &dra7xx_mailbox_hwmod_class,
1029 .clkdm_name = "l4cfg_clkdm",
1030 .prcm = {
1031 .omap4 = {
1032 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET,
1033 .context_offs = DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET,
1034 },
1035 },
1036};
1037
1038/* mailbox7 */
1039static struct omap_hwmod dra7xx_mailbox7_hwmod = {
1040 .name = "mailbox7",
1041 .class = &dra7xx_mailbox_hwmod_class,
1042 .clkdm_name = "l4cfg_clkdm",
1043 .prcm = {
1044 .omap4 = {
1045 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET,
1046 .context_offs = DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET,
1047 },
1048 },
1049};
1050
1051/* mailbox8 */
1052static struct omap_hwmod dra7xx_mailbox8_hwmod = {
1053 .name = "mailbox8",
1054 .class = &dra7xx_mailbox_hwmod_class,
1055 .clkdm_name = "l4cfg_clkdm",
1056 .prcm = {
1057 .omap4 = {
1058 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET,
1059 .context_offs = DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET,
1060 },
1061 },
1062};
1063
1064/* mailbox9 */
1065static struct omap_hwmod dra7xx_mailbox9_hwmod = {
1066 .name = "mailbox9",
1067 .class = &dra7xx_mailbox_hwmod_class,
1068 .clkdm_name = "l4cfg_clkdm",
1069 .prcm = {
1070 .omap4 = {
1071 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET,
1072 .context_offs = DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET,
1073 },
1074 },
1075};
1076
1077/* mailbox10 */
1078static struct omap_hwmod dra7xx_mailbox10_hwmod = {
1079 .name = "mailbox10",
1080 .class = &dra7xx_mailbox_hwmod_class,
1081 .clkdm_name = "l4cfg_clkdm",
1082 .prcm = {
1083 .omap4 = {
1084 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET,
1085 .context_offs = DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET,
1086 },
1087 },
1088};
1089
1090/* mailbox11 */
1091static struct omap_hwmod dra7xx_mailbox11_hwmod = {
1092 .name = "mailbox11",
1093 .class = &dra7xx_mailbox_hwmod_class,
1094 .clkdm_name = "l4cfg_clkdm",
1095 .prcm = {
1096 .omap4 = {
1097 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET,
1098 .context_offs = DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET,
1099 },
1100 },
1101};
1102
1103/* mailbox12 */
1104static struct omap_hwmod dra7xx_mailbox12_hwmod = {
1105 .name = "mailbox12",
1106 .class = &dra7xx_mailbox_hwmod_class,
1107 .clkdm_name = "l4cfg_clkdm",
1108 .prcm = {
1109 .omap4 = {
1110 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET,
1111 .context_offs = DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET,
1112 },
1113 },
1114};
1115
1116/* mailbox13 */
1117static struct omap_hwmod dra7xx_mailbox13_hwmod = {
1118 .name = "mailbox13",
1119 .class = &dra7xx_mailbox_hwmod_class,
1120 .clkdm_name = "l4cfg_clkdm",
1121 .prcm = {
1122 .omap4 = {
1123 .clkctrl_offs = DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET,
1124 .context_offs = DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET,
1125 },
1126 },
1127};
1128
1129/*
942 * 'mcspi' class 1130 * 'mcspi' class
943 * 1131 *
944 */ 1132 */
@@ -2246,6 +2434,110 @@ static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2246 .user = OCP_USER_MPU | OCP_USER_SDMA, 2434 .user = OCP_USER_MPU | OCP_USER_SDMA,
2247}; 2435};
2248 2436
2437/* l4_cfg -> mailbox1 */
2438static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mailbox1 = {
2439 .master = &dra7xx_l4_cfg_hwmod,
2440 .slave = &dra7xx_mailbox1_hwmod,
2441 .clk = "l3_iclk_div",
2442 .user = OCP_USER_MPU | OCP_USER_SDMA,
2443};
2444
2445/* l4_per3 -> mailbox2 */
2446static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox2 = {
2447 .master = &dra7xx_l4_per3_hwmod,
2448 .slave = &dra7xx_mailbox2_hwmod,
2449 .clk = "l3_iclk_div",
2450 .user = OCP_USER_MPU | OCP_USER_SDMA,
2451};
2452
2453/* l4_per3 -> mailbox3 */
2454static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox3 = {
2455 .master = &dra7xx_l4_per3_hwmod,
2456 .slave = &dra7xx_mailbox3_hwmod,
2457 .clk = "l3_iclk_div",
2458 .user = OCP_USER_MPU | OCP_USER_SDMA,
2459};
2460
2461/* l4_per3 -> mailbox4 */
2462static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox4 = {
2463 .master = &dra7xx_l4_per3_hwmod,
2464 .slave = &dra7xx_mailbox4_hwmod,
2465 .clk = "l3_iclk_div",
2466 .user = OCP_USER_MPU | OCP_USER_SDMA,
2467};
2468
2469/* l4_per3 -> mailbox5 */
2470static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox5 = {
2471 .master = &dra7xx_l4_per3_hwmod,
2472 .slave = &dra7xx_mailbox5_hwmod,
2473 .clk = "l3_iclk_div",
2474 .user = OCP_USER_MPU | OCP_USER_SDMA,
2475};
2476
2477/* l4_per3 -> mailbox6 */
2478static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox6 = {
2479 .master = &dra7xx_l4_per3_hwmod,
2480 .slave = &dra7xx_mailbox6_hwmod,
2481 .clk = "l3_iclk_div",
2482 .user = OCP_USER_MPU | OCP_USER_SDMA,
2483};
2484
2485/* l4_per3 -> mailbox7 */
2486static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox7 = {
2487 .master = &dra7xx_l4_per3_hwmod,
2488 .slave = &dra7xx_mailbox7_hwmod,
2489 .clk = "l3_iclk_div",
2490 .user = OCP_USER_MPU | OCP_USER_SDMA,
2491};
2492
2493/* l4_per3 -> mailbox8 */
2494static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox8 = {
2495 .master = &dra7xx_l4_per3_hwmod,
2496 .slave = &dra7xx_mailbox8_hwmod,
2497 .clk = "l3_iclk_div",
2498 .user = OCP_USER_MPU | OCP_USER_SDMA,
2499};
2500
2501/* l4_per3 -> mailbox9 */
2502static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox9 = {
2503 .master = &dra7xx_l4_per3_hwmod,
2504 .slave = &dra7xx_mailbox9_hwmod,
2505 .clk = "l3_iclk_div",
2506 .user = OCP_USER_MPU | OCP_USER_SDMA,
2507};
2508
2509/* l4_per3 -> mailbox10 */
2510static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox10 = {
2511 .master = &dra7xx_l4_per3_hwmod,
2512 .slave = &dra7xx_mailbox10_hwmod,
2513 .clk = "l3_iclk_div",
2514 .user = OCP_USER_MPU | OCP_USER_SDMA,
2515};
2516
2517/* l4_per3 -> mailbox11 */
2518static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox11 = {
2519 .master = &dra7xx_l4_per3_hwmod,
2520 .slave = &dra7xx_mailbox11_hwmod,
2521 .clk = "l3_iclk_div",
2522 .user = OCP_USER_MPU | OCP_USER_SDMA,
2523};
2524
2525/* l4_per3 -> mailbox12 */
2526static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox12 = {
2527 .master = &dra7xx_l4_per3_hwmod,
2528 .slave = &dra7xx_mailbox12_hwmod,
2529 .clk = "l3_iclk_div",
2530 .user = OCP_USER_MPU | OCP_USER_SDMA,
2531};
2532
2533/* l4_per3 -> mailbox13 */
2534static struct omap_hwmod_ocp_if dra7xx_l4_per3__mailbox13 = {
2535 .master = &dra7xx_l4_per3_hwmod,
2536 .slave = &dra7xx_mailbox13_hwmod,
2537 .clk = "l3_iclk_div",
2538 .user = OCP_USER_MPU | OCP_USER_SDMA,
2539};
2540
2249/* l4_per1 -> mcspi1 */ 2541/* l4_per1 -> mcspi1 */
2250static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = { 2542static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2251 .master = &dra7xx_l4_per1_hwmod, 2543 .master = &dra7xx_l4_per1_hwmod,
@@ -2662,6 +2954,19 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2662 &dra7xx_l4_per1__i2c3, 2954 &dra7xx_l4_per1__i2c3,
2663 &dra7xx_l4_per1__i2c4, 2955 &dra7xx_l4_per1__i2c4,
2664 &dra7xx_l4_per1__i2c5, 2956 &dra7xx_l4_per1__i2c5,
2957 &dra7xx_l4_cfg__mailbox1,
2958 &dra7xx_l4_per3__mailbox2,
2959 &dra7xx_l4_per3__mailbox3,
2960 &dra7xx_l4_per3__mailbox4,
2961 &dra7xx_l4_per3__mailbox5,
2962 &dra7xx_l4_per3__mailbox6,
2963 &dra7xx_l4_per3__mailbox7,
2964 &dra7xx_l4_per3__mailbox8,
2965 &dra7xx_l4_per3__mailbox9,
2966 &dra7xx_l4_per3__mailbox10,
2967 &dra7xx_l4_per3__mailbox11,
2968 &dra7xx_l4_per3__mailbox12,
2969 &dra7xx_l4_per3__mailbox13,
2665 &dra7xx_l4_per1__mcspi1, 2970 &dra7xx_l4_per1__mcspi1,
2666 &dra7xx_l4_per1__mcspi2, 2971 &dra7xx_l4_per1__mcspi2,
2667 &dra7xx_l4_per1__mcspi3, 2972 &dra7xx_l4_per1__mcspi3,