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authorMathias Krause <minipli@googlemail.com>2014-08-26 12:49:45 -0400
committerIngo Molnar <mingo@kernel.org>2014-09-09 00:53:06 -0400
commit066ce64c7e867e95e5fee7c5f6b852710486392a (patch)
treec375c6ce21cff99ed8faf196f6285b1fad4810f8
parent70691d4a0bf7c871559d4ef1b0056edefbca123b (diff)
perf/x86/intel: Mark initialization code as such
A few of the initialization functions are missing the __init annotation. Fix this and thereby allow ~680 additional bytes of code to be released after initialization. Signed-off-by: Mathias Krause <minipli@googlemail.com> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: x86@kernel.org Link: http://lkml.kernel.org/r/1409071785-26015-1-git-send-email-minipli@googlemail.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_ds.c2
-rw-r--r--arch/x86/kernel/cpu/perf_event_intel_lbr.c8
2 files changed, 5 insertions, 5 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c
index 9dc419991772..b1553d05a5cb 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
@@ -1014,7 +1014,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1014 * BTS, PEBS probe and setup 1014 * BTS, PEBS probe and setup
1015 */ 1015 */
1016 1016
1017void intel_ds_init(void) 1017void __init intel_ds_init(void)
1018{ 1018{
1019 /* 1019 /*
1020 * No support for 32bit formats 1020 * No support for 32bit formats
diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 9dd2459a4c73..4af10617de33 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -697,7 +697,7 @@ static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX] = {
697}; 697};
698 698
699/* core */ 699/* core */
700void intel_pmu_lbr_init_core(void) 700void __init intel_pmu_lbr_init_core(void)
701{ 701{
702 x86_pmu.lbr_nr = 4; 702 x86_pmu.lbr_nr = 4;
703 x86_pmu.lbr_tos = MSR_LBR_TOS; 703 x86_pmu.lbr_tos = MSR_LBR_TOS;
@@ -712,7 +712,7 @@ void intel_pmu_lbr_init_core(void)
712} 712}
713 713
714/* nehalem/westmere */ 714/* nehalem/westmere */
715void intel_pmu_lbr_init_nhm(void) 715void __init intel_pmu_lbr_init_nhm(void)
716{ 716{
717 x86_pmu.lbr_nr = 16; 717 x86_pmu.lbr_nr = 16;
718 x86_pmu.lbr_tos = MSR_LBR_TOS; 718 x86_pmu.lbr_tos = MSR_LBR_TOS;
@@ -733,7 +733,7 @@ void intel_pmu_lbr_init_nhm(void)
733} 733}
734 734
735/* sandy bridge */ 735/* sandy bridge */
736void intel_pmu_lbr_init_snb(void) 736void __init intel_pmu_lbr_init_snb(void)
737{ 737{
738 x86_pmu.lbr_nr = 16; 738 x86_pmu.lbr_nr = 16;
739 x86_pmu.lbr_tos = MSR_LBR_TOS; 739 x86_pmu.lbr_tos = MSR_LBR_TOS;
@@ -753,7 +753,7 @@ void intel_pmu_lbr_init_snb(void)
753} 753}
754 754
755/* atom */ 755/* atom */
756void intel_pmu_lbr_init_atom(void) 756void __init intel_pmu_lbr_init_atom(void)
757{ 757{
758 /* 758 /*
759 * only models starting at stepping 10 seems 759 * only models starting at stepping 10 seems