diff options
author | Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> | 2013-06-25 14:28:59 -0400 |
---|---|---|
committer | Tony Luck <tony.luck@intel.com> | 2013-06-25 16:53:27 -0400 |
commit | 0644414e62561f0ba1bea7c5ba6a94cc50dac3e3 (patch) | |
tree | deb10365752b0959a3429bb1e19b6d785d354cbc | |
parent | 9e895ace5d82df8929b16f58e9f515f6d54ab82d (diff) |
mce: acpi/apei: Add comments to clarify usage of the various bitfields in the MCA subsystem
There is some confusion about the 'mce_poll_banks' and 'mce_banks_owned'
per-cpu bitmaps. Provide comments so that we all know exactly what these
are used for, and why.
Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Acked-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Tony Luck <tony.luck@intel.com>
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce.c | 5 | ||||
-rw-r--r-- | arch/x86/kernel/cpu/mcheck/mce_intel.c | 12 |
2 files changed, 16 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 9239504b41cb..bf49cdbb010f 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c | |||
@@ -89,7 +89,10 @@ static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait); | |||
89 | static DEFINE_PER_CPU(struct mce, mces_seen); | 89 | static DEFINE_PER_CPU(struct mce, mces_seen); |
90 | static int cpu_missing; | 90 | static int cpu_missing; |
91 | 91 | ||
92 | /* MCA banks polled by the period polling timer for corrected events */ | 92 | /* |
93 | * MCA banks polled by the period polling timer for corrected events. | ||
94 | * With Intel CMCI, this only has MCA banks which do not support CMCI (if any). | ||
95 | */ | ||
93 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { | 96 | DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = { |
94 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL | 97 | [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL |
95 | }; | 98 | }; |
diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index ae1697c2afe3..d56405309dc1 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c | |||
@@ -24,6 +24,18 @@ | |||
24 | * Also supports reliable discovery of shared banks. | 24 | * Also supports reliable discovery of shared banks. |
25 | */ | 25 | */ |
26 | 26 | ||
27 | /* | ||
28 | * CMCI can be delivered to multiple cpus that share a machine check bank | ||
29 | * so we need to designate a single cpu to process errors logged in each bank | ||
30 | * in the interrupt handler (otherwise we would have many races and potential | ||
31 | * double reporting of the same error). | ||
32 | * Note that this can change when a cpu is offlined or brought online since | ||
33 | * some MCA banks are shared across cpus. When a cpu is offlined, cmci_clear() | ||
34 | * disables CMCI on all banks owned by the cpu and clears this bitfield. At | ||
35 | * this point, cmci_rediscover() kicks in and a different cpu may end up | ||
36 | * taking ownership of some of the shared MCA banks that were previously | ||
37 | * owned by the offlined cpu. | ||
38 | */ | ||
27 | static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned); | 39 | static DEFINE_PER_CPU(mce_banks_t, mce_banks_owned); |
28 | 40 | ||
29 | /* | 41 | /* |