diff options
author | Arnd Bergmann <arnd@arndb.de> | 2013-03-28 07:25:51 -0400 |
---|---|---|
committer | Arnd Bergmann <arnd@arndb.de> | 2013-03-28 07:25:51 -0400 |
commit | 063ab6daeb2ba5ef8f47c3fc04a749936c62d5bb (patch) | |
tree | 43532e85397b7105999851a2875db9bbf043080e | |
parent | cde35bd027023b052316c14ae3fc01e2f487a6ab (diff) | |
parent | dbaf6a8d5de7b63f85eea10a47681f920cbf7385 (diff) |
Merge branch 'prima2/multiplatform' into next/multiplatform
This series enables multiplatform support on the SIRF prima2/marco/atlas6
platform. The code was already quite tidy, so this is a relatively simple
change, and it follows similar changes we made to other ARMv7 based
platforms recently.
* prima2/multiplatform:
ARM: sirf: enable support in multi_v7_defconfig
ARM: sirf: enable multiplatform support
ARM: sirf: use clocksource_of infrastructure
ARM: sirf: move debug-macro.S to include/debug/sirf.S
ARM: sirf: enable sparse IRQ
ARM: sirf: move irq driver to drivers/irqchip
ARM: sirf: fix prima2 interrupt lookup
pinctrl: sirf: convert to linear irq domain
clocksource: make CLOCKSOURCE_OF_DECLARE type safe
ARM/dts: prima2: add .dtsi for atlas6 and .dts for atla6-evb board
arm: prima2: add new SiRFatlas6 machine in common board
ARM: smp_twd: convert to use CLKSRC_OF init
clocksource: tegra20: use the device_node pointer passed to init
clocksource: pass DT node pointer to init functions
clocksource: add empty version of clocksource_of_init
Conflicts:
arch/arm/configs/multi_v7_defconfig
arch/arm/mach-spear/spear13xx.c
Tested-by: Barry Song <Barry.Song@csr.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
40 files changed, 1047 insertions, 511 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index e2c7ecf0d1ca..6423b587fa23 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -49,7 +49,6 @@ config ARM | |||
49 | select HAVE_REGS_AND_STACK_ACCESS_API | 49 | select HAVE_REGS_AND_STACK_ACCESS_API |
50 | select HAVE_SYSCALL_TRACEPOINTS | 50 | select HAVE_SYSCALL_TRACEPOINTS |
51 | select HAVE_UID16 | 51 | select HAVE_UID16 |
52 | select HAVE_VIRT_TO_BUS | ||
53 | select KTIME_SCALAR | 52 | select KTIME_SCALAR |
54 | select PERF_USE_VMALLOC | 53 | select PERF_USE_VMALLOC |
55 | select RTC_LIB | 54 | select RTC_LIB |
@@ -404,21 +403,6 @@ config ARCH_GEMINI | |||
404 | help | 403 | help |
405 | Support for the Cortina Systems Gemini family SoCs | 404 | Support for the Cortina Systems Gemini family SoCs |
406 | 405 | ||
407 | config ARCH_SIRF | ||
408 | bool "CSR SiRF" | ||
409 | select ARCH_REQUIRE_GPIOLIB | ||
410 | select AUTO_ZRELADDR | ||
411 | select COMMON_CLK | ||
412 | select GENERIC_CLOCKEVENTS | ||
413 | select GENERIC_IRQ_CHIP | ||
414 | select MIGHT_HAVE_CACHE_L2X0 | ||
415 | select NO_IOPORT | ||
416 | select PINCTRL | ||
417 | select PINCTRL_SIRF | ||
418 | select USE_OF | ||
419 | help | ||
420 | Support for CSR SiRFprimaII/Marco/Polo platforms | ||
421 | |||
422 | config ARCH_EBSA110 | 406 | config ARCH_EBSA110 |
423 | bool "EBSA-110" | 407 | bool "EBSA-110" |
424 | select ARCH_USES_GETTIMEOFFSET | 408 | select ARCH_USES_GETTIMEOFFSET |
@@ -1557,6 +1541,7 @@ config HAVE_ARM_ARCH_TIMER | |||
1557 | config HAVE_ARM_TWD | 1541 | config HAVE_ARM_TWD |
1558 | bool | 1542 | bool |
1559 | depends on SMP | 1543 | depends on SMP |
1544 | select CLKSRC_OF if OF | ||
1560 | help | 1545 | help |
1561 | This options enables support for the ARM timer and watchdog unit | 1546 | This options enables support for the ARM timer and watchdog unit |
1562 | 1547 | ||
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 5115ff9e8a2a..fd17127b4188 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
@@ -608,6 +608,7 @@ config DEBUG_LL_INCLUDE | |||
608 | default "debug/nomadik.S" if DEBUG_NOMADIK_UART | 608 | default "debug/nomadik.S" if DEBUG_NOMADIK_UART |
609 | default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART | 609 | default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART |
610 | default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART | 610 | default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART |
611 | default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 | ||
611 | default "debug/socfpga.S" if DEBUG_SOCFPGA_UART | 612 | default "debug/socfpga.S" if DEBUG_SOCFPGA_UART |
612 | default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 | 613 | default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 |
613 | default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ | 614 | default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \ |
diff --git a/arch/arm/boot/dts/atlas6-evb.dts b/arch/arm/boot/dts/atlas6-evb.dts new file mode 100644 index 000000000000..ab042ca8dea1 --- /dev/null +++ b/arch/arm/boot/dts/atlas6-evb.dts | |||
@@ -0,0 +1,78 @@ | |||
1 | /* | ||
2 | * DTS file for CSR SiRFatlas6 Evaluation Board | ||
3 | * | ||
4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | /dts-v1/; | ||
10 | |||
11 | /include/ "atlas6.dtsi" | ||
12 | |||
13 | / { | ||
14 | model = "CSR SiRFatlas6 Evaluation Board"; | ||
15 | compatible = "sirf,atlas6-cb", "sirf,atlas6"; | ||
16 | |||
17 | memory { | ||
18 | reg = <0x00000000 0x20000000>; | ||
19 | }; | ||
20 | |||
21 | axi { | ||
22 | peri-iobg { | ||
23 | uart@b0060000 { | ||
24 | pinctrl-names = "default"; | ||
25 | pinctrl-0 = <&uart1_pins_a>; | ||
26 | }; | ||
27 | spi@b00d0000 { | ||
28 | status = "okay"; | ||
29 | pinctrl-names = "default"; | ||
30 | pinctrl-0 = <&spi0_pins_a>; | ||
31 | spi@0 { | ||
32 | compatible = "spidev"; | ||
33 | reg = <0>; | ||
34 | spi-max-frequency = <1000000>; | ||
35 | }; | ||
36 | }; | ||
37 | spi@b0170000 { | ||
38 | pinctrl-names = "default"; | ||
39 | pinctrl-0 = <&spi1_pins_a>; | ||
40 | }; | ||
41 | i2c0: i2c@b00e0000 { | ||
42 | status = "okay"; | ||
43 | pinctrl-names = "default"; | ||
44 | pinctrl-0 = <&i2c0_pins_a>; | ||
45 | lcd@40 { | ||
46 | compatible = "sirf,lcd"; | ||
47 | reg = <0x40>; | ||
48 | }; | ||
49 | }; | ||
50 | |||
51 | }; | ||
52 | disp-iobg { | ||
53 | lcd@90010000 { | ||
54 | status = "okay"; | ||
55 | pinctrl-names = "default"; | ||
56 | pinctrl-0 = <&lcd_24pins_a>; | ||
57 | }; | ||
58 | }; | ||
59 | }; | ||
60 | display: display@0 { | ||
61 | panels { | ||
62 | panel0: panel@0 { | ||
63 | panel-name = "Innolux TFT"; | ||
64 | hactive = <800>; | ||
65 | vactive = <480>; | ||
66 | left_margin = <20>; | ||
67 | right_margin = <234>; | ||
68 | upper_margin = <3>; | ||
69 | lower_margin = <41>; | ||
70 | hsync_len = <3>; | ||
71 | vsync_len = <2>; | ||
72 | pixclock = <33264000>; | ||
73 | sync = <3>; | ||
74 | timing = <0x88>; | ||
75 | }; | ||
76 | }; | ||
77 | }; | ||
78 | }; | ||
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi new file mode 100644 index 000000000000..7d1a27949c13 --- /dev/null +++ b/arch/arm/boot/dts/atlas6.dtsi | |||
@@ -0,0 +1,668 @@ | |||
1 | /* | ||
2 | * DTS file for CSR SiRFatlas6 SoC | ||
3 | * | ||
4 | * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | /include/ "skeleton.dtsi" | ||
10 | / { | ||
11 | compatible = "sirf,atlas6"; | ||
12 | #address-cells = <1>; | ||
13 | #size-cells = <1>; | ||
14 | interrupt-parent = <&intc>; | ||
15 | |||
16 | cpus { | ||
17 | #address-cells = <1>; | ||
18 | #size-cells = <0>; | ||
19 | |||
20 | cpu@0 { | ||
21 | reg = <0x0>; | ||
22 | d-cache-line-size = <32>; | ||
23 | i-cache-line-size = <32>; | ||
24 | d-cache-size = <32768>; | ||
25 | i-cache-size = <32768>; | ||
26 | /* from bootloader */ | ||
27 | timebase-frequency = <0>; | ||
28 | bus-frequency = <0>; | ||
29 | clock-frequency = <0>; | ||
30 | }; | ||
31 | }; | ||
32 | |||
33 | axi { | ||
34 | compatible = "simple-bus"; | ||
35 | #address-cells = <1>; | ||
36 | #size-cells = <1>; | ||
37 | ranges = <0x40000000 0x40000000 0x80000000>; | ||
38 | |||
39 | intc: interrupt-controller@80020000 { | ||
40 | #interrupt-cells = <1>; | ||
41 | interrupt-controller; | ||
42 | compatible = "sirf,prima2-intc"; | ||
43 | reg = <0x80020000 0x1000>; | ||
44 | }; | ||
45 | |||
46 | sys-iobg { | ||
47 | compatible = "simple-bus"; | ||
48 | #address-cells = <1>; | ||
49 | #size-cells = <1>; | ||
50 | ranges = <0x88000000 0x88000000 0x40000>; | ||
51 | |||
52 | clks: clock-controller@88000000 { | ||
53 | compatible = "sirf,atlas6-clkc"; | ||
54 | reg = <0x88000000 0x1000>; | ||
55 | interrupts = <3>; | ||
56 | #clock-cells = <1>; | ||
57 | }; | ||
58 | |||
59 | reset-controller@88010000 { | ||
60 | compatible = "sirf,prima2-rstc"; | ||
61 | reg = <0x88010000 0x1000>; | ||
62 | }; | ||
63 | |||
64 | rsc-controller@88020000 { | ||
65 | compatible = "sirf,prima2-rsc"; | ||
66 | reg = <0x88020000 0x1000>; | ||
67 | }; | ||
68 | }; | ||
69 | |||
70 | mem-iobg { | ||
71 | compatible = "simple-bus"; | ||
72 | #address-cells = <1>; | ||
73 | #size-cells = <1>; | ||
74 | ranges = <0x90000000 0x90000000 0x10000>; | ||
75 | |||
76 | memory-controller@90000000 { | ||
77 | compatible = "sirf,prima2-memc"; | ||
78 | reg = <0x90000000 0x10000>; | ||
79 | interrupts = <27>; | ||
80 | clocks = <&clks 5>; | ||
81 | }; | ||
82 | }; | ||
83 | |||
84 | disp-iobg { | ||
85 | compatible = "simple-bus"; | ||
86 | #address-cells = <1>; | ||
87 | #size-cells = <1>; | ||
88 | ranges = <0x90010000 0x90010000 0x30000>; | ||
89 | |||
90 | lcd@90010000 { | ||
91 | compatible = "sirf,prima2-lcd"; | ||
92 | reg = <0x90010000 0x20000>; | ||
93 | interrupts = <30>; | ||
94 | clocks = <&clks 34>; | ||
95 | display=<&display>; | ||
96 | /* later transfer to pwm */ | ||
97 | bl-gpio = <&gpio 7 0>; | ||
98 | default-panel = <&panel0>; | ||
99 | }; | ||
100 | |||
101 | vpp@90020000 { | ||
102 | compatible = "sirf,prima2-vpp"; | ||
103 | reg = <0x90020000 0x10000>; | ||
104 | interrupts = <31>; | ||
105 | clocks = <&clks 35>; | ||
106 | }; | ||
107 | }; | ||
108 | |||
109 | graphics-iobg { | ||
110 | compatible = "simple-bus"; | ||
111 | #address-cells = <1>; | ||
112 | #size-cells = <1>; | ||
113 | ranges = <0x98000000 0x98000000 0x8000000>; | ||
114 | |||
115 | graphics@98000000 { | ||
116 | compatible = "powervr,sgx510"; | ||
117 | reg = <0x98000000 0x8000000>; | ||
118 | interrupts = <6>; | ||
119 | clocks = <&clks 32>; | ||
120 | }; | ||
121 | }; | ||
122 | |||
123 | dsp-iobg { | ||
124 | compatible = "simple-bus"; | ||
125 | #address-cells = <1>; | ||
126 | #size-cells = <1>; | ||
127 | ranges = <0xa8000000 0xa8000000 0x2000000>; | ||
128 | |||
129 | dspif@a8000000 { | ||
130 | compatible = "sirf,prima2-dspif"; | ||
131 | reg = <0xa8000000 0x10000>; | ||
132 | interrupts = <9>; | ||
133 | }; | ||
134 | |||
135 | gps@a8010000 { | ||
136 | compatible = "sirf,prima2-gps"; | ||
137 | reg = <0xa8010000 0x10000>; | ||
138 | interrupts = <7>; | ||
139 | clocks = <&clks 9>; | ||
140 | }; | ||
141 | |||
142 | dsp@a9000000 { | ||
143 | compatible = "sirf,prima2-dsp"; | ||
144 | reg = <0xa9000000 0x1000000>; | ||
145 | interrupts = <8>; | ||
146 | clocks = <&clks 8>; | ||
147 | }; | ||
148 | }; | ||
149 | |||
150 | peri-iobg { | ||
151 | compatible = "simple-bus"; | ||
152 | #address-cells = <1>; | ||
153 | #size-cells = <1>; | ||
154 | ranges = <0xb0000000 0xb0000000 0x180000>, | ||
155 | <0x56000000 0x56000000 0x1b00000>; | ||
156 | |||
157 | timer@b0020000 { | ||
158 | compatible = "sirf,prima2-tick"; | ||
159 | reg = <0xb0020000 0x1000>; | ||
160 | interrupts = <0>; | ||
161 | }; | ||
162 | |||
163 | nand@b0030000 { | ||
164 | compatible = "sirf,prima2-nand"; | ||
165 | reg = <0xb0030000 0x10000>; | ||
166 | interrupts = <41>; | ||
167 | clocks = <&clks 26>; | ||
168 | }; | ||
169 | |||
170 | audio@b0040000 { | ||
171 | compatible = "sirf,prima2-audio"; | ||
172 | reg = <0xb0040000 0x10000>; | ||
173 | interrupts = <35>; | ||
174 | clocks = <&clks 27>; | ||
175 | }; | ||
176 | |||
177 | uart0: uart@b0050000 { | ||
178 | cell-index = <0>; | ||
179 | compatible = "sirf,prima2-uart"; | ||
180 | reg = <0xb0050000 0x1000>; | ||
181 | interrupts = <17>; | ||
182 | fifosize = <128>; | ||
183 | clocks = <&clks 13>; | ||
184 | }; | ||
185 | |||
186 | uart1: uart@b0060000 { | ||
187 | cell-index = <1>; | ||
188 | compatible = "sirf,prima2-uart"; | ||
189 | reg = <0xb0060000 0x1000>; | ||
190 | interrupts = <18>; | ||
191 | fifosize = <32>; | ||
192 | clocks = <&clks 14>; | ||
193 | }; | ||
194 | |||
195 | uart2: uart@b0070000 { | ||
196 | cell-index = <2>; | ||
197 | compatible = "sirf,prima2-uart"; | ||
198 | reg = <0xb0070000 0x1000>; | ||
199 | interrupts = <19>; | ||
200 | fifosize = <128>; | ||
201 | clocks = <&clks 15>; | ||
202 | }; | ||
203 | |||
204 | usp0: usp@b0080000 { | ||
205 | cell-index = <0>; | ||
206 | compatible = "sirf,prima2-usp"; | ||
207 | reg = <0xb0080000 0x10000>; | ||
208 | interrupts = <20>; | ||
209 | clocks = <&clks 28>; | ||
210 | }; | ||
211 | |||
212 | usp1: usp@b0090000 { | ||
213 | cell-index = <1>; | ||
214 | compatible = "sirf,prima2-usp"; | ||
215 | reg = <0xb0090000 0x10000>; | ||
216 | interrupts = <21>; | ||
217 | clocks = <&clks 29>; | ||
218 | }; | ||
219 | |||
220 | dmac0: dma-controller@b00b0000 { | ||
221 | cell-index = <0>; | ||
222 | compatible = "sirf,prima2-dmac"; | ||
223 | reg = <0xb00b0000 0x10000>; | ||
224 | interrupts = <12>; | ||
225 | clocks = <&clks 24>; | ||
226 | }; | ||
227 | |||
228 | dmac1: dma-controller@b0160000 { | ||
229 | cell-index = <1>; | ||
230 | compatible = "sirf,prima2-dmac"; | ||
231 | reg = <0xb0160000 0x10000>; | ||
232 | interrupts = <13>; | ||
233 | clocks = <&clks 25>; | ||
234 | }; | ||
235 | |||
236 | vip@b00C0000 { | ||
237 | compatible = "sirf,prima2-vip"; | ||
238 | reg = <0xb00C0000 0x10000>; | ||
239 | clocks = <&clks 31>; | ||
240 | }; | ||
241 | |||
242 | spi0: spi@b00d0000 { | ||
243 | cell-index = <0>; | ||
244 | compatible = "sirf,prima2-spi"; | ||
245 | reg = <0xb00d0000 0x10000>; | ||
246 | interrupts = <15>; | ||
247 | sirf,spi-num-chipselects = <1>; | ||
248 | cs-gpios = <&gpio 0 0>; | ||
249 | sirf,spi-dma-rx-channel = <25>; | ||
250 | sirf,spi-dma-tx-channel = <20>; | ||
251 | #address-cells = <1>; | ||
252 | #size-cells = <0>; | ||
253 | clocks = <&clks 19>; | ||
254 | status = "disabled"; | ||
255 | }; | ||
256 | |||
257 | spi1: spi@b0170000 { | ||
258 | cell-index = <1>; | ||
259 | compatible = "sirf,prima2-spi"; | ||
260 | reg = <0xb0170000 0x10000>; | ||
261 | interrupts = <16>; | ||
262 | clocks = <&clks 20>; | ||
263 | status = "disabled"; | ||
264 | }; | ||
265 | |||
266 | i2c0: i2c@b00e0000 { | ||
267 | cell-index = <0>; | ||
268 | compatible = "sirf,prima2-i2c"; | ||
269 | reg = <0xb00e0000 0x10000>; | ||
270 | interrupts = <24>; | ||
271 | #address-cells = <1>; | ||
272 | #size-cells = <0>; | ||
273 | clocks = <&clks 17>; | ||
274 | }; | ||
275 | |||
276 | i2c1: i2c@b00f0000 { | ||
277 | cell-index = <1>; | ||
278 | compatible = "sirf,prima2-i2c"; | ||
279 | reg = <0xb00f0000 0x10000>; | ||
280 | interrupts = <25>; | ||
281 | #address-cells = <1>; | ||
282 | #size-cells = <0>; | ||
283 | clocks = <&clks 18>; | ||
284 | }; | ||
285 | |||
286 | tsc@b0110000 { | ||
287 | compatible = "sirf,prima2-tsc"; | ||
288 | reg = <0xb0110000 0x10000>; | ||
289 | interrupts = <33>; | ||
290 | clocks = <&clks 16>; | ||
291 | }; | ||
292 | |||
293 | gpio: pinctrl@b0120000 { | ||
294 | #gpio-cells = <2>; | ||
295 | #interrupt-cells = <2>; | ||
296 | compatible = "sirf,atlas6-pinctrl"; | ||
297 | reg = <0xb0120000 0x10000>; | ||
298 | interrupts = <43 44 45 46 47>; | ||
299 | gpio-controller; | ||
300 | interrupt-controller; | ||
301 | |||
302 | lcd_16pins_a: lcd0@0 { | ||
303 | lcd { | ||
304 | sirf,pins = "lcd_16bitsgrp"; | ||
305 | sirf,function = "lcd_16bits"; | ||
306 | }; | ||
307 | }; | ||
308 | lcd_18pins_a: lcd0@1 { | ||
309 | lcd { | ||
310 | sirf,pins = "lcd_18bitsgrp"; | ||
311 | sirf,function = "lcd_18bits"; | ||
312 | }; | ||
313 | }; | ||
314 | lcd_24pins_a: lcd0@2 { | ||
315 | lcd { | ||
316 | sirf,pins = "lcd_24bitsgrp"; | ||
317 | sirf,function = "lcd_24bits"; | ||
318 | }; | ||
319 | }; | ||
320 | lcdrom_pins_a: lcdrom0@0 { | ||
321 | lcd { | ||
322 | sirf,pins = "lcdromgrp"; | ||
323 | sirf,function = "lcdrom"; | ||
324 | }; | ||
325 | }; | ||
326 | uart0_pins_a: uart0@0 { | ||
327 | uart { | ||
328 | sirf,pins = "uart0grp"; | ||
329 | sirf,function = "uart0"; | ||
330 | }; | ||
331 | }; | ||
332 | uart1_pins_a: uart1@0 { | ||
333 | uart { | ||
334 | sirf,pins = "uart1grp"; | ||
335 | sirf,function = "uart1"; | ||
336 | }; | ||
337 | }; | ||
338 | uart2_pins_a: uart2@0 { | ||
339 | uart { | ||
340 | sirf,pins = "uart2grp"; | ||
341 | sirf,function = "uart2"; | ||
342 | }; | ||
343 | }; | ||
344 | uart2_noflow_pins_a: uart2@1 { | ||
345 | uart { | ||
346 | sirf,pins = "uart2_nostreamctrlgrp"; | ||
347 | sirf,function = "uart2_nostreamctrl"; | ||
348 | }; | ||
349 | }; | ||
350 | spi0_pins_a: spi0@0 { | ||
351 | spi { | ||
352 | sirf,pins = "spi0grp"; | ||
353 | sirf,function = "spi0"; | ||
354 | }; | ||
355 | }; | ||
356 | spi1_pins_a: spi1@0 { | ||
357 | spi { | ||
358 | sirf,pins = "spi1grp"; | ||
359 | sirf,function = "spi1"; | ||
360 | }; | ||
361 | }; | ||
362 | i2c0_pins_a: i2c0@0 { | ||
363 | i2c { | ||
364 | sirf,pins = "i2c0grp"; | ||
365 | sirf,function = "i2c0"; | ||
366 | }; | ||
367 | }; | ||
368 | i2c1_pins_a: i2c1@0 { | ||
369 | i2c { | ||
370 | sirf,pins = "i2c1grp"; | ||
371 | sirf,function = "i2c1"; | ||
372 | }; | ||
373 | }; | ||
374 | pwm0_pins_a: pwm0@0 { | ||
375 | pwm { | ||
376 | sirf,pins = "pwm0grp"; | ||
377 | sirf,function = "pwm0"; | ||
378 | }; | ||
379 | }; | ||
380 | pwm1_pins_a: pwm1@0 { | ||
381 | pwm { | ||
382 | sirf,pins = "pwm1grp"; | ||
383 | sirf,function = "pwm1"; | ||
384 | }; | ||
385 | }; | ||
386 | pwm2_pins_a: pwm2@0 { | ||
387 | pwm { | ||
388 | sirf,pins = "pwm2grp"; | ||
389 | sirf,function = "pwm2"; | ||
390 | }; | ||
391 | }; | ||
392 | pwm3_pins_a: pwm3@0 { | ||
393 | pwm { | ||
394 | sirf,pins = "pwm3grp"; | ||
395 | sirf,function = "pwm3"; | ||
396 | }; | ||
397 | }; | ||
398 | pwm4_pins_a: pwm4@0 { | ||
399 | pwm { | ||
400 | sirf,pins = "pwm4grp"; | ||
401 | sirf,function = "pwm4"; | ||
402 | }; | ||
403 | }; | ||
404 | gps_pins_a: gps@0 { | ||
405 | gps { | ||
406 | sirf,pins = "gpsgrp"; | ||
407 | sirf,function = "gps"; | ||
408 | }; | ||
409 | }; | ||
410 | vip_pins_a: vip@0 { | ||
411 | vip { | ||
412 | sirf,pins = "vipgrp"; | ||
413 | sirf,function = "vip"; | ||
414 | }; | ||
415 | }; | ||
416 | sdmmc0_pins_a: sdmmc0@0 { | ||
417 | sdmmc0 { | ||
418 | sirf,pins = "sdmmc0grp"; | ||
419 | sirf,function = "sdmmc0"; | ||
420 | }; | ||
421 | }; | ||
422 | sdmmc1_pins_a: sdmmc1@0 { | ||
423 | sdmmc1 { | ||
424 | sirf,pins = "sdmmc1grp"; | ||
425 | sirf,function = "sdmmc1"; | ||
426 | }; | ||
427 | }; | ||
428 | sdmmc2_pins_a: sdmmc2@0 { | ||
429 | sdmmc2 { | ||
430 | sirf,pins = "sdmmc2grp"; | ||
431 | sirf,function = "sdmmc2"; | ||
432 | }; | ||
433 | }; | ||
434 | sdmmc2_nowp_pins_a: sdmmc2_nowp@0 { | ||
435 | sdmmc2_nowp { | ||
436 | sirf,pins = "sdmmc2_nowpgrp"; | ||
437 | sirf,function = "sdmmc2_nowp"; | ||
438 | }; | ||
439 | }; | ||
440 | sdmmc3_pins_a: sdmmc3@0 { | ||
441 | sdmmc3 { | ||
442 | sirf,pins = "sdmmc3grp"; | ||
443 | sirf,function = "sdmmc3"; | ||
444 | }; | ||
445 | }; | ||
446 | sdmmc5_pins_a: sdmmc5@0 { | ||
447 | sdmmc5 { | ||
448 | sirf,pins = "sdmmc5grp"; | ||
449 | sirf,function = "sdmmc5"; | ||
450 | }; | ||
451 | }; | ||
452 | i2s_pins_a: i2s@0 { | ||
453 | i2s { | ||
454 | sirf,pins = "i2sgrp"; | ||
455 | sirf,function = "i2s"; | ||
456 | }; | ||
457 | }; | ||
458 | i2s_no_din_pins_a: i2s_no_din@0 { | ||
459 | i2s_no_din { | ||
460 | sirf,pins = "i2s_no_dingrp"; | ||
461 | sirf,function = "i2s_no_din"; | ||
462 | }; | ||
463 | }; | ||
464 | i2s_6chn_pins_a: i2s_6chn@0 { | ||
465 | i2s_6chn { | ||
466 | sirf,pins = "i2s_6chngrp"; | ||
467 | sirf,function = "i2s_6chn"; | ||
468 | }; | ||
469 | }; | ||
470 | ac97_pins_a: ac97@0 { | ||
471 | ac97 { | ||
472 | sirf,pins = "ac97grp"; | ||
473 | sirf,function = "ac97"; | ||
474 | }; | ||
475 | }; | ||
476 | nand_pins_a: nand@0 { | ||
477 | nand { | ||
478 | sirf,pins = "nandgrp"; | ||
479 | sirf,function = "nand"; | ||
480 | }; | ||
481 | }; | ||
482 | usp0_pins_a: usp0@0 { | ||
483 | usp0 { | ||
484 | sirf,pins = "usp0grp"; | ||
485 | sirf,function = "usp0"; | ||
486 | }; | ||
487 | }; | ||
488 | usp1_pins_a: usp1@0 { | ||
489 | usp1 { | ||
490 | sirf,pins = "usp1grp"; | ||
491 | sirf,function = "usp1"; | ||
492 | }; | ||
493 | }; | ||
494 | usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 { | ||
495 | usb0_upli_drvbus { | ||
496 | sirf,pins = "usb0_upli_drvbusgrp"; | ||
497 | sirf,function = "usb0_upli_drvbus"; | ||
498 | }; | ||
499 | }; | ||
500 | usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 { | ||
501 | usb1_utmi_drvbus { | ||
502 | sirf,pins = "usb1_utmi_drvbusgrp"; | ||
503 | sirf,function = "usb1_utmi_drvbus"; | ||
504 | }; | ||
505 | }; | ||
506 | warm_rst_pins_a: warm_rst@0 { | ||
507 | warm_rst { | ||
508 | sirf,pins = "warm_rstgrp"; | ||
509 | sirf,function = "warm_rst"; | ||
510 | }; | ||
511 | }; | ||
512 | pulse_count_pins_a: pulse_count@0 { | ||
513 | pulse_count { | ||
514 | sirf,pins = "pulse_countgrp"; | ||
515 | sirf,function = "pulse_count"; | ||
516 | }; | ||
517 | }; | ||
518 | cko0_rst_pins_a: cko0_rst@0 { | ||
519 | cko0_rst { | ||
520 | sirf,pins = "cko0_rstgrp"; | ||
521 | sirf,function = "cko0_rst"; | ||
522 | }; | ||
523 | }; | ||
524 | cko1_rst_pins_a: cko1_rst@0 { | ||
525 | cko1_rst { | ||
526 | sirf,pins = "cko1_rstgrp"; | ||
527 | sirf,function = "cko1_rst"; | ||
528 | }; | ||
529 | }; | ||
530 | }; | ||
531 | |||
532 | pwm@b0130000 { | ||
533 | compatible = "sirf,prima2-pwm"; | ||
534 | reg = <0xb0130000 0x10000>; | ||
535 | clocks = <&clks 21>; | ||
536 | }; | ||
537 | |||
538 | efusesys@b0140000 { | ||
539 | compatible = "sirf,prima2-efuse"; | ||
540 | reg = <0xb0140000 0x10000>; | ||
541 | clocks = <&clks 22>; | ||
542 | }; | ||
543 | |||
544 | pulsec@b0150000 { | ||
545 | compatible = "sirf,prima2-pulsec"; | ||
546 | reg = <0xb0150000 0x10000>; | ||
547 | interrupts = <48>; | ||
548 | clocks = <&clks 23>; | ||
549 | }; | ||
550 | |||
551 | pci-iobg { | ||
552 | compatible = "sirf,prima2-pciiobg", "simple-bus"; | ||
553 | #address-cells = <1>; | ||
554 | #size-cells = <1>; | ||
555 | ranges = <0x56000000 0x56000000 0x1b00000>; | ||
556 | |||
557 | sd0: sdhci@56000000 { | ||
558 | cell-index = <0>; | ||
559 | compatible = "sirf,prima2-sdhc"; | ||
560 | reg = <0x56000000 0x100000>; | ||
561 | interrupts = <38>; | ||
562 | bus-width = <8>; | ||
563 | clocks = <&clks 36>; | ||
564 | }; | ||
565 | |||
566 | sd1: sdhci@56100000 { | ||
567 | cell-index = <1>; | ||
568 | compatible = "sirf,prima2-sdhc"; | ||
569 | reg = <0x56100000 0x100000>; | ||
570 | interrupts = <38>; | ||
571 | status = "disabled"; | ||
572 | clocks = <&clks 36>; | ||
573 | }; | ||
574 | |||
575 | sd2: sdhci@56200000 { | ||
576 | cell-index = <2>; | ||
577 | compatible = "sirf,prima2-sdhc"; | ||
578 | reg = <0x56200000 0x100000>; | ||
579 | interrupts = <23>; | ||
580 | status = "disabled"; | ||
581 | clocks = <&clks 37>; | ||
582 | }; | ||
583 | |||
584 | sd3: sdhci@56300000 { | ||
585 | cell-index = <3>; | ||
586 | compatible = "sirf,prima2-sdhc"; | ||
587 | reg = <0x56300000 0x100000>; | ||
588 | interrupts = <23>; | ||
589 | status = "disabled"; | ||
590 | clocks = <&clks 37>; | ||
591 | }; | ||
592 | |||
593 | sd5: sdhci@56500000 { | ||
594 | cell-index = <5>; | ||
595 | compatible = "sirf,prima2-sdhc"; | ||
596 | reg = <0x56500000 0x100000>; | ||
597 | interrupts = <39>; | ||
598 | status = "disabled"; | ||
599 | clocks = <&clks 38>; | ||
600 | }; | ||
601 | |||
602 | pci-copy@57900000 { | ||
603 | compatible = "sirf,prima2-pcicp"; | ||
604 | reg = <0x57900000 0x100000>; | ||
605 | interrupts = <40>; | ||
606 | }; | ||
607 | |||
608 | rom-interface@57a00000 { | ||
609 | compatible = "sirf,prima2-romif"; | ||
610 | reg = <0x57a00000 0x100000>; | ||
611 | }; | ||
612 | }; | ||
613 | }; | ||
614 | |||
615 | rtc-iobg { | ||
616 | compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus"; | ||
617 | #address-cells = <1>; | ||
618 | #size-cells = <1>; | ||
619 | reg = <0x80030000 0x10000>; | ||
620 | |||
621 | gpsrtc@1000 { | ||
622 | compatible = "sirf,prima2-gpsrtc"; | ||
623 | reg = <0x1000 0x1000>; | ||
624 | interrupts = <55 56 57>; | ||
625 | }; | ||
626 | |||
627 | sysrtc@2000 { | ||
628 | compatible = "sirf,prima2-sysrtc"; | ||
629 | reg = <0x2000 0x1000>; | ||
630 | interrupts = <52 53 54>; | ||
631 | }; | ||
632 | |||
633 | pwrc@3000 { | ||
634 | compatible = "sirf,prima2-pwrc"; | ||
635 | reg = <0x3000 0x1000>; | ||
636 | interrupts = <32>; | ||
637 | }; | ||
638 | }; | ||
639 | |||
640 | uus-iobg { | ||
641 | compatible = "simple-bus"; | ||
642 | #address-cells = <1>; | ||
643 | #size-cells = <1>; | ||
644 | ranges = <0xb8000000 0xb8000000 0x40000>; | ||
645 | |||
646 | usb0: usb@b00e0000 { | ||
647 | compatible = "chipidea,ci13611a-prima2"; | ||
648 | reg = <0xb8000000 0x10000>; | ||
649 | interrupts = <10>; | ||
650 | clocks = <&clks 40>; | ||
651 | }; | ||
652 | |||
653 | usb1: usb@b00f0000 { | ||
654 | compatible = "chipidea,ci13611a-prima2"; | ||
655 | reg = <0xb8010000 0x10000>; | ||
656 | interrupts = <11>; | ||
657 | clocks = <&clks 41>; | ||
658 | }; | ||
659 | |||
660 | security@b00f0000 { | ||
661 | compatible = "sirf,prima2-security"; | ||
662 | reg = <0xb8030000 0x10000>; | ||
663 | interrupts = <42>; | ||
664 | clocks = <&clks 7>; | ||
665 | }; | ||
666 | }; | ||
667 | }; | ||
668 | }; | ||
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 3bf0c543216a..e3f2f6a5709b 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig | |||
@@ -3,6 +3,7 @@ CONFIG_NO_HZ=y | |||
3 | CONFIG_HIGH_RES_TIMERS=y | 3 | CONFIG_HIGH_RES_TIMERS=y |
4 | CONFIG_ARCH_MVEBU=y | 4 | CONFIG_ARCH_MVEBU=y |
5 | CONFIG_MACH_ARMADA_370=y | 5 | CONFIG_MACH_ARMADA_370=y |
6 | CONFIG_ARCH_SIRF=y | ||
6 | CONFIG_MACH_ARMADA_XP=y | 7 | CONFIG_MACH_ARMADA_XP=y |
7 | CONFIG_ARCH_HIGHBANK=y | 8 | CONFIG_ARCH_HIGHBANK=y |
8 | CONFIG_ARCH_SOCFPGA=y | 9 | CONFIG_ARCH_SOCFPGA=y |
@@ -40,12 +41,16 @@ CONFIG_KEYBOARD_SPEAR=y | |||
40 | CONFIG_SERIAL_AMBA_PL011=y | 41 | CONFIG_SERIAL_AMBA_PL011=y |
41 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y | 42 | CONFIG_SERIAL_AMBA_PL011_CONSOLE=y |
42 | CONFIG_SERIAL_OF_PLATFORM=y | 43 | CONFIG_SERIAL_OF_PLATFORM=y |
44 | CONFIG_SERIAL_SIRFSOC=y | ||
45 | CONFIG_SERIAL_SIRFSOC_CONSOLE=y | ||
43 | CONFIG_IPMI_HANDLER=y | 46 | CONFIG_IPMI_HANDLER=y |
44 | CONFIG_IPMI_SI=y | 47 | CONFIG_IPMI_SI=y |
45 | CONFIG_I2C=y | 48 | CONFIG_I2C=y |
46 | CONFIG_I2C_DESIGNWARE_PLATFORM=y | 49 | CONFIG_I2C_DESIGNWARE_PLATFORM=y |
50 | CONFIG_I2C_SIRF=y | ||
47 | CONFIG_SPI=y | 51 | CONFIG_SPI=y |
48 | CONFIG_SPI_PL022=y | 52 | CONFIG_SPI_PL022=y |
53 | CONFIG_SPI_SIRF=y | ||
49 | CONFIG_GPIO_PL061=y | 54 | CONFIG_GPIO_PL061=y |
50 | CONFIG_FB=y | 55 | CONFIG_FB=y |
51 | CONFIG_FB_ARMCLCD=y | 56 | CONFIG_FB_ARMCLCD=y |
@@ -66,4 +71,5 @@ CONFIG_RTC_CLASS=y | |||
66 | CONFIG_RTC_DRV_PL031=y | 71 | CONFIG_RTC_DRV_PL031=y |
67 | CONFIG_DMADEVICES=y | 72 | CONFIG_DMADEVICES=y |
68 | CONFIG_PL330_DMA=y | 73 | CONFIG_PL330_DMA=y |
74 | CONFIG_SIRF_DMA=y | ||
69 | CONFIG_DW_DMAC=y | 75 | CONFIG_DW_DMAC=y |
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h index 0f01f4677bd2..7b2899c2f7fc 100644 --- a/arch/arm/include/asm/smp_twd.h +++ b/arch/arm/include/asm/smp_twd.h | |||
@@ -34,12 +34,4 @@ struct twd_local_timer name __initdata = { \ | |||
34 | 34 | ||
35 | int twd_local_timer_register(struct twd_local_timer *); | 35 | int twd_local_timer_register(struct twd_local_timer *); |
36 | 36 | ||
37 | #ifdef CONFIG_HAVE_ARM_TWD | ||
38 | void twd_local_timer_of_register(void); | ||
39 | #else | ||
40 | static inline void twd_local_timer_of_register(void) | ||
41 | { | ||
42 | } | ||
43 | #endif | ||
44 | |||
45 | #endif | 37 | #endif |
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/include/debug/sirf.S index c10510d01a44..dbf250cf18e6 100644 --- a/arch/arm/mach-prima2/include/mach/uart.h +++ b/arch/arm/include/debug/sirf.S | |||
@@ -1,15 +1,11 @@ | |||
1 | /* | 1 | /* |
2 | * arch/arm/mach-prima2/include/mach/uart.h | 2 | * arch/arm/mach-prima2/include/mach/debug-macro.S |
3 | * | 3 | * |
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | 4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. |
5 | * | 5 | * |
6 | * Licensed under GPLv2 or later. | 6 | * Licensed under GPLv2 or later. |
7 | */ | 7 | */ |
8 | 8 | ||
9 | #ifndef __MACH_PRIMA2_SIRFSOC_UART_H | ||
10 | #define __MACH_PRIMA2_SIRFSOC_UART_H | ||
11 | |||
12 | /* UART-1: used as serial debug port */ | ||
13 | #if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) | 9 | #if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) |
14 | #define SIRFSOC_UART1_PA_BASE 0xb0060000 | 10 | #define SIRFSOC_UART1_PA_BASE 0xb0060000 |
15 | #elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) | 11 | #elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) |
@@ -17,8 +13,8 @@ | |||
17 | #else | 13 | #else |
18 | #define SIRFSOC_UART1_PA_BASE 0 | 14 | #define SIRFSOC_UART1_PA_BASE 0 |
19 | #endif | 15 | #endif |
20 | #define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000) | 16 | |
21 | #define SIRFSOC_UART1_SIZE SZ_4K | 17 | #define SIRFSOC_UART1_VA_BASE 0xFEC60000 |
22 | 18 | ||
23 | #define SIRFSOC_UART_TXFIFO_STATUS 0x0114 | 19 | #define SIRFSOC_UART_TXFIFO_STATUS 0x0114 |
24 | #define SIRFSOC_UART_TXFIFO_DATA 0x0118 | 20 | #define SIRFSOC_UART_TXFIFO_DATA 0x0118 |
@@ -26,4 +22,21 @@ | |||
26 | #define SIRFSOC_UART1_TXFIFO_FULL (1 << 5) | 22 | #define SIRFSOC_UART1_TXFIFO_FULL (1 << 5) |
27 | #define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6) | 23 | #define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6) |
28 | 24 | ||
29 | #endif | 25 | .macro addruart, rp, rv, tmp |
26 | ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical | ||
27 | ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual | ||
28 | .endm | ||
29 | |||
30 | .macro senduart,rd,rx | ||
31 | str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA] | ||
32 | .endm | ||
33 | |||
34 | .macro busyuart,rd,rx | ||
35 | .endm | ||
36 | |||
37 | .macro waituart,rd,rx | ||
38 | 1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS] | ||
39 | tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY | ||
40 | beq 1001b | ||
41 | .endm | ||
42 | |||
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c index 3f2565037480..90525d9d290b 100644 --- a/arch/arm/kernel/smp_twd.c +++ b/arch/arm/kernel/smp_twd.c | |||
@@ -362,25 +362,13 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt) | |||
362 | } | 362 | } |
363 | 363 | ||
364 | #ifdef CONFIG_OF | 364 | #ifdef CONFIG_OF |
365 | const static struct of_device_id twd_of_match[] __initconst = { | 365 | static void __init twd_local_timer_of_register(struct device_node *np) |
366 | { .compatible = "arm,cortex-a9-twd-timer", }, | ||
367 | { .compatible = "arm,cortex-a5-twd-timer", }, | ||
368 | { .compatible = "arm,arm11mp-twd-timer", }, | ||
369 | { }, | ||
370 | }; | ||
371 | |||
372 | void __init twd_local_timer_of_register(void) | ||
373 | { | 366 | { |
374 | struct device_node *np; | ||
375 | int err; | 367 | int err; |
376 | 368 | ||
377 | if (!is_smp() || !setup_max_cpus) | 369 | if (!is_smp() || !setup_max_cpus) |
378 | return; | 370 | return; |
379 | 371 | ||
380 | np = of_find_matching_node(NULL, twd_of_match); | ||
381 | if (!np) | ||
382 | return; | ||
383 | |||
384 | twd_ppi = irq_of_parse_and_map(np, 0); | 372 | twd_ppi = irq_of_parse_and_map(np, 0); |
385 | if (!twd_ppi) { | 373 | if (!twd_ppi) { |
386 | err = -EINVAL; | 374 | err = -EINVAL; |
@@ -398,4 +386,7 @@ void __init twd_local_timer_of_register(void) | |||
398 | out: | 386 | out: |
399 | WARN(err, "twd_local_timer_of_register failed (%d)\n", err); | 387 | WARN(err, "twd_local_timer_of_register failed (%d)\n", err); |
400 | } | 388 | } |
389 | CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register); | ||
390 | CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register); | ||
391 | CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register); | ||
401 | #endif | 392 | #endif |
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c index a4f9f50247d4..76c1170b3528 100644 --- a/arch/arm/mach-highbank/highbank.c +++ b/arch/arm/mach-highbank/highbank.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #include <asm/cacheflush.h> | 32 | #include <asm/cacheflush.h> |
33 | #include <asm/cputype.h> | 33 | #include <asm/cputype.h> |
34 | #include <asm/smp_plat.h> | 34 | #include <asm/smp_plat.h> |
35 | #include <asm/smp_twd.h> | ||
36 | #include <asm/hardware/arm_timer.h> | 35 | #include <asm/hardware/arm_timer.h> |
37 | #include <asm/hardware/timer-sp.h> | 36 | #include <asm/hardware/timer-sp.h> |
38 | #include <asm/hardware/cache-l2x0.h> | 37 | #include <asm/hardware/cache-l2x0.h> |
@@ -119,10 +118,10 @@ static void __init highbank_timer_init(void) | |||
119 | sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); | 118 | sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); |
120 | sp804_clockevents_init(timer_base, irq, "timer0"); | 119 | sp804_clockevents_init(timer_base, irq, "timer0"); |
121 | 120 | ||
122 | twd_local_timer_of_register(); | ||
123 | |||
124 | arch_timer_of_register(); | 121 | arch_timer_of_register(); |
125 | arch_timer_sched_clock_init(); | 122 | arch_timer_sched_clock_init(); |
123 | |||
124 | clocksource_of_init(); | ||
126 | } | 125 | } |
127 | 126 | ||
128 | static void highbank_power_off(void) | 127 | static void highbank_power_off(void) |
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 9ffd103b27e4..b59ddcb57c78 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c | |||
@@ -12,6 +12,7 @@ | |||
12 | 12 | ||
13 | #include <linux/clk.h> | 13 | #include <linux/clk.h> |
14 | #include <linux/clkdev.h> | 14 | #include <linux/clkdev.h> |
15 | #include <linux/clocksource.h> | ||
15 | #include <linux/cpu.h> | 16 | #include <linux/cpu.h> |
16 | #include <linux/delay.h> | 17 | #include <linux/delay.h> |
17 | #include <linux/export.h> | 18 | #include <linux/export.h> |
@@ -28,11 +29,9 @@ | |||
28 | #include <linux/regmap.h> | 29 | #include <linux/regmap.h> |
29 | #include <linux/micrel_phy.h> | 30 | #include <linux/micrel_phy.h> |
30 | #include <linux/mfd/syscon.h> | 31 | #include <linux/mfd/syscon.h> |
31 | #include <asm/smp_twd.h> | ||
32 | #include <asm/hardware/cache-l2x0.h> | 32 | #include <asm/hardware/cache-l2x0.h> |
33 | #include <asm/mach/arch.h> | 33 | #include <asm/mach/arch.h> |
34 | #include <asm/mach/map.h> | 34 | #include <asm/mach/map.h> |
35 | #include <asm/mach/time.h> | ||
36 | #include <asm/system_misc.h> | 35 | #include <asm/system_misc.h> |
37 | 36 | ||
38 | #include "common.h" | 37 | #include "common.h" |
@@ -292,7 +291,7 @@ static void __init imx6q_init_irq(void) | |||
292 | static void __init imx6q_timer_init(void) | 291 | static void __init imx6q_timer_init(void) |
293 | { | 292 | { |
294 | mx6q_clocks_init(); | 293 | mx6q_clocks_init(); |
295 | twd_local_timer_of_register(); | 294 | clocksource_of_init(); |
296 | imx_print_silicon_rev("i.MX6Q", imx6q_revision()); | 295 | imx_print_silicon_rev("i.MX6Q", imx6q_revision()); |
297 | } | 296 | } |
298 | 297 | ||
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c index 2bdd4cf17a8f..4fd80257c73e 100644 --- a/arch/arm/mach-omap2/timer.c +++ b/arch/arm/mach-omap2/timer.c | |||
@@ -597,7 +597,7 @@ void __init omap4_local_timer_init(void) | |||
597 | int err; | 597 | int err; |
598 | 598 | ||
599 | if (of_have_populated_dt()) { | 599 | if (of_have_populated_dt()) { |
600 | twd_local_timer_of_register(); | 600 | clocksource_of_init(); |
601 | return; | 601 | return; |
602 | } | 602 | } |
603 | 603 | ||
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index 4f7379fe01e2..587c0bd70434 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig | |||
@@ -1,6 +1,26 @@ | |||
1 | config ARCH_SIRF | ||
2 | bool "CSR SiRF" if ARCH_MULTI_V7 | ||
3 | select ARCH_REQUIRE_GPIOLIB | ||
4 | select GENERIC_CLOCKEVENTS | ||
5 | select GENERIC_IRQ_CHIP | ||
6 | select MIGHT_HAVE_CACHE_L2X0 | ||
7 | select NO_IOPORT | ||
8 | select PINCTRL | ||
9 | select PINCTRL_SIRF | ||
10 | help | ||
11 | Support for CSR SiRFprimaII/Marco/Polo platforms | ||
12 | |||
1 | if ARCH_SIRF | 13 | if ARCH_SIRF |
2 | 14 | ||
3 | menu "CSR SiRF primaII/Marco/Polo Specific Features" | 15 | menu "CSR SiRF atlas6/primaII/Marco/Polo Specific Features" |
16 | |||
17 | config ARCH_ATLAS6 | ||
18 | bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform" | ||
19 | default y | ||
20 | select CPU_V7 | ||
21 | select SIRF_IRQ | ||
22 | help | ||
23 | Support for CSR SiRFSoC ARM Cortex A9 Platform | ||
4 | 24 | ||
5 | config ARCH_PRIMA2 | 25 | config ARCH_PRIMA2 |
6 | bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" | 26 | bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform" |
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile index bfe360cbd177..7a6b4a323125 100644 --- a/arch/arm/mach-prima2/Makefile +++ b/arch/arm/mach-prima2/Makefile | |||
@@ -4,8 +4,7 @@ obj-y += rtciobrg.o | |||
4 | obj-$(CONFIG_DEBUG_LL) += lluart.o | 4 | obj-$(CONFIG_DEBUG_LL) += lluart.o |
5 | obj-$(CONFIG_CACHE_L2X0) += l2x0.o | 5 | obj-$(CONFIG_CACHE_L2X0) += l2x0.o |
6 | obj-$(CONFIG_SUSPEND) += pm.o sleep.o | 6 | obj-$(CONFIG_SUSPEND) += pm.o sleep.o |
7 | obj-$(CONFIG_SIRF_IRQ) += irq.o | ||
8 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 7 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
9 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 8 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
10 | obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o | 9 | |
11 | obj-$(CONFIG_ARCH_MARCO) += timer-marco.o | 10 | CFLAGS_hotplug.o += -march=armv7-a |
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c index 2d57aa479a7b..4f94cd87972a 100644 --- a/arch/arm/mach-prima2/common.c +++ b/arch/arm/mach-prima2/common.c | |||
@@ -6,6 +6,7 @@ | |||
6 | * Licensed under GPLv2 or later. | 6 | * Licensed under GPLv2 or later. |
7 | */ | 7 | */ |
8 | 8 | ||
9 | #include <linux/clocksource.h> | ||
9 | #include <linux/init.h> | 10 | #include <linux/init.h> |
10 | #include <linux/kernel.h> | 11 | #include <linux/kernel.h> |
11 | #include <linux/irqchip.h> | 12 | #include <linux/irqchip.h> |
@@ -31,12 +32,38 @@ void __init sirfsoc_init_late(void) | |||
31 | sirfsoc_pm_init(); | 32 | sirfsoc_pm_init(); |
32 | } | 33 | } |
33 | 34 | ||
35 | static __init void sirfsoc_init_time(void) | ||
36 | { | ||
37 | /* initialize clocking early, we want to set the OS timer */ | ||
38 | sirfsoc_of_clk_init(); | ||
39 | clocksource_of_init(); | ||
40 | } | ||
41 | |||
34 | static __init void sirfsoc_map_io(void) | 42 | static __init void sirfsoc_map_io(void) |
35 | { | 43 | { |
36 | sirfsoc_map_lluart(); | 44 | sirfsoc_map_lluart(); |
37 | sirfsoc_map_scu(); | 45 | sirfsoc_map_scu(); |
38 | } | 46 | } |
39 | 47 | ||
48 | #ifdef CONFIG_ARCH_ATLAS6 | ||
49 | static const char *atlas6_dt_match[] __initdata = { | ||
50 | "sirf,atlas6", | ||
51 | NULL | ||
52 | }; | ||
53 | |||
54 | DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)") | ||
55 | /* Maintainer: Barry Song <baohua.song@csr.com> */ | ||
56 | .nr_irqs = 128, | ||
57 | .map_io = sirfsoc_map_io, | ||
58 | .init_irq = irqchip_init, | ||
59 | .init_time = sirfsoc_init_time, | ||
60 | .init_machine = sirfsoc_mach_init, | ||
61 | .init_late = sirfsoc_init_late, | ||
62 | .dt_compat = atlas6_dt_match, | ||
63 | .restart = sirfsoc_restart, | ||
64 | MACHINE_END | ||
65 | #endif | ||
66 | |||
40 | #ifdef CONFIG_ARCH_PRIMA2 | 67 | #ifdef CONFIG_ARCH_PRIMA2 |
41 | static const char *prima2_dt_match[] __initdata = { | 68 | static const char *prima2_dt_match[] __initdata = { |
42 | "sirf,prima2", | 69 | "sirf,prima2", |
@@ -45,12 +72,10 @@ static const char *prima2_dt_match[] __initdata = { | |||
45 | 72 | ||
46 | DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") | 73 | DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") |
47 | /* Maintainer: Barry Song <baohua.song@csr.com> */ | 74 | /* Maintainer: Barry Song <baohua.song@csr.com> */ |
75 | .nr_irqs = 128, | ||
48 | .map_io = sirfsoc_map_io, | 76 | .map_io = sirfsoc_map_io, |
49 | .init_irq = sirfsoc_of_irq_init, | 77 | .init_irq = irqchip_init, |
50 | .init_time = sirfsoc_prima2_timer_init, | 78 | .init_time = sirfsoc_init_time, |
51 | #ifdef CONFIG_MULTI_IRQ_HANDLER | ||
52 | .handle_irq = sirfsoc_handle_irq, | ||
53 | #endif | ||
54 | .dma_zone_size = SZ_256M, | 79 | .dma_zone_size = SZ_256M, |
55 | .init_machine = sirfsoc_mach_init, | 80 | .init_machine = sirfsoc_mach_init, |
56 | .init_late = sirfsoc_init_late, | 81 | .init_late = sirfsoc_init_late, |
@@ -70,7 +95,7 @@ DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)") | |||
70 | .smp = smp_ops(sirfsoc_smp_ops), | 95 | .smp = smp_ops(sirfsoc_smp_ops), |
71 | .map_io = sirfsoc_map_io, | 96 | .map_io = sirfsoc_map_io, |
72 | .init_irq = irqchip_init, | 97 | .init_irq = irqchip_init, |
73 | .init_time = sirfsoc_marco_timer_init, | 98 | .init_time = sirfsoc_init_time, |
74 | .init_machine = sirfsoc_mach_init, | 99 | .init_machine = sirfsoc_mach_init, |
75 | .init_late = sirfsoc_init_late, | 100 | .init_late = sirfsoc_init_late, |
76 | .dt_compat = marco_dt_match, | 101 | .dt_compat = marco_dt_match, |
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h index b7c26b62e4a7..81135cd88e54 100644 --- a/arch/arm/mach-prima2/common.h +++ b/arch/arm/mach-prima2/common.h | |||
@@ -13,8 +13,8 @@ | |||
13 | #include <asm/mach/time.h> | 13 | #include <asm/mach/time.h> |
14 | #include <asm/exception.h> | 14 | #include <asm/exception.h> |
15 | 15 | ||
16 | extern void sirfsoc_prima2_timer_init(void); | 16 | #define SIRFSOC_VA_BASE _AC(0xFEC00000, UL) |
17 | extern void sirfsoc_marco_timer_init(void); | 17 | #define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000)) |
18 | 18 | ||
19 | extern struct smp_operations sirfsoc_smp_ops; | 19 | extern struct smp_operations sirfsoc_smp_ops; |
20 | extern void sirfsoc_secondary_startup(void); | 20 | extern void sirfsoc_secondary_startup(void); |
diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-prima2/include/mach/clkdev.h deleted file mode 100644 index 66932518b1b7..000000000000 --- a/arch/arm/mach-prima2/include/mach/clkdev.h +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-prima2/include/mach/clkdev.h | ||
3 | * | ||
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | #ifndef __MACH_CLKDEV_H | ||
10 | #define __MACH_CLKDEV_H | ||
11 | |||
12 | #define __clk_get(clk) ({ 1; }) | ||
13 | #define __clk_put(clk) do { } while (0) | ||
14 | |||
15 | #endif | ||
diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-prima2/include/mach/debug-macro.S deleted file mode 100644 index cd97492bb075..000000000000 --- a/arch/arm/mach-prima2/include/mach/debug-macro.S +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-prima2/include/mach/debug-macro.S | ||
3 | * | ||
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | #include <mach/hardware.h> | ||
10 | #include <mach/uart.h> | ||
11 | |||
12 | .macro addruart, rp, rv, tmp | ||
13 | ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical | ||
14 | ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual | ||
15 | .endm | ||
16 | |||
17 | .macro senduart,rd,rx | ||
18 | str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA] | ||
19 | .endm | ||
20 | |||
21 | .macro busyuart,rd,rx | ||
22 | .endm | ||
23 | |||
24 | .macro waituart,rd,rx | ||
25 | 1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS] | ||
26 | tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY | ||
27 | beq 1001b | ||
28 | .endm | ||
29 | |||
diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S deleted file mode 100644 index 86434e7a5be9..000000000000 --- a/arch/arm/mach-prima2/include/mach/entry-macro.S +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-prima2/include/mach/entry-macro.S | ||
3 | * | ||
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | #include <mach/hardware.h> | ||
10 | |||
11 | #define SIRFSOC_INT_ID 0x38 | ||
12 | |||
13 | .macro get_irqnr_preamble, base, tmp | ||
14 | ldr \base, =sirfsoc_intc_base | ||
15 | ldr \base, [\base] | ||
16 | .endm | ||
17 | |||
18 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
19 | ldr \irqnr, [\base, #SIRFSOC_INT_ID] @ Get the highest priority irq | ||
20 | cmp \irqnr, #0x40 @ the irq num can't be larger than 0x3f | ||
21 | movges \irqnr, #0 | ||
22 | .endm | ||
diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-prima2/include/mach/hardware.h deleted file mode 100644 index 105b96964f25..000000000000 --- a/arch/arm/mach-prima2/include/mach/hardware.h +++ /dev/null | |||
@@ -1,15 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-prima2/include/mach/hardware.h | ||
3 | * | ||
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | #ifndef __MACH_HARDWARE_H__ | ||
10 | #define __MACH_HARDWARE_H__ | ||
11 | |||
12 | #include <asm/sizes.h> | ||
13 | #include <mach/map.h> | ||
14 | |||
15 | #endif | ||
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h deleted file mode 100644 index b778a0f248ed..000000000000 --- a/arch/arm/mach-prima2/include/mach/irqs.h +++ /dev/null | |||
@@ -1,17 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-prima2/include/mach/irqs.h | ||
3 | * | ||
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARCH_IRQS_H | ||
10 | #define __ASM_ARCH_IRQS_H | ||
11 | |||
12 | #define SIRFSOC_INTENAL_IRQ_START 0 | ||
13 | #define SIRFSOC_INTENAL_IRQ_END 127 | ||
14 | #define SIRFSOC_GPIO_IRQ_START (SIRFSOC_INTENAL_IRQ_END + 1) | ||
15 | #define NR_IRQS 288 | ||
16 | |||
17 | #endif | ||
diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h deleted file mode 100644 index 6f243532570c..000000000000 --- a/arch/arm/mach-prima2/include/mach/map.h +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | /* | ||
2 | * memory & I/O static mapping definitions for CSR SiRFprimaII | ||
3 | * | ||
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | #ifndef __MACH_PRIMA2_MAP_H__ | ||
10 | #define __MACH_PRIMA2_MAP_H__ | ||
11 | |||
12 | #include <linux/const.h> | ||
13 | |||
14 | #define SIRFSOC_VA_BASE _AC(0xFEC00000, UL) | ||
15 | |||
16 | #define SIRFSOC_VA(x) (SIRFSOC_VA_BASE + ((x) & 0x00FFF000)) | ||
17 | |||
18 | #endif | ||
diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-prima2/include/mach/timex.h deleted file mode 100644 index d6f98a75e562..000000000000 --- a/arch/arm/mach-prima2/include/mach/timex.h +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-prima2/include/mach/timex.h | ||
3 | * | ||
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | #ifndef __MACH_TIMEX_H__ | ||
10 | #define __MACH_TIMEX_H__ | ||
11 | |||
12 | #define CLOCK_TICK_RATE 1000000 | ||
13 | |||
14 | #endif | ||
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h deleted file mode 100644 index d1513a33709a..000000000000 --- a/arch/arm/mach-prima2/include/mach/uncompress.h +++ /dev/null | |||
@@ -1,41 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-prima2/include/mach/uncompress.h | ||
3 | * | ||
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARCH_UNCOMPRESS_H | ||
10 | #define __ASM_ARCH_UNCOMPRESS_H | ||
11 | |||
12 | #include <linux/io.h> | ||
13 | #include <mach/hardware.h> | ||
14 | #include <mach/uart.h> | ||
15 | |||
16 | void arch_decomp_setup(void) | ||
17 | { | ||
18 | } | ||
19 | |||
20 | static __inline__ void putc(char c) | ||
21 | { | ||
22 | /* | ||
23 | * during kernel decompression, all mappings are flat: | ||
24 | * virt_addr == phys_addr | ||
25 | */ | ||
26 | if (!SIRFSOC_UART1_PA_BASE) | ||
27 | return; | ||
28 | |||
29 | while (__raw_readl((void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS) | ||
30 | & SIRFSOC_UART1_TXFIFO_FULL) | ||
31 | barrier(); | ||
32 | |||
33 | __raw_writel(c, (void __iomem *)SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA); | ||
34 | } | ||
35 | |||
36 | static inline void flush(void) | ||
37 | { | ||
38 | } | ||
39 | |||
40 | #endif | ||
41 | |||
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c deleted file mode 100644 index 6c0f3e9c43fb..000000000000 --- a/arch/arm/mach-prima2/irq.c +++ /dev/null | |||
@@ -1,129 +0,0 @@ | |||
1 | /* | ||
2 | * interrupt controller support for CSR SiRFprimaII | ||
3 | * | ||
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | #include <linux/init.h> | ||
10 | #include <linux/io.h> | ||
11 | #include <linux/irq.h> | ||
12 | #include <linux/of.h> | ||
13 | #include <linux/of_address.h> | ||
14 | #include <linux/irqdomain.h> | ||
15 | #include <linux/syscore_ops.h> | ||
16 | #include <asm/mach/irq.h> | ||
17 | #include <asm/exception.h> | ||
18 | #include <mach/hardware.h> | ||
19 | |||
20 | #define SIRFSOC_INT_RISC_MASK0 0x0018 | ||
21 | #define SIRFSOC_INT_RISC_MASK1 0x001C | ||
22 | #define SIRFSOC_INT_RISC_LEVEL0 0x0020 | ||
23 | #define SIRFSOC_INT_RISC_LEVEL1 0x0024 | ||
24 | #define SIRFSOC_INIT_IRQ_ID 0x0038 | ||
25 | |||
26 | void __iomem *sirfsoc_intc_base; | ||
27 | |||
28 | static __init void | ||
29 | sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) | ||
30 | { | ||
31 | struct irq_chip_generic *gc; | ||
32 | struct irq_chip_type *ct; | ||
33 | |||
34 | gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq); | ||
35 | ct = gc->chip_types; | ||
36 | |||
37 | ct->chip.irq_mask = irq_gc_mask_clr_bit; | ||
38 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | ||
39 | ct->regs.mask = SIRFSOC_INT_RISC_MASK0; | ||
40 | |||
41 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0); | ||
42 | } | ||
43 | |||
44 | static __init void sirfsoc_irq_init(void) | ||
45 | { | ||
46 | sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32); | ||
47 | sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, | ||
48 | SIRFSOC_INTENAL_IRQ_END + 1 - 32); | ||
49 | |||
50 | writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); | ||
51 | writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); | ||
52 | |||
53 | writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); | ||
54 | writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); | ||
55 | } | ||
56 | |||
57 | asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) | ||
58 | { | ||
59 | u32 irqstat, irqnr; | ||
60 | |||
61 | irqstat = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INIT_IRQ_ID); | ||
62 | irqnr = irqstat & 0xff; | ||
63 | |||
64 | handle_IRQ(irqnr, regs); | ||
65 | } | ||
66 | |||
67 | static struct of_device_id intc_ids[] = { | ||
68 | { .compatible = "sirf,prima2-intc" }, | ||
69 | {}, | ||
70 | }; | ||
71 | |||
72 | void __init sirfsoc_of_irq_init(void) | ||
73 | { | ||
74 | struct device_node *np; | ||
75 | |||
76 | np = of_find_matching_node(NULL, intc_ids); | ||
77 | if (!np) | ||
78 | return; | ||
79 | |||
80 | sirfsoc_intc_base = of_iomap(np, 0); | ||
81 | if (!sirfsoc_intc_base) | ||
82 | panic("unable to map intc cpu registers\n"); | ||
83 | |||
84 | irq_domain_add_legacy(np, SIRFSOC_INTENAL_IRQ_END + 1, 0, 0, | ||
85 | &irq_domain_simple_ops, NULL); | ||
86 | |||
87 | of_node_put(np); | ||
88 | |||
89 | sirfsoc_irq_init(); | ||
90 | } | ||
91 | |||
92 | struct sirfsoc_irq_status { | ||
93 | u32 mask0; | ||
94 | u32 mask1; | ||
95 | u32 level0; | ||
96 | u32 level1; | ||
97 | }; | ||
98 | |||
99 | static struct sirfsoc_irq_status sirfsoc_irq_st; | ||
100 | |||
101 | static int sirfsoc_irq_suspend(void) | ||
102 | { | ||
103 | sirfsoc_irq_st.mask0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); | ||
104 | sirfsoc_irq_st.mask1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); | ||
105 | sirfsoc_irq_st.level0 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); | ||
106 | sirfsoc_irq_st.level1 = readl_relaxed(sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); | ||
107 | |||
108 | return 0; | ||
109 | } | ||
110 | |||
111 | static void sirfsoc_irq_resume(void) | ||
112 | { | ||
113 | writel_relaxed(sirfsoc_irq_st.mask0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0); | ||
114 | writel_relaxed(sirfsoc_irq_st.mask1, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1); | ||
115 | writel_relaxed(sirfsoc_irq_st.level0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0); | ||
116 | writel_relaxed(sirfsoc_irq_st.level1, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1); | ||
117 | } | ||
118 | |||
119 | static struct syscore_ops sirfsoc_irq_syscore_ops = { | ||
120 | .suspend = sirfsoc_irq_suspend, | ||
121 | .resume = sirfsoc_irq_resume, | ||
122 | }; | ||
123 | |||
124 | static int __init sirfsoc_irq_pm_init(void) | ||
125 | { | ||
126 | register_syscore_ops(&sirfsoc_irq_syscore_ops); | ||
127 | return 0; | ||
128 | } | ||
129 | device_initcall(sirfsoc_irq_pm_init); | ||
diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c index a89f9b3c8cc5..99c0c927ca4a 100644 --- a/arch/arm/mach-prima2/lluart.c +++ b/arch/arm/mach-prima2/lluart.c | |||
@@ -9,8 +9,18 @@ | |||
9 | #include <linux/kernel.h> | 9 | #include <linux/kernel.h> |
10 | #include <asm/page.h> | 10 | #include <asm/page.h> |
11 | #include <asm/mach/map.h> | 11 | #include <asm/mach/map.h> |
12 | #include <mach/map.h> | 12 | #include "common.h" |
13 | #include <mach/uart.h> | 13 | |
14 | #if defined(CONFIG_DEBUG_SIRFPRIMA2_UART1) | ||
15 | #define SIRFSOC_UART1_PA_BASE 0xb0060000 | ||
16 | #elif defined(CONFIG_DEBUG_SIRFMARCO_UART1) | ||
17 | #define SIRFSOC_UART1_PA_BASE 0xcc060000 | ||
18 | #else | ||
19 | #define SIRFSOC_UART1_PA_BASE 0 | ||
20 | #endif | ||
21 | |||
22 | #define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000) | ||
23 | #define SIRFSOC_UART1_SIZE SZ_4K | ||
14 | 24 | ||
15 | void __init sirfsoc_map_lluart(void) | 25 | void __init sirfsoc_map_lluart(void) |
16 | { | 26 | { |
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c index 4b788310f6a6..d52e322e616c 100644 --- a/arch/arm/mach-prima2/platsmp.c +++ b/arch/arm/mach-prima2/platsmp.c | |||
@@ -18,7 +18,6 @@ | |||
18 | #include <asm/smp_scu.h> | 18 | #include <asm/smp_scu.h> |
19 | #include <asm/cacheflush.h> | 19 | #include <asm/cacheflush.h> |
20 | #include <asm/cputype.h> | 20 | #include <asm/cputype.h> |
21 | #include <mach/map.h> | ||
22 | 21 | ||
23 | #include "common.h" | 22 | #include "common.h" |
24 | 23 | ||
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c index 1b97e8623472..6dd208997176 100644 --- a/arch/arm/mach-spear/spear13xx.c +++ b/arch/arm/mach-spear/spear13xx.c | |||
@@ -15,12 +15,12 @@ | |||
15 | 15 | ||
16 | #include <linux/amba/pl022.h> | 16 | #include <linux/amba/pl022.h> |
17 | #include <linux/clk.h> | 17 | #include <linux/clk.h> |
18 | #include <linux/clocksource.h> | ||
18 | #include <linux/dw_dmac.h> | 19 | #include <linux/dw_dmac.h> |
19 | #include <linux/err.h> | 20 | #include <linux/err.h> |
20 | #include <linux/of.h> | 21 | #include <linux/of.h> |
21 | #include <asm/hardware/cache-l2x0.h> | 22 | #include <asm/hardware/cache-l2x0.h> |
22 | #include <asm/mach/map.h> | 23 | #include <asm/mach/map.h> |
23 | #include <asm/smp_twd.h> | ||
24 | #include "generic.h" | 24 | #include "generic.h" |
25 | #include <mach/spear.h> | 25 | #include <mach/spear.h> |
26 | 26 | ||
@@ -180,5 +180,5 @@ void __init spear13xx_timer_init(void) | |||
180 | clk_put(pclk); | 180 | clk_put(pclk); |
181 | 181 | ||
182 | spear_setup_of_timer(); | 182 | spear_setup_of_timer(); |
183 | twd_local_timer_of_register(); | 183 | clocksource_of_init(); |
184 | } | 184 | } |
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index a6af0b8732ba..d07bbe7f04a6 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c | |||
@@ -7,6 +7,7 @@ | |||
7 | #include <linux/io.h> | 7 | #include <linux/io.h> |
8 | #include <linux/errno.h> | 8 | #include <linux/errno.h> |
9 | #include <linux/clksrc-dbx500-prcmu.h> | 9 | #include <linux/clksrc-dbx500-prcmu.h> |
10 | #include <linux/clocksource.h> | ||
10 | #include <linux/of.h> | 11 | #include <linux/of.h> |
11 | #include <linux/of_address.h> | 12 | #include <linux/of_address.h> |
12 | #include <linux/platform_data/clocksource-nomadik-mtu.h> | 13 | #include <linux/platform_data/clocksource-nomadik-mtu.h> |
@@ -32,7 +33,7 @@ static void __init ux500_twd_init(void) | |||
32 | twd_local_timer = &u8500_twd_local_timer; | 33 | twd_local_timer = &u8500_twd_local_timer; |
33 | 34 | ||
34 | if (of_have_populated_dt()) | 35 | if (of_have_populated_dt()) |
35 | twd_local_timer_of_register(); | 36 | clocksource_of_init(); |
36 | else { | 37 | else { |
37 | err = twd_local_timer_register(twd_local_timer); | 38 | err = twd_local_timer_register(twd_local_timer); |
38 | if (err) | 39 | if (err) |
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c index 915683cb67d6..d0ad78998cb6 100644 --- a/arch/arm/mach-vexpress/v2m.c +++ b/arch/arm/mach-vexpress/v2m.c | |||
@@ -5,6 +5,7 @@ | |||
5 | #include <linux/amba/bus.h> | 5 | #include <linux/amba/bus.h> |
6 | #include <linux/amba/mmci.h> | 6 | #include <linux/amba/mmci.h> |
7 | #include <linux/io.h> | 7 | #include <linux/io.h> |
8 | #include <linux/clocksource.h> | ||
8 | #include <linux/smp.h> | 9 | #include <linux/smp.h> |
9 | #include <linux/init.h> | 10 | #include <linux/init.h> |
10 | #include <linux/irqchip.h> | 11 | #include <linux/irqchip.h> |
@@ -25,7 +26,6 @@ | |||
25 | #include <asm/arch_timer.h> | 26 | #include <asm/arch_timer.h> |
26 | #include <asm/mach-types.h> | 27 | #include <asm/mach-types.h> |
27 | #include <asm/sizes.h> | 28 | #include <asm/sizes.h> |
28 | #include <asm/smp_twd.h> | ||
29 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
30 | #include <asm/mach/map.h> | 30 | #include <asm/mach/map.h> |
31 | #include <asm/mach/time.h> | 31 | #include <asm/mach/time.h> |
@@ -435,6 +435,7 @@ static void __init v2m_dt_timer_init(void) | |||
435 | 435 | ||
436 | vexpress_clk_of_init(); | 436 | vexpress_clk_of_init(); |
437 | 437 | ||
438 | clocksource_of_init(); | ||
438 | do { | 439 | do { |
439 | node = of_find_compatible_node(node, NULL, "arm,sp804"); | 440 | node = of_find_compatible_node(node, NULL, "arm,sp804"); |
440 | } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB); | 441 | } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB); |
@@ -445,8 +446,7 @@ static void __init v2m_dt_timer_init(void) | |||
445 | irq_of_parse_and_map(node, 0)); | 446 | irq_of_parse_and_map(node, 0)); |
446 | } | 447 | } |
447 | 448 | ||
448 | if (arch_timer_of_register() != 0) | 449 | arch_timer_of_register(); |
449 | twd_local_timer_of_register(); | ||
450 | 450 | ||
451 | if (arch_timer_sched_clock_init() != 0) | 451 | if (arch_timer_sched_clock_init() != 0) |
452 | versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), | 452 | versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), |
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 4d8283aec5b5..5e2176f9453f 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile | |||
@@ -16,6 +16,8 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += nomadik-mtu.o | |||
16 | obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o | 16 | obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o |
17 | obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o | 17 | obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o |
18 | obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o | 18 | obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o |
19 | obj-$(CONFIG_ARCH_MARCO) += timer-marco.o | ||
20 | obj-$(CONFIG_ARCH_PRIMA2) += timer-prima2.o | ||
19 | obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o | 21 | obj-$(CONFIG_SUNXI_TIMER) += sunxi_timer.o |
20 | obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o | 22 | obj-$(CONFIG_ARCH_TEGRA) += tegra20_timer.o |
21 | obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o | 23 | obj-$(CONFIG_VT8500_TIMER) += vt8500_timer.o |
diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c index 50c68fef944b..766611d29945 100644 --- a/drivers/clocksource/bcm2835_timer.c +++ b/drivers/clocksource/bcm2835_timer.c | |||
@@ -95,23 +95,13 @@ static irqreturn_t bcm2835_time_interrupt(int irq, void *dev_id) | |||
95 | } | 95 | } |
96 | } | 96 | } |
97 | 97 | ||
98 | static struct of_device_id bcm2835_time_match[] __initconst = { | 98 | static void __init bcm2835_timer_init(struct device_node *node) |
99 | { .compatible = "brcm,bcm2835-system-timer" }, | ||
100 | {} | ||
101 | }; | ||
102 | |||
103 | static void __init bcm2835_timer_init(void) | ||
104 | { | 99 | { |
105 | struct device_node *node; | ||
106 | void __iomem *base; | 100 | void __iomem *base; |
107 | u32 freq; | 101 | u32 freq; |
108 | int irq; | 102 | int irq; |
109 | struct bcm2835_timer *timer; | 103 | struct bcm2835_timer *timer; |
110 | 104 | ||
111 | node = of_find_matching_node(NULL, bcm2835_time_match); | ||
112 | if (!node) | ||
113 | panic("No bcm2835 timer node"); | ||
114 | |||
115 | base = of_iomap(node, 0); | 105 | base = of_iomap(node, 0); |
116 | if (!base) | 106 | if (!base) |
117 | panic("Can't remap registers"); | 107 | panic("Can't remap registers"); |
diff --git a/drivers/clocksource/clksrc-of.c b/drivers/clocksource/clksrc-of.c index bdabdaa8d00f..37f5325bec95 100644 --- a/drivers/clocksource/clksrc-of.c +++ b/drivers/clocksource/clksrc-of.c | |||
@@ -16,6 +16,7 @@ | |||
16 | 16 | ||
17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
18 | #include <linux/of.h> | 18 | #include <linux/of.h> |
19 | #include <linux/clocksource.h> | ||
19 | 20 | ||
20 | extern struct of_device_id __clksrc_of_table[]; | 21 | extern struct of_device_id __clksrc_of_table[]; |
21 | 22 | ||
@@ -26,10 +27,10 @@ void __init clocksource_of_init(void) | |||
26 | { | 27 | { |
27 | struct device_node *np; | 28 | struct device_node *np; |
28 | const struct of_device_id *match; | 29 | const struct of_device_id *match; |
29 | void (*init_func)(void); | 30 | clocksource_of_init_fn init_func; |
30 | 31 | ||
31 | for_each_matching_node_and_match(np, __clksrc_of_table, &match) { | 32 | for_each_matching_node_and_match(np, __clksrc_of_table, &match) { |
32 | init_func = match->data; | 33 | init_func = match->data; |
33 | init_func(); | 34 | init_func(np); |
34 | } | 35 | } |
35 | } | 36 | } |
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c index 0bde03feb095..2e4d8a666c36 100644 --- a/drivers/clocksource/tegra20_timer.c +++ b/drivers/clocksource/tegra20_timer.c | |||
@@ -154,29 +154,12 @@ static struct irqaction tegra_timer_irq = { | |||
154 | .dev_id = &tegra_clockevent, | 154 | .dev_id = &tegra_clockevent, |
155 | }; | 155 | }; |
156 | 156 | ||
157 | static const struct of_device_id timer_match[] __initconst = { | 157 | static void __init tegra20_init_timer(struct device_node *np) |
158 | { .compatible = "nvidia,tegra20-timer" }, | ||
159 | {} | ||
160 | }; | ||
161 | |||
162 | static const struct of_device_id rtc_match[] __initconst = { | ||
163 | { .compatible = "nvidia,tegra20-rtc" }, | ||
164 | {} | ||
165 | }; | ||
166 | |||
167 | static void __init tegra20_init_timer(void) | ||
168 | { | 158 | { |
169 | struct device_node *np; | ||
170 | struct clk *clk; | 159 | struct clk *clk; |
171 | unsigned long rate; | 160 | unsigned long rate; |
172 | int ret; | 161 | int ret; |
173 | 162 | ||
174 | np = of_find_matching_node(NULL, timer_match); | ||
175 | if (!np) { | ||
176 | pr_err("Failed to find timer DT node\n"); | ||
177 | BUG(); | ||
178 | } | ||
179 | |||
180 | timer_reg_base = of_iomap(np, 0); | 163 | timer_reg_base = of_iomap(np, 0); |
181 | if (!timer_reg_base) { | 164 | if (!timer_reg_base) { |
182 | pr_err("Can't map timer registers\n"); | 165 | pr_err("Can't map timer registers\n"); |
@@ -200,30 +183,6 @@ static void __init tegra20_init_timer(void) | |||
200 | 183 | ||
201 | of_node_put(np); | 184 | of_node_put(np); |
202 | 185 | ||
203 | np = of_find_matching_node(NULL, rtc_match); | ||
204 | if (!np) { | ||
205 | pr_err("Failed to find RTC DT node\n"); | ||
206 | BUG(); | ||
207 | } | ||
208 | |||
209 | rtc_base = of_iomap(np, 0); | ||
210 | if (!rtc_base) { | ||
211 | pr_err("Can't map RTC registers"); | ||
212 | BUG(); | ||
213 | } | ||
214 | |||
215 | /* | ||
216 | * rtc registers are used by read_persistent_clock, keep the rtc clock | ||
217 | * enabled | ||
218 | */ | ||
219 | clk = clk_get_sys("rtc-tegra", NULL); | ||
220 | if (IS_ERR(clk)) | ||
221 | pr_warn("Unable to get rtc-tegra clock\n"); | ||
222 | else | ||
223 | clk_prepare_enable(clk); | ||
224 | |||
225 | of_node_put(np); | ||
226 | |||
227 | switch (rate) { | 186 | switch (rate) { |
228 | case 12000000: | 187 | case 12000000: |
229 | timer_writel(0x000b, TIMERUS_USEC_CFG); | 188 | timer_writel(0x000b, TIMERUS_USEC_CFG); |
@@ -259,12 +218,34 @@ static void __init tegra20_init_timer(void) | |||
259 | tegra_clockevent.irq = tegra_timer_irq.irq; | 218 | tegra_clockevent.irq = tegra_timer_irq.irq; |
260 | clockevents_config_and_register(&tegra_clockevent, 1000000, | 219 | clockevents_config_and_register(&tegra_clockevent, 1000000, |
261 | 0x1, 0x1fffffff); | 220 | 0x1, 0x1fffffff); |
262 | #ifdef CONFIG_HAVE_ARM_TWD | 221 | } |
263 | twd_local_timer_of_register(); | 222 | CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); |
264 | #endif | 223 | |
224 | static void __init tegra20_init_rtc(struct device_node *np) | ||
225 | { | ||
226 | struct clk *clk; | ||
227 | |||
228 | rtc_base = of_iomap(np, 0); | ||
229 | if (!rtc_base) { | ||
230 | pr_err("Can't map RTC registers"); | ||
231 | BUG(); | ||
232 | } | ||
233 | |||
234 | /* | ||
235 | * rtc registers are used by read_persistent_clock, keep the rtc clock | ||
236 | * enabled | ||
237 | */ | ||
238 | clk = clk_get_sys("rtc-tegra", NULL); | ||
239 | if (IS_ERR(clk)) | ||
240 | pr_warn("Unable to get rtc-tegra clock\n"); | ||
241 | else | ||
242 | clk_prepare_enable(clk); | ||
243 | |||
244 | of_node_put(np); | ||
245 | |||
265 | register_persistent_clock(NULL, tegra_read_persistent_clock); | 246 | register_persistent_clock(NULL, tegra_read_persistent_clock); |
266 | } | 247 | } |
267 | CLOCKSOURCE_OF_DECLARE(tegra20, "nvidia,tegra20-timer", tegra20_init_timer); | 248 | CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); |
268 | 249 | ||
269 | #ifdef CONFIG_PM | 250 | #ifdef CONFIG_PM |
270 | static u32 usec_config; | 251 | static u32 usec_config; |
diff --git a/arch/arm/mach-prima2/timer-marco.c b/drivers/clocksource/timer-marco.c index f4eea2e97eb0..97738dbf3e3b 100644 --- a/arch/arm/mach-prima2/timer-marco.c +++ b/drivers/clocksource/timer-marco.c | |||
@@ -21,8 +21,6 @@ | |||
21 | #include <asm/localtimer.h> | 21 | #include <asm/localtimer.h> |
22 | #include <asm/mach/time.h> | 22 | #include <asm/mach/time.h> |
23 | 23 | ||
24 | #include "common.h" | ||
25 | |||
26 | #define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000 | 24 | #define SIRFSOC_TIMER_32COUNTER_0_CTRL 0x0000 |
27 | #define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004 | 25 | #define SIRFSOC_TIMER_32COUNTER_1_CTRL 0x0004 |
28 | #define SIRFSOC_TIMER_MATCH_0 0x0018 | 26 | #define SIRFSOC_TIMER_MATCH_0 0x0018 |
@@ -53,7 +51,6 @@ static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { | |||
53 | static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; | 51 | static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; |
54 | 52 | ||
55 | static void __iomem *sirfsoc_timer_base; | 53 | static void __iomem *sirfsoc_timer_base; |
56 | static void __init sirfsoc_of_timer_map(void); | ||
57 | 54 | ||
58 | /* disable count and interrupt */ | 55 | /* disable count and interrupt */ |
59 | static inline void sirfsoc_timer_count_disable(int idx) | 56 | static inline void sirfsoc_timer_count_disable(int idx) |
@@ -242,15 +239,12 @@ static void __init sirfsoc_clockevent_init(void) | |||
242 | } | 239 | } |
243 | 240 | ||
244 | /* initialize the kernel jiffy timer source */ | 241 | /* initialize the kernel jiffy timer source */ |
245 | void __init sirfsoc_marco_timer_init(void) | 242 | static void __init sirfsoc_marco_timer_init(void) |
246 | { | 243 | { |
247 | unsigned long rate; | 244 | unsigned long rate; |
248 | u32 timer_div; | 245 | u32 timer_div; |
249 | struct clk *clk; | 246 | struct clk *clk; |
250 | 247 | ||
251 | /* initialize clocking early, we want to set the OS timer */ | ||
252 | sirfsoc_of_clk_init(); | ||
253 | |||
254 | /* timer's input clock is io clock */ | 248 | /* timer's input clock is io clock */ |
255 | clk = clk_get_sys("io", NULL); | 249 | clk = clk_get_sys("io", NULL); |
256 | 250 | ||
@@ -260,8 +254,6 @@ void __init sirfsoc_marco_timer_init(void) | |||
260 | BUG_ON(rate < CLOCK_TICK_RATE); | 254 | BUG_ON(rate < CLOCK_TICK_RATE); |
261 | BUG_ON(rate % CLOCK_TICK_RATE); | 255 | BUG_ON(rate % CLOCK_TICK_RATE); |
262 | 256 | ||
263 | sirfsoc_of_timer_map(); | ||
264 | |||
265 | /* Initialize the timer dividers */ | 257 | /* Initialize the timer dividers */ |
266 | timer_div = rate / CLOCK_TICK_RATE - 1; | 258 | timer_div = rate / CLOCK_TICK_RATE - 1; |
267 | writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); | 259 | writel_relaxed(timer_div << 16, sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL); |
@@ -286,18 +278,8 @@ void __init sirfsoc_marco_timer_init(void) | |||
286 | sirfsoc_clockevent_init(); | 278 | sirfsoc_clockevent_init(); |
287 | } | 279 | } |
288 | 280 | ||
289 | static struct of_device_id timer_ids[] = { | 281 | static void __init sirfsoc_of_timer_init(struct device_node *np) |
290 | { .compatible = "sirf,marco-tick" }, | ||
291 | {}, | ||
292 | }; | ||
293 | |||
294 | static void __init sirfsoc_of_timer_map(void) | ||
295 | { | 282 | { |
296 | struct device_node *np; | ||
297 | |||
298 | np = of_find_matching_node(NULL, timer_ids); | ||
299 | if (!np) | ||
300 | return; | ||
301 | sirfsoc_timer_base = of_iomap(np, 0); | 283 | sirfsoc_timer_base = of_iomap(np, 0); |
302 | if (!sirfsoc_timer_base) | 284 | if (!sirfsoc_timer_base) |
303 | panic("unable to map timer cpu registers\n"); | 285 | panic("unable to map timer cpu registers\n"); |
@@ -312,5 +294,6 @@ static void __init sirfsoc_of_timer_map(void) | |||
312 | panic("No irq passed for timer1 via DT\n"); | 294 | panic("No irq passed for timer1 via DT\n"); |
313 | #endif | 295 | #endif |
314 | 296 | ||
315 | of_node_put(np); | 297 | sirfsoc_marco_timer_init(); |
316 | } | 298 | } |
299 | CLOCKSOURCE_OF_DECLARE(sirfsoc_marco_timer, "sirf,marco-tick", sirfsoc_of_timer_init ); | ||
diff --git a/arch/arm/mach-prima2/timer-prima2.c b/drivers/clocksource/timer-prima2.c index 6da584f8a949..760882665d7a 100644 --- a/arch/arm/mach-prima2/timer-prima2.c +++ b/drivers/clocksource/timer-prima2.c | |||
@@ -16,13 +16,11 @@ | |||
16 | #include <linux/err.h> | 16 | #include <linux/err.h> |
17 | #include <linux/slab.h> | 17 | #include <linux/slab.h> |
18 | #include <linux/of.h> | 18 | #include <linux/of.h> |
19 | #include <linux/of_irq.h> | ||
19 | #include <linux/of_address.h> | 20 | #include <linux/of_address.h> |
20 | #include <mach/map.h> | ||
21 | #include <asm/sched_clock.h> | 21 | #include <asm/sched_clock.h> |
22 | #include <asm/mach/time.h> | 22 | #include <asm/mach/time.h> |
23 | 23 | ||
24 | #include "common.h" | ||
25 | |||
26 | #define SIRFSOC_TIMER_COUNTER_LO 0x0000 | 24 | #define SIRFSOC_TIMER_COUNTER_LO 0x0000 |
27 | #define SIRFSOC_TIMER_COUNTER_HI 0x0004 | 25 | #define SIRFSOC_TIMER_COUNTER_HI 0x0004 |
28 | #define SIRFSOC_TIMER_MATCH_0 0x0008 | 26 | #define SIRFSOC_TIMER_MATCH_0 0x0008 |
@@ -55,7 +53,6 @@ static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = { | |||
55 | static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; | 53 | static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT]; |
56 | 54 | ||
57 | static void __iomem *sirfsoc_timer_base; | 55 | static void __iomem *sirfsoc_timer_base; |
58 | static void __init sirfsoc_of_timer_map(void); | ||
59 | 56 | ||
60 | /* timer0 interrupt handler */ | 57 | /* timer0 interrupt handler */ |
61 | static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) | 58 | static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id) |
@@ -181,14 +178,11 @@ static void __init sirfsoc_clockevent_init(void) | |||
181 | } | 178 | } |
182 | 179 | ||
183 | /* initialize the kernel jiffy timer source */ | 180 | /* initialize the kernel jiffy timer source */ |
184 | void __init sirfsoc_prima2_timer_init(void) | 181 | static void __init sirfsoc_prima2_timer_init(struct device_node *np) |
185 | { | 182 | { |
186 | unsigned long rate; | 183 | unsigned long rate; |
187 | struct clk *clk; | 184 | struct clk *clk; |
188 | 185 | ||
189 | /* initialize clocking early, we want to set the OS timer */ | ||
190 | sirfsoc_of_clk_init(); | ||
191 | |||
192 | /* timer's input clock is io clock */ | 186 | /* timer's input clock is io clock */ |
193 | clk = clk_get_sys("io", NULL); | 187 | clk = clk_get_sys("io", NULL); |
194 | 188 | ||
@@ -199,7 +193,11 @@ void __init sirfsoc_prima2_timer_init(void) | |||
199 | BUG_ON(rate < CLOCK_TICK_RATE); | 193 | BUG_ON(rate < CLOCK_TICK_RATE); |
200 | BUG_ON(rate % CLOCK_TICK_RATE); | 194 | BUG_ON(rate % CLOCK_TICK_RATE); |
201 | 195 | ||
202 | sirfsoc_of_timer_map(); | 196 | sirfsoc_timer_base = of_iomap(np, 0); |
197 | if (!sirfsoc_timer_base) | ||
198 | panic("unable to map timer cpu registers\n"); | ||
199 | |||
200 | sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0); | ||
203 | 201 | ||
204 | writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV); | 202 | writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV); |
205 | writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); | 203 | writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO); |
@@ -214,28 +212,4 @@ void __init sirfsoc_prima2_timer_init(void) | |||
214 | 212 | ||
215 | sirfsoc_clockevent_init(); | 213 | sirfsoc_clockevent_init(); |
216 | } | 214 | } |
217 | 215 | CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer, "sirf,prima2-tick", sirfsoc_prima2_timer_init); | |
218 | static struct of_device_id timer_ids[] = { | ||
219 | { .compatible = "sirf,prima2-tick" }, | ||
220 | {}, | ||
221 | }; | ||
222 | |||
223 | static void __init sirfsoc_of_timer_map(void) | ||
224 | { | ||
225 | struct device_node *np; | ||
226 | const unsigned int *intspec; | ||
227 | |||
228 | np = of_find_matching_node(NULL, timer_ids); | ||
229 | if (!np) | ||
230 | return; | ||
231 | sirfsoc_timer_base = of_iomap(np, 0); | ||
232 | if (!sirfsoc_timer_base) | ||
233 | panic("unable to map timer cpu registers\n"); | ||
234 | |||
235 | /* Get the interrupts property */ | ||
236 | intspec = of_get_property(np, "interrupts", NULL); | ||
237 | BUG_ON(!intspec); | ||
238 | sirfsoc_timer_irq.irq = be32_to_cpup(intspec); | ||
239 | |||
240 | of_node_put(np); | ||
241 | } | ||
diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/vt8500_timer.c index 8efc86b5b5dd..64f553f04fa4 100644 --- a/drivers/clocksource/vt8500_timer.c +++ b/drivers/clocksource/vt8500_timer.c | |||
@@ -129,22 +129,10 @@ static struct irqaction irq = { | |||
129 | .dev_id = &clockevent, | 129 | .dev_id = &clockevent, |
130 | }; | 130 | }; |
131 | 131 | ||
132 | static struct of_device_id vt8500_timer_ids[] = { | 132 | static void __init vt8500_timer_init(struct device_node *np) |
133 | { .compatible = "via,vt8500-timer" }, | ||
134 | { } | ||
135 | }; | ||
136 | |||
137 | static void __init vt8500_timer_init(void) | ||
138 | { | 133 | { |
139 | struct device_node *np; | ||
140 | int timer_irq; | 134 | int timer_irq; |
141 | 135 | ||
142 | np = of_find_matching_node(NULL, vt8500_timer_ids); | ||
143 | if (!np) { | ||
144 | pr_err("%s: Timer description missing from Device Tree\n", | ||
145 | __func__); | ||
146 | return; | ||
147 | } | ||
148 | regbase = of_iomap(np, 0); | 136 | regbase = of_iomap(np, 0); |
149 | if (!regbase) { | 137 | if (!regbase) { |
150 | pr_err("%s: Missing iobase description in Device Tree\n", | 138 | pr_err("%s: Missing iobase description in Device Tree\n", |
@@ -177,4 +165,4 @@ static void __init vt8500_timer_init(void) | |||
177 | 4, 0xf0000000); | 165 | 4, 0xf0000000); |
178 | } | 166 | } |
179 | 167 | ||
180 | CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init) | 168 | CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init); |
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile index 98e3b87bdf1b..5cb6bd24d8bf 100644 --- a/drivers/irqchip/Makefile +++ b/drivers/irqchip/Makefile | |||
@@ -8,4 +8,5 @@ obj-$(CONFIG_ARCH_SUNXI) += irq-sunxi.o | |||
8 | obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o | 8 | obj-$(CONFIG_ARCH_SPEAR3XX) += spear-shirq.o |
9 | obj-$(CONFIG_ARM_GIC) += irq-gic.o | 9 | obj-$(CONFIG_ARM_GIC) += irq-gic.o |
10 | obj-$(CONFIG_ARM_VIC) += irq-vic.o | 10 | obj-$(CONFIG_ARM_VIC) += irq-vic.o |
11 | obj-$(CONFIG_SIRF_IRQ) += irq-sirfsoc.o | ||
11 | obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o | 12 | obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o |
diff --git a/drivers/irqchip/irq-sirfsoc.c b/drivers/irqchip/irq-sirfsoc.c new file mode 100644 index 000000000000..69ea44ebcf61 --- /dev/null +++ b/drivers/irqchip/irq-sirfsoc.c | |||
@@ -0,0 +1,126 @@ | |||
1 | /* | ||
2 | * interrupt controller support for CSR SiRFprimaII | ||
3 | * | ||
4 | * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. | ||
5 | * | ||
6 | * Licensed under GPLv2 or later. | ||
7 | */ | ||
8 | |||
9 | #include <linux/init.h> | ||
10 | #include <linux/io.h> | ||
11 | #include <linux/irq.h> | ||
12 | #include <linux/of.h> | ||
13 | #include <linux/of_address.h> | ||
14 | #include <linux/irqdomain.h> | ||
15 | #include <linux/syscore_ops.h> | ||
16 | #include <asm/mach/irq.h> | ||
17 | #include <asm/exception.h> | ||
18 | #include "irqchip.h" | ||
19 | |||
20 | #define SIRFSOC_INT_RISC_MASK0 0x0018 | ||
21 | #define SIRFSOC_INT_RISC_MASK1 0x001C | ||
22 | #define SIRFSOC_INT_RISC_LEVEL0 0x0020 | ||
23 | #define SIRFSOC_INT_RISC_LEVEL1 0x0024 | ||
24 | #define SIRFSOC_INIT_IRQ_ID 0x0038 | ||
25 | |||
26 | #define SIRFSOC_NUM_IRQS 128 | ||
27 | |||
28 | static struct irq_domain *sirfsoc_irqdomain; | ||
29 | |||
30 | static __init void | ||
31 | sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) | ||
32 | { | ||
33 | struct irq_chip_generic *gc; | ||
34 | struct irq_chip_type *ct; | ||
35 | |||
36 | gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq); | ||
37 | ct = gc->chip_types; | ||
38 | |||
39 | ct->chip.irq_mask = irq_gc_mask_clr_bit; | ||
40 | ct->chip.irq_unmask = irq_gc_mask_set_bit; | ||
41 | ct->regs.mask = SIRFSOC_INT_RISC_MASK0; | ||
42 | |||
43 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0); | ||
44 | } | ||
45 | |||
46 | static asmlinkage void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs) | ||
47 | { | ||
48 | void __iomem *base = sirfsoc_irqdomain->host_data; | ||
49 | u32 irqstat, irqnr; | ||
50 | |||
51 | irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); | ||
52 | irqnr = irq_find_mapping(sirfsoc_irqdomain, irqstat & 0xff); | ||
53 | |||
54 | handle_IRQ(irqnr, regs); | ||
55 | } | ||
56 | |||
57 | static int __init sirfsoc_irq_init(struct device_node *np, struct device_node *parent) | ||
58 | { | ||
59 | void __iomem *base = of_iomap(np, 0); | ||
60 | if (!base) | ||
61 | panic("unable to map intc cpu registers\n"); | ||
62 | |||
63 | /* using legacy because irqchip_generic does not work with linear */ | ||
64 | sirfsoc_irqdomain = irq_domain_add_legacy(np, SIRFSOC_NUM_IRQS, 0, 0, | ||
65 | &irq_domain_simple_ops, base); | ||
66 | |||
67 | sirfsoc_alloc_gc(base, 0, 32); | ||
68 | sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32); | ||
69 | |||
70 | writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); | ||
71 | writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1); | ||
72 | |||
73 | writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0); | ||
74 | writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1); | ||
75 | |||
76 | set_handle_irq(sirfsoc_handle_irq); | ||
77 | |||
78 | return 0; | ||
79 | } | ||
80 | IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init); | ||
81 | |||
82 | struct sirfsoc_irq_status { | ||
83 | u32 mask0; | ||
84 | u32 mask1; | ||
85 | u32 level0; | ||
86 | u32 level1; | ||
87 | }; | ||
88 | |||
89 | static struct sirfsoc_irq_status sirfsoc_irq_st; | ||
90 | |||
91 | static int sirfsoc_irq_suspend(void) | ||
92 | { | ||
93 | void __iomem *base = sirfsoc_irqdomain->host_data; | ||
94 | |||
95 | sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0); | ||
96 | sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1); | ||
97 | sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0); | ||
98 | sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1); | ||
99 | |||
100 | return 0; | ||
101 | } | ||
102 | |||
103 | static void sirfsoc_irq_resume(void) | ||
104 | { | ||
105 | void __iomem *base = sirfsoc_irqdomain->host_data; | ||
106 | |||
107 | writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0); | ||
108 | writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1); | ||
109 | writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0); | ||
110 | writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1); | ||
111 | } | ||
112 | |||
113 | static struct syscore_ops sirfsoc_irq_syscore_ops = { | ||
114 | .suspend = sirfsoc_irq_suspend, | ||
115 | .resume = sirfsoc_irq_resume, | ||
116 | }; | ||
117 | |||
118 | static int __init sirfsoc_irq_pm_init(void) | ||
119 | { | ||
120 | if (!sirfsoc_irqdomain) | ||
121 | return 0; | ||
122 | |||
123 | register_syscore_ops(&sirfsoc_irq_syscore_ops); | ||
124 | return 0; | ||
125 | } | ||
126 | device_initcall(sirfsoc_irq_pm_init); | ||
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c index d02498b30c6e..eaea149aa9c5 100644 --- a/drivers/pinctrl/pinctrl-sirf.c +++ b/drivers/pinctrl/pinctrl-sirf.c | |||
@@ -1347,7 +1347,7 @@ static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |||
1347 | struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip), | 1347 | struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip), |
1348 | struct sirfsoc_gpio_bank, chip); | 1348 | struct sirfsoc_gpio_bank, chip); |
1349 | 1349 | ||
1350 | return irq_find_mapping(bank->domain, offset); | 1350 | return irq_create_mapping(bank->domain, offset); |
1351 | } | 1351 | } |
1352 | 1352 | ||
1353 | static inline int sirfsoc_gpio_to_offset(unsigned int gpio) | 1353 | static inline int sirfsoc_gpio_to_offset(unsigned int gpio) |
@@ -1485,7 +1485,6 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) | |||
1485 | struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq); | 1485 | struct sirfsoc_gpio_bank *bank = irq_get_handler_data(irq); |
1486 | u32 status, ctrl; | 1486 | u32 status, ctrl; |
1487 | int idx = 0; | 1487 | int idx = 0; |
1488 | unsigned int first_irq; | ||
1489 | struct irq_chip *chip = irq_get_chip(irq); | 1488 | struct irq_chip *chip = irq_get_chip(irq); |
1490 | 1489 | ||
1491 | chained_irq_enter(chip, desc); | 1490 | chained_irq_enter(chip, desc); |
@@ -1499,8 +1498,6 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) | |||
1499 | return; | 1498 | return; |
1500 | } | 1499 | } |
1501 | 1500 | ||
1502 | first_irq = bank->domain->revmap_data.legacy.first_irq; | ||
1503 | |||
1504 | while (status) { | 1501 | while (status) { |
1505 | ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); | 1502 | ctrl = readl(bank->chip.regs + SIRFSOC_GPIO_CTRL(bank->id, idx)); |
1506 | 1503 | ||
@@ -1511,7 +1508,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) | |||
1511 | if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { | 1508 | if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { |
1512 | pr_debug("%s: gpio id %d idx %d happens\n", | 1509 | pr_debug("%s: gpio id %d idx %d happens\n", |
1513 | __func__, bank->id, idx); | 1510 | __func__, bank->id, idx); |
1514 | generic_handle_irq(first_irq + idx); | 1511 | generic_handle_irq(irq_find_mapping(bank->domain, idx)); |
1515 | } | 1512 | } |
1516 | 1513 | ||
1517 | idx++; | 1514 | idx++; |
@@ -1770,9 +1767,8 @@ static int sirfsoc_gpio_probe(struct device_node *np) | |||
1770 | goto out; | 1767 | goto out; |
1771 | } | 1768 | } |
1772 | 1769 | ||
1773 | bank->domain = irq_domain_add_legacy(np, SIRFSOC_GPIO_BANK_SIZE, | 1770 | bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE, |
1774 | SIRFSOC_GPIO_IRQ_START + i * SIRFSOC_GPIO_BANK_SIZE, 0, | 1771 | &sirfsoc_gpio_irq_simple_ops, bank); |
1775 | &sirfsoc_gpio_irq_simple_ops, bank); | ||
1776 | 1772 | ||
1777 | if (!bank->domain) { | 1773 | if (!bank->domain) { |
1778 | pr_err("%s: Failed to create irqdomain\n", np->full_name); | 1774 | pr_err("%s: Failed to create irqdomain\n", np->full_name); |
diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index 27cfda427dd9..ac33184b14fd 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h | |||
@@ -332,15 +332,23 @@ extern int clocksource_mmio_init(void __iomem *, const char *, | |||
332 | 332 | ||
333 | extern int clocksource_i8253_init(void); | 333 | extern int clocksource_i8253_init(void); |
334 | 334 | ||
335 | struct device_node; | ||
336 | typedef void(*clocksource_of_init_fn)(struct device_node *); | ||
335 | #ifdef CONFIG_CLKSRC_OF | 337 | #ifdef CONFIG_CLKSRC_OF |
336 | extern void clocksource_of_init(void); | 338 | extern void clocksource_of_init(void); |
337 | 339 | ||
338 | #define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \ | 340 | #define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \ |
339 | static const struct of_device_id __clksrc_of_table_##name \ | 341 | static const struct of_device_id __clksrc_of_table_##name \ |
340 | __used __section(__clksrc_of_table) \ | 342 | __used __section(__clksrc_of_table) \ |
341 | = { .compatible = compat, .data = fn }; | 343 | = { .compatible = compat, \ |
344 | .data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn } | ||
342 | #else | 345 | #else |
343 | #define CLOCKSOURCE_OF_DECLARE(name, compat, fn) | 346 | static inline void clocksource_of_init(void) {} |
347 | #define CLOCKSOURCE_OF_DECLARE(name, compat, fn) \ | ||
348 | static const struct of_device_id __clksrc_of_table_##name \ | ||
349 | __unused __section(__clksrc_of_table) \ | ||
350 | = { .compatible = compat, \ | ||
351 | .data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn } | ||
344 | #endif | 352 | #endif |
345 | 353 | ||
346 | #endif /* _LINUX_CLOCKSOURCE_H */ | 354 | #endif /* _LINUX_CLOCKSOURCE_H */ |