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authorSamuel Ortiz <sameo@linux.intel.com>2012-07-08 18:17:44 -0400
committerSamuel Ortiz <sameo@linux.intel.com>2012-07-08 18:17:44 -0400
commit0620de5983c82c95d83302e7f10064545a6996c5 (patch)
tree5b273ea4fccc8ab48e3d3100af3483c27e78043c
parent3a8e39c9f475dd061d1bbb7bf3b819f601df33e5 (diff)
parent3afbac957e3c59037a4ecaf19d68f6c8104299fc (diff)
Merge tag 'mfd/wm5102' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc into for-next
mfd: Initial support for Wolfson Arizona platform and WM5102 devices The Wolfson Arizona platform is used to provide common register interface to a series of low power audio hub CODECs, starting with the WM5102. Since the features of these devices work over a range of subsystems an MFD core driver is provided to instantiate the subdevices and arbitrate access between them. As the new regmap wake IRQ functionality is used as part of the driver it is incorporated as a dependency.
Diffstat
-rw-r--r--drivers/base/regmap/regmap-irq.c51
-rw-r--r--drivers/mfd/Kconfig29
-rw-r--r--drivers/mfd/Makefile7
-rw-r--r--drivers/mfd/arizona-core.c527
-rw-r--r--drivers/mfd/arizona-i2c.c89
-rw-r--r--drivers/mfd/arizona-irq.c267
-rw-r--r--drivers/mfd/arizona-spi.c91
-rw-r--r--drivers/mfd/arizona.h33
-rw-r--r--drivers/mfd/wm5102-tables.c2399
-rw-r--r--include/linux/mfd/arizona/core.h102
-rw-r--r--include/linux/mfd/arizona/pdata.h119
-rw-r--r--include/linux/mfd/arizona/registers.h6222
-rw-r--r--include/linux/regmap.h2
13 files changed, 9938 insertions, 0 deletions
diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c
index 4fac4b9be88f..b480b529f020 100644
--- a/drivers/base/regmap/regmap-irq.c
+++ b/drivers/base/regmap/regmap-irq.c
@@ -29,9 +29,13 @@ struct regmap_irq_chip_data {
29 int irq_base; 29 int irq_base;
30 struct irq_domain *domain; 30 struct irq_domain *domain;
31 31
32 int irq;
33 int wake_count;
34
32 unsigned int *status_buf; 35 unsigned int *status_buf;
33 unsigned int *mask_buf; 36 unsigned int *mask_buf;
34 unsigned int *mask_buf_def; 37 unsigned int *mask_buf_def;
38 unsigned int *wake_buf;
35 39
36 unsigned int irq_reg_stride; 40 unsigned int irq_reg_stride;
37}; 41};
@@ -71,6 +75,16 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
71 d->chip->mask_base + (i * map->reg_stride)); 75 d->chip->mask_base + (i * map->reg_stride));
72 } 76 }
73 77
78 /* If we've changed our wakeup count propagate it to the parent */
79 if (d->wake_count < 0)
80 for (i = d->wake_count; i < 0; i++)
81 irq_set_irq_wake(d->irq, 0);
82 else if (d->wake_count > 0)
83 for (i = 0; i < d->wake_count; i++)
84 irq_set_irq_wake(d->irq, 1);
85
86 d->wake_count = 0;
87
74 mutex_unlock(&d->lock); 88 mutex_unlock(&d->lock);
75} 89}
76 90
@@ -92,12 +106,35 @@ static void regmap_irq_disable(struct irq_data *data)
92 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; 106 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask;
93} 107}
94 108
109static int regmap_irq_set_wake(struct irq_data *data, unsigned int on)
110{
111 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data);
112 struct regmap *map = d->map;
113 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq);
114
115 if (!d->chip->wake_base)
116 return -EINVAL;
117
118 if (on) {
119 d->wake_buf[irq_data->reg_offset / map->reg_stride]
120 &= ~irq_data->mask;
121 d->wake_count++;
122 } else {
123 d->wake_buf[irq_data->reg_offset / map->reg_stride]
124 |= irq_data->mask;
125 d->wake_count--;
126 }
127
128 return 0;
129}
130
95static struct irq_chip regmap_irq_chip = { 131static struct irq_chip regmap_irq_chip = {
96 .name = "regmap", 132 .name = "regmap",
97 .irq_bus_lock = regmap_irq_lock, 133 .irq_bus_lock = regmap_irq_lock,
98 .irq_bus_sync_unlock = regmap_irq_sync_unlock, 134 .irq_bus_sync_unlock = regmap_irq_sync_unlock,
99 .irq_disable = regmap_irq_disable, 135 .irq_disable = regmap_irq_disable,
100 .irq_enable = regmap_irq_enable, 136 .irq_enable = regmap_irq_enable,
137 .irq_set_wake = regmap_irq_set_wake,
101}; 138};
102 139
103static irqreturn_t regmap_irq_thread(int irq, void *d) 140static irqreturn_t regmap_irq_thread(int irq, void *d)
@@ -240,6 +277,14 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
240 if (!d->mask_buf_def) 277 if (!d->mask_buf_def)
241 goto err_alloc; 278 goto err_alloc;
242 279
280 if (chip->wake_base) {
281 d->wake_buf = kzalloc(sizeof(unsigned int) * chip->num_regs,
282 GFP_KERNEL);
283 if (!d->wake_buf)
284 goto err_alloc;
285 }
286
287 d->irq = irq;
243 d->map = map; 288 d->map = map;
244 d->chip = chip; 289 d->chip = chip;
245 d->irq_base = irq_base; 290 d->irq_base = irq_base;
@@ -294,6 +339,7 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
294err_domain: 339err_domain:
295 /* Should really dispose of the domain but... */ 340 /* Should really dispose of the domain but... */
296err_alloc: 341err_alloc:
342 kfree(d->wake_buf);
297 kfree(d->mask_buf_def); 343 kfree(d->mask_buf_def);
298 kfree(d->mask_buf); 344 kfree(d->mask_buf);
299 kfree(d->status_buf); 345 kfree(d->status_buf);
@@ -315,6 +361,7 @@ void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d)
315 361
316 free_irq(irq, d); 362 free_irq(irq, d);
317 /* We should unmap the domain but... */ 363 /* We should unmap the domain but... */
364 kfree(d->wake_buf);
318 kfree(d->mask_buf_def); 365 kfree(d->mask_buf_def);
319 kfree(d->mask_buf); 366 kfree(d->mask_buf);
320 kfree(d->status_buf); 367 kfree(d->status_buf);
@@ -346,6 +393,10 @@ EXPORT_SYMBOL_GPL(regmap_irq_chip_get_base);
346 */ 393 */
347int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq) 394int regmap_irq_get_virq(struct regmap_irq_chip_data *data, int irq)
348{ 395{
396 /* Handle holes in the IRQ list */
397 if (!data->chip->irqs[irq].mask)
398 return -EINVAL;
399
349 return irq_create_mapping(data->domain, irq); 400 return irq_create_mapping(data->domain, irq);
350} 401}
351EXPORT_SYMBOL_GPL(regmap_irq_get_virq); 402EXPORT_SYMBOL_GPL(regmap_irq_get_virq);
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index aaa048a437c0..11ee6ec76011 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -495,6 +495,35 @@ config MFD_S5M_CORE
495 additional drivers must be enabled in order to use the functionality 495 additional drivers must be enabled in order to use the functionality
496 of the device 496 of the device
497 497
498config MFD_ARIZONA
499 tristate
500
501config MFD_ARIZONA_I2C
502 tristate "Support Wolfson Microelectronics Arizona platform with I2C"
503 select MFD_ARIZONA
504 select MFD_CORE
505 select REGMAP_I2C
506 depends on I2C
507 help
508 Support for the Wolfson Microelectronics Arizona platform audio SoC
509 core functionality controlled via I2C.
510
511config MFD_ARIZONA_SPI
512 tristate "Support Wolfson Microelectronics Arizona platform with SPI"
513 select MFD_ARIZONA
514 select MFD_CORE
515 select REGMAP_SPI
516 depends on SPI_MASTER
517 help
518 Support for the Wolfson Microelectronics Arizona platform audio SoC
519 core functionality controlled via I2C.
520
521config MFD_WM5102
522 bool "Support Wolfson Microelectronics WM5102"
523 depends on MFD_ARIZONA
524 help
525 Support for Wolfson Microelectronics WM5102 low power audio SoC
526
498config MFD_WM8400 527config MFD_WM8400
499 bool "Support Wolfson Microelectronics WM8400" 528 bool "Support Wolfson Microelectronics WM8400"
500 select MFD_CORE 529 select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 8ee7a3bf595b..f28885bb103c 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -24,6 +24,13 @@ obj-$(CONFIG_MFD_T7L66XB) += t7l66xb.o tmio_core.o
24obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o tmio_core.o 24obj-$(CONFIG_MFD_TC6387XB) += tc6387xb.o tmio_core.o
25obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o tmio_core.o 25obj-$(CONFIG_MFD_TC6393XB) += tc6393xb.o tmio_core.o
26 26
27obj-$(CONFIG_MFD_ARIZONA) += arizona-core.o
28obj-$(CONFIG_MFD_ARIZONA) += arizona-irq.o
29obj-$(CONFIG_MFD_ARIZONA_I2C) += arizona-i2c.o
30obj-$(CONFIG_MFD_ARIZONA_SPI) += arizona-spi.o
31ifneq ($(CONFIG_MFD_WM5102),n)
32obj-$(CONFIG_MFD_ARIZONA) += wm5102-tables.o
33endif
27obj-$(CONFIG_MFD_WM8400) += wm8400-core.o 34obj-$(CONFIG_MFD_WM8400) += wm8400-core.o
28wm831x-objs := wm831x-core.o wm831x-irq.o wm831x-otp.o 35wm831x-objs := wm831x-core.o wm831x-irq.o wm831x-otp.o
29wm831x-objs += wm831x-auxadc.o 36wm831x-objs += wm831x-auxadc.o
diff --git a/drivers/mfd/arizona-core.c b/drivers/mfd/arizona-core.c
new file mode 100644
index 000000000000..42cb28b2b5c8
--- /dev/null
+++ b/drivers/mfd/arizona-core.c
@@ -0,0 +1,527 @@
1/*
2 * Arizona core driver
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/delay.h>
14#include <linux/gpio.h>
15#include <linux/interrupt.h>
16#include <linux/mfd/core.h>
17#include <linux/module.h>
18#include <linux/pm_runtime.h>
19#include <linux/regmap.h>
20#include <linux/regulator/consumer.h>
21#include <linux/slab.h>
22
23#include <linux/mfd/arizona/core.h>
24#include <linux/mfd/arizona/registers.h>
25
26#include "arizona.h"
27
28static const char *wm5102_core_supplies[] = {
29 "AVDD",
30 "DBVDD1",
31 "DCVDD",
32};
33
34int arizona_clk32k_enable(struct arizona *arizona)
35{
36 int ret = 0;
37
38 mutex_lock(&arizona->clk_lock);
39
40 arizona->clk32k_ref++;
41
42 if (arizona->clk32k_ref == 1)
43 ret = regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
44 ARIZONA_CLK_32K_ENA,
45 ARIZONA_CLK_32K_ENA);
46
47 if (ret != 0)
48 arizona->clk32k_ref--;
49
50 mutex_unlock(&arizona->clk_lock);
51
52 return ret;
53}
54EXPORT_SYMBOL_GPL(arizona_clk32k_enable);
55
56int arizona_clk32k_disable(struct arizona *arizona)
57{
58 int ret = 0;
59
60 mutex_lock(&arizona->clk_lock);
61
62 BUG_ON(arizona->clk32k_ref <= 0);
63
64 arizona->clk32k_ref--;
65
66 if (arizona->clk32k_ref == 0)
67 regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
68 ARIZONA_CLK_32K_ENA, 0);
69
70 mutex_unlock(&arizona->clk_lock);
71
72 return ret;
73}
74EXPORT_SYMBOL_GPL(arizona_clk32k_disable);
75
76static irqreturn_t arizona_clkgen_err(int irq, void *data)
77{
78 struct arizona *arizona = data;
79
80 dev_err(arizona->dev, "CLKGEN error\n");
81
82 return IRQ_HANDLED;
83}
84
85static irqreturn_t arizona_underclocked(int irq, void *data)
86{
87 struct arizona *arizona = data;
88 unsigned int val;
89 int ret;
90
91 ret = regmap_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_8,
92 &val);
93 if (ret != 0) {
94 dev_err(arizona->dev, "Failed to read underclock status: %d\n",
95 ret);
96 return IRQ_NONE;
97 }
98
99 if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
100 dev_err(arizona->dev, "AIF3 underclocked\n");
101 if (val & ARIZONA_AIF3_UNDERCLOCKED_STS)
102 dev_err(arizona->dev, "AIF3 underclocked\n");
103 if (val & ARIZONA_AIF2_UNDERCLOCKED_STS)
104 dev_err(arizona->dev, "AIF1 underclocked\n");
105 if (val & ARIZONA_ISRC2_UNDERCLOCKED_STS)
106 dev_err(arizona->dev, "ISRC2 underclocked\n");
107 if (val & ARIZONA_ISRC1_UNDERCLOCKED_STS)
108 dev_err(arizona->dev, "ISRC1 underclocked\n");
109 if (val & ARIZONA_FX_UNDERCLOCKED_STS)
110 dev_err(arizona->dev, "FX underclocked\n");
111 if (val & ARIZONA_ASRC_UNDERCLOCKED_STS)
112 dev_err(arizona->dev, "ASRC underclocked\n");
113 if (val & ARIZONA_DAC_UNDERCLOCKED_STS)
114 dev_err(arizona->dev, "DAC underclocked\n");
115 if (val & ARIZONA_ADC_UNDERCLOCKED_STS)
116 dev_err(arizona->dev, "ADC underclocked\n");
117 if (val & ARIZONA_MIXER_UNDERCLOCKED_STS)
118 dev_err(arizona->dev, "Mixer underclocked\n");
119
120 return IRQ_HANDLED;
121}
122
123static irqreturn_t arizona_overclocked(int irq, void *data)
124{
125 struct arizona *arizona = data;
126 unsigned int val[2];
127 int ret;
128
129 ret = regmap_bulk_read(arizona->regmap, ARIZONA_INTERRUPT_RAW_STATUS_6,
130 &val[0], 2);
131 if (ret != 0) {
132 dev_err(arizona->dev, "Failed to read overclock status: %d\n",
133 ret);
134 return IRQ_NONE;
135 }
136
137 if (val[0] & ARIZONA_PWM_OVERCLOCKED_STS)
138 dev_err(arizona->dev, "PWM overclocked\n");
139 if (val[0] & ARIZONA_FX_CORE_OVERCLOCKED_STS)
140 dev_err(arizona->dev, "FX core overclocked\n");
141 if (val[0] & ARIZONA_DAC_SYS_OVERCLOCKED_STS)
142 dev_err(arizona->dev, "DAC SYS overclocked\n");
143 if (val[0] & ARIZONA_DAC_WARP_OVERCLOCKED_STS)
144 dev_err(arizona->dev, "DAC WARP overclocked\n");
145 if (val[0] & ARIZONA_ADC_OVERCLOCKED_STS)
146 dev_err(arizona->dev, "ADC overclocked\n");
147 if (val[0] & ARIZONA_MIXER_OVERCLOCKED_STS)
148 dev_err(arizona->dev, "Mixer overclocked\n");
149 if (val[0] & ARIZONA_AIF3_SYNC_OVERCLOCKED_STS)
150 dev_err(arizona->dev, "AIF3 overclocked\n");
151 if (val[0] & ARIZONA_AIF2_SYNC_OVERCLOCKED_STS)
152 dev_err(arizona->dev, "AIF2 overclocked\n");
153 if (val[0] & ARIZONA_AIF1_SYNC_OVERCLOCKED_STS)
154 dev_err(arizona->dev, "AIF1 overclocked\n");
155 if (val[0] & ARIZONA_PAD_CTRL_OVERCLOCKED_STS)
156 dev_err(arizona->dev, "Pad control overclocked\n");
157
158 if (val[1] & ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS)
159 dev_err(arizona->dev, "Slimbus subsystem overclocked\n");
160 if (val[1] & ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS)
161 dev_err(arizona->dev, "Slimbus async overclocked\n");
162 if (val[1] & ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS)
163 dev_err(arizona->dev, "Slimbus sync overclocked\n");
164 if (val[1] & ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS)
165 dev_err(arizona->dev, "ASRC async system overclocked\n");
166 if (val[1] & ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS)
167 dev_err(arizona->dev, "ASRC async WARP overclocked\n");
168 if (val[1] & ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS)
169 dev_err(arizona->dev, "ASRC sync system overclocked\n");
170 if (val[1] & ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS)
171 dev_err(arizona->dev, "ASRC sync WARP overclocked\n");
172 if (val[1] & ARIZONA_ADSP2_1_OVERCLOCKED_STS)
173 dev_err(arizona->dev, "DSP1 overclocked\n");
174 if (val[1] & ARIZONA_ISRC2_OVERCLOCKED_STS)
175 dev_err(arizona->dev, "ISRC2 overclocked\n");
176 if (val[1] & ARIZONA_ISRC1_OVERCLOCKED_STS)
177 dev_err(arizona->dev, "ISRC1 overclocked\n");
178
179 return IRQ_HANDLED;
180}
181
182static int arizona_wait_for_boot(struct arizona *arizona)
183{
184 unsigned int reg;
185 int ret, i;
186
187 /*
188 * We can't use an interrupt as we need to runtime resume to do so,
189 * we won't race with the interrupt handler as it'll be blocked on
190 * runtime resume.
191 */
192 for (i = 0; i < 5; i++) {
193 msleep(1);
194
195 ret = regmap_read(arizona->regmap,
196 ARIZONA_INTERRUPT_RAW_STATUS_5, &reg);
197 if (ret != 0) {
198 dev_err(arizona->dev, "Failed to read boot state: %d\n",
199 ret);
200 return ret;
201 }
202
203 if (reg & ARIZONA_BOOT_DONE_STS)
204 break;
205 }
206
207 if (reg & ARIZONA_BOOT_DONE_STS) {
208 regmap_write(arizona->regmap, ARIZONA_INTERRUPT_STATUS_5,
209 ARIZONA_BOOT_DONE_STS);
210 } else {
211 dev_err(arizona->dev, "Device boot timed out: %x\n", reg);
212 return -ETIMEDOUT;
213 }
214
215 pm_runtime_mark_last_busy(arizona->dev);
216
217 return 0;
218}
219
220#ifdef CONFIG_PM_RUNTIME
221static int arizona_runtime_resume(struct device *dev)
222{
223 struct arizona *arizona = dev_get_drvdata(dev);
224 int ret;
225
226 if (arizona->pdata.ldoena)
227 gpio_set_value_cansleep(arizona->pdata.ldoena, 1);
228
229 regcache_cache_only(arizona->regmap, false);
230
231 ret = arizona_wait_for_boot(arizona);
232 if (ret != 0)
233 return ret;
234
235 regcache_sync(arizona->regmap);
236
237 return 0;
238}
239
240static int arizona_runtime_suspend(struct device *dev)
241{
242 struct arizona *arizona = dev_get_drvdata(dev);
243
244 if (arizona->pdata.ldoena) {
245 gpio_set_value_cansleep(arizona->pdata.ldoena, 0);
246 regcache_cache_only(arizona->regmap, true);
247 regcache_mark_dirty(arizona->regmap);
248 }
249
250 return 0;
251}
252#endif
253
254const struct dev_pm_ops arizona_pm_ops = {
255 SET_RUNTIME_PM_OPS(arizona_runtime_suspend,
256 arizona_runtime_resume,
257 NULL)
258};
259EXPORT_SYMBOL_GPL(arizona_pm_ops);
260
261static struct mfd_cell early_devs[] = {
262 { .name = "arizona-ldo1" },
263};
264
265static struct mfd_cell wm5102_devs[] = {
266 { .name = "arizona-extcon" },
267 { .name = "arizona-gpio" },
268 { .name = "arizona-micsupp" },
269 { .name = "arizona-pwm" },
270 { .name = "wm5102-codec" },
271};
272
273int __devinit arizona_dev_init(struct arizona *arizona)
274{
275 struct device *dev = arizona->dev;
276 const char *type_name;
277 unsigned int reg, val;
278 int ret, i;
279
280 dev_set_drvdata(arizona->dev, arizona);
281 mutex_init(&arizona->clk_lock);
282
283 if (dev_get_platdata(arizona->dev))
284 memcpy(&arizona->pdata, dev_get_platdata(arizona->dev),
285 sizeof(arizona->pdata));
286
287 regcache_cache_only(arizona->regmap, true);
288
289 switch (arizona->type) {
290 case WM5102:
291 for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++)
292 arizona->core_supplies[i].supply
293 = wm5102_core_supplies[i];
294 arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies);
295 break;
296 default:
297 dev_err(arizona->dev, "Unknown device type %d\n",
298 arizona->type);
299 return -EINVAL;
300 }
301
302 ret = mfd_add_devices(arizona->dev, -1, early_devs,
303 ARRAY_SIZE(early_devs), NULL, 0);
304 if (ret != 0) {
305 dev_err(dev, "Failed to add early children: %d\n", ret);
306 return ret;
307 }
308
309 ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies,
310 arizona->core_supplies);
311 if (ret != 0) {
312 dev_err(dev, "Failed to request core supplies: %d\n",
313 ret);
314 goto err_early;
315 }
316
317 ret = regulator_bulk_enable(arizona->num_core_supplies,
318 arizona->core_supplies);
319 if (ret != 0) {
320 dev_err(dev, "Failed to enable core supplies: %d\n",
321 ret);
322 goto err_early;
323 }
324
325 if (arizona->pdata.reset) {
326 /* Start out with /RESET low to put the chip into reset */
327 ret = gpio_request_one(arizona->pdata.reset,
328 GPIOF_DIR_OUT | GPIOF_INIT_LOW,
329 "arizona /RESET");
330 if (ret != 0) {
331 dev_err(dev, "Failed to request /RESET: %d\n", ret);
332 goto err_enable;
333 }
334
335 gpio_set_value_cansleep(arizona->pdata.reset, 1);
336 }
337
338 if (arizona->pdata.ldoena) {
339 ret = gpio_request_one(arizona->pdata.ldoena,
340 GPIOF_DIR_OUT | GPIOF_INIT_HIGH,
341 "arizona LDOENA");
342 if (ret != 0) {
343 dev_err(dev, "Failed to request LDOENA: %d\n", ret);
344 goto err_reset;
345 }
346 }
347
348 regcache_cache_only(arizona->regmap, false);
349
350 ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, &reg);
351 if (ret != 0) {
352 dev_err(dev, "Failed to read ID register: %d\n", ret);
353 goto err_ldoena;
354 }
355
356 ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION,
357 &arizona->rev);
358 if (ret != 0) {
359 dev_err(dev, "Failed to read revision register: %d\n", ret);
360 goto err_ldoena;
361 }
362 arizona->rev &= ARIZONA_DEVICE_REVISION_MASK;
363
364 switch (reg) {
365 case 0x5102:
366 type_name = "WM5102";
367 if (arizona->type != WM5102) {
368 dev_err(arizona->dev, "WM5102 registered as %d\n",
369 arizona->type);
370 arizona->type = WM5102;
371 }
372 ret = wm5102_patch(arizona);
373 break;
374
375 default:
376 dev_err(arizona->dev, "Unknown device ID %x\n", reg);
377 goto err_ldoena;
378 }
379
380 dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A');
381
382 if (ret != 0)
383 dev_err(arizona->dev, "Failed to apply patch: %d\n", ret);
384
385 /* If we have a /RESET GPIO we'll already be reset */
386 if (!arizona->pdata.reset) {
387 ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0);
388 if (ret != 0) {
389 dev_err(dev, "Failed to reset device: %d\n", ret);
390 goto err_ldoena;
391 }
392 }
393
394 arizona_wait_for_boot(arizona);
395
396 for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) {
397 if (!arizona->pdata.gpio_defaults[i])
398 continue;
399
400 regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i,
401 arizona->pdata.gpio_defaults[i]);
402 }
403
404 pm_runtime_set_autosuspend_delay(arizona->dev, 100);
405 pm_runtime_use_autosuspend(arizona->dev);
406 pm_runtime_enable(arizona->dev);
407
408 /* Chip default */
409 if (!arizona->pdata.clk32k_src)
410 arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2;
411
412 switch (arizona->pdata.clk32k_src) {
413 case ARIZONA_32KZ_MCLK1:
414 case ARIZONA_32KZ_MCLK2:
415 regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
416 ARIZONA_CLK_32K_SRC_MASK,
417 arizona->pdata.clk32k_src - 1);
418 break;
419 case ARIZONA_32KZ_NONE:
420 regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1,
421 ARIZONA_CLK_32K_SRC_MASK, 2);
422 break;
423 default:
424 dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n",
425 arizona->pdata.clk32k_src);
426 ret = -EINVAL;
427 goto err_ldoena;
428 }
429
430 for (i = 0; i < ARIZONA_MAX_INPUT; i++) {
431 /* Default for both is 0 so noop with defaults */
432 val = arizona->pdata.dmic_ref[i]
433 << ARIZONA_IN1_DMIC_SUP_SHIFT;
434 val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT;
435
436 regmap_update_bits(arizona->regmap,
437 ARIZONA_IN1L_CONTROL + (i * 8),
438 ARIZONA_IN1_DMIC_SUP_MASK |
439 ARIZONA_IN1_MODE_MASK, val);
440 }
441
442 for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) {
443 /* Default is 0 so noop with defaults */
444 if (arizona->pdata.out_mono[i])
445 val = ARIZONA_OUT1_MONO;
446 else
447 val = 0;
448
449 regmap_update_bits(arizona->regmap,
450 ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8),
451 ARIZONA_OUT1_MONO, val);
452 }
453
454 BUILD_BUG_ON(ARIZONA_MAX_PDM_SPK > 1);
455 for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) {
456 if (arizona->pdata.spk_mute[i])
457 regmap_update_bits(arizona->regmap,
458 ARIZONA_PDM_SPK1_CTRL_1,
459 ARIZONA_SPK1_MUTE_ENDIAN_MASK |
460 ARIZONA_SPK1_MUTE_SEQ1_MASK,
461 arizona->pdata.spk_mute[i]);
462
463 if (arizona->pdata.spk_fmt[i])
464 regmap_update_bits(arizona->regmap,
465 ARIZONA_PDM_SPK1_CTRL_2,
466 ARIZONA_SPK1_FMT_MASK,
467 arizona->pdata.spk_fmt[i]);
468 }
469
470 /* Set up for interrupts */
471 ret = arizona_irq_init(arizona);
472 if (ret != 0)
473 goto err_ldoena;
474
475 arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error",
476 arizona_clkgen_err, arizona);
477 arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked",
478 arizona_overclocked, arizona);
479 arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked",
480 arizona_underclocked, arizona);
481
482 switch (arizona->type) {
483 case WM5102:
484 ret = mfd_add_devices(arizona->dev, -1, wm5102_devs,
485 ARRAY_SIZE(wm5102_devs), NULL, 0);
486 break;
487 }
488
489 if (ret != 0) {
490 dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret);
491 goto err_irq;
492 }
493
494 return 0;
495
496err_irq:
497 arizona_irq_exit(arizona);
498err_ldoena:
499 if (arizona->pdata.ldoena) {
500 gpio_set_value_cansleep(arizona->pdata.ldoena, 0);
501 gpio_free(arizona->pdata.ldoena);
502 }
503err_reset:
504 if (arizona->pdata.reset) {
505 gpio_set_value_cansleep(arizona->pdata.reset, 1);
506 gpio_free(arizona->pdata.reset);
507 }
508err_enable:
509 regulator_bulk_disable(ARRAY_SIZE(arizona->core_supplies),
510 arizona->core_supplies);
511err_early:
512 mfd_remove_devices(dev);
513 return ret;
514}
515EXPORT_SYMBOL_GPL(arizona_dev_init);
516
517int __devexit arizona_dev_exit(struct arizona *arizona)
518{
519 mfd_remove_devices(arizona->dev);
520 arizona_free_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, arizona);
521 arizona_free_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, arizona);
522 arizona_free_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, arizona);
523 pm_runtime_disable(arizona->dev);
524 arizona_irq_exit(arizona);
525 return 0;
526}
527EXPORT_SYMBOL_GPL(arizona_dev_exit);
diff --git a/drivers/mfd/arizona-i2c.c b/drivers/mfd/arizona-i2c.c
new file mode 100644
index 000000000000..75fb110105e1
--- /dev/null
+++ b/drivers/mfd/arizona-i2c.c
@@ -0,0 +1,89 @@
1/*
2 * Arizona-i2c.c -- Arizona I2C bus interface
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/i2c.h>
15#include <linux/module.h>
16#include <linux/pm_runtime.h>
17#include <linux/regmap.h>
18#include <linux/regulator/consumer.h>
19#include <linux/slab.h>
20
21#include <linux/mfd/arizona/core.h>
22
23#include "arizona.h"
24
25static __devinit int arizona_i2c_probe(struct i2c_client *i2c,
26 const struct i2c_device_id *id)
27{
28 struct arizona *arizona;
29 const struct regmap_config *regmap_config;
30 int ret;
31
32 switch (id->driver_data) {
33 case WM5102:
34 regmap_config = &wm5102_i2c_regmap;
35 break;
36 default:
37 dev_err(&i2c->dev, "Unknown device type %ld\n",
38 id->driver_data);
39 return -EINVAL;
40 }
41
42 arizona = devm_kzalloc(&i2c->dev, sizeof(*arizona), GFP_KERNEL);
43 if (arizona == NULL)
44 return -ENOMEM;
45
46 arizona->regmap = devm_regmap_init_i2c(i2c, regmap_config);
47 if (IS_ERR(arizona->regmap)) {
48 ret = PTR_ERR(arizona->regmap);
49 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
50 ret);
51 return ret;
52 }
53
54 arizona->type = id->driver_data;
55 arizona->dev = &i2c->dev;
56 arizona->irq = i2c->irq;
57
58 return arizona_dev_init(arizona);
59}
60
61static int __devexit arizona_i2c_remove(struct i2c_client *i2c)
62{
63 struct arizona *arizona = dev_get_drvdata(&i2c->dev);
64 arizona_dev_exit(arizona);
65 return 0;
66}
67
68static const struct i2c_device_id arizona_i2c_id[] = {
69 { "wm5102", WM5102 },
70 { }
71};
72MODULE_DEVICE_TABLE(i2c, arizona_i2c_id);
73
74static struct i2c_driver arizona_i2c_driver = {
75 .driver = {
76 .name = "arizona",
77 .owner = THIS_MODULE,
78 .pm = &arizona_pm_ops,
79 },
80 .probe = arizona_i2c_probe,
81 .remove = __devexit_p(arizona_i2c_remove),
82 .id_table = arizona_i2c_id,
83};
84
85module_i2c_driver(arizona_i2c_driver);
86
87MODULE_DESCRIPTION("Arizona I2C bus interface");
88MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
89MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/arizona-irq.c b/drivers/mfd/arizona-irq.c
new file mode 100644
index 000000000000..4c7894046a39
--- /dev/null
+++ b/drivers/mfd/arizona-irq.c
@@ -0,0 +1,267 @@
1/*
2 * Arizona interrupt support
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/delay.h>
14#include <linux/gpio.h>
15#include <linux/interrupt.h>
16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/module.h>
19#include <linux/pm_runtime.h>
20#include <linux/regmap.h>
21#include <linux/regulator/consumer.h>
22#include <linux/slab.h>
23
24#include <linux/mfd/arizona/core.h>
25#include <linux/mfd/arizona/registers.h>
26
27#include "arizona.h"
28
29static int arizona_map_irq(struct arizona *arizona, int irq)
30{
31 int ret;
32
33 ret = regmap_irq_get_virq(arizona->aod_irq_chip, irq);
34 if (ret < 0)
35 ret = regmap_irq_get_virq(arizona->irq_chip, irq);
36
37 return ret;
38}
39
40int arizona_request_irq(struct arizona *arizona, int irq, char *name,
41 irq_handler_t handler, void *data)
42{
43 irq = arizona_map_irq(arizona, irq);
44 if (irq < 0)
45 return irq;
46
47 return request_threaded_irq(irq, NULL, handler, IRQF_ONESHOT,
48 name, data);
49}
50EXPORT_SYMBOL_GPL(arizona_request_irq);
51
52void arizona_free_irq(struct arizona *arizona, int irq, void *data)
53{
54 irq = arizona_map_irq(arizona, irq);
55 if (irq < 0)
56 return;
57
58 free_irq(irq, data);
59}
60EXPORT_SYMBOL_GPL(arizona_free_irq);
61
62int arizona_set_irq_wake(struct arizona *arizona, int irq, int on)
63{
64 irq = arizona_map_irq(arizona, irq);
65 if (irq < 0)
66 return irq;
67
68 return irq_set_irq_wake(irq, on);
69}
70EXPORT_SYMBOL_GPL(arizona_set_irq_wake);
71
72static irqreturn_t arizona_boot_done(int irq, void *data)
73{
74 struct arizona *arizona = data;
75
76 dev_dbg(arizona->dev, "Boot done\n");
77
78 return IRQ_HANDLED;
79}
80
81static irqreturn_t arizona_ctrlif_err(int irq, void *data)
82{
83 struct arizona *arizona = data;
84
85 /*
86 * For pretty much all potential sources a register cache sync
87 * won't help, we've just got a software bug somewhere.
88 */
89 dev_err(arizona->dev, "Control interface error\n");
90
91 return IRQ_HANDLED;
92}
93
94static irqreturn_t arizona_irq_thread(int irq, void *data)
95{
96 struct arizona *arizona = data;
97 int i, ret;
98
99 ret = pm_runtime_get_sync(arizona->dev);
100 if (ret < 0) {
101 dev_err(arizona->dev, "Failed to resume device: %d\n", ret);
102 return IRQ_NONE;
103 }
104
105 /* Check both domains */
106 for (i = 0; i < 2; i++)
107 handle_nested_irq(irq_find_mapping(arizona->virq, i));
108
109 pm_runtime_mark_last_busy(arizona->dev);
110 pm_runtime_put_autosuspend(arizona->dev);
111
112 return IRQ_HANDLED;
113}
114
115static void arizona_irq_enable(struct irq_data *data)
116{
117}
118
119static void arizona_irq_disable(struct irq_data *data)
120{
121}
122
123static struct irq_chip arizona_irq_chip = {
124 .name = "arizona",
125 .irq_disable = arizona_irq_disable,
126 .irq_enable = arizona_irq_enable,
127};
128
129static int arizona_irq_map(struct irq_domain *h, unsigned int virq,
130 irq_hw_number_t hw)
131{
132 struct regmap_irq_chip_data *data = h->host_data;
133
134 irq_set_chip_data(virq, data);
135 irq_set_chip_and_handler(virq, &arizona_irq_chip, handle_edge_irq);
136 irq_set_nested_thread(virq, 1);
137
138 /* ARM needs us to explicitly flag the IRQ as valid
139 * and will set them noprobe when we do so. */
140#ifdef CONFIG_ARM
141 set_irq_flags(virq, IRQF_VALID);
142#else
143 irq_set_noprobe(virq);
144#endif
145
146 return 0;
147}
148
149static struct irq_domain_ops arizona_domain_ops = {
150 .map = arizona_irq_map,
151 .xlate = irq_domain_xlate_twocell,
152};
153
154int arizona_irq_init(struct arizona *arizona)
155{
156 int flags = IRQF_ONESHOT;
157 int ret, i;
158 const struct regmap_irq_chip *aod, *irq;
159
160 switch (arizona->type) {
161 case WM5102:
162 aod = &wm5102_aod;
163 irq = &wm5102_irq;
164 break;
165 default:
166 BUG_ON("Unknown Arizona class device" == NULL);
167 return -EINVAL;
168 }
169
170 if (arizona->pdata.irq_active_high) {
171 ret = regmap_update_bits(arizona->regmap, ARIZONA_IRQ_CTRL_1,
172 ARIZONA_IRQ_POL, 0);
173 if (ret != 0) {
174 dev_err(arizona->dev, "Couldn't set IRQ polarity: %d\n",
175 ret);
176 goto err;
177 }
178
179 flags |= IRQF_TRIGGER_HIGH;
180 } else {
181 flags |= IRQF_TRIGGER_LOW;
182 }
183
184 /* Allocate a virtual IRQ domain to distribute to the regmap domains */
185 arizona->virq = irq_domain_add_linear(NULL, 2, &arizona_domain_ops,
186 arizona);
187 if (!arizona->virq) {
188 ret = -EINVAL;
189 goto err;
190 }
191
192 ret = regmap_add_irq_chip(arizona->regmap,
193 irq_create_mapping(arizona->virq, 0),
194 IRQF_ONESHOT, -1, aod,
195 &arizona->aod_irq_chip);
196 if (ret != 0) {
197 dev_err(arizona->dev, "Failed to add AOD IRQs: %d\n", ret);
198 goto err_domain;
199 }
200
201 ret = regmap_add_irq_chip(arizona->regmap,
202 irq_create_mapping(arizona->virq, 1),
203 IRQF_ONESHOT, -1, irq,
204 &arizona->irq_chip);
205 if (ret != 0) {
206 dev_err(arizona->dev, "Failed to add AOD IRQs: %d\n", ret);
207 goto err_aod;
208 }
209
210 /* Make sure the boot done IRQ is unmasked for resumes */
211 i = arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE);
212 ret = request_threaded_irq(i, NULL, arizona_boot_done, IRQF_ONESHOT,
213 "Boot done", arizona);
214 if (ret != 0) {
215 dev_err(arizona->dev, "Failed to request boot done %d: %d\n",
216 arizona->irq, ret);
217 goto err_boot_done;
218 }
219
220 /* Handle control interface errors in the core */
221 i = arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR);
222 ret = request_threaded_irq(i, NULL, arizona_ctrlif_err, IRQF_ONESHOT,
223 "Control interface error", arizona);
224 if (ret != 0) {
225 dev_err(arizona->dev, "Failed to request boot done %d: %d\n",
226 arizona->irq, ret);
227 goto err_ctrlif;
228 }
229
230 ret = request_threaded_irq(arizona->irq, NULL, arizona_irq_thread,
231 flags, "arizona", arizona);
232
233 if (ret != 0) {
234 dev_err(arizona->dev, "Failed to request IRQ %d: %d\n",
235 arizona->irq, ret);
236 goto err_main_irq;
237 }
238
239 return 0;
240
241err_main_irq:
242 free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR), arizona);
243err_ctrlif:
244 free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE), arizona);
245err_boot_done:
246 regmap_del_irq_chip(irq_create_mapping(arizona->virq, 1),
247 arizona->irq_chip);
248err_aod:
249 regmap_del_irq_chip(irq_create_mapping(arizona->virq, 0),
250 arizona->aod_irq_chip);
251err_domain:
252err:
253 return ret;
254}
255
256int arizona_irq_exit(struct arizona *arizona)
257{
258 free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_CTRLIF_ERR), arizona);
259 free_irq(arizona_map_irq(arizona, ARIZONA_IRQ_BOOT_DONE), arizona);
260 regmap_del_irq_chip(irq_create_mapping(arizona->virq, 1),
261 arizona->irq_chip);
262 regmap_del_irq_chip(irq_create_mapping(arizona->virq, 0),
263 arizona->aod_irq_chip);
264 free_irq(arizona->irq, arizona);
265
266 return 0;
267}
diff --git a/drivers/mfd/arizona-spi.c b/drivers/mfd/arizona-spi.c
new file mode 100644
index 000000000000..f4bedaf875e6
--- /dev/null
+++ b/drivers/mfd/arizona-spi.c
@@ -0,0 +1,91 @@
1/*
2 * arizona-spi.c -- Arizona SPI bus interface
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/module.h>
15#include <linux/pm_runtime.h>
16#include <linux/regmap.h>
17#include <linux/regulator/consumer.h>
18#include <linux/slab.h>
19#include <linux/spi/spi.h>
20
21#include <linux/mfd/arizona/core.h>
22
23#include "arizona.h"
24
25static int __devinit arizona_spi_probe(struct spi_device *spi)
26{
27 const struct spi_device_id *id = spi_get_device_id(spi);
28 struct arizona *arizona;
29 const struct regmap_config *regmap_config;
30 int ret;
31
32 switch (id->driver_data) {
33#ifdef CONFIG_MFD_WM5102
34 case WM5102:
35 regmap_config = &wm5102_spi_regmap;
36 break;
37#endif
38 default:
39 dev_err(&spi->dev, "Unknown device type %ld\n",
40 id->driver_data);
41 return -EINVAL;
42 }
43
44 arizona = devm_kzalloc(&spi->dev, sizeof(*arizona), GFP_KERNEL);
45 if (arizona == NULL)
46 return -ENOMEM;
47
48 arizona->regmap = devm_regmap_init_spi(spi, regmap_config);
49 if (IS_ERR(arizona->regmap)) {
50 ret = PTR_ERR(arizona->regmap);
51 dev_err(&spi->dev, "Failed to allocate register map: %d\n",
52 ret);
53 return ret;
54 }
55
56 arizona->type = id->driver_data;
57 arizona->dev = &spi->dev;
58 arizona->irq = spi->irq;
59
60 return arizona_dev_init(arizona);
61}
62
63static int __devexit arizona_spi_remove(struct spi_device *spi)
64{
65 struct arizona *arizona = dev_get_drvdata(&spi->dev);
66 arizona_dev_exit(arizona);
67 return 0;
68}
69
70static const struct spi_device_id arizona_spi_ids[] = {
71 { "wm5102", WM5102 },
72 { },
73};
74MODULE_DEVICE_TABLE(spi, arizona_spi_ids);
75
76static struct spi_driver arizona_spi_driver = {
77 .driver = {
78 .name = "arizona",
79 .owner = THIS_MODULE,
80 .pm = &arizona_pm_ops,
81 },
82 .probe = arizona_spi_probe,
83 .remove = __devexit_p(arizona_spi_remove),
84 .id_table = arizona_spi_ids,
85};
86
87module_spi_driver(arizona_spi_driver);
88
89MODULE_DESCRIPTION("Arizona SPI bus interface");
90MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
91MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/arizona.h b/drivers/mfd/arizona.h
new file mode 100644
index 000000000000..1c9f333a9c17
--- /dev/null
+++ b/drivers/mfd/arizona.h
@@ -0,0 +1,33 @@
1/*
2 * wm5102.h -- WM5102 MFD internals
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _WM5102_H
14#define _WM5102_H
15
16#include <linux/regmap.h>
17#include <linux/pm.h>
18
19struct wm_arizona;
20
21extern const struct regmap_config wm5102_i2c_regmap;
22extern const struct regmap_config wm5102_spi_regmap;
23extern const struct dev_pm_ops arizona_pm_ops;
24
25extern const struct regmap_irq_chip wm5102_aod;
26extern const struct regmap_irq_chip wm5102_irq;
27
28int arizona_dev_init(struct arizona *arizona);
29int arizona_dev_exit(struct arizona *arizona);
30int arizona_irq_init(struct arizona *arizona);
31int arizona_irq_exit(struct arizona *arizona);
32
33#endif
diff --git a/drivers/mfd/wm5102-tables.c b/drivers/mfd/wm5102-tables.c
new file mode 100644
index 000000000000..9b38b6b412dc
--- /dev/null
+++ b/drivers/mfd/wm5102-tables.c
@@ -0,0 +1,2399 @@
1/*
2 * wm5102-tables.c -- WM5102 data tables
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14
15#include <linux/mfd/arizona/core.h>
16#include <linux/mfd/arizona/registers.h>
17
18#include "arizona.h"
19
20#define WM5102_NUM_AOD_ISR 2
21#define WM5102_NUM_ISR 5
22
23static const struct reg_default wm5102_reva_patch[] = {
24 { 0x80, 0x0003 },
25 { 0x221, 0x0090 },
26 { 0x211, 0x0014 },
27 { 0x212, 0x0000 },
28 { 0x214, 0x000C },
29 { 0x171, 0x0002 },
30 { 0x171, 0x0000 },
31 { 0x461, 0x8000 },
32 { 0x463, 0x50F0 },
33 { 0x465, 0x4820 },
34 { 0x467, 0x4040 },
35 { 0x469, 0x3940 },
36 { 0x46B, 0x3310 },
37 { 0x46D, 0x2D80 },
38 { 0x46F, 0x2890 },
39 { 0x471, 0x1990 },
40 { 0x473, 0x1450 },
41 { 0x475, 0x1020 },
42 { 0x477, 0x0CD0 },
43 { 0x479, 0x0A30 },
44 { 0x47B, 0x0810 },
45 { 0x47D, 0x0510 },
46 { 0x500, 0x000D },
47 { 0x507, 0x1820 },
48 { 0x508, 0x1820 },
49 { 0x540, 0x000D },
50 { 0x547, 0x1820 },
51 { 0x548, 0x1820 },
52 { 0x580, 0x000D },
53 { 0x587, 0x1820 },
54 { 0x588, 0x1820 },
55 { 0x101, 0x8140 },
56 { 0x3000, 0x2225 },
57 { 0x3001, 0x3a03 },
58 { 0x3002, 0x0225 },
59 { 0x3003, 0x0801 },
60 { 0x3004, 0x6249 },
61 { 0x3005, 0x0c04 },
62 { 0x3006, 0x0225 },
63 { 0x3007, 0x5901 },
64 { 0x3008, 0xe249 },
65 { 0x3009, 0x030d },
66 { 0x300a, 0x0249 },
67 { 0x300b, 0x2c01 },
68 { 0x300c, 0xe249 },
69 { 0x300d, 0x4342 },
70 { 0x300e, 0xe249 },
71 { 0x300f, 0x73c0 },
72 { 0x3010, 0x4249 },
73 { 0x3011, 0x0c00 },
74 { 0x3012, 0x0225 },
75 { 0x3013, 0x1f01 },
76 { 0x3014, 0x0225 },
77 { 0x3015, 0x1e01 },
78 { 0x3016, 0x0225 },
79 { 0x3017, 0xfa00 },
80 { 0x3018, 0x0000 },
81 { 0x3019, 0xf000 },
82 { 0x301a, 0x0000 },
83 { 0x301b, 0xf000 },
84 { 0x301c, 0x0000 },
85 { 0x301d, 0xf000 },
86 { 0x301e, 0x0000 },
87 { 0x301f, 0xf000 },
88 { 0x3020, 0x0000 },
89 { 0x3021, 0xf000 },
90 { 0x3022, 0x0000 },
91 { 0x3023, 0xf000 },
92 { 0x3024, 0x0000 },
93 { 0x3025, 0xf000 },
94 { 0x3026, 0x0000 },
95 { 0x3027, 0xf000 },
96 { 0x3028, 0x0000 },
97 { 0x3029, 0xf000 },
98 { 0x302a, 0x0000 },
99 { 0x302b, 0xf000 },
100 { 0x302c, 0x0000 },
101 { 0x302d, 0xf000 },
102 { 0x302e, 0x0000 },
103 { 0x302f, 0xf000 },
104 { 0x3030, 0x0225 },
105 { 0x3031, 0x1a01 },
106 { 0x3032, 0x0225 },
107 { 0x3033, 0x1e00 },
108 { 0x3034, 0x0225 },
109 { 0x3035, 0x1f00 },
110 { 0x3036, 0x6225 },
111 { 0x3037, 0xf800 },
112 { 0x3038, 0x0000 },
113 { 0x3039, 0xf000 },
114 { 0x303a, 0x0000 },
115 { 0x303b, 0xf000 },
116 { 0x303c, 0x0000 },
117 { 0x303d, 0xf000 },
118 { 0x303e, 0x0000 },
119 { 0x303f, 0xf000 },
120 { 0x3040, 0x2226 },
121 { 0x3041, 0x3a03 },
122 { 0x3042, 0x0226 },
123 { 0x3043, 0x0801 },
124 { 0x3044, 0x6249 },
125 { 0x3045, 0x0c06 },
126 { 0x3046, 0x0226 },
127 { 0x3047, 0x5901 },
128 { 0x3048, 0xe249 },
129 { 0x3049, 0x030d },
130 { 0x304a, 0x0249 },
131 { 0x304b, 0x2c01 },
132 { 0x304c, 0xe249 },
133 { 0x304d, 0x4342 },
134 { 0x304e, 0xe249 },
135 { 0x304f, 0x73c0 },
136 { 0x3050, 0x4249 },
137 { 0x3051, 0x0c00 },
138 { 0x3052, 0x0226 },
139 { 0x3053, 0x1f01 },
140 { 0x3054, 0x0226 },
141 { 0x3055, 0x1e01 },
142 { 0x3056, 0x0226 },
143 { 0x3057, 0xfa00 },
144 { 0x3058, 0x0000 },
145 { 0x3059, 0xf000 },
146 { 0x305a, 0x0000 },
147 { 0x305b, 0xf000 },
148 { 0x305c, 0x0000 },
149 { 0x305d, 0xf000 },
150 { 0x305e, 0x0000 },
151 { 0x305f, 0xf000 },
152 { 0x3060, 0x0000 },
153 { 0x3061, 0xf000 },
154 { 0x3062, 0x0000 },
155 { 0x3063, 0xf000 },
156 { 0x3064, 0x0000 },
157 { 0x3065, 0xf000 },
158 { 0x3066, 0x0000 },
159 { 0x3067, 0xf000 },
160 { 0x3068, 0x0000 },
161 { 0x3069, 0xf000 },
162 { 0x306a, 0x0000 },
163 { 0x306b, 0xf000 },
164 { 0x306c, 0x0000 },
165 { 0x306d, 0xf000 },
166 { 0x306e, 0x0000 },
167 { 0x306f, 0xf000 },
168 { 0x3070, 0x0226 },
169 { 0x3071, 0x1a01 },
170 { 0x3072, 0x0226 },
171 { 0x3073, 0x1e00 },
172 { 0x3074, 0x0226 },
173 { 0x3075, 0x1f00 },
174 { 0x3076, 0x6226 },
175 { 0x3077, 0xf800 },
176 { 0x3078, 0x0000 },
177 { 0x3079, 0xf000 },
178 { 0x307a, 0x0000 },
179 { 0x307b, 0xf000 },
180 { 0x307c, 0x0000 },
181 { 0x307d, 0xf000 },
182 { 0x307e, 0x0000 },
183 { 0x307f, 0xf000 },
184 { 0x3080, 0x2227 },
185 { 0x3081, 0x3a03 },
186 { 0x3082, 0x0227 },
187 { 0x3083, 0x0801 },
188 { 0x3084, 0x6255 },
189 { 0x3085, 0x0c04 },
190 { 0x3086, 0x0227 },
191 { 0x3087, 0x5901 },
192 { 0x3088, 0xe255 },
193 { 0x3089, 0x030d },
194 { 0x308a, 0x0255 },
195 { 0x308b, 0x2c01 },
196 { 0x308c, 0xe255 },
197 { 0x308d, 0x4342 },
198 { 0x308e, 0xe255 },
199 { 0x308f, 0x73c0 },
200 { 0x3090, 0x4255 },
201 { 0x3091, 0x0c00 },
202 { 0x3092, 0x0227 },
203 { 0x3093, 0x1f01 },
204 { 0x3094, 0x0227 },
205 { 0x3095, 0x1e01 },
206 { 0x3096, 0x0227 },
207 { 0x3097, 0xfa00 },
208 { 0x3098, 0x0000 },
209 { 0x3099, 0xf000 },
210 { 0x309a, 0x0000 },
211 { 0x309b, 0xf000 },
212 { 0x309c, 0x0000 },
213 { 0x309d, 0xf000 },
214 { 0x309e, 0x0000 },
215 { 0x309f, 0xf000 },
216 { 0x30a0, 0x0000 },
217 { 0x30a1, 0xf000 },
218 { 0x30a2, 0x0000 },
219 { 0x30a3, 0xf000 },
220 { 0x30a4, 0x0000 },
221 { 0x30a5, 0xf000 },
222 { 0x30a6, 0x0000 },
223 { 0x30a7, 0xf000 },
224 { 0x30a8, 0x0000 },
225 { 0x30a9, 0xf000 },
226 { 0x30aa, 0x0000 },
227 { 0x30ab, 0xf000 },
228 { 0x30ac, 0x0000 },
229 { 0x30ad, 0xf000 },
230 { 0x30ae, 0x0000 },
231 { 0x30af, 0xf000 },
232 { 0x30b0, 0x0227 },
233 { 0x30b1, 0x1a01 },
234 { 0x30b2, 0x0227 },
235 { 0x30b3, 0x1e00 },
236 { 0x30b4, 0x0227 },
237 { 0x30b5, 0x1f00 },
238 { 0x30b6, 0x6227 },
239 { 0x30b7, 0xf800 },
240 { 0x30b8, 0x0000 },
241 { 0x30b9, 0xf000 },
242 { 0x30ba, 0x0000 },
243 { 0x30bb, 0xf000 },
244 { 0x30bc, 0x0000 },
245 { 0x30bd, 0xf000 },
246 { 0x30be, 0x0000 },
247 { 0x30bf, 0xf000 },
248 { 0x30c0, 0x2228 },
249 { 0x30c1, 0x3a03 },
250 { 0x30c2, 0x0228 },
251 { 0x30c3, 0x0801 },
252 { 0x30c4, 0x6255 },
253 { 0x30c5, 0x0c06 },
254 { 0x30c6, 0x0228 },
255 { 0x30c7, 0x5901 },
256 { 0x30c8, 0xe255 },
257 { 0x30c9, 0x030d },
258 { 0x30ca, 0x0255 },
259 { 0x30cb, 0x2c01 },
260 { 0x30cc, 0xe255 },
261 { 0x30cd, 0x4342 },
262 { 0x30ce, 0xe255 },
263 { 0x30cf, 0x73c0 },
264 { 0x30d0, 0x4255 },
265 { 0x30d1, 0x0c00 },
266 { 0x30d2, 0x0228 },
267 { 0x30d3, 0x1f01 },
268 { 0x30d4, 0x0228 },
269 { 0x30d5, 0x1e01 },
270 { 0x30d6, 0x0228 },
271 { 0x30d7, 0xfa00 },
272 { 0x30d8, 0x0000 },
273 { 0x30d9, 0xf000 },
274 { 0x30da, 0x0000 },
275 { 0x30db, 0xf000 },
276 { 0x30dc, 0x0000 },
277 { 0x30dd, 0xf000 },
278 { 0x30de, 0x0000 },
279 { 0x30df, 0xf000 },
280 { 0x30e0, 0x0000 },
281 { 0x30e1, 0xf000 },
282 { 0x30e2, 0x0000 },
283 { 0x30e3, 0xf000 },
284 { 0x30e4, 0x0000 },
285 { 0x30e5, 0xf000 },
286 { 0x30e6, 0x0000 },
287 { 0x30e7, 0xf000 },
288 { 0x30e8, 0x0000 },
289 { 0x30e9, 0xf000 },
290 { 0x30ea, 0x0000 },
291 { 0x30eb, 0xf000 },
292 { 0x30ec, 0x0000 },
293 { 0x30ed, 0xf000 },
294 { 0x30ee, 0x0000 },
295 { 0x30ef, 0xf000 },
296 { 0x30f0, 0x0228 },
297 { 0x30f1, 0x1a01 },
298 { 0x30f2, 0x0228 },
299 { 0x30f3, 0x1e00 },
300 { 0x30f4, 0x0228 },
301 { 0x30f5, 0x1f00 },
302 { 0x30f6, 0x6228 },
303 { 0x30f7, 0xf800 },
304 { 0x30f8, 0x0000 },
305 { 0x30f9, 0xf000 },
306 { 0x30fa, 0x0000 },
307 { 0x30fb, 0xf000 },
308 { 0x30fc, 0x0000 },
309 { 0x30fd, 0xf000 },
310 { 0x30fe, 0x0000 },
311 { 0x30ff, 0xf000 },
312 { 0x3100, 0x222b },
313 { 0x3101, 0x3a03 },
314 { 0x3102, 0x222b },
315 { 0x3103, 0x5803 },
316 { 0x3104, 0xe26f },
317 { 0x3105, 0x030d },
318 { 0x3106, 0x626f },
319 { 0x3107, 0x2c01 },
320 { 0x3108, 0xe26f },
321 { 0x3109, 0x4342 },
322 { 0x310a, 0xe26f },
323 { 0x310b, 0x73c0 },
324 { 0x310c, 0x026f },
325 { 0x310d, 0x0c00 },
326 { 0x310e, 0x022b },
327 { 0x310f, 0x1f01 },
328 { 0x3110, 0x022b },
329 { 0x3111, 0x1e01 },
330 { 0x3112, 0x022b },
331 { 0x3113, 0xfa00 },
332 { 0x3114, 0x0000 },
333 { 0x3115, 0xf000 },
334 { 0x3116, 0x0000 },
335 { 0x3117, 0xf000 },
336 { 0x3118, 0x0000 },
337 { 0x3119, 0xf000 },
338 { 0x311a, 0x0000 },
339 { 0x311b, 0xf000 },
340 { 0x311c, 0x0000 },
341 { 0x311d, 0xf000 },
342 { 0x311e, 0x0000 },
343 { 0x311f, 0xf000 },
344 { 0x3120, 0x022b },
345 { 0x3121, 0x0a01 },
346 { 0x3122, 0x022b },
347 { 0x3123, 0x1e00 },
348 { 0x3124, 0x022b },
349 { 0x3125, 0x1f00 },
350 { 0x3126, 0x622b },
351 { 0x3127, 0xf800 },
352 { 0x3128, 0x0000 },
353 { 0x3129, 0xf000 },
354 { 0x312a, 0x0000 },
355 { 0x312b, 0xf000 },
356 { 0x312c, 0x0000 },
357 { 0x312d, 0xf000 },
358 { 0x312e, 0x0000 },
359 { 0x312f, 0xf000 },
360 { 0x3130, 0x0000 },
361 { 0x3131, 0xf000 },
362 { 0x3132, 0x0000 },
363 { 0x3133, 0xf000 },
364 { 0x3134, 0x0000 },
365 { 0x3135, 0xf000 },
366 { 0x3136, 0x0000 },
367 { 0x3137, 0xf000 },
368 { 0x3138, 0x0000 },
369 { 0x3139, 0xf000 },
370 { 0x313a, 0x0000 },
371 { 0x313b, 0xf000 },
372 { 0x313c, 0x0000 },
373 { 0x313d, 0xf000 },
374 { 0x313e, 0x0000 },
375 { 0x313f, 0xf000 },
376 { 0x3140, 0x0000 },
377 { 0x3141, 0xf000 },
378 { 0x3142, 0x0000 },
379 { 0x3143, 0xf000 },
380 { 0x3144, 0x0000 },
381 { 0x3145, 0xf000 },
382 { 0x3146, 0x0000 },
383 { 0x3147, 0xf000 },
384 { 0x3148, 0x0000 },
385 { 0x3149, 0xf000 },
386 { 0x314a, 0x0000 },
387 { 0x314b, 0xf000 },
388 { 0x314c, 0x0000 },
389 { 0x314d, 0xf000 },
390 { 0x314e, 0x0000 },
391 { 0x314f, 0xf000 },
392 { 0x3150, 0x0000 },
393 { 0x3151, 0xf000 },
394 { 0x3152, 0x0000 },
395 { 0x3153, 0xf000 },
396 { 0x3154, 0x0000 },
397 { 0x3155, 0xf000 },
398 { 0x3156, 0x0000 },
399 { 0x3157, 0xf000 },
400 { 0x3158, 0x0000 },
401 { 0x3159, 0xf000 },
402 { 0x315a, 0x0000 },
403 { 0x315b, 0xf000 },
404 { 0x315c, 0x0000 },
405 { 0x315d, 0xf000 },
406 { 0x315e, 0x0000 },
407 { 0x315f, 0xf000 },
408 { 0x3160, 0x0000 },
409 { 0x3161, 0xf000 },
410 { 0x3162, 0x0000 },
411 { 0x3163, 0xf000 },
412 { 0x3164, 0x0000 },
413 { 0x3165, 0xf000 },
414 { 0x3166, 0x0000 },
415 { 0x3167, 0xf000 },
416 { 0x3168, 0x0000 },
417 { 0x3169, 0xf000 },
418 { 0x316a, 0x0000 },
419 { 0x316b, 0xf000 },
420 { 0x316c, 0x0000 },
421 { 0x316d, 0xf000 },
422 { 0x316e, 0x0000 },
423 { 0x316f, 0xf000 },
424 { 0x3170, 0x0000 },
425 { 0x3171, 0xf000 },
426 { 0x3172, 0x0000 },
427 { 0x3173, 0xf000 },
428 { 0x3174, 0x0000 },
429 { 0x3175, 0xf000 },
430 { 0x3176, 0x0000 },
431 { 0x3177, 0xf000 },
432 { 0x3178, 0x0000 },
433 { 0x3179, 0xf000 },
434 { 0x317a, 0x0000 },
435 { 0x317b, 0xf000 },
436 { 0x317c, 0x0000 },
437 { 0x317d, 0xf000 },
438 { 0x317e, 0x0000 },
439 { 0x317f, 0xf000 },
440 { 0x3180, 0x2001 },
441 { 0x3181, 0xf101 },
442 { 0x3182, 0x0000 },
443 { 0x3183, 0xf000 },
444 { 0x3184, 0x0000 },
445 { 0x3185, 0xf000 },
446 { 0x3186, 0x0000 },
447 { 0x3187, 0xf000 },
448 { 0x3188, 0x0000 },
449 { 0x3189, 0xf000 },
450 { 0x318a, 0x0000 },
451 { 0x318b, 0xf000 },
452 { 0x318c, 0x0000 },
453 { 0x318d, 0xf000 },
454 { 0x318e, 0x0000 },
455 { 0x318f, 0xf000 },
456 { 0x3190, 0x0000 },
457 { 0x3191, 0xf000 },
458 { 0x3192, 0x0000 },
459 { 0x3193, 0xf000 },
460 { 0x3194, 0x0000 },
461 { 0x3195, 0xf000 },
462 { 0x3196, 0x0000 },
463 { 0x3197, 0xf000 },
464 { 0x3198, 0x0000 },
465 { 0x3199, 0xf000 },
466 { 0x319a, 0x0000 },
467 { 0x319b, 0xf000 },
468 { 0x319c, 0x0000 },
469 { 0x319d, 0xf000 },
470 { 0x319e, 0x0000 },
471 { 0x319f, 0xf000 },
472 { 0x31a0, 0x0000 },
473 { 0x31a1, 0xf000 },
474 { 0x31a2, 0x0000 },
475 { 0x31a3, 0xf000 },
476 { 0x31a4, 0x0000 },
477 { 0x31a5, 0xf000 },
478 { 0x31a6, 0x0000 },
479 { 0x31a7, 0xf000 },
480 { 0x31a8, 0x0000 },
481 { 0x31a9, 0xf000 },
482 { 0x31aa, 0x0000 },
483 { 0x31ab, 0xf000 },
484 { 0x31ac, 0x0000 },
485 { 0x31ad, 0xf000 },
486 { 0x31ae, 0x0000 },
487 { 0x31af, 0xf000 },
488 { 0x31b0, 0x0000 },
489 { 0x31b1, 0xf000 },
490 { 0x31b2, 0x0000 },
491 { 0x31b3, 0xf000 },
492 { 0x31b4, 0x0000 },
493 { 0x31b5, 0xf000 },
494 { 0x31b6, 0x0000 },
495 { 0x31b7, 0xf000 },
496 { 0x31b8, 0x0000 },
497 { 0x31b9, 0xf000 },
498 { 0x31ba, 0x0000 },
499 { 0x31bb, 0xf000 },
500 { 0x31bc, 0x0000 },
501 { 0x31bd, 0xf000 },
502 { 0x31be, 0x0000 },
503 { 0x31bf, 0xf000 },
504 { 0x31c0, 0x0000 },
505 { 0x31c1, 0xf000 },
506 { 0x31c2, 0x0000 },
507 { 0x31c3, 0xf000 },
508 { 0x31c4, 0x0000 },
509 { 0x31c5, 0xf000 },
510 { 0x31c6, 0x0000 },
511 { 0x31c7, 0xf000 },
512 { 0x31c8, 0x0000 },
513 { 0x31c9, 0xf000 },
514 { 0x31ca, 0x0000 },
515 { 0x31cb, 0xf000 },
516 { 0x31cc, 0x0000 },
517 { 0x31cd, 0xf000 },
518 { 0x31ce, 0x0000 },
519 { 0x31cf, 0xf000 },
520 { 0x31d0, 0x0000 },
521 { 0x31d1, 0xf000 },
522 { 0x31d2, 0x0000 },
523 { 0x31d3, 0xf000 },
524 { 0x31d4, 0x0000 },
525 { 0x31d5, 0xf000 },
526 { 0x31d6, 0x0000 },
527 { 0x31d7, 0xf000 },
528 { 0x31d8, 0x0000 },
529 { 0x31d9, 0xf000 },
530 { 0x31da, 0x0000 },
531 { 0x31db, 0xf000 },
532 { 0x31dc, 0x0000 },
533 { 0x31dd, 0xf000 },
534 { 0x31de, 0x0000 },
535 { 0x31df, 0xf000 },
536 { 0x31e0, 0x0000 },
537 { 0x31e1, 0xf000 },
538 { 0x31e2, 0x0000 },
539 { 0x31e3, 0xf000 },
540 { 0x31e4, 0x0000 },
541 { 0x31e5, 0xf000 },
542 { 0x31e6, 0x0000 },
543 { 0x31e7, 0xf000 },
544 { 0x31e8, 0x0000 },
545 { 0x31e9, 0xf000 },
546 { 0x31ea, 0x0000 },
547 { 0x31eb, 0xf000 },
548 { 0x31ec, 0x0000 },
549 { 0x31ed, 0xf000 },
550 { 0x31ee, 0x0000 },
551 { 0x31ef, 0xf000 },
552 { 0x31f0, 0x0000 },
553 { 0x31f1, 0xf000 },
554 { 0x31f2, 0x0000 },
555 { 0x31f3, 0xf000 },
556 { 0x31f4, 0x0000 },
557 { 0x31f5, 0xf000 },
558 { 0x31f6, 0x0000 },
559 { 0x31f7, 0xf000 },
560 { 0x31f8, 0x0000 },
561 { 0x31f9, 0xf000 },
562 { 0x31fa, 0x0000 },
563 { 0x31fb, 0xf000 },
564 { 0x31fc, 0x0000 },
565 { 0x31fd, 0xf000 },
566 { 0x31fe, 0x0000 },
567 { 0x31ff, 0xf000 },
568 { 0x024d, 0xff50 },
569 { 0x0252, 0xff50 },
570 { 0x0259, 0x0112 },
571 { 0x025e, 0x0112 },
572 { 0x101, 0x0304 },
573 { 0x80, 0x0000 },
574};
575
576/* We use a function so we can use ARRAY_SIZE() */
577int wm5102_patch(struct arizona *arizona)
578{
579 switch (arizona->rev) {
580 case 0:
581 return regmap_register_patch(arizona->regmap,
582 wm5102_reva_patch,
583 ARRAY_SIZE(wm5102_reva_patch));
584 default:
585 return 0;
586 }
587}
588
589static const struct regmap_irq wm5102_aod_irqs[ARIZONA_NUM_IRQ] = {
590 [ARIZONA_IRQ_GP5_FALL] = { .mask = ARIZONA_GP5_FALL_EINT1 },
591 [ARIZONA_IRQ_GP5_RISE] = { .mask = ARIZONA_GP5_RISE_EINT1 },
592 [ARIZONA_IRQ_JD_FALL] = { .mask = ARIZONA_JD1_FALL_EINT1 },
593 [ARIZONA_IRQ_JD_RISE] = { .mask = ARIZONA_JD1_RISE_EINT1 },
594};
595
596const struct regmap_irq_chip wm5102_aod = {
597 .name = "wm5102 AOD",
598 .status_base = ARIZONA_AOD_IRQ1,
599 .mask_base = ARIZONA_AOD_IRQ_MASK_IRQ1,
600 .ack_base = ARIZONA_AOD_IRQ1,
601 .wake_base = ARIZONA_WAKE_CONTROL,
602 .num_regs = 1,
603 .irqs = wm5102_aod_irqs,
604 .num_irqs = ARRAY_SIZE(wm5102_aod_irqs),
605};
606
607static const struct regmap_irq wm5102_irqs[ARIZONA_NUM_IRQ] = {
608 [ARIZONA_IRQ_GP4] = { .reg_offset = 0, .mask = ARIZONA_GP4_EINT1 },
609 [ARIZONA_IRQ_GP3] = { .reg_offset = 0, .mask = ARIZONA_GP3_EINT1 },
610 [ARIZONA_IRQ_GP2] = { .reg_offset = 0, .mask = ARIZONA_GP2_EINT1 },
611 [ARIZONA_IRQ_GP1] = { .reg_offset = 0, .mask = ARIZONA_GP1_EINT1 },
612
613 [ARIZONA_IRQ_DSP1_RAM_RDY] = {
614 .reg_offset = 1, .mask = ARIZONA_DSP1_RAM_RDY_EINT1
615 },
616 [ARIZONA_IRQ_DSP_IRQ2] = {
617 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ2_EINT1
618 },
619 [ARIZONA_IRQ_DSP_IRQ1] = {
620 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ1_EINT1
621 },
622
623 [ARIZONA_IRQ_SPK_SHUTDOWN_WARN] = {
624 .reg_offset = 2, .mask = ARIZONA_SPK_SHUTDOWN_WARN_EINT1
625 },
626 [ARIZONA_IRQ_SPK_SHUTDOWN] = {
627 .reg_offset = 2, .mask = ARIZONA_SPK_SHUTDOWN_EINT1
628 },
629 [ARIZONA_IRQ_HPDET] = {
630 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
631 },
632 [ARIZONA_IRQ_MICDET] = {
633 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
634 },
635 [ARIZONA_IRQ_WSEQ_DONE] = {
636 .reg_offset = 2, .mask = ARIZONA_WSEQ_DONE_EINT1
637 },
638 [ARIZONA_IRQ_DRC2_SIG_DET] = {
639 .reg_offset = 2, .mask = ARIZONA_DRC2_SIG_DET_EINT1
640 },
641 [ARIZONA_IRQ_DRC1_SIG_DET] = {
642 .reg_offset = 2, .mask = ARIZONA_DRC1_SIG_DET_EINT1
643 },
644 [ARIZONA_IRQ_ASRC2_LOCK] = {
645 .reg_offset = 2, .mask = ARIZONA_ASRC2_LOCK_EINT1
646 },
647 [ARIZONA_IRQ_ASRC1_LOCK] = {
648 .reg_offset = 2, .mask = ARIZONA_ASRC1_LOCK_EINT1
649 },
650 [ARIZONA_IRQ_UNDERCLOCKED] = {
651 .reg_offset = 2, .mask = ARIZONA_UNDERCLOCKED_EINT1
652 },
653 [ARIZONA_IRQ_OVERCLOCKED] = {
654 .reg_offset = 2, .mask = ARIZONA_OVERCLOCKED_EINT1
655 },
656 [ARIZONA_IRQ_FLL2_LOCK] = {
657 .reg_offset = 2, .mask = ARIZONA_FLL2_LOCK_EINT1
658 },
659 [ARIZONA_IRQ_FLL1_LOCK] = {
660 .reg_offset = 2, .mask = ARIZONA_FLL1_LOCK_EINT1
661 },
662 [ARIZONA_IRQ_CLKGEN_ERR] = {
663 .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_EINT1
664 },
665 [ARIZONA_IRQ_CLKGEN_ERR_ASYNC] = {
666 .reg_offset = 2, .mask = ARIZONA_CLKGEN_ERR_ASYNC_EINT1
667 },
668
669 [ARIZONA_IRQ_ASRC_CFG_ERR] = {
670 .reg_offset = 3, .mask = ARIZONA_ASRC_CFG_ERR_EINT1
671 },
672 [ARIZONA_IRQ_AIF3_ERR] = {
673 .reg_offset = 3, .mask = ARIZONA_AIF3_ERR_EINT1
674 },
675 [ARIZONA_IRQ_AIF2_ERR] = {
676 .reg_offset = 3, .mask = ARIZONA_AIF2_ERR_EINT1
677 },
678 [ARIZONA_IRQ_AIF1_ERR] = {
679 .reg_offset = 3, .mask = ARIZONA_AIF1_ERR_EINT1
680 },
681 [ARIZONA_IRQ_CTRLIF_ERR] = {
682 .reg_offset = 3, .mask = ARIZONA_CTRLIF_ERR_EINT1
683 },
684 [ARIZONA_IRQ_MIXER_DROPPED_SAMPLES] = {
685 .reg_offset = 3, .mask = ARIZONA_MIXER_DROPPED_SAMPLE_EINT1
686 },
687 [ARIZONA_IRQ_ASYNC_CLK_ENA_LOW] = {
688 .reg_offset = 3, .mask = ARIZONA_ASYNC_CLK_ENA_LOW_EINT1
689 },
690 [ARIZONA_IRQ_SYSCLK_ENA_LOW] = {
691 .reg_offset = 3, .mask = ARIZONA_SYSCLK_ENA_LOW_EINT1
692 },
693 [ARIZONA_IRQ_ISRC1_CFG_ERR] = {
694 .reg_offset = 3, .mask = ARIZONA_ISRC1_CFG_ERR_EINT1
695 },
696 [ARIZONA_IRQ_ISRC2_CFG_ERR] = {
697 .reg_offset = 3, .mask = ARIZONA_ISRC2_CFG_ERR_EINT1
698 },
699
700 [ARIZONA_IRQ_BOOT_DONE] = {
701 .reg_offset = 4, .mask = ARIZONA_BOOT_DONE_EINT1
702 },
703 [ARIZONA_IRQ_DCS_DAC_DONE] = {
704 .reg_offset = 4, .mask = ARIZONA_DCS_DAC_DONE_EINT1
705 },
706 [ARIZONA_IRQ_DCS_HP_DONE] = {
707 .reg_offset = 4, .mask = ARIZONA_DCS_HP_DONE_EINT1
708 },
709 [ARIZONA_IRQ_FLL2_CLOCK_OK] = {
710 .reg_offset = 4, .mask = ARIZONA_FLL2_CLOCK_OK_EINT1
711 },
712 [ARIZONA_IRQ_FLL1_CLOCK_OK] = {
713 .reg_offset = 4, .mask = ARIZONA_FLL1_CLOCK_OK_EINT1
714 },
715};
716
717const struct regmap_irq_chip wm5102_irq = {
718 .name = "wm5102 IRQ",
719 .status_base = ARIZONA_INTERRUPT_STATUS_1,
720 .mask_base = ARIZONA_INTERRUPT_STATUS_1_MASK,
721 .ack_base = ARIZONA_INTERRUPT_STATUS_1,
722 .num_regs = 5,
723 .irqs = wm5102_irqs,
724 .num_irqs = ARRAY_SIZE(wm5102_irqs),
725};
726
727static const struct reg_default wm5102_reg_default[] = {
728 { 0x00000008, 0x0019 }, /* R8 - Ctrl IF SPI CFG 1 */
729 { 0x00000009, 0x0001 }, /* R9 - Ctrl IF I2C1 CFG 1 */
730 { 0x0000000D, 0x0000 }, /* R13 - Ctrl IF Status 1 */
731 { 0x00000016, 0x0000 }, /* R22 - Write Sequencer Ctrl 0 */
732 { 0x00000017, 0x0000 }, /* R23 - Write Sequencer Ctrl 1 */
733 { 0x00000018, 0x0000 }, /* R24 - Write Sequencer Ctrl 2 */
734 { 0x0000001A, 0x0000 }, /* R26 - Write Sequencer PROM */
735 { 0x00000020, 0x0000 }, /* R32 - Tone Generator 1 */
736 { 0x00000021, 0x1000 }, /* R33 - Tone Generator 2 */
737 { 0x00000022, 0x0000 }, /* R34 - Tone Generator 3 */
738 { 0x00000023, 0x1000 }, /* R35 - Tone Generator 4 */
739 { 0x00000024, 0x0000 }, /* R36 - Tone Generator 5 */
740 { 0x00000030, 0x0000 }, /* R48 - PWM Drive 1 */
741 { 0x00000031, 0x0100 }, /* R49 - PWM Drive 2 */
742 { 0x00000032, 0x0100 }, /* R50 - PWM Drive 3 */
743 { 0x00000040, 0x0000 }, /* R64 - Wake control */
744 { 0x00000041, 0x0000 }, /* R65 - Sequence control */
745 { 0x00000061, 0x01FF }, /* R97 - Sample Rate Sequence Select 1 */
746 { 0x00000062, 0x01FF }, /* R98 - Sample Rate Sequence Select 2 */
747 { 0x00000063, 0x01FF }, /* R99 - Sample Rate Sequence Select 3 */
748 { 0x00000064, 0x01FF }, /* R100 - Sample Rate Sequence Select 4 */
749 { 0x00000068, 0x01FF }, /* R104 - Always On Triggers Sequence Select 1 */
750 { 0x00000069, 0x01FF }, /* R105 - Always On Triggers Sequence Select 2 */
751 { 0x0000006A, 0x01FF }, /* R106 - Always On Triggers Sequence Select 3 */
752 { 0x0000006B, 0x01FF }, /* R107 - Always On Triggers Sequence Select 4 */
753 { 0x0000006C, 0x01FF }, /* R108 - Always On Triggers Sequence Select 5 */
754 { 0x0000006D, 0x01FF }, /* R109 - Always On Triggers Sequence Select 6 */
755 { 0x00000070, 0x0000 }, /* R112 - Comfort Noise Generator */
756 { 0x00000090, 0x0000 }, /* R144 - Haptics Control 1 */
757 { 0x00000091, 0x7FFF }, /* R145 - Haptics Control 2 */
758 { 0x00000092, 0x0000 }, /* R146 - Haptics phase 1 intensity */
759 { 0x00000093, 0x0000 }, /* R147 - Haptics phase 1 duration */
760 { 0x00000094, 0x0000 }, /* R148 - Haptics phase 2 intensity */
761 { 0x00000095, 0x0000 }, /* R149 - Haptics phase 2 duration */
762 { 0x00000096, 0x0000 }, /* R150 - Haptics phase 3 intensity */
763 { 0x00000097, 0x0000 }, /* R151 - Haptics phase 3 duration */
764 { 0x00000100, 0x0001 }, /* R256 - Clock 32k 1 */
765 { 0x00000101, 0x0304 }, /* R257 - System Clock 1 */
766 { 0x00000102, 0x0011 }, /* R258 - Sample rate 1 */
767 { 0x00000103, 0x0011 }, /* R259 - Sample rate 2 */
768 { 0x00000104, 0x0011 }, /* R260 - Sample rate 3 */
769 { 0x00000112, 0x0305 }, /* R274 - Async clock 1 */
770 { 0x00000113, 0x0011 }, /* R275 - Async sample rate 1 */
771 { 0x00000149, 0x0000 }, /* R329 - Output system clock */
772 { 0x0000014A, 0x0000 }, /* R330 - Output async clock */
773 { 0x00000152, 0x0000 }, /* R338 - Rate Estimator 1 */
774 { 0x00000153, 0x0000 }, /* R339 - Rate Estimator 2 */
775 { 0x00000154, 0x0000 }, /* R340 - Rate Estimator 3 */
776 { 0x00000155, 0x0000 }, /* R341 - Rate Estimator 4 */
777 { 0x00000156, 0x0000 }, /* R342 - Rate Estimator 5 */
778 { 0x00000171, 0x0000 }, /* R369 - FLL1 Control 1 */
779 { 0x00000172, 0x0008 }, /* R370 - FLL1 Control 2 */
780 { 0x00000173, 0x0018 }, /* R371 - FLL1 Control 3 */
781 { 0x00000174, 0x007D }, /* R372 - FLL1 Control 4 */
782 { 0x00000175, 0x0004 }, /* R373 - FLL1 Control 5 */
783 { 0x00000176, 0x0000 }, /* R374 - FLL1 Control 6 */
784 { 0x00000177, 0x0181 }, /* R375 - FLL1 Loop Filter Test 1 */
785 { 0x00000181, 0x0000 }, /* R385 - FLL1 Synchroniser 1 */
786 { 0x00000182, 0x0000 }, /* R386 - FLL1 Synchroniser 2 */
787 { 0x00000183, 0x0000 }, /* R387 - FLL1 Synchroniser 3 */
788 { 0x00000184, 0x0000 }, /* R388 - FLL1 Synchroniser 4 */
789 { 0x00000185, 0x0000 }, /* R389 - FLL1 Synchroniser 5 */
790 { 0x00000186, 0x0000 }, /* R390 - FLL1 Synchroniser 6 */
791 { 0x00000189, 0x0000 }, /* R393 - FLL1 Spread Spectrum */
792 { 0x0000018A, 0x0004 }, /* R394 - FLL1 GPIO Clock */
793 { 0x00000191, 0x0000 }, /* R401 - FLL2 Control 1 */
794 { 0x00000192, 0x0008 }, /* R402 - FLL2 Control 2 */
795 { 0x00000193, 0x0018 }, /* R403 - FLL2 Control 3 */
796 { 0x00000194, 0x007D }, /* R404 - FLL2 Control 4 */
797 { 0x00000195, 0x0004 }, /* R405 - FLL2 Control 5 */
798 { 0x00000196, 0x0000 }, /* R406 - FLL2 Control 6 */
799 { 0x00000197, 0x0000 }, /* R407 - FLL2 Loop Filter Test 1 */
800 { 0x000001A1, 0x0000 }, /* R417 - FLL2 Synchroniser 1 */
801 { 0x000001A2, 0x0000 }, /* R418 - FLL2 Synchroniser 2 */
802 { 0x000001A3, 0x0000 }, /* R419 - FLL2 Synchroniser 3 */
803 { 0x000001A4, 0x0000 }, /* R420 - FLL2 Synchroniser 4 */
804 { 0x000001A5, 0x0000 }, /* R421 - FLL2 Synchroniser 5 */
805 { 0x000001A6, 0x0000 }, /* R422 - FLL2 Synchroniser 6 */
806 { 0x000001A9, 0x0000 }, /* R425 - FLL2 Spread Spectrum */
807 { 0x000001AA, 0x0004 }, /* R426 - FLL2 GPIO Clock */
808 { 0x00000200, 0x0006 }, /* R512 - Mic Charge Pump 1 */
809 { 0x00000210, 0x00D4 }, /* R528 - LDO1 Control 1 */
810 { 0x00000213, 0x0344 }, /* R531 - LDO2 Control 1 */
811 { 0x00000218, 0x01A6 }, /* R536 - Mic Bias Ctrl 1 */
812 { 0x00000219, 0x01A6 }, /* R537 - Mic Bias Ctrl 2 */
813 { 0x0000021A, 0x01A6 }, /* R538 - Mic Bias Ctrl 3 */
814 { 0x00000293, 0x0000 }, /* R659 - Accessory Detect Mode 1 */
815 { 0x0000029B, 0x0020 }, /* R667 - Headphone Detect 1 */
816 { 0x0000029C, 0x0000 }, /* R668 - Headphone Detect 2 */
817 { 0x000002A3, 0x1102 }, /* R675 - Mic Detect 1 */
818 { 0x000002A4, 0x009F }, /* R676 - Mic Detect 2 */
819 { 0x000002A5, 0x0000 }, /* R677 - Mic Detect 3 */
820 { 0x000002C3, 0x0000 }, /* R707 - Mic noise mix control 1 */
821 { 0x000002CB, 0x0000 }, /* R715 - Isolation control */
822 { 0x000002D3, 0x0000 }, /* R723 - Jack detect analogue */
823 { 0x00000300, 0x0000 }, /* R768 - Input Enables */
824 { 0x00000308, 0x0000 }, /* R776 - Input Rate */
825 { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */
826 { 0x00000310, 0x2080 }, /* R784 - IN1L Control */
827 { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */
828 { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */
829 { 0x00000314, 0x0080 }, /* R788 - IN1R Control */
830 { 0x00000315, 0x0180 }, /* R789 - ADC Digital Volume 1R */
831 { 0x00000316, 0x0000 }, /* R790 - DMIC1R Control */
832 { 0x00000318, 0x2080 }, /* R792 - IN2L Control */
833 { 0x00000319, 0x0180 }, /* R793 - ADC Digital Volume 2L */
834 { 0x0000031A, 0x0000 }, /* R794 - DMIC2L Control */
835 { 0x0000031C, 0x0080 }, /* R796 - IN2R Control */
836 { 0x0000031D, 0x0180 }, /* R797 - ADC Digital Volume 2R */
837 { 0x0000031E, 0x0000 }, /* R798 - DMIC2R Control */
838 { 0x00000320, 0x2080 }, /* R800 - IN3L Control */
839 { 0x00000321, 0x0180 }, /* R801 - ADC Digital Volume 3L */
840 { 0x00000322, 0x0000 }, /* R802 - DMIC3L Control */
841 { 0x00000324, 0x0080 }, /* R804 - IN3R Control */
842 { 0x00000325, 0x0180 }, /* R805 - ADC Digital Volume 3R */
843 { 0x00000326, 0x0000 }, /* R806 - DMIC3R Control */
844 { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
845 { 0x00000408, 0x0000 }, /* R1032 - Output Rate 1 */
846 { 0x00000409, 0x0022 }, /* R1033 - Output Volume Ramp */
847 { 0x00000410, 0x0080 }, /* R1040 - Output Path Config 1L */
848 { 0x00000411, 0x0180 }, /* R1041 - DAC Digital Volume 1L */
849 { 0x00000412, 0x0080 }, /* R1042 - DAC Volume Limit 1L */
850 { 0x00000413, 0x0001 }, /* R1043 - Noise Gate Select 1L */
851 { 0x00000414, 0x0080 }, /* R1044 - Output Path Config 1R */
852 { 0x00000415, 0x0180 }, /* R1045 - DAC Digital Volume 1R */
853 { 0x00000416, 0x0080 }, /* R1046 - DAC Volume Limit 1R */
854 { 0x00000417, 0x0002 }, /* R1047 - Noise Gate Select 1R */
855 { 0x00000418, 0x0080 }, /* R1048 - Output Path Config 2L */
856 { 0x00000419, 0x0180 }, /* R1049 - DAC Digital Volume 2L */
857 { 0x0000041A, 0x0080 }, /* R1050 - DAC Volume Limit 2L */
858 { 0x0000041B, 0x0004 }, /* R1051 - Noise Gate Select 2L */
859 { 0x0000041C, 0x0080 }, /* R1052 - Output Path Config 2R */
860 { 0x0000041D, 0x0180 }, /* R1053 - DAC Digital Volume 2R */
861 { 0x0000041E, 0x0080 }, /* R1054 - DAC Volume Limit 2R */
862 { 0x0000041F, 0x0008 }, /* R1055 - Noise Gate Select 2R */
863 { 0x00000420, 0x0080 }, /* R1056 - Output Path Config 3L */
864 { 0x00000421, 0x0180 }, /* R1057 - DAC Digital Volume 3L */
865 { 0x00000422, 0x0080 }, /* R1058 - DAC Volume Limit 3L */
866 { 0x00000423, 0x0010 }, /* R1059 - Noise Gate Select 3L */
867 { 0x00000424, 0x0080 }, /* R1060 - Output Path Config 3R */
868 { 0x00000425, 0x0180 }, /* R1061 - DAC Digital Volume 3R */
869 { 0x00000426, 0x0080 }, /* R1062 - DAC Volume Limit 3R */
870 { 0x00000428, 0x0000 }, /* R1064 - Output Path Config 4L */
871 { 0x00000429, 0x0180 }, /* R1065 - DAC Digital Volume 4L */
872 { 0x0000042A, 0x0080 }, /* R1066 - Out Volume 4L */
873 { 0x0000042B, 0x0040 }, /* R1067 - Noise Gate Select 4L */
874 { 0x0000042C, 0x0000 }, /* R1068 - Output Path Config 4R */
875 { 0x0000042D, 0x0180 }, /* R1069 - DAC Digital Volume 4R */
876 { 0x0000042E, 0x0080 }, /* R1070 - Out Volume 4R */
877 { 0x0000042F, 0x0080 }, /* R1071 - Noise Gate Select 4R */
878 { 0x00000430, 0x0000 }, /* R1072 - Output Path Config 5L */
879 { 0x00000431, 0x0180 }, /* R1073 - DAC Digital Volume 5L */
880 { 0x00000432, 0x0080 }, /* R1074 - DAC Volume Limit 5L */
881 { 0x00000433, 0x0100 }, /* R1075 - Noise Gate Select 5L */
882 { 0x00000434, 0x0000 }, /* R1076 - Output Path Config 5R */
883 { 0x00000435, 0x0180 }, /* R1077 - DAC Digital Volume 5R */
884 { 0x00000436, 0x0080 }, /* R1078 - DAC Volume Limit 5R */
885 { 0x00000437, 0x0200 }, /* R1079 - Noise Gate Select 5R */
886 { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
887 { 0x00000458, 0x0001 }, /* R1112 - Noise Gate Control */
888 { 0x00000490, 0x0069 }, /* R1168 - PDM SPK1 CTRL 1 */
889 { 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */
890 { 0x000004DC, 0x0000 }, /* R1244 - DAC comp 1 */
891 { 0x000004DD, 0x0000 }, /* R1245 - DAC comp 2 */
892 { 0x000004DE, 0x0000 }, /* R1246 - DAC comp 3 */
893 { 0x000004DF, 0x0000 }, /* R1247 - DAC comp 4 */
894 { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
895 { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
896 { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
897 { 0x00000503, 0x0000 }, /* R1283 - AIF1 Rate Ctrl */
898 { 0x00000504, 0x0000 }, /* R1284 - AIF1 Format */
899 { 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */
900 { 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */
901 { 0x00000507, 0x1818 }, /* R1287 - AIF1 Frame Ctrl 1 */
902 { 0x00000508, 0x1818 }, /* R1288 - AIF1 Frame Ctrl 2 */
903 { 0x00000509, 0x0000 }, /* R1289 - AIF1 Frame Ctrl 3 */
904 { 0x0000050A, 0x0001 }, /* R1290 - AIF1 Frame Ctrl 4 */
905 { 0x0000050B, 0x0002 }, /* R1291 - AIF1 Frame Ctrl 5 */
906 { 0x0000050C, 0x0003 }, /* R1292 - AIF1 Frame Ctrl 6 */
907 { 0x0000050D, 0x0004 }, /* R1293 - AIF1 Frame Ctrl 7 */
908 { 0x0000050E, 0x0005 }, /* R1294 - AIF1 Frame Ctrl 8 */
909 { 0x0000050F, 0x0006 }, /* R1295 - AIF1 Frame Ctrl 9 */
910 { 0x00000510, 0x0007 }, /* R1296 - AIF1 Frame Ctrl 10 */
911 { 0x00000511, 0x0000 }, /* R1297 - AIF1 Frame Ctrl 11 */
912 { 0x00000512, 0x0001 }, /* R1298 - AIF1 Frame Ctrl 12 */
913 { 0x00000513, 0x0002 }, /* R1299 - AIF1 Frame Ctrl 13 */
914 { 0x00000514, 0x0003 }, /* R1300 - AIF1 Frame Ctrl 14 */
915 { 0x00000515, 0x0004 }, /* R1301 - AIF1 Frame Ctrl 15 */
916 { 0x00000516, 0x0005 }, /* R1302 - AIF1 Frame Ctrl 16 */
917 { 0x00000517, 0x0006 }, /* R1303 - AIF1 Frame Ctrl 17 */
918 { 0x00000518, 0x0007 }, /* R1304 - AIF1 Frame Ctrl 18 */
919 { 0x00000519, 0x0000 }, /* R1305 - AIF1 Tx Enables */
920 { 0x0000051A, 0x0000 }, /* R1306 - AIF1 Rx Enables */
921 { 0x0000051B, 0x0000 }, /* R1307 - AIF1 Force Write */
922 { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */
923 { 0x00000541, 0x0008 }, /* R1345 - AIF2 Tx Pin Ctrl */
924 { 0x00000542, 0x0000 }, /* R1346 - AIF2 Rx Pin Ctrl */
925 { 0x00000543, 0x0000 }, /* R1347 - AIF2 Rate Ctrl */
926 { 0x00000544, 0x0000 }, /* R1348 - AIF2 Format */
927 { 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */
928 { 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */
929 { 0x00000547, 0x1818 }, /* R1351 - AIF2 Frame Ctrl 1 */
930 { 0x00000548, 0x1818 }, /* R1352 - AIF2 Frame Ctrl 2 */
931 { 0x00000549, 0x0000 }, /* R1353 - AIF2 Frame Ctrl 3 */
932 { 0x0000054A, 0x0001 }, /* R1354 - AIF2 Frame Ctrl 4 */
933 { 0x00000551, 0x0000 }, /* R1361 - AIF2 Frame Ctrl 11 */
934 { 0x00000552, 0x0001 }, /* R1362 - AIF2 Frame Ctrl 12 */
935 { 0x00000559, 0x0000 }, /* R1369 - AIF2 Tx Enables */
936 { 0x0000055A, 0x0000 }, /* R1370 - AIF2 Rx Enables */
937 { 0x0000055B, 0x0000 }, /* R1371 - AIF2 Force Write */
938 { 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */
939 { 0x00000581, 0x0008 }, /* R1409 - AIF3 Tx Pin Ctrl */
940 { 0x00000582, 0x0000 }, /* R1410 - AIF3 Rx Pin Ctrl */
941 { 0x00000583, 0x0000 }, /* R1411 - AIF3 Rate Ctrl */
942 { 0x00000584, 0x0000 }, /* R1412 - AIF3 Format */
943 { 0x00000585, 0x0040 }, /* R1413 - AIF3 Tx BCLK Rate */
944 { 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */
945 { 0x00000587, 0x1818 }, /* R1415 - AIF3 Frame Ctrl 1 */
946 { 0x00000588, 0x1818 }, /* R1416 - AIF3 Frame Ctrl 2 */
947 { 0x00000589, 0x0000 }, /* R1417 - AIF3 Frame Ctrl 3 */
948 { 0x0000058A, 0x0001 }, /* R1418 - AIF3 Frame Ctrl 4 */
949 { 0x00000591, 0x0000 }, /* R1425 - AIF3 Frame Ctrl 11 */
950 { 0x00000592, 0x0001 }, /* R1426 - AIF3 Frame Ctrl 12 */
951 { 0x00000599, 0x0000 }, /* R1433 - AIF3 Tx Enables */
952 { 0x0000059A, 0x0000 }, /* R1434 - AIF3 Rx Enables */
953 { 0x0000059B, 0x0000 }, /* R1435 - AIF3 Force Write */
954 { 0x000005E3, 0x0004 }, /* R1507 - SLIMbus Framer Ref Gear */
955 { 0x000005E5, 0x0000 }, /* R1509 - SLIMbus Rates 1 */
956 { 0x000005E6, 0x0000 }, /* R1510 - SLIMbus Rates 2 */
957 { 0x000005E7, 0x0000 }, /* R1511 - SLIMbus Rates 3 */
958 { 0x000005E8, 0x0000 }, /* R1512 - SLIMbus Rates 4 */
959 { 0x000005E9, 0x0000 }, /* R1513 - SLIMbus Rates 5 */
960 { 0x000005EA, 0x0000 }, /* R1514 - SLIMbus Rates 6 */
961 { 0x000005EB, 0x0000 }, /* R1515 - SLIMbus Rates 7 */
962 { 0x000005EC, 0x0000 }, /* R1516 - SLIMbus Rates 8 */
963 { 0x000005F5, 0x0000 }, /* R1525 - SLIMbus RX Channel Enable */
964 { 0x000005F6, 0x0000 }, /* R1526 - SLIMbus TX Channel Enable */
965 { 0x00000640, 0x0000 }, /* R1600 - PWM1MIX Input 1 Source */
966 { 0x00000641, 0x0080 }, /* R1601 - PWM1MIX Input 1 Volume */
967 { 0x00000642, 0x0000 }, /* R1602 - PWM1MIX Input 2 Source */
968 { 0x00000643, 0x0080 }, /* R1603 - PWM1MIX Input 2 Volume */
969 { 0x00000644, 0x0000 }, /* R1604 - PWM1MIX Input 3 Source */
970 { 0x00000645, 0x0080 }, /* R1605 - PWM1MIX Input 3 Volume */
971 { 0x00000646, 0x0000 }, /* R1606 - PWM1MIX Input 4 Source */
972 { 0x00000647, 0x0080 }, /* R1607 - PWM1MIX Input 4 Volume */
973 { 0x00000648, 0x0000 }, /* R1608 - PWM2MIX Input 1 Source */
974 { 0x00000649, 0x0080 }, /* R1609 - PWM2MIX Input 1 Volume */
975 { 0x0000064A, 0x0000 }, /* R1610 - PWM2MIX Input 2 Source */
976 { 0x0000064B, 0x0080 }, /* R1611 - PWM2MIX Input 2 Volume */
977 { 0x0000064C, 0x0000 }, /* R1612 - PWM2MIX Input 3 Source */
978 { 0x0000064D, 0x0080 }, /* R1613 - PWM2MIX Input 3 Volume */
979 { 0x0000064E, 0x0000 }, /* R1614 - PWM2MIX Input 4 Source */
980 { 0x0000064F, 0x0080 }, /* R1615 - PWM2MIX Input 4 Volume */
981 { 0x00000660, 0x0000 }, /* R1632 - MICMIX Input 1 Source */
982 { 0x00000661, 0x0080 }, /* R1633 - MICMIX Input 1 Volume */
983 { 0x00000662, 0x0000 }, /* R1634 - MICMIX Input 2 Source */
984 { 0x00000663, 0x0080 }, /* R1635 - MICMIX Input 2 Volume */
985 { 0x00000664, 0x0000 }, /* R1636 - MICMIX Input 3 Source */
986 { 0x00000665, 0x0080 }, /* R1637 - MICMIX Input 3 Volume */
987 { 0x00000666, 0x0000 }, /* R1638 - MICMIX Input 4 Source */
988 { 0x00000667, 0x0080 }, /* R1639 - MICMIX Input 4 Volume */
989 { 0x00000668, 0x0000 }, /* R1640 - NOISEMIX Input 1 Source */
990 { 0x00000669, 0x0080 }, /* R1641 - NOISEMIX Input 1 Volume */
991 { 0x0000066A, 0x0000 }, /* R1642 - NOISEMIX Input 2 Source */
992 { 0x0000066B, 0x0080 }, /* R1643 - NOISEMIX Input 2 Volume */
993 { 0x0000066C, 0x0000 }, /* R1644 - NOISEMIX Input 3 Source */
994 { 0x0000066D, 0x0080 }, /* R1645 - NOISEMIX Input 3 Volume */
995 { 0x0000066E, 0x0000 }, /* R1646 - NOISEMIX Input 4 Source */
996 { 0x0000066F, 0x0080 }, /* R1647 - NOISEMIX Input 4 Volume */
997 { 0x00000680, 0x0000 }, /* R1664 - OUT1LMIX Input 1 Source */
998 { 0x00000681, 0x0080 }, /* R1665 - OUT1LMIX Input 1 Volume */
999 { 0x00000682, 0x0000 }, /* R1666 - OUT1LMIX Input 2 Source */
1000 { 0x00000683, 0x0080 }, /* R1667 - OUT1LMIX Input 2 Volume */
1001 { 0x00000684, 0x0000 }, /* R1668 - OUT1LMIX Input 3 Source */
1002 { 0x00000685, 0x0080 }, /* R1669 - OUT1LMIX Input 3 Volume */
1003 { 0x00000686, 0x0000 }, /* R1670 - OUT1LMIX Input 4 Source */
1004 { 0x00000687, 0x0080 }, /* R1671 - OUT1LMIX Input 4 Volume */
1005 { 0x00000688, 0x0000 }, /* R1672 - OUT1RMIX Input 1 Source */
1006 { 0x00000689, 0x0080 }, /* R1673 - OUT1RMIX Input 1 Volume */
1007 { 0x0000068A, 0x0000 }, /* R1674 - OUT1RMIX Input 2 Source */
1008 { 0x0000068B, 0x0080 }, /* R1675 - OUT1RMIX Input 2 Volume */
1009 { 0x0000068C, 0x0000 }, /* R1676 - OUT1RMIX Input 3 Source */
1010 { 0x0000068D, 0x0080 }, /* R1677 - OUT1RMIX Input 3 Volume */
1011 { 0x0000068E, 0x0000 }, /* R1678 - OUT1RMIX Input 4 Source */
1012 { 0x0000068F, 0x0080 }, /* R1679 - OUT1RMIX Input 4 Volume */
1013 { 0x00000690, 0x0000 }, /* R1680 - OUT2LMIX Input 1 Source */
1014 { 0x00000691, 0x0080 }, /* R1681 - OUT2LMIX Input 1 Volume */
1015 { 0x00000692, 0x0000 }, /* R1682 - OUT2LMIX Input 2 Source */
1016 { 0x00000693, 0x0080 }, /* R1683 - OUT2LMIX Input 2 Volume */
1017 { 0x00000694, 0x0000 }, /* R1684 - OUT2LMIX Input 3 Source */
1018 { 0x00000695, 0x0080 }, /* R1685 - OUT2LMIX Input 3 Volume */
1019 { 0x00000696, 0x0000 }, /* R1686 - OUT2LMIX Input 4 Source */
1020 { 0x00000697, 0x0080 }, /* R1687 - OUT2LMIX Input 4 Volume */
1021 { 0x00000698, 0x0000 }, /* R1688 - OUT2RMIX Input 1 Source */
1022 { 0x00000699, 0x0080 }, /* R1689 - OUT2RMIX Input 1 Volume */
1023 { 0x0000069A, 0x0000 }, /* R1690 - OUT2RMIX Input 2 Source */
1024 { 0x0000069B, 0x0080 }, /* R1691 - OUT2RMIX Input 2 Volume */
1025 { 0x0000069C, 0x0000 }, /* R1692 - OUT2RMIX Input 3 Source */
1026 { 0x0000069D, 0x0080 }, /* R1693 - OUT2RMIX Input 3 Volume */
1027 { 0x0000069E, 0x0000 }, /* R1694 - OUT2RMIX Input 4 Source */
1028 { 0x0000069F, 0x0080 }, /* R1695 - OUT2RMIX Input 4 Volume */
1029 { 0x000006A0, 0x0000 }, /* R1696 - OUT3LMIX Input 1 Source */
1030 { 0x000006A1, 0x0080 }, /* R1697 - OUT3LMIX Input 1 Volume */
1031 { 0x000006A2, 0x0000 }, /* R1698 - OUT3LMIX Input 2 Source */
1032 { 0x000006A3, 0x0080 }, /* R1699 - OUT3LMIX Input 2 Volume */
1033 { 0x000006A4, 0x0000 }, /* R1700 - OUT3LMIX Input 3 Source */
1034 { 0x000006A5, 0x0080 }, /* R1701 - OUT3LMIX Input 3 Volume */
1035 { 0x000006A6, 0x0000 }, /* R1702 - OUT3LMIX Input 4 Source */
1036 { 0x000006A7, 0x0080 }, /* R1703 - OUT3LMIX Input 4 Volume */
1037 { 0x000006B0, 0x0000 }, /* R1712 - OUT4LMIX Input 1 Source */
1038 { 0x000006B1, 0x0080 }, /* R1713 - OUT4LMIX Input 1 Volume */
1039 { 0x000006B2, 0x0000 }, /* R1714 - OUT4LMIX Input 2 Source */
1040 { 0x000006B3, 0x0080 }, /* R1715 - OUT4LMIX Input 2 Volume */
1041 { 0x000006B4, 0x0000 }, /* R1716 - OUT4LMIX Input 3 Source */
1042 { 0x000006B5, 0x0080 }, /* R1717 - OUT4LMIX Input 3 Volume */
1043 { 0x000006B6, 0x0000 }, /* R1718 - OUT4LMIX Input 4 Source */
1044 { 0x000006B7, 0x0080 }, /* R1719 - OUT4LMIX Input 4 Volume */
1045 { 0x000006B8, 0x0000 }, /* R1720 - OUT4RMIX Input 1 Source */
1046 { 0x000006B9, 0x0080 }, /* R1721 - OUT4RMIX Input 1 Volume */
1047 { 0x000006BA, 0x0000 }, /* R1722 - OUT4RMIX Input 2 Source */
1048 { 0x000006BB, 0x0080 }, /* R1723 - OUT4RMIX Input 2 Volume */
1049 { 0x000006BC, 0x0000 }, /* R1724 - OUT4RMIX Input 3 Source */
1050 { 0x000006BD, 0x0080 }, /* R1725 - OUT4RMIX Input 3 Volume */
1051 { 0x000006BE, 0x0000 }, /* R1726 - OUT4RMIX Input 4 Source */
1052 { 0x000006BF, 0x0080 }, /* R1727 - OUT4RMIX Input 4 Volume */
1053 { 0x000006C0, 0x0000 }, /* R1728 - OUT5LMIX Input 1 Source */
1054 { 0x000006C1, 0x0080 }, /* R1729 - OUT5LMIX Input 1 Volume */
1055 { 0x000006C2, 0x0000 }, /* R1730 - OUT5LMIX Input 2 Source */
1056 { 0x000006C3, 0x0080 }, /* R1731 - OUT5LMIX Input 2 Volume */
1057 { 0x000006C4, 0x0000 }, /* R1732 - OUT5LMIX Input 3 Source */
1058 { 0x000006C5, 0x0080 }, /* R1733 - OUT5LMIX Input 3 Volume */
1059 { 0x000006C6, 0x0000 }, /* R1734 - OUT5LMIX Input 4 Source */
1060 { 0x000006C7, 0x0080 }, /* R1735 - OUT5LMIX Input 4 Volume */
1061 { 0x000006C8, 0x0000 }, /* R1736 - OUT5RMIX Input 1 Source */
1062 { 0x000006C9, 0x0080 }, /* R1737 - OUT5RMIX Input 1 Volume */
1063 { 0x000006CA, 0x0000 }, /* R1738 - OUT5RMIX Input 2 Source */
1064 { 0x000006CB, 0x0080 }, /* R1739 - OUT5RMIX Input 2 Volume */
1065 { 0x000006CC, 0x0000 }, /* R1740 - OUT5RMIX Input 3 Source */
1066 { 0x000006CD, 0x0080 }, /* R1741 - OUT5RMIX Input 3 Volume */
1067 { 0x000006CE, 0x0000 }, /* R1742 - OUT5RMIX Input 4 Source */
1068 { 0x000006CF, 0x0080 }, /* R1743 - OUT5RMIX Input 4 Volume */
1069 { 0x00000700, 0x0000 }, /* R1792 - AIF1TX1MIX Input 1 Source */
1070 { 0x00000701, 0x0080 }, /* R1793 - AIF1TX1MIX Input 1 Volume */
1071 { 0x00000702, 0x0000 }, /* R1794 - AIF1TX1MIX Input 2 Source */
1072 { 0x00000703, 0x0080 }, /* R1795 - AIF1TX1MIX Input 2 Volume */
1073 { 0x00000704, 0x0000 }, /* R1796 - AIF1TX1MIX Input 3 Source */
1074 { 0x00000705, 0x0080 }, /* R1797 - AIF1TX1MIX Input 3 Volume */
1075 { 0x00000706, 0x0000 }, /* R1798 - AIF1TX1MIX Input 4 Source */
1076 { 0x00000707, 0x0080 }, /* R1799 - AIF1TX1MIX Input 4 Volume */
1077 { 0x00000708, 0x0000 }, /* R1800 - AIF1TX2MIX Input 1 Source */
1078 { 0x00000709, 0x0080 }, /* R1801 - AIF1TX2MIX Input 1 Volume */
1079 { 0x0000070A, 0x0000 }, /* R1802 - AIF1TX2MIX Input 2 Source */
1080 { 0x0000070B, 0x0080 }, /* R1803 - AIF1TX2MIX Input 2 Volume */
1081 { 0x0000070C, 0x0000 }, /* R1804 - AIF1TX2MIX Input 3 Source */
1082 { 0x0000070D, 0x0080 }, /* R1805 - AIF1TX2MIX Input 3 Volume */
1083 { 0x0000070E, 0x0000 }, /* R1806 - AIF1TX2MIX Input 4 Source */
1084 { 0x0000070F, 0x0080 }, /* R1807 - AIF1TX2MIX Input 4 Volume */
1085 { 0x00000710, 0x0000 }, /* R1808 - AIF1TX3MIX Input 1 Source */
1086 { 0x00000711, 0x0080 }, /* R1809 - AIF1TX3MIX Input 1 Volume */
1087 { 0x00000712, 0x0000 }, /* R1810 - AIF1TX3MIX Input 2 Source */
1088 { 0x00000713, 0x0080 }, /* R1811 - AIF1TX3MIX Input 2 Volume */
1089 { 0x00000714, 0x0000 }, /* R1812 - AIF1TX3MIX Input 3 Source */
1090 { 0x00000715, 0x0080 }, /* R1813 - AIF1TX3MIX Input 3 Volume */
1091 { 0x00000716, 0x0000 }, /* R1814 - AIF1TX3MIX Input 4 Source */
1092 { 0x00000717, 0x0080 }, /* R1815 - AIF1TX3MIX Input 4 Volume */
1093 { 0x00000718, 0x0000 }, /* R1816 - AIF1TX4MIX Input 1 Source */
1094 { 0x00000719, 0x0080 }, /* R1817 - AIF1TX4MIX Input 1 Volume */
1095 { 0x0000071A, 0x0000 }, /* R1818 - AIF1TX4MIX Input 2 Source */
1096 { 0x0000071B, 0x0080 }, /* R1819 - AIF1TX4MIX Input 2 Volume */
1097 { 0x0000071C, 0x0000 }, /* R1820 - AIF1TX4MIX Input 3 Source */
1098 { 0x0000071D, 0x0080 }, /* R1821 - AIF1TX4MIX Input 3 Volume */
1099 { 0x0000071E, 0x0000 }, /* R1822 - AIF1TX4MIX Input 4 Source */
1100 { 0x0000071F, 0x0080 }, /* R1823 - AIF1TX4MIX Input 4 Volume */
1101 { 0x00000720, 0x0000 }, /* R1824 - AIF1TX5MIX Input 1 Source */
1102 { 0x00000721, 0x0080 }, /* R1825 - AIF1TX5MIX Input 1 Volume */
1103 { 0x00000722, 0x0000 }, /* R1826 - AIF1TX5MIX Input 2 Source */
1104 { 0x00000723, 0x0080 }, /* R1827 - AIF1TX5MIX Input 2 Volume */
1105 { 0x00000724, 0x0000 }, /* R1828 - AIF1TX5MIX Input 3 Source */
1106 { 0x00000725, 0x0080 }, /* R1829 - AIF1TX5MIX Input 3 Volume */
1107 { 0x00000726, 0x0000 }, /* R1830 - AIF1TX5MIX Input 4 Source */
1108 { 0x00000727, 0x0080 }, /* R1831 - AIF1TX5MIX Input 4 Volume */
1109 { 0x00000728, 0x0000 }, /* R1832 - AIF1TX6MIX Input 1 Source */
1110 { 0x00000729, 0x0080 }, /* R1833 - AIF1TX6MIX Input 1 Volume */
1111 { 0x0000072A, 0x0000 }, /* R1834 - AIF1TX6MIX Input 2 Source */
1112 { 0x0000072B, 0x0080 }, /* R1835 - AIF1TX6MIX Input 2 Volume */
1113 { 0x0000072C, 0x0000 }, /* R1836 - AIF1TX6MIX Input 3 Source */
1114 { 0x0000072D, 0x0080 }, /* R1837 - AIF1TX6MIX Input 3 Volume */
1115 { 0x0000072E, 0x0000 }, /* R1838 - AIF1TX6MIX Input 4 Source */
1116 { 0x0000072F, 0x0080 }, /* R1839 - AIF1TX6MIX Input 4 Volume */
1117 { 0x00000730, 0x0000 }, /* R1840 - AIF1TX7MIX Input 1 Source */
1118 { 0x00000731, 0x0080 }, /* R1841 - AIF1TX7MIX Input 1 Volume */
1119 { 0x00000732, 0x0000 }, /* R1842 - AIF1TX7MIX Input 2 Source */
1120 { 0x00000733, 0x0080 }, /* R1843 - AIF1TX7MIX Input 2 Volume */
1121 { 0x00000734, 0x0000 }, /* R1844 - AIF1TX7MIX Input 3 Source */
1122 { 0x00000735, 0x0080 }, /* R1845 - AIF1TX7MIX Input 3 Volume */
1123 { 0x00000736, 0x0000 }, /* R1846 - AIF1TX7MIX Input 4 Source */
1124 { 0x00000737, 0x0080 }, /* R1847 - AIF1TX7MIX Input 4 Volume */
1125 { 0x00000738, 0x0000 }, /* R1848 - AIF1TX8MIX Input 1 Source */
1126 { 0x00000739, 0x0080 }, /* R1849 - AIF1TX8MIX Input 1 Volume */
1127 { 0x0000073A, 0x0000 }, /* R1850 - AIF1TX8MIX Input 2 Source */
1128 { 0x0000073B, 0x0080 }, /* R1851 - AIF1TX8MIX Input 2 Volume */
1129 { 0x0000073C, 0x0000 }, /* R1852 - AIF1TX8MIX Input 3 Source */
1130 { 0x0000073D, 0x0080 }, /* R1853 - AIF1TX8MIX Input 3 Volume */
1131 { 0x0000073E, 0x0000 }, /* R1854 - AIF1TX8MIX Input 4 Source */
1132 { 0x0000073F, 0x0080 }, /* R1855 - AIF1TX8MIX Input 4 Volume */
1133 { 0x00000740, 0x0000 }, /* R1856 - AIF2TX1MIX Input 1 Source */
1134 { 0x00000741, 0x0080 }, /* R1857 - AIF2TX1MIX Input 1 Volume */
1135 { 0x00000742, 0x0000 }, /* R1858 - AIF2TX1MIX Input 2 Source */
1136 { 0x00000743, 0x0080 }, /* R1859 - AIF2TX1MIX Input 2 Volume */
1137 { 0x00000744, 0x0000 }, /* R1860 - AIF2TX1MIX Input 3 Source */
1138 { 0x00000745, 0x0080 }, /* R1861 - AIF2TX1MIX Input 3 Volume */
1139 { 0x00000746, 0x0000 }, /* R1862 - AIF2TX1MIX Input 4 Source */
1140 { 0x00000747, 0x0080 }, /* R1863 - AIF2TX1MIX Input 4 Volume */
1141 { 0x00000748, 0x0000 }, /* R1864 - AIF2TX2MIX Input 1 Source */
1142 { 0x00000749, 0x0080 }, /* R1865 - AIF2TX2MIX Input 1 Volume */
1143 { 0x0000074A, 0x0000 }, /* R1866 - AIF2TX2MIX Input 2 Source */
1144 { 0x0000074B, 0x0080 }, /* R1867 - AIF2TX2MIX Input 2 Volume */
1145 { 0x0000074C, 0x0000 }, /* R1868 - AIF2TX2MIX Input 3 Source */
1146 { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */
1147 { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */
1148 { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */
1149 { 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */
1150 { 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */
1151 { 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */
1152 { 0x00000783, 0x0080 }, /* R1923 - AIF3TX1MIX Input 2 Volume */
1153 { 0x00000784, 0x0000 }, /* R1924 - AIF3TX1MIX Input 3 Source */
1154 { 0x00000785, 0x0080 }, /* R1925 - AIF3TX1MIX Input 3 Volume */
1155 { 0x00000786, 0x0000 }, /* R1926 - AIF3TX1MIX Input 4 Source */
1156 { 0x00000787, 0x0080 }, /* R1927 - AIF3TX1MIX Input 4 Volume */
1157 { 0x00000788, 0x0000 }, /* R1928 - AIF3TX2MIX Input 1 Source */
1158 { 0x00000789, 0x0080 }, /* R1929 - AIF3TX2MIX Input 1 Volume */
1159 { 0x0000078A, 0x0000 }, /* R1930 - AIF3TX2MIX Input 2 Source */
1160 { 0x0000078B, 0x0080 }, /* R1931 - AIF3TX2MIX Input 2 Volume */
1161 { 0x0000078C, 0x0000 }, /* R1932 - AIF3TX2MIX Input 3 Source */
1162 { 0x0000078D, 0x0080 }, /* R1933 - AIF3TX2MIX Input 3 Volume */
1163 { 0x0000078E, 0x0000 }, /* R1934 - AIF3TX2MIX Input 4 Source */
1164 { 0x0000078F, 0x0080 }, /* R1935 - AIF3TX2MIX Input 4 Volume */
1165 { 0x000007C0, 0x0000 }, /* R1984 - SLIMTX1MIX Input 1 Source */
1166 { 0x000007C1, 0x0080 }, /* R1985 - SLIMTX1MIX Input 1 Volume */
1167 { 0x000007C2, 0x0000 }, /* R1986 - SLIMTX1MIX Input 2 Source */
1168 { 0x000007C3, 0x0080 }, /* R1987 - SLIMTX1MIX Input 2 Volume */
1169 { 0x000007C4, 0x0000 }, /* R1988 - SLIMTX1MIX Input 3 Source */
1170 { 0x000007C5, 0x0080 }, /* R1989 - SLIMTX1MIX Input 3 Volume */
1171 { 0x000007C6, 0x0000 }, /* R1990 - SLIMTX1MIX Input 4 Source */
1172 { 0x000007C7, 0x0080 }, /* R1991 - SLIMTX1MIX Input 4 Volume */
1173 { 0x000007C8, 0x0000 }, /* R1992 - SLIMTX2MIX Input 1 Source */
1174 { 0x000007C9, 0x0080 }, /* R1993 - SLIMTX2MIX Input 1 Volume */
1175 { 0x000007CA, 0x0000 }, /* R1994 - SLIMTX2MIX Input 2 Source */
1176 { 0x000007CB, 0x0080 }, /* R1995 - SLIMTX2MIX Input 2 Volume */
1177 { 0x000007CC, 0x0000 }, /* R1996 - SLIMTX2MIX Input 3 Source */
1178 { 0x000007CD, 0x0080 }, /* R1997 - SLIMTX2MIX Input 3 Volume */
1179 { 0x000007CE, 0x0000 }, /* R1998 - SLIMTX2MIX Input 4 Source */
1180 { 0x000007CF, 0x0080 }, /* R1999 - SLIMTX2MIX Input 4 Volume */
1181 { 0x000007D0, 0x0000 }, /* R2000 - SLIMTX3MIX Input 1 Source */
1182 { 0x000007D1, 0x0080 }, /* R2001 - SLIMTX3MIX Input 1 Volume */
1183 { 0x000007D2, 0x0000 }, /* R2002 - SLIMTX3MIX Input 2 Source */
1184 { 0x000007D3, 0x0080 }, /* R2003 - SLIMTX3MIX Input 2 Volume */
1185 { 0x000007D4, 0x0000 }, /* R2004 - SLIMTX3MIX Input 3 Source */
1186 { 0x000007D5, 0x0080 }, /* R2005 - SLIMTX3MIX Input 3 Volume */
1187 { 0x000007D6, 0x0000 }, /* R2006 - SLIMTX3MIX Input 4 Source */
1188 { 0x000007D7, 0x0080 }, /* R2007 - SLIMTX3MIX Input 4 Volume */
1189 { 0x000007D8, 0x0000 }, /* R2008 - SLIMTX4MIX Input 1 Source */
1190 { 0x000007D9, 0x0080 }, /* R2009 - SLIMTX4MIX Input 1 Volume */
1191 { 0x000007DA, 0x0000 }, /* R2010 - SLIMTX4MIX Input 2 Source */
1192 { 0x000007DB, 0x0080 }, /* R2011 - SLIMTX4MIX Input 2 Volume */
1193 { 0x000007DC, 0x0000 }, /* R2012 - SLIMTX4MIX Input 3 Source */
1194 { 0x000007DD, 0x0080 }, /* R2013 - SLIMTX4MIX Input 3 Volume */
1195 { 0x000007DE, 0x0000 }, /* R2014 - SLIMTX4MIX Input 4 Source */
1196 { 0x000007DF, 0x0080 }, /* R2015 - SLIMTX4MIX Input 4 Volume */
1197 { 0x000007E0, 0x0000 }, /* R2016 - SLIMTX5MIX Input 1 Source */
1198 { 0x000007E1, 0x0080 }, /* R2017 - SLIMTX5MIX Input 1 Volume */
1199 { 0x000007E2, 0x0000 }, /* R2018 - SLIMTX5MIX Input 2 Source */
1200 { 0x000007E3, 0x0080 }, /* R2019 - SLIMTX5MIX Input 2 Volume */
1201 { 0x000007E4, 0x0000 }, /* R2020 - SLIMTX5MIX Input 3 Source */
1202 { 0x000007E5, 0x0080 }, /* R2021 - SLIMTX5MIX Input 3 Volume */
1203 { 0x000007E6, 0x0000 }, /* R2022 - SLIMTX5MIX Input 4 Source */
1204 { 0x000007E7, 0x0080 }, /* R2023 - SLIMTX5MIX Input 4 Volume */
1205 { 0x000007E8, 0x0000 }, /* R2024 - SLIMTX6MIX Input 1 Source */
1206 { 0x000007E9, 0x0080 }, /* R2025 - SLIMTX6MIX Input 1 Volume */
1207 { 0x000007EA, 0x0000 }, /* R2026 - SLIMTX6MIX Input 2 Source */
1208 { 0x000007EB, 0x0080 }, /* R2027 - SLIMTX6MIX Input 2 Volume */
1209 { 0x000007EC, 0x0000 }, /* R2028 - SLIMTX6MIX Input 3 Source */
1210 { 0x000007ED, 0x0080 }, /* R2029 - SLIMTX6MIX Input 3 Volume */
1211 { 0x000007EE, 0x0000 }, /* R2030 - SLIMTX6MIX Input 4 Source */
1212 { 0x000007EF, 0x0080 }, /* R2031 - SLIMTX6MIX Input 4 Volume */
1213 { 0x000007F0, 0x0000 }, /* R2032 - SLIMTX7MIX Input 1 Source */
1214 { 0x000007F1, 0x0080 }, /* R2033 - SLIMTX7MIX Input 1 Volume */
1215 { 0x000007F2, 0x0000 }, /* R2034 - SLIMTX7MIX Input 2 Source */
1216 { 0x000007F3, 0x0080 }, /* R2035 - SLIMTX7MIX Input 2 Volume */
1217 { 0x000007F4, 0x0000 }, /* R2036 - SLIMTX7MIX Input 3 Source */
1218 { 0x000007F5, 0x0080 }, /* R2037 - SLIMTX7MIX Input 3 Volume */
1219 { 0x000007F6, 0x0000 }, /* R2038 - SLIMTX7MIX Input 4 Source */
1220 { 0x000007F7, 0x0080 }, /* R2039 - SLIMTX7MIX Input 4 Volume */
1221 { 0x000007F8, 0x0000 }, /* R2040 - SLIMTX8MIX Input 1 Source */
1222 { 0x000007F9, 0x0080 }, /* R2041 - SLIMTX8MIX Input 1 Volume */
1223 { 0x000007FA, 0x0000 }, /* R2042 - SLIMTX8MIX Input 2 Source */
1224 { 0x000007FB, 0x0080 }, /* R2043 - SLIMTX8MIX Input 2 Volume */
1225 { 0x000007FC, 0x0000 }, /* R2044 - SLIMTX8MIX Input 3 Source */
1226 { 0x000007FD, 0x0080 }, /* R2045 - SLIMTX8MIX Input 3 Volume */
1227 { 0x000007FE, 0x0000 }, /* R2046 - SLIMTX8MIX Input 4 Source */
1228 { 0x000007FF, 0x0080 }, /* R2047 - SLIMTX8MIX Input 4 Volume */
1229 { 0x00000880, 0x0000 }, /* R2176 - EQ1MIX Input 1 Source */
1230 { 0x00000881, 0x0080 }, /* R2177 - EQ1MIX Input 1 Volume */
1231 { 0x00000882, 0x0000 }, /* R2178 - EQ1MIX Input 2 Source */
1232 { 0x00000883, 0x0080 }, /* R2179 - EQ1MIX Input 2 Volume */
1233 { 0x00000884, 0x0000 }, /* R2180 - EQ1MIX Input 3 Source */
1234 { 0x00000885, 0x0080 }, /* R2181 - EQ1MIX Input 3 Volume */
1235 { 0x00000886, 0x0000 }, /* R2182 - EQ1MIX Input 4 Source */
1236 { 0x00000887, 0x0080 }, /* R2183 - EQ1MIX Input 4 Volume */
1237 { 0x00000888, 0x0000 }, /* R2184 - EQ2MIX Input 1 Source */
1238 { 0x00000889, 0x0080 }, /* R2185 - EQ2MIX Input 1 Volume */
1239 { 0x0000088A, 0x0000 }, /* R2186 - EQ2MIX Input 2 Source */
1240 { 0x0000088B, 0x0080 }, /* R2187 - EQ2MIX Input 2 Volume */
1241 { 0x0000088C, 0x0000 }, /* R2188 - EQ2MIX Input 3 Source */
1242 { 0x0000088D, 0x0080 }, /* R2189 - EQ2MIX Input 3 Volume */
1243 { 0x0000088E, 0x0000 }, /* R2190 - EQ2MIX Input 4 Source */
1244 { 0x0000088F, 0x0080 }, /* R2191 - EQ2MIX Input 4 Volume */
1245 { 0x00000890, 0x0000 }, /* R2192 - EQ3MIX Input 1 Source */
1246 { 0x00000891, 0x0080 }, /* R2193 - EQ3MIX Input 1 Volume */
1247 { 0x00000892, 0x0000 }, /* R2194 - EQ3MIX Input 2 Source */
1248 { 0x00000893, 0x0080 }, /* R2195 - EQ3MIX Input 2 Volume */
1249 { 0x00000894, 0x0000 }, /* R2196 - EQ3MIX Input 3 Source */
1250 { 0x00000895, 0x0080 }, /* R2197 - EQ3MIX Input 3 Volume */
1251 { 0x00000896, 0x0000 }, /* R2198 - EQ3MIX Input 4 Source */
1252 { 0x00000897, 0x0080 }, /* R2199 - EQ3MIX Input 4 Volume */
1253 { 0x00000898, 0x0000 }, /* R2200 - EQ4MIX Input 1 Source */
1254 { 0x00000899, 0x0080 }, /* R2201 - EQ4MIX Input 1 Volume */
1255 { 0x0000089A, 0x0000 }, /* R2202 - EQ4MIX Input 2 Source */
1256 { 0x0000089B, 0x0080 }, /* R2203 - EQ4MIX Input 2 Volume */
1257 { 0x0000089C, 0x0000 }, /* R2204 - EQ4MIX Input 3 Source */
1258 { 0x0000089D, 0x0080 }, /* R2205 - EQ4MIX Input 3 Volume */
1259 { 0x0000089E, 0x0000 }, /* R2206 - EQ4MIX Input 4 Source */
1260 { 0x0000089F, 0x0080 }, /* R2207 - EQ4MIX Input 4 Volume */
1261 { 0x000008C0, 0x0000 }, /* R2240 - DRC1LMIX Input 1 Source */
1262 { 0x000008C1, 0x0080 }, /* R2241 - DRC1LMIX Input 1 Volume */
1263 { 0x000008C2, 0x0000 }, /* R2242 - DRC1LMIX Input 2 Source */
1264 { 0x000008C3, 0x0080 }, /* R2243 - DRC1LMIX Input 2 Volume */
1265 { 0x000008C4, 0x0000 }, /* R2244 - DRC1LMIX Input 3 Source */
1266 { 0x000008C5, 0x0080 }, /* R2245 - DRC1LMIX Input 3 Volume */
1267 { 0x000008C6, 0x0000 }, /* R2246 - DRC1LMIX Input 4 Source */
1268 { 0x000008C7, 0x0080 }, /* R2247 - DRC1LMIX Input 4 Volume */
1269 { 0x000008C8, 0x0000 }, /* R2248 - DRC1RMIX Input 1 Source */
1270 { 0x000008C9, 0x0080 }, /* R2249 - DRC1RMIX Input 1 Volume */
1271 { 0x000008CA, 0x0000 }, /* R2250 - DRC1RMIX Input 2 Source */
1272 { 0x000008CB, 0x0080 }, /* R2251 - DRC1RMIX Input 2 Volume */
1273 { 0x000008CC, 0x0000 }, /* R2252 - DRC1RMIX Input 3 Source */
1274 { 0x000008CD, 0x0080 }, /* R2253 - DRC1RMIX Input 3 Volume */
1275 { 0x000008CE, 0x0000 }, /* R2254 - DRC1RMIX Input 4 Source */
1276 { 0x000008CF, 0x0080 }, /* R2255 - DRC1RMIX Input 4 Volume */
1277 { 0x000008D0, 0x0000 }, /* R2256 - DRC2LMIX Input 1 Source */
1278 { 0x000008D1, 0x0080 }, /* R2257 - DRC2LMIX Input 1 Volume */
1279 { 0x000008D2, 0x0000 }, /* R2258 - DRC2LMIX Input 2 Source */
1280 { 0x000008D3, 0x0080 }, /* R2259 - DRC2LMIX Input 2 Volume */
1281 { 0x000008D4, 0x0000 }, /* R2260 - DRC2LMIX Input 3 Source */
1282 { 0x000008D5, 0x0080 }, /* R2261 - DRC2LMIX Input 3 Volume */
1283 { 0x000008D6, 0x0000 }, /* R2262 - DRC2LMIX Input 4 Source */
1284 { 0x000008D7, 0x0080 }, /* R2263 - DRC2LMIX Input 4 Volume */
1285 { 0x000008D8, 0x0000 }, /* R2264 - DRC2RMIX Input 1 Source */
1286 { 0x000008D9, 0x0080 }, /* R2265 - DRC2RMIX Input 1 Volume */
1287 { 0x000008DA, 0x0000 }, /* R2266 - DRC2RMIX Input 2 Source */
1288 { 0x000008DB, 0x0080 }, /* R2267 - DRC2RMIX Input 2 Volume */
1289 { 0x000008DC, 0x0000 }, /* R2268 - DRC2RMIX Input 3 Source */
1290 { 0x000008DD, 0x0080 }, /* R2269 - DRC2RMIX Input 3 Volume */
1291 { 0x000008DE, 0x0000 }, /* R2270 - DRC2RMIX Input 4 Source */
1292 { 0x000008DF, 0x0080 }, /* R2271 - DRC2RMIX Input 4 Volume */
1293 { 0x00000900, 0x0000 }, /* R2304 - HPLP1MIX Input 1 Source */
1294 { 0x00000901, 0x0080 }, /* R2305 - HPLP1MIX Input 1 Volume */
1295 { 0x00000902, 0x0000 }, /* R2306 - HPLP1MIX Input 2 Source */
1296 { 0x00000903, 0x0080 }, /* R2307 - HPLP1MIX Input 2 Volume */
1297 { 0x00000904, 0x0000 }, /* R2308 - HPLP1MIX Input 3 Source */
1298 { 0x00000905, 0x0080 }, /* R2309 - HPLP1MIX Input 3 Volume */
1299 { 0x00000906, 0x0000 }, /* R2310 - HPLP1MIX Input 4 Source */
1300 { 0x00000907, 0x0080 }, /* R2311 - HPLP1MIX Input 4 Volume */
1301 { 0x00000908, 0x0000 }, /* R2312 - HPLP2MIX Input 1 Source */
1302 { 0x00000909, 0x0080 }, /* R2313 - HPLP2MIX Input 1 Volume */
1303 { 0x0000090A, 0x0000 }, /* R2314 - HPLP2MIX Input 2 Source */
1304 { 0x0000090B, 0x0080 }, /* R2315 - HPLP2MIX Input 2 Volume */
1305 { 0x0000090C, 0x0000 }, /* R2316 - HPLP2MIX Input 3 Source */
1306 { 0x0000090D, 0x0080 }, /* R2317 - HPLP2MIX Input 3 Volume */
1307 { 0x0000090E, 0x0000 }, /* R2318 - HPLP2MIX Input 4 Source */
1308 { 0x0000090F, 0x0080 }, /* R2319 - HPLP2MIX Input 4 Volume */
1309 { 0x00000910, 0x0000 }, /* R2320 - HPLP3MIX Input 1 Source */
1310 { 0x00000911, 0x0080 }, /* R2321 - HPLP3MIX Input 1 Volume */
1311 { 0x00000912, 0x0000 }, /* R2322 - HPLP3MIX Input 2 Source */
1312 { 0x00000913, 0x0080 }, /* R2323 - HPLP3MIX Input 2 Volume */
1313 { 0x00000914, 0x0000 }, /* R2324 - HPLP3MIX Input 3 Source */
1314 { 0x00000915, 0x0080 }, /* R2325 - HPLP3MIX Input 3 Volume */
1315 { 0x00000916, 0x0000 }, /* R2326 - HPLP3MIX Input 4 Source */
1316 { 0x00000917, 0x0080 }, /* R2327 - HPLP3MIX Input 4 Volume */
1317 { 0x00000918, 0x0000 }, /* R2328 - HPLP4MIX Input 1 Source */
1318 { 0x00000919, 0x0080 }, /* R2329 - HPLP4MIX Input 1 Volume */
1319 { 0x0000091A, 0x0000 }, /* R2330 - HPLP4MIX Input 2 Source */
1320 { 0x0000091B, 0x0080 }, /* R2331 - HPLP4MIX Input 2 Volume */
1321 { 0x0000091C, 0x0000 }, /* R2332 - HPLP4MIX Input 3 Source */
1322 { 0x0000091D, 0x0080 }, /* R2333 - HPLP4MIX Input 3 Volume */
1323 { 0x0000091E, 0x0000 }, /* R2334 - HPLP4MIX Input 4 Source */
1324 { 0x0000091F, 0x0080 }, /* R2335 - HPLP4MIX Input 4 Volume */
1325 { 0x00000940, 0x0000 }, /* R2368 - DSP1LMIX Input 1 Source */
1326 { 0x00000941, 0x0080 }, /* R2369 - DSP1LMIX Input 1 Volume */
1327 { 0x00000942, 0x0000 }, /* R2370 - DSP1LMIX Input 2 Source */
1328 { 0x00000943, 0x0080 }, /* R2371 - DSP1LMIX Input 2 Volume */
1329 { 0x00000944, 0x0000 }, /* R2372 - DSP1LMIX Input 3 Source */
1330 { 0x00000945, 0x0080 }, /* R2373 - DSP1LMIX Input 3 Volume */
1331 { 0x00000946, 0x0000 }, /* R2374 - DSP1LMIX Input 4 Source */
1332 { 0x00000947, 0x0080 }, /* R2375 - DSP1LMIX Input 4 Volume */
1333 { 0x00000948, 0x0000 }, /* R2376 - DSP1RMIX Input 1 Source */
1334 { 0x00000949, 0x0080 }, /* R2377 - DSP1RMIX Input 1 Volume */
1335 { 0x0000094A, 0x0000 }, /* R2378 - DSP1RMIX Input 2 Source */
1336 { 0x0000094B, 0x0080 }, /* R2379 - DSP1RMIX Input 2 Volume */
1337 { 0x0000094C, 0x0000 }, /* R2380 - DSP1RMIX Input 3 Source */
1338 { 0x0000094D, 0x0080 }, /* R2381 - DSP1RMIX Input 3 Volume */
1339 { 0x0000094E, 0x0000 }, /* R2382 - DSP1RMIX Input 4 Source */
1340 { 0x0000094F, 0x0080 }, /* R2383 - DSP1RMIX Input 4 Volume */
1341 { 0x00000950, 0x0000 }, /* R2384 - DSP1AUX1MIX Input 1 Source */
1342 { 0x00000958, 0x0000 }, /* R2392 - DSP1AUX2MIX Input 1 Source */
1343 { 0x00000960, 0x0000 }, /* R2400 - DSP1AUX3MIX Input 1 Source */
1344 { 0x00000968, 0x0000 }, /* R2408 - DSP1AUX4MIX Input 1 Source */
1345 { 0x00000970, 0x0000 }, /* R2416 - DSP1AUX5MIX Input 1 Source */
1346 { 0x00000978, 0x0000 }, /* R2424 - DSP1AUX6MIX Input 1 Source */
1347 { 0x00000A80, 0x0000 }, /* R2688 - ASRC1LMIX Input 1 Source */
1348 { 0x00000A88, 0x0000 }, /* R2696 - ASRC1RMIX Input 1 Source */
1349 { 0x00000A90, 0x0000 }, /* R2704 - ASRC2LMIX Input 1 Source */
1350 { 0x00000A98, 0x0000 }, /* R2712 - ASRC2RMIX Input 1 Source */
1351 { 0x00000B00, 0x0000 }, /* R2816 - ISRC1DEC1MIX Input 1 Source */
1352 { 0x00000B08, 0x0000 }, /* R2824 - ISRC1DEC2MIX Input 1 Source */
1353 { 0x00000B20, 0x0000 }, /* R2848 - ISRC1INT1MIX Input 1 Source */
1354 { 0x00000B28, 0x0000 }, /* R2856 - ISRC1INT2MIX Input 1 Source */
1355 { 0x00000B40, 0x0000 }, /* R2880 - ISRC2DEC1MIX Input 1 Source */
1356 { 0x00000B48, 0x0000 }, /* R2888 - ISRC2DEC2MIX Input 1 Source */
1357 { 0x00000B60, 0x0000 }, /* R2912 - ISRC2INT1MIX Input 1 Source */
1358 { 0x00000B68, 0x0000 }, /* R2920 - ISRC2INT2MIX Input 1 Source */
1359 { 0x00000C00, 0xA101 }, /* R3072 - GPIO1 CTRL */
1360 { 0x00000C01, 0xA101 }, /* R3073 - GPIO2 CTRL */
1361 { 0x00000C02, 0xA101 }, /* R3074 - GPIO3 CTRL */
1362 { 0x00000C03, 0xA101 }, /* R3075 - GPIO4 CTRL */
1363 { 0x00000C04, 0xA101 }, /* R3076 - GPIO5 CTRL */
1364 { 0x00000C0F, 0x0400 }, /* R3087 - IRQ CTRL 1 */
1365 { 0x00000C10, 0x1000 }, /* R3088 - GPIO Debounce Config */
1366 { 0x00000C20, 0x8002 }, /* R3104 - Misc Pad Ctrl 1 */
1367 { 0x00000C21, 0x8001 }, /* R3105 - Misc Pad Ctrl 2 */
1368 { 0x00000C22, 0x0000 }, /* R3106 - Misc Pad Ctrl 3 */
1369 { 0x00000C23, 0x0000 }, /* R3107 - Misc Pad Ctrl 4 */
1370 { 0x00000C24, 0x0000 }, /* R3108 - Misc Pad Ctrl 5 */
1371 { 0x00000C25, 0x0000 }, /* R3109 - Misc Pad Ctrl 6 */
1372 { 0x00000D08, 0xFFFF }, /* R3336 - Interrupt Status 1 Mask */
1373 { 0x00000D09, 0xFFFF }, /* R3337 - Interrupt Status 2 Mask */
1374 { 0x00000D0A, 0xFFFF }, /* R3338 - Interrupt Status 3 Mask */
1375 { 0x00000D0B, 0xFFFF }, /* R3339 - Interrupt Status 4 Mask */
1376 { 0x00000D0C, 0xFEFF }, /* R3340 - Interrupt Status 5 Mask */
1377 { 0x00000D0F, 0x0000 }, /* R3343 - Interrupt Control */
1378 { 0x00000D18, 0xFFFF }, /* R3352 - IRQ2 Status 1 Mask */
1379 { 0x00000D19, 0xFFFF }, /* R3353 - IRQ2 Status 2 Mask */
1380 { 0x00000D1A, 0xFFFF }, /* R3354 - IRQ2 Status 3 Mask */
1381 { 0x00000D1B, 0xFFFF }, /* R3355 - IRQ2 Status 4 Mask */
1382 { 0x00000D1C, 0xFFFF }, /* R3356 - IRQ2 Status 5 Mask */
1383 { 0x00000D1F, 0x0000 }, /* R3359 - IRQ2 Control */
1384 { 0x00000D41, 0x0000 }, /* R3393 - ADSP2 IRQ0 */
1385 { 0x00000D53, 0xFFFF }, /* R3411 - AOD IRQ Mask IRQ1 */
1386 { 0x00000D54, 0xFFFF }, /* R3412 - AOD IRQ Mask IRQ2 */
1387 { 0x00000D56, 0x0000 }, /* R3414 - Jack detect debounce */
1388 { 0x00000E00, 0x0000 }, /* R3584 - FX_Ctrl1 */
1389 { 0x00000E01, 0x0000 }, /* R3585 - FX_Ctrl2 */
1390 { 0x00000E10, 0x6318 }, /* R3600 - EQ1_1 */
1391 { 0x00000E11, 0x6300 }, /* R3601 - EQ1_2 */
1392 { 0x00000E12, 0x0FC8 }, /* R3602 - EQ1_3 */
1393 { 0x00000E13, 0x03FE }, /* R3603 - EQ1_4 */
1394 { 0x00000E14, 0x00E0 }, /* R3604 - EQ1_5 */
1395 { 0x00000E15, 0x1EC4 }, /* R3605 - EQ1_6 */
1396 { 0x00000E16, 0xF136 }, /* R3606 - EQ1_7 */
1397 { 0x00000E17, 0x0409 }, /* R3607 - EQ1_8 */
1398 { 0x00000E18, 0x04CC }, /* R3608 - EQ1_9 */
1399 { 0x00000E19, 0x1C9B }, /* R3609 - EQ1_10 */
1400 { 0x00000E1A, 0xF337 }, /* R3610 - EQ1_11 */
1401 { 0x00000E1B, 0x040B }, /* R3611 - EQ1_12 */
1402 { 0x00000E1C, 0x0CBB }, /* R3612 - EQ1_13 */
1403 { 0x00000E1D, 0x16F8 }, /* R3613 - EQ1_14 */
1404 { 0x00000E1E, 0xF7D9 }, /* R3614 - EQ1_15 */
1405 { 0x00000E1F, 0x040A }, /* R3615 - EQ1_16 */
1406 { 0x00000E20, 0x1F14 }, /* R3616 - EQ1_17 */
1407 { 0x00000E21, 0x058C }, /* R3617 - EQ1_18 */
1408 { 0x00000E22, 0x0563 }, /* R3618 - EQ1_19 */
1409 { 0x00000E23, 0x4000 }, /* R3619 - EQ1_20 */
1410 { 0x00000E24, 0x0B75 }, /* R3620 - EQ1_21 */
1411 { 0x00000E26, 0x6318 }, /* R3622 - EQ2_1 */
1412 { 0x00000E27, 0x6300 }, /* R3623 - EQ2_2 */
1413 { 0x00000E28, 0x0FC8 }, /* R3624 - EQ2_3 */
1414 { 0x00000E29, 0x03FE }, /* R3625 - EQ2_4 */
1415 { 0x00000E2A, 0x00E0 }, /* R3626 - EQ2_5 */
1416 { 0x00000E2B, 0x1EC4 }, /* R3627 - EQ2_6 */
1417 { 0x00000E2C, 0xF136 }, /* R3628 - EQ2_7 */
1418 { 0x00000E2D, 0x0409 }, /* R3629 - EQ2_8 */
1419 { 0x00000E2E, 0x04CC }, /* R3630 - EQ2_9 */
1420 { 0x00000E2F, 0x1C9B }, /* R3631 - EQ2_10 */
1421 { 0x00000E30, 0xF337 }, /* R3632 - EQ2_11 */
1422 { 0x00000E31, 0x040B }, /* R3633 - EQ2_12 */
1423 { 0x00000E32, 0x0CBB }, /* R3634 - EQ2_13 */
1424 { 0x00000E33, 0x16F8 }, /* R3635 - EQ2_14 */
1425 { 0x00000E34, 0xF7D9 }, /* R3636 - EQ2_15 */
1426 { 0x00000E35, 0x040A }, /* R3637 - EQ2_16 */
1427 { 0x00000E36, 0x1F14 }, /* R3638 - EQ2_17 */
1428 { 0x00000E37, 0x058C }, /* R3639 - EQ2_18 */
1429 { 0x00000E38, 0x0563 }, /* R3640 - EQ2_19 */
1430 { 0x00000E39, 0x4000 }, /* R3641 - EQ2_20 */
1431 { 0x00000E3A, 0x0B75 }, /* R3642 - EQ2_21 */
1432 { 0x00000E3C, 0x6318 }, /* R3644 - EQ3_1 */
1433 { 0x00000E3D, 0x6300 }, /* R3645 - EQ3_2 */
1434 { 0x00000E3E, 0x0FC8 }, /* R3646 - EQ3_3 */
1435 { 0x00000E3F, 0x03FE }, /* R3647 - EQ3_4 */
1436 { 0x00000E40, 0x00E0 }, /* R3648 - EQ3_5 */
1437 { 0x00000E41, 0x1EC4 }, /* R3649 - EQ3_6 */
1438 { 0x00000E42, 0xF136 }, /* R3650 - EQ3_7 */
1439 { 0x00000E43, 0x0409 }, /* R3651 - EQ3_8 */
1440 { 0x00000E44, 0x04CC }, /* R3652 - EQ3_9 */
1441 { 0x00000E45, 0x1C9B }, /* R3653 - EQ3_10 */
1442 { 0x00000E46, 0xF337 }, /* R3654 - EQ3_11 */
1443 { 0x00000E47, 0x040B }, /* R3655 - EQ3_12 */
1444 { 0x00000E48, 0x0CBB }, /* R3656 - EQ3_13 */
1445 { 0x00000E49, 0x16F8 }, /* R3657 - EQ3_14 */
1446 { 0x00000E4A, 0xF7D9 }, /* R3658 - EQ3_15 */
1447 { 0x00000E4B, 0x040A }, /* R3659 - EQ3_16 */
1448 { 0x00000E4C, 0x1F14 }, /* R3660 - EQ3_17 */
1449 { 0x00000E4D, 0x058C }, /* R3661 - EQ3_18 */
1450 { 0x00000E4E, 0x0563 }, /* R3662 - EQ3_19 */
1451 { 0x00000E4F, 0x4000 }, /* R3663 - EQ3_20 */
1452 { 0x00000E50, 0x0B75 }, /* R3664 - EQ3_21 */
1453 { 0x00000E52, 0x6318 }, /* R3666 - EQ4_1 */
1454 { 0x00000E53, 0x6300 }, /* R3667 - EQ4_2 */
1455 { 0x00000E54, 0x0FC8 }, /* R3668 - EQ4_3 */
1456 { 0x00000E55, 0x03FE }, /* R3669 - EQ4_4 */
1457 { 0x00000E56, 0x00E0 }, /* R3670 - EQ4_5 */
1458 { 0x00000E57, 0x1EC4 }, /* R3671 - EQ4_6 */
1459 { 0x00000E58, 0xF136 }, /* R3672 - EQ4_7 */
1460 { 0x00000E59, 0x0409 }, /* R3673 - EQ4_8 */
1461 { 0x00000E5A, 0x04CC }, /* R3674 - EQ4_9 */
1462 { 0x00000E5B, 0x1C9B }, /* R3675 - EQ4_10 */
1463 { 0x00000E5C, 0xF337 }, /* R3676 - EQ4_11 */
1464 { 0x00000E5D, 0x040B }, /* R3677 - EQ4_12 */
1465 { 0x00000E5E, 0x0CBB }, /* R3678 - EQ4_13 */
1466 { 0x00000E5F, 0x16F8 }, /* R3679 - EQ4_14 */
1467 { 0x00000E60, 0xF7D9 }, /* R3680 - EQ4_15 */
1468 { 0x00000E61, 0x040A }, /* R3681 - EQ4_16 */
1469 { 0x00000E62, 0x1F14 }, /* R3682 - EQ4_17 */
1470 { 0x00000E63, 0x058C }, /* R3683 - EQ4_18 */
1471 { 0x00000E64, 0x0563 }, /* R3684 - EQ4_19 */
1472 { 0x00000E65, 0x4000 }, /* R3685 - EQ4_20 */
1473 { 0x00000E66, 0x0B75 }, /* R3686 - EQ4_21 */
1474 { 0x00000E80, 0x0018 }, /* R3712 - DRC1 ctrl1 */
1475 { 0x00000E81, 0x0933 }, /* R3713 - DRC1 ctrl2 */
1476 { 0x00000E82, 0x0018 }, /* R3714 - DRC1 ctrl3 */
1477 { 0x00000E83, 0x0000 }, /* R3715 - DRC1 ctrl4 */
1478 { 0x00000E84, 0x0000 }, /* R3716 - DRC1 ctrl5 */
1479 { 0x00000E89, 0x0018 }, /* R3721 - DRC2 ctrl1 */
1480 { 0x00000E8A, 0x0933 }, /* R3722 - DRC2 ctrl2 */
1481 { 0x00000E8B, 0x0018 }, /* R3723 - DRC2 ctrl3 */
1482 { 0x00000E8C, 0x0000 }, /* R3724 - DRC2 ctrl4 */
1483 { 0x00000E8D, 0x0000 }, /* R3725 - DRC2 ctrl5 */
1484 { 0x00000EC0, 0x0000 }, /* R3776 - HPLPF1_1 */
1485 { 0x00000EC1, 0x0000 }, /* R3777 - HPLPF1_2 */
1486 { 0x00000EC4, 0x0000 }, /* R3780 - HPLPF2_1 */
1487 { 0x00000EC5, 0x0000 }, /* R3781 - HPLPF2_2 */
1488 { 0x00000EC8, 0x0000 }, /* R3784 - HPLPF3_1 */
1489 { 0x00000EC9, 0x0000 }, /* R3785 - HPLPF3_2 */
1490 { 0x00000ECC, 0x0000 }, /* R3788 - HPLPF4_1 */
1491 { 0x00000ECD, 0x0000 }, /* R3789 - HPLPF4_2 */
1492 { 0x00000EE0, 0x0000 }, /* R3808 - ASRC_ENABLE */
1493 { 0x00000EE2, 0x0000 }, /* R3810 - ASRC_RATE1 */
1494 { 0x00000EE3, 0x4000 }, /* R3811 - ASRC_RATE2 */
1495 { 0x00000EF0, 0x0000 }, /* R3824 - ISRC 1 CTRL 1 */
1496 { 0x00000EF1, 0x0000 }, /* R3825 - ISRC 1 CTRL 2 */
1497 { 0x00000EF2, 0x0000 }, /* R3826 - ISRC 1 CTRL 3 */
1498 { 0x00000EF3, 0x0000 }, /* R3827 - ISRC 2 CTRL 1 */
1499 { 0x00000EF4, 0x0000 }, /* R3828 - ISRC 2 CTRL 2 */
1500 { 0x00000EF5, 0x0000 }, /* R3829 - ISRC 2 CTRL 3 */
1501 { 0x00000EF6, 0x0000 }, /* R3830 - ISRC 3 CTRL 1 */
1502 { 0x00000EF7, 0x0000 }, /* R3831 - ISRC 3 CTRL 2 */
1503 { 0x00000EF8, 0x0000 }, /* R3832 - ISRC 3 CTRL 3 */
1504 { 0x00001100, 0x0010 }, /* R4352 - DSP1 Control 1 */
1505 { 0x00001101, 0x0000 }, /* R4353 - DSP1 Clocking 1 */
1506};
1507
1508static bool wm5102_readable_register(struct device *dev, unsigned int reg)
1509{
1510 switch (reg) {
1511 case ARIZONA_SOFTWARE_RESET:
1512 case ARIZONA_DEVICE_REVISION:
1513 case ARIZONA_CTRL_IF_SPI_CFG_1:
1514 case ARIZONA_CTRL_IF_I2C1_CFG_1:
1515 case ARIZONA_CTRL_IF_STATUS_1:
1516 case ARIZONA_WRITE_SEQUENCER_CTRL_0:
1517 case ARIZONA_WRITE_SEQUENCER_CTRL_1:
1518 case ARIZONA_WRITE_SEQUENCER_CTRL_2:
1519 case ARIZONA_WRITE_SEQUENCER_PROM:
1520 case ARIZONA_TONE_GENERATOR_1:
1521 case ARIZONA_TONE_GENERATOR_2:
1522 case ARIZONA_TONE_GENERATOR_3:
1523 case ARIZONA_TONE_GENERATOR_4:
1524 case ARIZONA_TONE_GENERATOR_5:
1525 case ARIZONA_PWM_DRIVE_1:
1526 case ARIZONA_PWM_DRIVE_2:
1527 case ARIZONA_PWM_DRIVE_3:
1528 case ARIZONA_WAKE_CONTROL:
1529 case ARIZONA_SEQUENCE_CONTROL:
1530 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1:
1531 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2:
1532 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3:
1533 case ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4:
1534 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1:
1535 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2:
1536 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3:
1537 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4:
1538 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5:
1539 case ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6:
1540 case ARIZONA_COMFORT_NOISE_GENERATOR:
1541 case ARIZONA_HAPTICS_CONTROL_1:
1542 case ARIZONA_HAPTICS_CONTROL_2:
1543 case ARIZONA_HAPTICS_PHASE_1_INTENSITY:
1544 case ARIZONA_HAPTICS_PHASE_1_DURATION:
1545 case ARIZONA_HAPTICS_PHASE_2_INTENSITY:
1546 case ARIZONA_HAPTICS_PHASE_2_DURATION:
1547 case ARIZONA_HAPTICS_PHASE_3_INTENSITY:
1548 case ARIZONA_HAPTICS_PHASE_3_DURATION:
1549 case ARIZONA_HAPTICS_STATUS:
1550 case ARIZONA_CLOCK_32K_1:
1551 case ARIZONA_SYSTEM_CLOCK_1:
1552 case ARIZONA_SAMPLE_RATE_1:
1553 case ARIZONA_SAMPLE_RATE_2:
1554 case ARIZONA_SAMPLE_RATE_3:
1555 case ARIZONA_SAMPLE_RATE_1_STATUS:
1556 case ARIZONA_SAMPLE_RATE_2_STATUS:
1557 case ARIZONA_SAMPLE_RATE_3_STATUS:
1558 case ARIZONA_ASYNC_CLOCK_1:
1559 case ARIZONA_ASYNC_SAMPLE_RATE_1:
1560 case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
1561 case ARIZONA_OUTPUT_SYSTEM_CLOCK:
1562 case ARIZONA_OUTPUT_ASYNC_CLOCK:
1563 case ARIZONA_RATE_ESTIMATOR_1:
1564 case ARIZONA_RATE_ESTIMATOR_2:
1565 case ARIZONA_RATE_ESTIMATOR_3:
1566 case ARIZONA_RATE_ESTIMATOR_4:
1567 case ARIZONA_RATE_ESTIMATOR_5:
1568 case ARIZONA_FLL1_CONTROL_1:
1569 case ARIZONA_FLL1_CONTROL_2:
1570 case ARIZONA_FLL1_CONTROL_3:
1571 case ARIZONA_FLL1_CONTROL_4:
1572 case ARIZONA_FLL1_CONTROL_5:
1573 case ARIZONA_FLL1_CONTROL_6:
1574 case ARIZONA_FLL1_LOOP_FILTER_TEST_1:
1575 case ARIZONA_FLL1_SYNCHRONISER_1:
1576 case ARIZONA_FLL1_SYNCHRONISER_2:
1577 case ARIZONA_FLL1_SYNCHRONISER_3:
1578 case ARIZONA_FLL1_SYNCHRONISER_4:
1579 case ARIZONA_FLL1_SYNCHRONISER_5:
1580 case ARIZONA_FLL1_SYNCHRONISER_6:
1581 case ARIZONA_FLL1_SPREAD_SPECTRUM:
1582 case ARIZONA_FLL1_GPIO_CLOCK:
1583 case ARIZONA_FLL2_CONTROL_1:
1584 case ARIZONA_FLL2_CONTROL_2:
1585 case ARIZONA_FLL2_CONTROL_3:
1586 case ARIZONA_FLL2_CONTROL_4:
1587 case ARIZONA_FLL2_CONTROL_5:
1588 case ARIZONA_FLL2_CONTROL_6:
1589 case ARIZONA_FLL2_LOOP_FILTER_TEST_1:
1590 case ARIZONA_FLL2_SYNCHRONISER_1:
1591 case ARIZONA_FLL2_SYNCHRONISER_2:
1592 case ARIZONA_FLL2_SYNCHRONISER_3:
1593 case ARIZONA_FLL2_SYNCHRONISER_4:
1594 case ARIZONA_FLL2_SYNCHRONISER_5:
1595 case ARIZONA_FLL2_SYNCHRONISER_6:
1596 case ARIZONA_FLL2_SPREAD_SPECTRUM:
1597 case ARIZONA_FLL2_GPIO_CLOCK:
1598 case ARIZONA_MIC_CHARGE_PUMP_1:
1599 case ARIZONA_LDO1_CONTROL_1:
1600 case ARIZONA_LDO2_CONTROL_1:
1601 case ARIZONA_MIC_BIAS_CTRL_1:
1602 case ARIZONA_MIC_BIAS_CTRL_2:
1603 case ARIZONA_MIC_BIAS_CTRL_3:
1604 case ARIZONA_ACCESSORY_DETECT_MODE_1:
1605 case ARIZONA_HEADPHONE_DETECT_1:
1606 case ARIZONA_HEADPHONE_DETECT_2:
1607 case ARIZONA_MIC_DETECT_1:
1608 case ARIZONA_MIC_DETECT_2:
1609 case ARIZONA_MIC_DETECT_3:
1610 case ARIZONA_MIC_NOISE_MIX_CONTROL_1:
1611 case ARIZONA_ISOLATION_CONTROL:
1612 case ARIZONA_JACK_DETECT_ANALOGUE:
1613 case ARIZONA_INPUT_ENABLES:
1614 case ARIZONA_INPUT_RATE:
1615 case ARIZONA_INPUT_VOLUME_RAMP:
1616 case ARIZONA_IN1L_CONTROL:
1617 case ARIZONA_ADC_DIGITAL_VOLUME_1L:
1618 case ARIZONA_DMIC1L_CONTROL:
1619 case ARIZONA_IN1R_CONTROL:
1620 case ARIZONA_ADC_DIGITAL_VOLUME_1R:
1621 case ARIZONA_DMIC1R_CONTROL:
1622 case ARIZONA_IN2L_CONTROL:
1623 case ARIZONA_ADC_DIGITAL_VOLUME_2L:
1624 case ARIZONA_DMIC2L_CONTROL:
1625 case ARIZONA_IN2R_CONTROL:
1626 case ARIZONA_ADC_DIGITAL_VOLUME_2R:
1627 case ARIZONA_DMIC2R_CONTROL:
1628 case ARIZONA_IN3L_CONTROL:
1629 case ARIZONA_ADC_DIGITAL_VOLUME_3L:
1630 case ARIZONA_DMIC3L_CONTROL:
1631 case ARIZONA_IN3R_CONTROL:
1632 case ARIZONA_ADC_DIGITAL_VOLUME_3R:
1633 case ARIZONA_DMIC3R_CONTROL:
1634 case ARIZONA_OUTPUT_ENABLES_1:
1635 case ARIZONA_OUTPUT_STATUS_1:
1636 case ARIZONA_OUTPUT_RATE_1:
1637 case ARIZONA_OUTPUT_VOLUME_RAMP:
1638 case ARIZONA_OUTPUT_PATH_CONFIG_1L:
1639 case ARIZONA_DAC_DIGITAL_VOLUME_1L:
1640 case ARIZONA_DAC_VOLUME_LIMIT_1L:
1641 case ARIZONA_NOISE_GATE_SELECT_1L:
1642 case ARIZONA_OUTPUT_PATH_CONFIG_1R:
1643 case ARIZONA_DAC_DIGITAL_VOLUME_1R:
1644 case ARIZONA_DAC_VOLUME_LIMIT_1R:
1645 case ARIZONA_NOISE_GATE_SELECT_1R:
1646 case ARIZONA_OUTPUT_PATH_CONFIG_2L:
1647 case ARIZONA_DAC_DIGITAL_VOLUME_2L:
1648 case ARIZONA_DAC_VOLUME_LIMIT_2L:
1649 case ARIZONA_NOISE_GATE_SELECT_2L:
1650 case ARIZONA_OUTPUT_PATH_CONFIG_2R:
1651 case ARIZONA_DAC_DIGITAL_VOLUME_2R:
1652 case ARIZONA_DAC_VOLUME_LIMIT_2R:
1653 case ARIZONA_NOISE_GATE_SELECT_2R:
1654 case ARIZONA_OUTPUT_PATH_CONFIG_3L:
1655 case ARIZONA_DAC_DIGITAL_VOLUME_3L:
1656 case ARIZONA_DAC_VOLUME_LIMIT_3L:
1657 case ARIZONA_NOISE_GATE_SELECT_3L:
1658 case ARIZONA_OUTPUT_PATH_CONFIG_3R:
1659 case ARIZONA_DAC_DIGITAL_VOLUME_3R:
1660 case ARIZONA_DAC_VOLUME_LIMIT_3R:
1661 case ARIZONA_OUTPUT_PATH_CONFIG_4L:
1662 case ARIZONA_DAC_DIGITAL_VOLUME_4L:
1663 case ARIZONA_OUT_VOLUME_4L:
1664 case ARIZONA_NOISE_GATE_SELECT_4L:
1665 case ARIZONA_OUTPUT_PATH_CONFIG_4R:
1666 case ARIZONA_DAC_DIGITAL_VOLUME_4R:
1667 case ARIZONA_OUT_VOLUME_4R:
1668 case ARIZONA_NOISE_GATE_SELECT_4R:
1669 case ARIZONA_OUTPUT_PATH_CONFIG_5L:
1670 case ARIZONA_DAC_DIGITAL_VOLUME_5L:
1671 case ARIZONA_DAC_VOLUME_LIMIT_5L:
1672 case ARIZONA_NOISE_GATE_SELECT_5L:
1673 case ARIZONA_OUTPUT_PATH_CONFIG_5R:
1674 case ARIZONA_DAC_DIGITAL_VOLUME_5R:
1675 case ARIZONA_DAC_VOLUME_LIMIT_5R:
1676 case ARIZONA_NOISE_GATE_SELECT_5R:
1677 case ARIZONA_DAC_AEC_CONTROL_1:
1678 case ARIZONA_NOISE_GATE_CONTROL:
1679 case ARIZONA_PDM_SPK1_CTRL_1:
1680 case ARIZONA_PDM_SPK1_CTRL_2:
1681 case ARIZONA_DAC_COMP_1:
1682 case ARIZONA_DAC_COMP_2:
1683 case ARIZONA_DAC_COMP_3:
1684 case ARIZONA_DAC_COMP_4:
1685 case ARIZONA_AIF1_BCLK_CTRL:
1686 case ARIZONA_AIF1_TX_PIN_CTRL:
1687 case ARIZONA_AIF1_RX_PIN_CTRL:
1688 case ARIZONA_AIF1_RATE_CTRL:
1689 case ARIZONA_AIF1_FORMAT:
1690 case ARIZONA_AIF1_TX_BCLK_RATE:
1691 case ARIZONA_AIF1_RX_BCLK_RATE:
1692 case ARIZONA_AIF1_FRAME_CTRL_1:
1693 case ARIZONA_AIF1_FRAME_CTRL_2:
1694 case ARIZONA_AIF1_FRAME_CTRL_3:
1695 case ARIZONA_AIF1_FRAME_CTRL_4:
1696 case ARIZONA_AIF1_FRAME_CTRL_5:
1697 case ARIZONA_AIF1_FRAME_CTRL_6:
1698 case ARIZONA_AIF1_FRAME_CTRL_7:
1699 case ARIZONA_AIF1_FRAME_CTRL_8:
1700 case ARIZONA_AIF1_FRAME_CTRL_9:
1701 case ARIZONA_AIF1_FRAME_CTRL_10:
1702 case ARIZONA_AIF1_FRAME_CTRL_11:
1703 case ARIZONA_AIF1_FRAME_CTRL_12:
1704 case ARIZONA_AIF1_FRAME_CTRL_13:
1705 case ARIZONA_AIF1_FRAME_CTRL_14:
1706 case ARIZONA_AIF1_FRAME_CTRL_15:
1707 case ARIZONA_AIF1_FRAME_CTRL_16:
1708 case ARIZONA_AIF1_FRAME_CTRL_17:
1709 case ARIZONA_AIF1_FRAME_CTRL_18:
1710 case ARIZONA_AIF1_TX_ENABLES:
1711 case ARIZONA_AIF1_RX_ENABLES:
1712 case ARIZONA_AIF1_FORCE_WRITE:
1713 case ARIZONA_AIF2_BCLK_CTRL:
1714 case ARIZONA_AIF2_TX_PIN_CTRL:
1715 case ARIZONA_AIF2_RX_PIN_CTRL:
1716 case ARIZONA_AIF2_RATE_CTRL:
1717 case ARIZONA_AIF2_FORMAT:
1718 case ARIZONA_AIF2_TX_BCLK_RATE:
1719 case ARIZONA_AIF2_RX_BCLK_RATE:
1720 case ARIZONA_AIF2_FRAME_CTRL_1:
1721 case ARIZONA_AIF2_FRAME_CTRL_2:
1722 case ARIZONA_AIF2_FRAME_CTRL_3:
1723 case ARIZONA_AIF2_FRAME_CTRL_4:
1724 case ARIZONA_AIF2_FRAME_CTRL_11:
1725 case ARIZONA_AIF2_FRAME_CTRL_12:
1726 case ARIZONA_AIF2_TX_ENABLES:
1727 case ARIZONA_AIF2_RX_ENABLES:
1728 case ARIZONA_AIF2_FORCE_WRITE:
1729 case ARIZONA_AIF3_BCLK_CTRL:
1730 case ARIZONA_AIF3_TX_PIN_CTRL:
1731 case ARIZONA_AIF3_RX_PIN_CTRL:
1732 case ARIZONA_AIF3_RATE_CTRL:
1733 case ARIZONA_AIF3_FORMAT:
1734 case ARIZONA_AIF3_TX_BCLK_RATE:
1735 case ARIZONA_AIF3_RX_BCLK_RATE:
1736 case ARIZONA_AIF3_FRAME_CTRL_1:
1737 case ARIZONA_AIF3_FRAME_CTRL_2:
1738 case ARIZONA_AIF3_FRAME_CTRL_3:
1739 case ARIZONA_AIF3_FRAME_CTRL_4:
1740 case ARIZONA_AIF3_FRAME_CTRL_11:
1741 case ARIZONA_AIF3_FRAME_CTRL_12:
1742 case ARIZONA_AIF3_TX_ENABLES:
1743 case ARIZONA_AIF3_RX_ENABLES:
1744 case ARIZONA_AIF3_FORCE_WRITE:
1745 case ARIZONA_SLIMBUS_FRAMER_REF_GEAR:
1746 case ARIZONA_SLIMBUS_RATES_1:
1747 case ARIZONA_SLIMBUS_RATES_2:
1748 case ARIZONA_SLIMBUS_RATES_3:
1749 case ARIZONA_SLIMBUS_RATES_4:
1750 case ARIZONA_SLIMBUS_RATES_5:
1751 case ARIZONA_SLIMBUS_RATES_6:
1752 case ARIZONA_SLIMBUS_RATES_7:
1753 case ARIZONA_SLIMBUS_RATES_8:
1754 case ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE:
1755 case ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE:
1756 case ARIZONA_SLIMBUS_RX_PORT_STATUS:
1757 case ARIZONA_SLIMBUS_TX_PORT_STATUS:
1758 case ARIZONA_PWM1MIX_INPUT_1_SOURCE:
1759 case ARIZONA_PWM1MIX_INPUT_1_VOLUME:
1760 case ARIZONA_PWM1MIX_INPUT_2_SOURCE:
1761 case ARIZONA_PWM1MIX_INPUT_2_VOLUME:
1762 case ARIZONA_PWM1MIX_INPUT_3_SOURCE:
1763 case ARIZONA_PWM1MIX_INPUT_3_VOLUME:
1764 case ARIZONA_PWM1MIX_INPUT_4_SOURCE:
1765 case ARIZONA_PWM1MIX_INPUT_4_VOLUME:
1766 case ARIZONA_PWM2MIX_INPUT_1_SOURCE:
1767 case ARIZONA_PWM2MIX_INPUT_1_VOLUME:
1768 case ARIZONA_PWM2MIX_INPUT_2_SOURCE:
1769 case ARIZONA_PWM2MIX_INPUT_2_VOLUME:
1770 case ARIZONA_PWM2MIX_INPUT_3_SOURCE:
1771 case ARIZONA_PWM2MIX_INPUT_3_VOLUME:
1772 case ARIZONA_PWM2MIX_INPUT_4_SOURCE:
1773 case ARIZONA_PWM2MIX_INPUT_4_VOLUME:
1774 case ARIZONA_MICMIX_INPUT_1_SOURCE:
1775 case ARIZONA_MICMIX_INPUT_1_VOLUME:
1776 case ARIZONA_MICMIX_INPUT_2_SOURCE:
1777 case ARIZONA_MICMIX_INPUT_2_VOLUME:
1778 case ARIZONA_MICMIX_INPUT_3_SOURCE:
1779 case ARIZONA_MICMIX_INPUT_3_VOLUME:
1780 case ARIZONA_MICMIX_INPUT_4_SOURCE:
1781 case ARIZONA_MICMIX_INPUT_4_VOLUME:
1782 case ARIZONA_NOISEMIX_INPUT_1_SOURCE:
1783 case ARIZONA_NOISEMIX_INPUT_1_VOLUME:
1784 case ARIZONA_NOISEMIX_INPUT_2_SOURCE:
1785 case ARIZONA_NOISEMIX_INPUT_2_VOLUME:
1786 case ARIZONA_NOISEMIX_INPUT_3_SOURCE:
1787 case ARIZONA_NOISEMIX_INPUT_3_VOLUME:
1788 case ARIZONA_NOISEMIX_INPUT_4_SOURCE:
1789 case ARIZONA_NOISEMIX_INPUT_4_VOLUME:
1790 case ARIZONA_OUT1LMIX_INPUT_1_SOURCE:
1791 case ARIZONA_OUT1LMIX_INPUT_1_VOLUME:
1792 case ARIZONA_OUT1LMIX_INPUT_2_SOURCE:
1793 case ARIZONA_OUT1LMIX_INPUT_2_VOLUME:
1794 case ARIZONA_OUT1LMIX_INPUT_3_SOURCE:
1795 case ARIZONA_OUT1LMIX_INPUT_3_VOLUME:
1796 case ARIZONA_OUT1LMIX_INPUT_4_SOURCE:
1797 case ARIZONA_OUT1LMIX_INPUT_4_VOLUME:
1798 case ARIZONA_OUT1RMIX_INPUT_1_SOURCE:
1799 case ARIZONA_OUT1RMIX_INPUT_1_VOLUME:
1800 case ARIZONA_OUT1RMIX_INPUT_2_SOURCE:
1801 case ARIZONA_OUT1RMIX_INPUT_2_VOLUME:
1802 case ARIZONA_OUT1RMIX_INPUT_3_SOURCE:
1803 case ARIZONA_OUT1RMIX_INPUT_3_VOLUME:
1804 case ARIZONA_OUT1RMIX_INPUT_4_SOURCE:
1805 case ARIZONA_OUT1RMIX_INPUT_4_VOLUME:
1806 case ARIZONA_OUT2LMIX_INPUT_1_SOURCE:
1807 case ARIZONA_OUT2LMIX_INPUT_1_VOLUME:
1808 case ARIZONA_OUT2LMIX_INPUT_2_SOURCE:
1809 case ARIZONA_OUT2LMIX_INPUT_2_VOLUME:
1810 case ARIZONA_OUT2LMIX_INPUT_3_SOURCE:
1811 case ARIZONA_OUT2LMIX_INPUT_3_VOLUME:
1812 case ARIZONA_OUT2LMIX_INPUT_4_SOURCE:
1813 case ARIZONA_OUT2LMIX_INPUT_4_VOLUME:
1814 case ARIZONA_OUT2RMIX_INPUT_1_SOURCE:
1815 case ARIZONA_OUT2RMIX_INPUT_1_VOLUME:
1816 case ARIZONA_OUT2RMIX_INPUT_2_SOURCE:
1817 case ARIZONA_OUT2RMIX_INPUT_2_VOLUME:
1818 case ARIZONA_OUT2RMIX_INPUT_3_SOURCE:
1819 case ARIZONA_OUT2RMIX_INPUT_3_VOLUME:
1820 case ARIZONA_OUT2RMIX_INPUT_4_SOURCE:
1821 case ARIZONA_OUT2RMIX_INPUT_4_VOLUME:
1822 case ARIZONA_OUT3LMIX_INPUT_1_SOURCE:
1823 case ARIZONA_OUT3LMIX_INPUT_1_VOLUME:
1824 case ARIZONA_OUT3LMIX_INPUT_2_SOURCE:
1825 case ARIZONA_OUT3LMIX_INPUT_2_VOLUME:
1826 case ARIZONA_OUT3LMIX_INPUT_3_SOURCE:
1827 case ARIZONA_OUT3LMIX_INPUT_3_VOLUME:
1828 case ARIZONA_OUT3LMIX_INPUT_4_SOURCE:
1829 case ARIZONA_OUT3LMIX_INPUT_4_VOLUME:
1830 case ARIZONA_OUT4LMIX_INPUT_1_SOURCE:
1831 case ARIZONA_OUT4LMIX_INPUT_1_VOLUME:
1832 case ARIZONA_OUT4LMIX_INPUT_2_SOURCE:
1833 case ARIZONA_OUT4LMIX_INPUT_2_VOLUME:
1834 case ARIZONA_OUT4LMIX_INPUT_3_SOURCE:
1835 case ARIZONA_OUT4LMIX_INPUT_3_VOLUME:
1836 case ARIZONA_OUT4LMIX_INPUT_4_SOURCE:
1837 case ARIZONA_OUT4LMIX_INPUT_4_VOLUME:
1838 case ARIZONA_OUT4RMIX_INPUT_1_SOURCE:
1839 case ARIZONA_OUT4RMIX_INPUT_1_VOLUME:
1840 case ARIZONA_OUT4RMIX_INPUT_2_SOURCE:
1841 case ARIZONA_OUT4RMIX_INPUT_2_VOLUME:
1842 case ARIZONA_OUT4RMIX_INPUT_3_SOURCE:
1843 case ARIZONA_OUT4RMIX_INPUT_3_VOLUME:
1844 case ARIZONA_OUT4RMIX_INPUT_4_SOURCE:
1845 case ARIZONA_OUT4RMIX_INPUT_4_VOLUME:
1846 case ARIZONA_OUT5LMIX_INPUT_1_SOURCE:
1847 case ARIZONA_OUT5LMIX_INPUT_1_VOLUME:
1848 case ARIZONA_OUT5LMIX_INPUT_2_SOURCE:
1849 case ARIZONA_OUT5LMIX_INPUT_2_VOLUME:
1850 case ARIZONA_OUT5LMIX_INPUT_3_SOURCE:
1851 case ARIZONA_OUT5LMIX_INPUT_3_VOLUME:
1852 case ARIZONA_OUT5LMIX_INPUT_4_SOURCE:
1853 case ARIZONA_OUT5LMIX_INPUT_4_VOLUME:
1854 case ARIZONA_OUT5RMIX_INPUT_1_SOURCE:
1855 case ARIZONA_OUT5RMIX_INPUT_1_VOLUME:
1856 case ARIZONA_OUT5RMIX_INPUT_2_SOURCE:
1857 case ARIZONA_OUT5RMIX_INPUT_2_VOLUME:
1858 case ARIZONA_OUT5RMIX_INPUT_3_SOURCE:
1859 case ARIZONA_OUT5RMIX_INPUT_3_VOLUME:
1860 case ARIZONA_OUT5RMIX_INPUT_4_SOURCE:
1861 case ARIZONA_OUT5RMIX_INPUT_4_VOLUME:
1862 case ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE:
1863 case ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME:
1864 case ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE:
1865 case ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME:
1866 case ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE:
1867 case ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME:
1868 case ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE:
1869 case ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME:
1870 case ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE:
1871 case ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME:
1872 case ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE:
1873 case ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME:
1874 case ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE:
1875 case ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME:
1876 case ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE:
1877 case ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME:
1878 case ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE:
1879 case ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME:
1880 case ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE:
1881 case ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME:
1882 case ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE:
1883 case ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME:
1884 case ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE:
1885 case ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME:
1886 case ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE:
1887 case ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME:
1888 case ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE:
1889 case ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME:
1890 case ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE:
1891 case ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME:
1892 case ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE:
1893 case ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME:
1894 case ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE:
1895 case ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME:
1896 case ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE:
1897 case ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME:
1898 case ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE:
1899 case ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME:
1900 case ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE:
1901 case ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME:
1902 case ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE:
1903 case ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME:
1904 case ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE:
1905 case ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME:
1906 case ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE:
1907 case ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME:
1908 case ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE:
1909 case ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME:
1910 case ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE:
1911 case ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME:
1912 case ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE:
1913 case ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME:
1914 case ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE:
1915 case ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME:
1916 case ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE:
1917 case ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME:
1918 case ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE:
1919 case ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME:
1920 case ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE:
1921 case ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME:
1922 case ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE:
1923 case ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME:
1924 case ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE:
1925 case ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME:
1926 case ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE:
1927 case ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME:
1928 case ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE:
1929 case ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME:
1930 case ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE:
1931 case ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME:
1932 case ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE:
1933 case ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME:
1934 case ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE:
1935 case ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME:
1936 case ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE:
1937 case ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME:
1938 case ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE:
1939 case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME:
1940 case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE:
1941 case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME:
1942 case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE:
1943 case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME:
1944 case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE:
1945 case ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME:
1946 case ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE:
1947 case ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME:
1948 case ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE:
1949 case ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME:
1950 case ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE:
1951 case ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME:
1952 case ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE:
1953 case ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME:
1954 case ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE:
1955 case ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME:
1956 case ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE:
1957 case ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME:
1958 case ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE:
1959 case ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME:
1960 case ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE:
1961 case ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME:
1962 case ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE:
1963 case ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME:
1964 case ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE:
1965 case ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME:
1966 case ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE:
1967 case ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME:
1968 case ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE:
1969 case ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME:
1970 case ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE:
1971 case ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME:
1972 case ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE:
1973 case ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME:
1974 case ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE:
1975 case ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME:
1976 case ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE:
1977 case ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME:
1978 case ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE:
1979 case ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME:
1980 case ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE:
1981 case ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME:
1982 case ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE:
1983 case ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME:
1984 case ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE:
1985 case ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME:
1986 case ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE:
1987 case ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME:
1988 case ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE:
1989 case ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME:
1990 case ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE:
1991 case ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME:
1992 case ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE:
1993 case ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME:
1994 case ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE:
1995 case ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME:
1996 case ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE:
1997 case ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME:
1998 case ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE:
1999 case ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME:
2000 case ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE:
2001 case ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME:
2002 case ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE:
2003 case ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME:
2004 case ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE:
2005 case ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME:
2006 case ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE:
2007 case ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME:
2008 case ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE:
2009 case ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME:
2010 case ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE:
2011 case ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME:
2012 case ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE:
2013 case ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME:
2014 case ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE:
2015 case ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME:
2016 case ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE:
2017 case ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME:
2018 case ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE:
2019 case ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME:
2020 case ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE:
2021 case ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME:
2022 case ARIZONA_EQ1MIX_INPUT_1_SOURCE:
2023 case ARIZONA_EQ1MIX_INPUT_1_VOLUME:
2024 case ARIZONA_EQ1MIX_INPUT_2_SOURCE:
2025 case ARIZONA_EQ1MIX_INPUT_2_VOLUME:
2026 case ARIZONA_EQ1MIX_INPUT_3_SOURCE:
2027 case ARIZONA_EQ1MIX_INPUT_3_VOLUME:
2028 case ARIZONA_EQ1MIX_INPUT_4_SOURCE:
2029 case ARIZONA_EQ1MIX_INPUT_4_VOLUME:
2030 case ARIZONA_EQ2MIX_INPUT_1_SOURCE:
2031 case ARIZONA_EQ2MIX_INPUT_1_VOLUME:
2032 case ARIZONA_EQ2MIX_INPUT_2_SOURCE:
2033 case ARIZONA_EQ2MIX_INPUT_2_VOLUME:
2034 case ARIZONA_EQ2MIX_INPUT_3_SOURCE:
2035 case ARIZONA_EQ2MIX_INPUT_3_VOLUME:
2036 case ARIZONA_EQ2MIX_INPUT_4_SOURCE:
2037 case ARIZONA_EQ2MIX_INPUT_4_VOLUME:
2038 case ARIZONA_EQ3MIX_INPUT_1_SOURCE:
2039 case ARIZONA_EQ3MIX_INPUT_1_VOLUME:
2040 case ARIZONA_EQ3MIX_INPUT_2_SOURCE:
2041 case ARIZONA_EQ3MIX_INPUT_2_VOLUME:
2042 case ARIZONA_EQ3MIX_INPUT_3_SOURCE:
2043 case ARIZONA_EQ3MIX_INPUT_3_VOLUME:
2044 case ARIZONA_EQ3MIX_INPUT_4_SOURCE:
2045 case ARIZONA_EQ3MIX_INPUT_4_VOLUME:
2046 case ARIZONA_EQ4MIX_INPUT_1_SOURCE:
2047 case ARIZONA_EQ4MIX_INPUT_1_VOLUME:
2048 case ARIZONA_EQ4MIX_INPUT_2_SOURCE:
2049 case ARIZONA_EQ4MIX_INPUT_2_VOLUME:
2050 case ARIZONA_EQ4MIX_INPUT_3_SOURCE:
2051 case ARIZONA_EQ4MIX_INPUT_3_VOLUME:
2052 case ARIZONA_EQ4MIX_INPUT_4_SOURCE:
2053 case ARIZONA_EQ4MIX_INPUT_4_VOLUME:
2054 case ARIZONA_DRC1LMIX_INPUT_1_SOURCE:
2055 case ARIZONA_DRC1LMIX_INPUT_1_VOLUME:
2056 case ARIZONA_DRC1LMIX_INPUT_2_SOURCE:
2057 case ARIZONA_DRC1LMIX_INPUT_2_VOLUME:
2058 case ARIZONA_DRC1LMIX_INPUT_3_SOURCE:
2059 case ARIZONA_DRC1LMIX_INPUT_3_VOLUME:
2060 case ARIZONA_DRC1LMIX_INPUT_4_SOURCE:
2061 case ARIZONA_DRC1LMIX_INPUT_4_VOLUME:
2062 case ARIZONA_DRC1RMIX_INPUT_1_SOURCE:
2063 case ARIZONA_DRC1RMIX_INPUT_1_VOLUME:
2064 case ARIZONA_DRC1RMIX_INPUT_2_SOURCE:
2065 case ARIZONA_DRC1RMIX_INPUT_2_VOLUME:
2066 case ARIZONA_DRC1RMIX_INPUT_3_SOURCE:
2067 case ARIZONA_DRC1RMIX_INPUT_3_VOLUME:
2068 case ARIZONA_DRC1RMIX_INPUT_4_SOURCE:
2069 case ARIZONA_DRC1RMIX_INPUT_4_VOLUME:
2070 case ARIZONA_DRC2LMIX_INPUT_1_SOURCE:
2071 case ARIZONA_DRC2LMIX_INPUT_1_VOLUME:
2072 case ARIZONA_DRC2LMIX_INPUT_2_SOURCE:
2073 case ARIZONA_DRC2LMIX_INPUT_2_VOLUME:
2074 case ARIZONA_DRC2LMIX_INPUT_3_SOURCE:
2075 case ARIZONA_DRC2LMIX_INPUT_3_VOLUME:
2076 case ARIZONA_DRC2LMIX_INPUT_4_SOURCE:
2077 case ARIZONA_DRC2LMIX_INPUT_4_VOLUME:
2078 case ARIZONA_DRC2RMIX_INPUT_1_SOURCE:
2079 case ARIZONA_DRC2RMIX_INPUT_1_VOLUME:
2080 case ARIZONA_DRC2RMIX_INPUT_2_SOURCE:
2081 case ARIZONA_DRC2RMIX_INPUT_2_VOLUME:
2082 case ARIZONA_DRC2RMIX_INPUT_3_SOURCE:
2083 case ARIZONA_DRC2RMIX_INPUT_3_VOLUME:
2084 case ARIZONA_DRC2RMIX_INPUT_4_SOURCE:
2085 case ARIZONA_DRC2RMIX_INPUT_4_VOLUME:
2086 case ARIZONA_HPLP1MIX_INPUT_1_SOURCE:
2087 case ARIZONA_HPLP1MIX_INPUT_1_VOLUME:
2088 case ARIZONA_HPLP1MIX_INPUT_2_SOURCE:
2089 case ARIZONA_HPLP1MIX_INPUT_2_VOLUME:
2090 case ARIZONA_HPLP1MIX_INPUT_3_SOURCE:
2091 case ARIZONA_HPLP1MIX_INPUT_3_VOLUME:
2092 case ARIZONA_HPLP1MIX_INPUT_4_SOURCE:
2093 case ARIZONA_HPLP1MIX_INPUT_4_VOLUME:
2094 case ARIZONA_HPLP2MIX_INPUT_1_SOURCE:
2095 case ARIZONA_HPLP2MIX_INPUT_1_VOLUME:
2096 case ARIZONA_HPLP2MIX_INPUT_2_SOURCE:
2097 case ARIZONA_HPLP2MIX_INPUT_2_VOLUME:
2098 case ARIZONA_HPLP2MIX_INPUT_3_SOURCE:
2099 case ARIZONA_HPLP2MIX_INPUT_3_VOLUME:
2100 case ARIZONA_HPLP2MIX_INPUT_4_SOURCE:
2101 case ARIZONA_HPLP2MIX_INPUT_4_VOLUME:
2102 case ARIZONA_HPLP3MIX_INPUT_1_SOURCE:
2103 case ARIZONA_HPLP3MIX_INPUT_1_VOLUME:
2104 case ARIZONA_HPLP3MIX_INPUT_2_SOURCE:
2105 case ARIZONA_HPLP3MIX_INPUT_2_VOLUME:
2106 case ARIZONA_HPLP3MIX_INPUT_3_SOURCE:
2107 case ARIZONA_HPLP3MIX_INPUT_3_VOLUME:
2108 case ARIZONA_HPLP3MIX_INPUT_4_SOURCE:
2109 case ARIZONA_HPLP3MIX_INPUT_4_VOLUME:
2110 case ARIZONA_HPLP4MIX_INPUT_1_SOURCE:
2111 case ARIZONA_HPLP4MIX_INPUT_1_VOLUME:
2112 case ARIZONA_HPLP4MIX_INPUT_2_SOURCE:
2113 case ARIZONA_HPLP4MIX_INPUT_2_VOLUME:
2114 case ARIZONA_HPLP4MIX_INPUT_3_SOURCE:
2115 case ARIZONA_HPLP4MIX_INPUT_3_VOLUME:
2116 case ARIZONA_HPLP4MIX_INPUT_4_SOURCE:
2117 case ARIZONA_HPLP4MIX_INPUT_4_VOLUME:
2118 case ARIZONA_DSP1LMIX_INPUT_1_SOURCE:
2119 case ARIZONA_DSP1LMIX_INPUT_1_VOLUME:
2120 case ARIZONA_DSP1LMIX_INPUT_2_SOURCE:
2121 case ARIZONA_DSP1LMIX_INPUT_2_VOLUME:
2122 case ARIZONA_DSP1LMIX_INPUT_3_SOURCE:
2123 case ARIZONA_DSP1LMIX_INPUT_3_VOLUME:
2124 case ARIZONA_DSP1LMIX_INPUT_4_SOURCE:
2125 case ARIZONA_DSP1LMIX_INPUT_4_VOLUME:
2126 case ARIZONA_DSP1RMIX_INPUT_1_SOURCE:
2127 case ARIZONA_DSP1RMIX_INPUT_1_VOLUME:
2128 case ARIZONA_DSP1RMIX_INPUT_2_SOURCE:
2129 case ARIZONA_DSP1RMIX_INPUT_2_VOLUME:
2130 case ARIZONA_DSP1RMIX_INPUT_3_SOURCE:
2131 case ARIZONA_DSP1RMIX_INPUT_3_VOLUME:
2132 case ARIZONA_DSP1RMIX_INPUT_4_SOURCE:
2133 case ARIZONA_DSP1RMIX_INPUT_4_VOLUME:
2134 case ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE:
2135 case ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE:
2136 case ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE:
2137 case ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE:
2138 case ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE:
2139 case ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE:
2140 case ARIZONA_ASRC1LMIX_INPUT_1_SOURCE:
2141 case ARIZONA_ASRC1RMIX_INPUT_1_SOURCE:
2142 case ARIZONA_ASRC2LMIX_INPUT_1_SOURCE:
2143 case ARIZONA_ASRC2RMIX_INPUT_1_SOURCE:
2144 case ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE:
2145 case ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE:
2146 case ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE:
2147 case ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE:
2148 case ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE:
2149 case ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE:
2150 case ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE:
2151 case ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE:
2152 case ARIZONA_GPIO1_CTRL:
2153 case ARIZONA_GPIO2_CTRL:
2154 case ARIZONA_GPIO3_CTRL:
2155 case ARIZONA_GPIO4_CTRL:
2156 case ARIZONA_GPIO5_CTRL:
2157 case ARIZONA_IRQ_CTRL_1:
2158 case ARIZONA_GPIO_DEBOUNCE_CONFIG:
2159 case ARIZONA_MISC_PAD_CTRL_1:
2160 case ARIZONA_MISC_PAD_CTRL_2:
2161 case ARIZONA_MISC_PAD_CTRL_3:
2162 case ARIZONA_MISC_PAD_CTRL_4:
2163 case ARIZONA_MISC_PAD_CTRL_5:
2164 case ARIZONA_MISC_PAD_CTRL_6:
2165 case ARIZONA_INTERRUPT_STATUS_1:
2166 case ARIZONA_INTERRUPT_STATUS_2:
2167 case ARIZONA_INTERRUPT_STATUS_3:
2168 case ARIZONA_INTERRUPT_STATUS_4:
2169 case ARIZONA_INTERRUPT_STATUS_5:
2170 case ARIZONA_INTERRUPT_STATUS_1_MASK:
2171 case ARIZONA_INTERRUPT_STATUS_2_MASK:
2172 case ARIZONA_INTERRUPT_STATUS_3_MASK:
2173 case ARIZONA_INTERRUPT_STATUS_4_MASK:
2174 case ARIZONA_INTERRUPT_STATUS_5_MASK:
2175 case ARIZONA_INTERRUPT_CONTROL:
2176 case ARIZONA_IRQ2_STATUS_1:
2177 case ARIZONA_IRQ2_STATUS_2:
2178 case ARIZONA_IRQ2_STATUS_3:
2179 case ARIZONA_IRQ2_STATUS_4:
2180 case ARIZONA_IRQ2_STATUS_5:
2181 case ARIZONA_IRQ2_STATUS_1_MASK:
2182 case ARIZONA_IRQ2_STATUS_2_MASK:
2183 case ARIZONA_IRQ2_STATUS_3_MASK:
2184 case ARIZONA_IRQ2_STATUS_4_MASK:
2185 case ARIZONA_IRQ2_STATUS_5_MASK:
2186 case ARIZONA_IRQ2_CONTROL:
2187 case ARIZONA_INTERRUPT_RAW_STATUS_2:
2188 case ARIZONA_INTERRUPT_RAW_STATUS_3:
2189 case ARIZONA_INTERRUPT_RAW_STATUS_4:
2190 case ARIZONA_INTERRUPT_RAW_STATUS_5:
2191 case ARIZONA_INTERRUPT_RAW_STATUS_6:
2192 case ARIZONA_INTERRUPT_RAW_STATUS_7:
2193 case ARIZONA_INTERRUPT_RAW_STATUS_8:
2194 case ARIZONA_IRQ_PIN_STATUS:
2195 case ARIZONA_ADSP2_IRQ0:
2196 case ARIZONA_AOD_WKUP_AND_TRIG:
2197 case ARIZONA_AOD_IRQ1:
2198 case ARIZONA_AOD_IRQ2:
2199 case ARIZONA_AOD_IRQ_MASK_IRQ1:
2200 case ARIZONA_AOD_IRQ_MASK_IRQ2:
2201 case ARIZONA_AOD_IRQ_RAW_STATUS:
2202 case ARIZONA_JACK_DETECT_DEBOUNCE:
2203 case ARIZONA_FX_CTRL1:
2204 case ARIZONA_FX_CTRL2:
2205 case ARIZONA_EQ1_1:
2206 case ARIZONA_EQ1_2:
2207 case ARIZONA_EQ1_3:
2208 case ARIZONA_EQ1_4:
2209 case ARIZONA_EQ1_5:
2210 case ARIZONA_EQ1_6:
2211 case ARIZONA_EQ1_7:
2212 case ARIZONA_EQ1_8:
2213 case ARIZONA_EQ1_9:
2214 case ARIZONA_EQ1_10:
2215 case ARIZONA_EQ1_11:
2216 case ARIZONA_EQ1_12:
2217 case ARIZONA_EQ1_13:
2218 case ARIZONA_EQ1_14:
2219 case ARIZONA_EQ1_15:
2220 case ARIZONA_EQ1_16:
2221 case ARIZONA_EQ1_17:
2222 case ARIZONA_EQ1_18:
2223 case ARIZONA_EQ1_19:
2224 case ARIZONA_EQ1_20:
2225 case ARIZONA_EQ1_21:
2226 case ARIZONA_EQ2_1:
2227 case ARIZONA_EQ2_2:
2228 case ARIZONA_EQ2_3:
2229 case ARIZONA_EQ2_4:
2230 case ARIZONA_EQ2_5:
2231 case ARIZONA_EQ2_6:
2232 case ARIZONA_EQ2_7:
2233 case ARIZONA_EQ2_8:
2234 case ARIZONA_EQ2_9:
2235 case ARIZONA_EQ2_10:
2236 case ARIZONA_EQ2_11:
2237 case ARIZONA_EQ2_12:
2238 case ARIZONA_EQ2_13:
2239 case ARIZONA_EQ2_14:
2240 case ARIZONA_EQ2_15:
2241 case ARIZONA_EQ2_16:
2242 case ARIZONA_EQ2_17:
2243 case ARIZONA_EQ2_18:
2244 case ARIZONA_EQ2_19:
2245 case ARIZONA_EQ2_20:
2246 case ARIZONA_EQ2_21:
2247 case ARIZONA_EQ3_1:
2248 case ARIZONA_EQ3_2:
2249 case ARIZONA_EQ3_3:
2250 case ARIZONA_EQ3_4:
2251 case ARIZONA_EQ3_5:
2252 case ARIZONA_EQ3_6:
2253 case ARIZONA_EQ3_7:
2254 case ARIZONA_EQ3_8:
2255 case ARIZONA_EQ3_9:
2256 case ARIZONA_EQ3_10:
2257 case ARIZONA_EQ3_11:
2258 case ARIZONA_EQ3_12:
2259 case ARIZONA_EQ3_13:
2260 case ARIZONA_EQ3_14:
2261 case ARIZONA_EQ3_15:
2262 case ARIZONA_EQ3_16:
2263 case ARIZONA_EQ3_17:
2264 case ARIZONA_EQ3_18:
2265 case ARIZONA_EQ3_19:
2266 case ARIZONA_EQ3_20:
2267 case ARIZONA_EQ3_21:
2268 case ARIZONA_EQ4_1:
2269 case ARIZONA_EQ4_2:
2270 case ARIZONA_EQ4_3:
2271 case ARIZONA_EQ4_4:
2272 case ARIZONA_EQ4_5:
2273 case ARIZONA_EQ4_6:
2274 case ARIZONA_EQ4_7:
2275 case ARIZONA_EQ4_8:
2276 case ARIZONA_EQ4_9:
2277 case ARIZONA_EQ4_10:
2278 case ARIZONA_EQ4_11:
2279 case ARIZONA_EQ4_12:
2280 case ARIZONA_EQ4_13:
2281 case ARIZONA_EQ4_14:
2282 case ARIZONA_EQ4_15:
2283 case ARIZONA_EQ4_16:
2284 case ARIZONA_EQ4_17:
2285 case ARIZONA_EQ4_18:
2286 case ARIZONA_EQ4_19:
2287 case ARIZONA_EQ4_20:
2288 case ARIZONA_EQ4_21:
2289 case ARIZONA_DRC1_CTRL1:
2290 case ARIZONA_DRC1_CTRL2:
2291 case ARIZONA_DRC1_CTRL3:
2292 case ARIZONA_DRC1_CTRL4:
2293 case ARIZONA_DRC1_CTRL5:
2294 case ARIZONA_DRC2_CTRL1:
2295 case ARIZONA_DRC2_CTRL2:
2296 case ARIZONA_DRC2_CTRL3:
2297 case ARIZONA_DRC2_CTRL4:
2298 case ARIZONA_DRC2_CTRL5:
2299 case ARIZONA_HPLPF1_1:
2300 case ARIZONA_HPLPF1_2:
2301 case ARIZONA_HPLPF2_1:
2302 case ARIZONA_HPLPF2_2:
2303 case ARIZONA_HPLPF3_1:
2304 case ARIZONA_HPLPF3_2:
2305 case ARIZONA_HPLPF4_1:
2306 case ARIZONA_HPLPF4_2:
2307 case ARIZONA_ASRC_ENABLE:
2308 case ARIZONA_ASRC_RATE1:
2309 case ARIZONA_ASRC_RATE2:
2310 case ARIZONA_ISRC_1_CTRL_1:
2311 case ARIZONA_ISRC_1_CTRL_2:
2312 case ARIZONA_ISRC_1_CTRL_3:
2313 case ARIZONA_ISRC_2_CTRL_1:
2314 case ARIZONA_ISRC_2_CTRL_2:
2315 case ARIZONA_ISRC_2_CTRL_3:
2316 case ARIZONA_ISRC_3_CTRL_1:
2317 case ARIZONA_ISRC_3_CTRL_2:
2318 case ARIZONA_ISRC_3_CTRL_3:
2319 case ARIZONA_DSP1_CONTROL_1:
2320 case ARIZONA_DSP1_CLOCKING_1:
2321 case ARIZONA_DSP1_STATUS_1:
2322 case ARIZONA_DSP1_STATUS_2:
2323 return true;
2324 default:
2325 return false;
2326 }
2327}
2328
2329static bool wm5102_volatile_register(struct device *dev, unsigned int reg)
2330{
2331 switch (reg) {
2332 case ARIZONA_SOFTWARE_RESET:
2333 case ARIZONA_DEVICE_REVISION:
2334 case ARIZONA_OUTPUT_STATUS_1:
2335 case ARIZONA_SAMPLE_RATE_1_STATUS:
2336 case ARIZONA_SAMPLE_RATE_2_STATUS:
2337 case ARIZONA_SAMPLE_RATE_3_STATUS:
2338 case ARIZONA_HAPTICS_STATUS:
2339 case ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS:
2340 case ARIZONA_FX_CTRL2:
2341 case ARIZONA_INTERRUPT_STATUS_1:
2342 case ARIZONA_INTERRUPT_STATUS_2:
2343 case ARIZONA_INTERRUPT_STATUS_3:
2344 case ARIZONA_INTERRUPT_STATUS_4:
2345 case ARIZONA_INTERRUPT_STATUS_5:
2346 case ARIZONA_IRQ2_STATUS_1:
2347 case ARIZONA_IRQ2_STATUS_2:
2348 case ARIZONA_IRQ2_STATUS_3:
2349 case ARIZONA_IRQ2_STATUS_4:
2350 case ARIZONA_IRQ2_STATUS_5:
2351 case ARIZONA_INTERRUPT_RAW_STATUS_2:
2352 case ARIZONA_INTERRUPT_RAW_STATUS_3:
2353 case ARIZONA_INTERRUPT_RAW_STATUS_4:
2354 case ARIZONA_INTERRUPT_RAW_STATUS_5:
2355 case ARIZONA_INTERRUPT_RAW_STATUS_6:
2356 case ARIZONA_INTERRUPT_RAW_STATUS_7:
2357 case ARIZONA_INTERRUPT_RAW_STATUS_8:
2358 case ARIZONA_IRQ_PIN_STATUS:
2359 case ARIZONA_AOD_WKUP_AND_TRIG:
2360 case ARIZONA_AOD_IRQ1:
2361 case ARIZONA_AOD_IRQ2:
2362 case ARIZONA_AOD_IRQ_RAW_STATUS:
2363 case ARIZONA_DSP1_STATUS_1:
2364 case ARIZONA_DSP1_STATUS_2:
2365 case ARIZONA_MIC_DETECT_3:
2366 return true;
2367 default:
2368 return false;
2369 }
2370}
2371
2372const struct regmap_config wm5102_spi_regmap = {
2373 .reg_bits = 32,
2374 .pad_bits = 16,
2375 .val_bits = 16,
2376
2377 .max_register = ARIZONA_DSP1_STATUS_2,
2378 .readable_reg = wm5102_readable_register,
2379 .volatile_reg = wm5102_volatile_register,
2380
2381 .cache_type = REGCACHE_RBTREE,
2382 .reg_defaults = wm5102_reg_default,
2383 .num_reg_defaults = ARRAY_SIZE(wm5102_reg_default),
2384};
2385EXPORT_SYMBOL_GPL(wm5102_spi_regmap);
2386
2387const struct regmap_config wm5102_i2c_regmap = {
2388 .reg_bits = 32,
2389 .val_bits = 16,
2390
2391 .max_register = ARIZONA_DSP1_STATUS_2,
2392 .readable_reg = wm5102_readable_register,
2393 .volatile_reg = wm5102_volatile_register,
2394
2395 .cache_type = REGCACHE_RBTREE,
2396 .reg_defaults = wm5102_reg_default,
2397 .num_reg_defaults = ARRAY_SIZE(wm5102_reg_default),
2398};
2399EXPORT_SYMBOL_GPL(wm5102_i2c_regmap);
diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h
new file mode 100644
index 000000000000..0157d845c2ff
--- /dev/null
+++ b/include/linux/mfd/arizona/core.h
@@ -0,0 +1,102 @@
1/*
2 * Arizona MFD internals
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _WM_ARIZONA_CORE_H
14#define _WM_ARIZONA_CORE_H
15
16#include <linux/interrupt.h>
17#include <linux/regmap.h>
18#include <linux/regulator/consumer.h>
19#include <linux/mfd/arizona/pdata.h>
20
21#define ARIZONA_MAX_CORE_SUPPLIES 3
22
23enum arizona_type {
24 WM5102 = 1,
25};
26
27#define ARIZONA_IRQ_GP1 0
28#define ARIZONA_IRQ_GP2 1
29#define ARIZONA_IRQ_GP3 2
30#define ARIZONA_IRQ_GP4 3
31#define ARIZONA_IRQ_GP5_FALL 4
32#define ARIZONA_IRQ_GP5_RISE 5
33#define ARIZONA_IRQ_JD_FALL 6
34#define ARIZONA_IRQ_JD_RISE 7
35#define ARIZONA_IRQ_DSP1_RAM_RDY 8
36#define ARIZONA_IRQ_DSP_IRQ1 9
37#define ARIZONA_IRQ_DSP_IRQ2 10
38#define ARIZONA_IRQ_SPK_SHUTDOWN_WARN 11
39#define ARIZONA_IRQ_SPK_SHUTDOWN 12
40#define ARIZONA_IRQ_MICDET 13
41#define ARIZONA_IRQ_HPDET 14
42#define ARIZONA_IRQ_WSEQ_DONE 15
43#define ARIZONA_IRQ_DRC2_SIG_DET 16
44#define ARIZONA_IRQ_DRC1_SIG_DET 17
45#define ARIZONA_IRQ_ASRC2_LOCK 18
46#define ARIZONA_IRQ_ASRC1_LOCK 19
47#define ARIZONA_IRQ_UNDERCLOCKED 20
48#define ARIZONA_IRQ_OVERCLOCKED 21
49#define ARIZONA_IRQ_FLL2_LOCK 22
50#define ARIZONA_IRQ_FLL1_LOCK 23
51#define ARIZONA_IRQ_CLKGEN_ERR 24
52#define ARIZONA_IRQ_CLKGEN_ERR_ASYNC 25
53#define ARIZONA_IRQ_ASRC_CFG_ERR 26
54#define ARIZONA_IRQ_AIF3_ERR 27
55#define ARIZONA_IRQ_AIF2_ERR 28
56#define ARIZONA_IRQ_AIF1_ERR 29
57#define ARIZONA_IRQ_CTRLIF_ERR 30
58#define ARIZONA_IRQ_MIXER_DROPPED_SAMPLES 31
59#define ARIZONA_IRQ_ASYNC_CLK_ENA_LOW 32
60#define ARIZONA_IRQ_SYSCLK_ENA_LOW 33
61#define ARIZONA_IRQ_ISRC1_CFG_ERR 34
62#define ARIZONA_IRQ_ISRC2_CFG_ERR 35
63#define ARIZONA_IRQ_BOOT_DONE 36
64#define ARIZONA_IRQ_DCS_DAC_DONE 37
65#define ARIZONA_IRQ_DCS_HP_DONE 38
66#define ARIZONA_IRQ_FLL2_CLOCK_OK 39
67#define ARIZONA_IRQ_FLL1_CLOCK_OK 40
68
69#define ARIZONA_NUM_IRQ 41
70
71struct arizona {
72 struct regmap *regmap;
73 struct device *dev;
74
75 enum arizona_type type;
76 unsigned int rev;
77
78 int num_core_supplies;
79 struct regulator_bulk_data core_supplies[ARIZONA_MAX_CORE_SUPPLIES];
80
81 struct arizona_pdata pdata;
82
83 int irq;
84 struct irq_domain *virq;
85 struct regmap_irq_chip_data *aod_irq_chip;
86 struct regmap_irq_chip_data *irq_chip;
87
88 struct mutex clk_lock;
89 int clk32k_ref;
90};
91
92int arizona_clk32k_enable(struct arizona *arizona);
93int arizona_clk32k_disable(struct arizona *arizona);
94
95int arizona_request_irq(struct arizona *arizona, int irq, char *name,
96 irq_handler_t handler, void *data);
97void arizona_free_irq(struct arizona *arizona, int irq, void *data);
98int arizona_set_irq_wake(struct arizona *arizona, int irq, int on);
99
100int wm5102_patch(struct arizona *arizona);
101
102#endif
diff --git a/include/linux/mfd/arizona/pdata.h b/include/linux/mfd/arizona/pdata.h
new file mode 100644
index 000000000000..fa2cb9885d62
--- /dev/null
+++ b/include/linux/mfd/arizona/pdata.h
@@ -0,0 +1,119 @@
1/*
2 * Platform data for Arizona devices
3 *
4 * Copyright 2012 Wolfson Microelectronics. PLC.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef _ARIZONA_PDATA_H
12#define _ARIZONA_PDATA_H
13
14#define ARIZONA_GPN_DIR 0x8000 /* GPN_DIR */
15#define ARIZONA_GPN_DIR_MASK 0x8000 /* GPN_DIR */
16#define ARIZONA_GPN_DIR_SHIFT 15 /* GPN_DIR */
17#define ARIZONA_GPN_DIR_WIDTH 1 /* GPN_DIR */
18#define ARIZONA_GPN_PU 0x4000 /* GPN_PU */
19#define ARIZONA_GPN_PU_MASK 0x4000 /* GPN_PU */
20#define ARIZONA_GPN_PU_SHIFT 14 /* GPN_PU */
21#define ARIZONA_GPN_PU_WIDTH 1 /* GPN_PU */
22#define ARIZONA_GPN_PD 0x2000 /* GPN_PD */
23#define ARIZONA_GPN_PD_MASK 0x2000 /* GPN_PD */
24#define ARIZONA_GPN_PD_SHIFT 13 /* GPN_PD */
25#define ARIZONA_GPN_PD_WIDTH 1 /* GPN_PD */
26#define ARIZONA_GPN_LVL 0x0800 /* GPN_LVL */
27#define ARIZONA_GPN_LVL_MASK 0x0800 /* GPN_LVL */
28#define ARIZONA_GPN_LVL_SHIFT 11 /* GPN_LVL */
29#define ARIZONA_GPN_LVL_WIDTH 1 /* GPN_LVL */
30#define ARIZONA_GPN_POL 0x0400 /* GPN_POL */
31#define ARIZONA_GPN_POL_MASK 0x0400 /* GPN_POL */
32#define ARIZONA_GPN_POL_SHIFT 10 /* GPN_POL */
33#define ARIZONA_GPN_POL_WIDTH 1 /* GPN_POL */
34#define ARIZONA_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
35#define ARIZONA_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
36#define ARIZONA_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
37#define ARIZONA_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
38#define ARIZONA_GPN_DB 0x0100 /* GPN_DB */
39#define ARIZONA_GPN_DB_MASK 0x0100 /* GPN_DB */
40#define ARIZONA_GPN_DB_SHIFT 8 /* GPN_DB */
41#define ARIZONA_GPN_DB_WIDTH 1 /* GPN_DB */
42#define ARIZONA_GPN_FN_MASK 0x007F /* GPN_FN - [6:0] */
43#define ARIZONA_GPN_FN_SHIFT 0 /* GPN_FN - [6:0] */
44#define ARIZONA_GPN_FN_WIDTH 7 /* GPN_FN - [6:0] */
45
46#define ARIZONA_MAX_GPIO 5
47
48#define ARIZONA_32KZ_MCLK1 1
49#define ARIZONA_32KZ_MCLK2 2
50#define ARIZONA_32KZ_NONE 3
51
52#define ARIZONA_MAX_INPUT 3
53
54#define ARIZONA_DMIC_MICVDD 0
55#define ARIZONA_DMIC_MICBIAS1 1
56#define ARIZONA_DMIC_MICBIAS2 2
57#define ARIZONA_DMIC_MICBIAS3 3
58
59#define ARIZONA_INMODE_DIFF 0
60#define ARIZONA_INMODE_SE 1
61#define ARIZONA_INMODE_DMIC 2
62
63#define ARIZONA_MAX_OUTPUT 5
64
65#define ARIZONA_MAX_PDM_SPK 1
66
67struct regulator_init_data;
68
69struct arizona_micd_config {
70 unsigned int src;
71 unsigned int bias;
72 bool gpio;
73};
74
75struct arizona_pdata {
76 int reset; /** GPIO controlling /RESET, if any */
77 int ldoena; /** GPIO controlling LODENA, if any */
78
79 /** Regulator configuration for MICVDD */
80 struct regulator_init_data *micvdd;
81
82 /** Regulator configuration for LDO1 */
83 struct regulator_init_data *ldo1;
84
85 /** If a direct 32kHz clock is provided on an MCLK specify it here */
86 int clk32k_src;
87
88 bool irq_active_high; /** IRQ polarity */
89
90 /* Base GPIO */
91 int gpio_base;
92
93 /** Pin state for GPIO pins */
94 int gpio_defaults[ARIZONA_MAX_GPIO];
95
96 /** GPIO for mic detection polarity */
97 int micd_pol_gpio;
98
99 /** Headset polarity configurations */
100 struct arizona_micd_config *micd_configs;
101 int num_micd_configs;
102
103 /** Reference voltage for DMIC inputs */
104 int dmic_ref[ARIZONA_MAX_INPUT];
105
106 /** Mode of input structures */
107 int inmode[ARIZONA_MAX_INPUT];
108
109 /** Mode for outputs */
110 bool out_mono[ARIZONA_MAX_OUTPUT];
111
112 /** PDM speaker mute setting */
113 unsigned int spk_mute[ARIZONA_MAX_PDM_SPK];
114
115 /** PDM speaker format */
116 unsigned int spk_fmt[ARIZONA_MAX_PDM_SPK];
117};
118
119#endif
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
new file mode 100644
index 000000000000..989c47d681e0
--- /dev/null
+++ b/include/linux/mfd/arizona/registers.h
@@ -0,0 +1,6222 @@
1/*
2 * ARIZONA register definitions
3 *
4 * Copyright 2012 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef _ARIZONA_REGISTERS_H
14#define _ARIZONA_REGISTERS_H
15
16/*
17 * Register values.
18 */
19#define ARIZONA_SOFTWARE_RESET 0x00
20#define ARIZONA_DEVICE_REVISION 0x01
21#define ARIZONA_CTRL_IF_SPI_CFG_1 0x08
22#define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09
23#define ARIZONA_CTRL_IF_STATUS_1 0x0D
24#define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16
25#define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17
26#define ARIZONA_WRITE_SEQUENCER_CTRL_2 0x18
27#define ARIZONA_WRITE_SEQUENCER_PROM 0x1A
28#define ARIZONA_TONE_GENERATOR_1 0x20
29#define ARIZONA_TONE_GENERATOR_2 0x21
30#define ARIZONA_TONE_GENERATOR_3 0x22
31#define ARIZONA_TONE_GENERATOR_4 0x23
32#define ARIZONA_TONE_GENERATOR_5 0x24
33#define ARIZONA_PWM_DRIVE_1 0x30
34#define ARIZONA_PWM_DRIVE_2 0x31
35#define ARIZONA_PWM_DRIVE_3 0x32
36#define ARIZONA_WAKE_CONTROL 0x40
37#define ARIZONA_SEQUENCE_CONTROL 0x41
38#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1 0x61
39#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62
40#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63
41#define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64
42#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x68
43#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x69
44#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x6A
45#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x6B
46#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6C
47#define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6D
48#define ARIZONA_COMFORT_NOISE_GENERATOR 0x70
49#define ARIZONA_HAPTICS_CONTROL_1 0x90
50#define ARIZONA_HAPTICS_CONTROL_2 0x91
51#define ARIZONA_HAPTICS_PHASE_1_INTENSITY 0x92
52#define ARIZONA_HAPTICS_PHASE_1_DURATION 0x93
53#define ARIZONA_HAPTICS_PHASE_2_INTENSITY 0x94
54#define ARIZONA_HAPTICS_PHASE_2_DURATION 0x95
55#define ARIZONA_HAPTICS_PHASE_3_INTENSITY 0x96
56#define ARIZONA_HAPTICS_PHASE_3_DURATION 0x97
57#define ARIZONA_HAPTICS_STATUS 0x98
58#define ARIZONA_CLOCK_32K_1 0x100
59#define ARIZONA_SYSTEM_CLOCK_1 0x101
60#define ARIZONA_SAMPLE_RATE_1 0x102
61#define ARIZONA_SAMPLE_RATE_2 0x103
62#define ARIZONA_SAMPLE_RATE_3 0x104
63#define ARIZONA_SAMPLE_RATE_1_STATUS 0x10A
64#define ARIZONA_SAMPLE_RATE_2_STATUS 0x10B
65#define ARIZONA_SAMPLE_RATE_3_STATUS 0x10C
66#define ARIZONA_ASYNC_CLOCK_1 0x112
67#define ARIZONA_ASYNC_SAMPLE_RATE_1 0x113
68#define ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS 0x11B
69#define ARIZONA_OUTPUT_SYSTEM_CLOCK 0x149
70#define ARIZONA_OUTPUT_ASYNC_CLOCK 0x14A
71#define ARIZONA_RATE_ESTIMATOR_1 0x152
72#define ARIZONA_RATE_ESTIMATOR_2 0x153
73#define ARIZONA_RATE_ESTIMATOR_3 0x154
74#define ARIZONA_RATE_ESTIMATOR_4 0x155
75#define ARIZONA_RATE_ESTIMATOR_5 0x156
76#define ARIZONA_FLL1_CONTROL_1 0x171
77#define ARIZONA_FLL1_CONTROL_2 0x172
78#define ARIZONA_FLL1_CONTROL_3 0x173
79#define ARIZONA_FLL1_CONTROL_4 0x174
80#define ARIZONA_FLL1_CONTROL_5 0x175
81#define ARIZONA_FLL1_CONTROL_6 0x176
82#define ARIZONA_FLL1_LOOP_FILTER_TEST_1 0x177
83#define ARIZONA_FLL1_SYNCHRONISER_1 0x181
84#define ARIZONA_FLL1_SYNCHRONISER_2 0x182
85#define ARIZONA_FLL1_SYNCHRONISER_3 0x183
86#define ARIZONA_FLL1_SYNCHRONISER_4 0x184
87#define ARIZONA_FLL1_SYNCHRONISER_5 0x185
88#define ARIZONA_FLL1_SYNCHRONISER_6 0x186
89#define ARIZONA_FLL1_SPREAD_SPECTRUM 0x189
90#define ARIZONA_FLL1_GPIO_CLOCK 0x18A
91#define ARIZONA_FLL2_CONTROL_1 0x191
92#define ARIZONA_FLL2_CONTROL_2 0x192
93#define ARIZONA_FLL2_CONTROL_3 0x193
94#define ARIZONA_FLL2_CONTROL_4 0x194
95#define ARIZONA_FLL2_CONTROL_5 0x195
96#define ARIZONA_FLL2_CONTROL_6 0x196
97#define ARIZONA_FLL2_LOOP_FILTER_TEST_1 0x197
98#define ARIZONA_FLL2_SYNCHRONISER_1 0x1A1
99#define ARIZONA_FLL2_SYNCHRONISER_2 0x1A2
100#define ARIZONA_FLL2_SYNCHRONISER_3 0x1A3
101#define ARIZONA_FLL2_SYNCHRONISER_4 0x1A4
102#define ARIZONA_FLL2_SYNCHRONISER_5 0x1A5
103#define ARIZONA_FLL2_SYNCHRONISER_6 0x1A6
104#define ARIZONA_FLL2_SPREAD_SPECTRUM 0x1A9
105#define ARIZONA_FLL2_GPIO_CLOCK 0x1AA
106#define ARIZONA_MIC_CHARGE_PUMP_1 0x200
107#define ARIZONA_LDO1_CONTROL_1 0x210
108#define ARIZONA_LDO2_CONTROL_1 0x213
109#define ARIZONA_MIC_BIAS_CTRL_1 0x218
110#define ARIZONA_MIC_BIAS_CTRL_2 0x219
111#define ARIZONA_MIC_BIAS_CTRL_3 0x21A
112#define ARIZONA_ACCESSORY_DETECT_MODE_1 0x293
113#define ARIZONA_HEADPHONE_DETECT_1 0x29B
114#define ARIZONA_HEADPHONE_DETECT_2 0x29C
115#define ARIZONA_MIC_DETECT_1 0x2A3
116#define ARIZONA_MIC_DETECT_2 0x2A4
117#define ARIZONA_MIC_DETECT_3 0x2A5
118#define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3
119#define ARIZONA_ISOLATION_CONTROL 0x2CB
120#define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3
121#define ARIZONA_INPUT_ENABLES 0x300
122#define ARIZONA_INPUT_RATE 0x308
123#define ARIZONA_INPUT_VOLUME_RAMP 0x309
124#define ARIZONA_IN1L_CONTROL 0x310
125#define ARIZONA_ADC_DIGITAL_VOLUME_1L 0x311
126#define ARIZONA_DMIC1L_CONTROL 0x312
127#define ARIZONA_IN1R_CONTROL 0x314
128#define ARIZONA_ADC_DIGITAL_VOLUME_1R 0x315
129#define ARIZONA_DMIC1R_CONTROL 0x316
130#define ARIZONA_IN2L_CONTROL 0x318
131#define ARIZONA_ADC_DIGITAL_VOLUME_2L 0x319
132#define ARIZONA_DMIC2L_CONTROL 0x31A
133#define ARIZONA_IN2R_CONTROL 0x31C
134#define ARIZONA_ADC_DIGITAL_VOLUME_2R 0x31D
135#define ARIZONA_DMIC2R_CONTROL 0x31E
136#define ARIZONA_IN3L_CONTROL 0x320
137#define ARIZONA_ADC_DIGITAL_VOLUME_3L 0x321
138#define ARIZONA_DMIC3L_CONTROL 0x322
139#define ARIZONA_IN3R_CONTROL 0x324
140#define ARIZONA_ADC_DIGITAL_VOLUME_3R 0x325
141#define ARIZONA_DMIC3R_CONTROL 0x326
142#define ARIZONA_OUTPUT_ENABLES_1 0x400
143#define ARIZONA_OUTPUT_STATUS_1 0x401
144#define ARIZONA_OUTPUT_RATE_1 0x408
145#define ARIZONA_OUTPUT_VOLUME_RAMP 0x409
146#define ARIZONA_OUTPUT_PATH_CONFIG_1L 0x410
147#define ARIZONA_DAC_DIGITAL_VOLUME_1L 0x411
148#define ARIZONA_DAC_VOLUME_LIMIT_1L 0x412
149#define ARIZONA_NOISE_GATE_SELECT_1L 0x413
150#define ARIZONA_OUTPUT_PATH_CONFIG_1R 0x414
151#define ARIZONA_DAC_DIGITAL_VOLUME_1R 0x415
152#define ARIZONA_DAC_VOLUME_LIMIT_1R 0x416
153#define ARIZONA_NOISE_GATE_SELECT_1R 0x417
154#define ARIZONA_OUTPUT_PATH_CONFIG_2L 0x418
155#define ARIZONA_DAC_DIGITAL_VOLUME_2L 0x419
156#define ARIZONA_DAC_VOLUME_LIMIT_2L 0x41A
157#define ARIZONA_NOISE_GATE_SELECT_2L 0x41B
158#define ARIZONA_OUTPUT_PATH_CONFIG_2R 0x41C
159#define ARIZONA_DAC_DIGITAL_VOLUME_2R 0x41D
160#define ARIZONA_DAC_VOLUME_LIMIT_2R 0x41E
161#define ARIZONA_NOISE_GATE_SELECT_2R 0x41F
162#define ARIZONA_OUTPUT_PATH_CONFIG_3L 0x420
163#define ARIZONA_DAC_DIGITAL_VOLUME_3L 0x421
164#define ARIZONA_DAC_VOLUME_LIMIT_3L 0x422
165#define ARIZONA_NOISE_GATE_SELECT_3L 0x423
166#define ARIZONA_OUTPUT_PATH_CONFIG_3R 0x424
167#define ARIZONA_DAC_DIGITAL_VOLUME_3R 0x425
168#define ARIZONA_DAC_VOLUME_LIMIT_3R 0x426
169#define ARIZONA_OUTPUT_PATH_CONFIG_4L 0x428
170#define ARIZONA_DAC_DIGITAL_VOLUME_4L 0x429
171#define ARIZONA_OUT_VOLUME_4L 0x42A
172#define ARIZONA_NOISE_GATE_SELECT_4L 0x42B
173#define ARIZONA_OUTPUT_PATH_CONFIG_4R 0x42C
174#define ARIZONA_DAC_DIGITAL_VOLUME_4R 0x42D
175#define ARIZONA_OUT_VOLUME_4R 0x42E
176#define ARIZONA_NOISE_GATE_SELECT_4R 0x42F
177#define ARIZONA_OUTPUT_PATH_CONFIG_5L 0x430
178#define ARIZONA_DAC_DIGITAL_VOLUME_5L 0x431
179#define ARIZONA_DAC_VOLUME_LIMIT_5L 0x432
180#define ARIZONA_NOISE_GATE_SELECT_5L 0x433
181#define ARIZONA_OUTPUT_PATH_CONFIG_5R 0x434
182#define ARIZONA_DAC_DIGITAL_VOLUME_5R 0x435
183#define ARIZONA_DAC_VOLUME_LIMIT_5R 0x436
184#define ARIZONA_NOISE_GATE_SELECT_5R 0x437
185#define ARIZONA_DAC_AEC_CONTROL_1 0x450
186#define ARIZONA_NOISE_GATE_CONTROL 0x458
187#define ARIZONA_PDM_SPK1_CTRL_1 0x490
188#define ARIZONA_PDM_SPK1_CTRL_2 0x491
189#define ARIZONA_DAC_COMP_1 0x4DC
190#define ARIZONA_DAC_COMP_2 0x4DD
191#define ARIZONA_DAC_COMP_3 0x4DE
192#define ARIZONA_DAC_COMP_4 0x4DF
193#define ARIZONA_AIF1_BCLK_CTRL 0x500
194#define ARIZONA_AIF1_TX_PIN_CTRL 0x501
195#define ARIZONA_AIF1_RX_PIN_CTRL 0x502
196#define ARIZONA_AIF1_RATE_CTRL 0x503
197#define ARIZONA_AIF1_FORMAT 0x504
198#define ARIZONA_AIF1_TX_BCLK_RATE 0x505
199#define ARIZONA_AIF1_RX_BCLK_RATE 0x506
200#define ARIZONA_AIF1_FRAME_CTRL_1 0x507
201#define ARIZONA_AIF1_FRAME_CTRL_2 0x508
202#define ARIZONA_AIF1_FRAME_CTRL_3 0x509
203#define ARIZONA_AIF1_FRAME_CTRL_4 0x50A
204#define ARIZONA_AIF1_FRAME_CTRL_5 0x50B
205#define ARIZONA_AIF1_FRAME_CTRL_6 0x50C
206#define ARIZONA_AIF1_FRAME_CTRL_7 0x50D
207#define ARIZONA_AIF1_FRAME_CTRL_8 0x50E
208#define ARIZONA_AIF1_FRAME_CTRL_9 0x50F
209#define ARIZONA_AIF1_FRAME_CTRL_10 0x510
210#define ARIZONA_AIF1_FRAME_CTRL_11 0x511
211#define ARIZONA_AIF1_FRAME_CTRL_12 0x512
212#define ARIZONA_AIF1_FRAME_CTRL_13 0x513
213#define ARIZONA_AIF1_FRAME_CTRL_14 0x514
214#define ARIZONA_AIF1_FRAME_CTRL_15 0x515
215#define ARIZONA_AIF1_FRAME_CTRL_16 0x516
216#define ARIZONA_AIF1_FRAME_CTRL_17 0x517
217#define ARIZONA_AIF1_FRAME_CTRL_18 0x518
218#define ARIZONA_AIF1_TX_ENABLES 0x519
219#define ARIZONA_AIF1_RX_ENABLES 0x51A
220#define ARIZONA_AIF1_FORCE_WRITE 0x51B
221#define ARIZONA_AIF2_BCLK_CTRL 0x540
222#define ARIZONA_AIF2_TX_PIN_CTRL 0x541
223#define ARIZONA_AIF2_RX_PIN_CTRL 0x542
224#define ARIZONA_AIF2_RATE_CTRL 0x543
225#define ARIZONA_AIF2_FORMAT 0x544
226#define ARIZONA_AIF2_TX_BCLK_RATE 0x545
227#define ARIZONA_AIF2_RX_BCLK_RATE 0x546
228#define ARIZONA_AIF2_FRAME_CTRL_1 0x547
229#define ARIZONA_AIF2_FRAME_CTRL_2 0x548
230#define ARIZONA_AIF2_FRAME_CTRL_3 0x549
231#define ARIZONA_AIF2_FRAME_CTRL_4 0x54A
232#define ARIZONA_AIF2_FRAME_CTRL_11 0x551
233#define ARIZONA_AIF2_FRAME_CTRL_12 0x552
234#define ARIZONA_AIF2_TX_ENABLES 0x559
235#define ARIZONA_AIF2_RX_ENABLES 0x55A
236#define ARIZONA_AIF2_FORCE_WRITE 0x55B
237#define ARIZONA_AIF3_BCLK_CTRL 0x580
238#define ARIZONA_AIF3_TX_PIN_CTRL 0x581
239#define ARIZONA_AIF3_RX_PIN_CTRL 0x582
240#define ARIZONA_AIF3_RATE_CTRL 0x583
241#define ARIZONA_AIF3_FORMAT 0x584
242#define ARIZONA_AIF3_TX_BCLK_RATE 0x585
243#define ARIZONA_AIF3_RX_BCLK_RATE 0x586
244#define ARIZONA_AIF3_FRAME_CTRL_1 0x587
245#define ARIZONA_AIF3_FRAME_CTRL_2 0x588
246#define ARIZONA_AIF3_FRAME_CTRL_3 0x589
247#define ARIZONA_AIF3_FRAME_CTRL_4 0x58A
248#define ARIZONA_AIF3_FRAME_CTRL_11 0x591
249#define ARIZONA_AIF3_FRAME_CTRL_12 0x592
250#define ARIZONA_AIF3_TX_ENABLES 0x599
251#define ARIZONA_AIF3_RX_ENABLES 0x59A
252#define ARIZONA_AIF3_FORCE_WRITE 0x59B
253#define ARIZONA_SLIMBUS_FRAMER_REF_GEAR 0x5E3
254#define ARIZONA_SLIMBUS_RATES_1 0x5E5
255#define ARIZONA_SLIMBUS_RATES_2 0x5E6
256#define ARIZONA_SLIMBUS_RATES_3 0x5E7
257#define ARIZONA_SLIMBUS_RATES_4 0x5E8
258#define ARIZONA_SLIMBUS_RATES_5 0x5E9
259#define ARIZONA_SLIMBUS_RATES_6 0x5EA
260#define ARIZONA_SLIMBUS_RATES_7 0x5EB
261#define ARIZONA_SLIMBUS_RATES_8 0x5EC
262#define ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE 0x5F5
263#define ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE 0x5F6
264#define ARIZONA_SLIMBUS_RX_PORT_STATUS 0x5F7
265#define ARIZONA_SLIMBUS_TX_PORT_STATUS 0x5F8
266#define ARIZONA_PWM1MIX_INPUT_1_SOURCE 0x640
267#define ARIZONA_PWM1MIX_INPUT_1_VOLUME 0x641
268#define ARIZONA_PWM1MIX_INPUT_2_SOURCE 0x642
269#define ARIZONA_PWM1MIX_INPUT_2_VOLUME 0x643
270#define ARIZONA_PWM1MIX_INPUT_3_SOURCE 0x644
271#define ARIZONA_PWM1MIX_INPUT_3_VOLUME 0x645
272#define ARIZONA_PWM1MIX_INPUT_4_SOURCE 0x646
273#define ARIZONA_PWM1MIX_INPUT_4_VOLUME 0x647
274#define ARIZONA_PWM2MIX_INPUT_1_SOURCE 0x648
275#define ARIZONA_PWM2MIX_INPUT_1_VOLUME 0x649
276#define ARIZONA_PWM2MIX_INPUT_2_SOURCE 0x64A
277#define ARIZONA_PWM2MIX_INPUT_2_VOLUME 0x64B
278#define ARIZONA_PWM2MIX_INPUT_3_SOURCE 0x64C
279#define ARIZONA_PWM2MIX_INPUT_3_VOLUME 0x64D
280#define ARIZONA_PWM2MIX_INPUT_4_SOURCE 0x64E
281#define ARIZONA_PWM2MIX_INPUT_4_VOLUME 0x64F
282#define ARIZONA_MICMIX_INPUT_1_SOURCE 0x660
283#define ARIZONA_MICMIX_INPUT_1_VOLUME 0x661
284#define ARIZONA_MICMIX_INPUT_2_SOURCE 0x662
285#define ARIZONA_MICMIX_INPUT_2_VOLUME 0x663
286#define ARIZONA_MICMIX_INPUT_3_SOURCE 0x664
287#define ARIZONA_MICMIX_INPUT_3_VOLUME 0x665
288#define ARIZONA_MICMIX_INPUT_4_SOURCE 0x666
289#define ARIZONA_MICMIX_INPUT_4_VOLUME 0x667
290#define ARIZONA_NOISEMIX_INPUT_1_SOURCE 0x668
291#define ARIZONA_NOISEMIX_INPUT_1_VOLUME 0x669
292#define ARIZONA_NOISEMIX_INPUT_2_SOURCE 0x66A
293#define ARIZONA_NOISEMIX_INPUT_2_VOLUME 0x66B
294#define ARIZONA_NOISEMIX_INPUT_3_SOURCE 0x66C
295#define ARIZONA_NOISEMIX_INPUT_3_VOLUME 0x66D
296#define ARIZONA_NOISEMIX_INPUT_4_SOURCE 0x66E
297#define ARIZONA_NOISEMIX_INPUT_4_VOLUME 0x66F
298#define ARIZONA_OUT1LMIX_INPUT_1_SOURCE 0x680
299#define ARIZONA_OUT1LMIX_INPUT_1_VOLUME 0x681
300#define ARIZONA_OUT1LMIX_INPUT_2_SOURCE 0x682
301#define ARIZONA_OUT1LMIX_INPUT_2_VOLUME 0x683
302#define ARIZONA_OUT1LMIX_INPUT_3_SOURCE 0x684
303#define ARIZONA_OUT1LMIX_INPUT_3_VOLUME 0x685
304#define ARIZONA_OUT1LMIX_INPUT_4_SOURCE 0x686
305#define ARIZONA_OUT1LMIX_INPUT_4_VOLUME 0x687
306#define ARIZONA_OUT1RMIX_INPUT_1_SOURCE 0x688
307#define ARIZONA_OUT1RMIX_INPUT_1_VOLUME 0x689
308#define ARIZONA_OUT1RMIX_INPUT_2_SOURCE 0x68A
309#define ARIZONA_OUT1RMIX_INPUT_2_VOLUME 0x68B
310#define ARIZONA_OUT1RMIX_INPUT_3_SOURCE 0x68C
311#define ARIZONA_OUT1RMIX_INPUT_3_VOLUME 0x68D
312#define ARIZONA_OUT1RMIX_INPUT_4_SOURCE 0x68E
313#define ARIZONA_OUT1RMIX_INPUT_4_VOLUME 0x68F
314#define ARIZONA_OUT2LMIX_INPUT_1_SOURCE 0x690
315#define ARIZONA_OUT2LMIX_INPUT_1_VOLUME 0x691
316#define ARIZONA_OUT2LMIX_INPUT_2_SOURCE 0x692
317#define ARIZONA_OUT2LMIX_INPUT_2_VOLUME 0x693
318#define ARIZONA_OUT2LMIX_INPUT_3_SOURCE 0x694
319#define ARIZONA_OUT2LMIX_INPUT_3_VOLUME 0x695
320#define ARIZONA_OUT2LMIX_INPUT_4_SOURCE 0x696
321#define ARIZONA_OUT2LMIX_INPUT_4_VOLUME 0x697
322#define ARIZONA_OUT2RMIX_INPUT_1_SOURCE 0x698
323#define ARIZONA_OUT2RMIX_INPUT_1_VOLUME 0x699
324#define ARIZONA_OUT2RMIX_INPUT_2_SOURCE 0x69A
325#define ARIZONA_OUT2RMIX_INPUT_2_VOLUME 0x69B
326#define ARIZONA_OUT2RMIX_INPUT_3_SOURCE 0x69C
327#define ARIZONA_OUT2RMIX_INPUT_3_VOLUME 0x69D
328#define ARIZONA_OUT2RMIX_INPUT_4_SOURCE 0x69E
329#define ARIZONA_OUT2RMIX_INPUT_4_VOLUME 0x69F
330#define ARIZONA_OUT3LMIX_INPUT_1_SOURCE 0x6A0
331#define ARIZONA_OUT3LMIX_INPUT_1_VOLUME 0x6A1
332#define ARIZONA_OUT3LMIX_INPUT_2_SOURCE 0x6A2
333#define ARIZONA_OUT3LMIX_INPUT_2_VOLUME 0x6A3
334#define ARIZONA_OUT3LMIX_INPUT_3_SOURCE 0x6A4
335#define ARIZONA_OUT3LMIX_INPUT_3_VOLUME 0x6A5
336#define ARIZONA_OUT3LMIX_INPUT_4_SOURCE 0x6A6
337#define ARIZONA_OUT3LMIX_INPUT_4_VOLUME 0x6A7
338#define ARIZONA_OUT4LMIX_INPUT_1_SOURCE 0x6B0
339#define ARIZONA_OUT4LMIX_INPUT_1_VOLUME 0x6B1
340#define ARIZONA_OUT4LMIX_INPUT_2_SOURCE 0x6B2
341#define ARIZONA_OUT4LMIX_INPUT_2_VOLUME 0x6B3
342#define ARIZONA_OUT4LMIX_INPUT_3_SOURCE 0x6B4
343#define ARIZONA_OUT4LMIX_INPUT_3_VOLUME 0x6B5
344#define ARIZONA_OUT4LMIX_INPUT_4_SOURCE 0x6B6
345#define ARIZONA_OUT4LMIX_INPUT_4_VOLUME 0x6B7
346#define ARIZONA_OUT4RMIX_INPUT_1_SOURCE 0x6B8
347#define ARIZONA_OUT4RMIX_INPUT_1_VOLUME 0x6B9
348#define ARIZONA_OUT4RMIX_INPUT_2_SOURCE 0x6BA
349#define ARIZONA_OUT4RMIX_INPUT_2_VOLUME 0x6BB
350#define ARIZONA_OUT4RMIX_INPUT_3_SOURCE 0x6BC
351#define ARIZONA_OUT4RMIX_INPUT_3_VOLUME 0x6BD
352#define ARIZONA_OUT4RMIX_INPUT_4_SOURCE 0x6BE
353#define ARIZONA_OUT4RMIX_INPUT_4_VOLUME 0x6BF
354#define ARIZONA_OUT5LMIX_INPUT_1_SOURCE 0x6C0
355#define ARIZONA_OUT5LMIX_INPUT_1_VOLUME 0x6C1
356#define ARIZONA_OUT5LMIX_INPUT_2_SOURCE 0x6C2
357#define ARIZONA_OUT5LMIX_INPUT_2_VOLUME 0x6C3
358#define ARIZONA_OUT5LMIX_INPUT_3_SOURCE 0x6C4
359#define ARIZONA_OUT5LMIX_INPUT_3_VOLUME 0x6C5
360#define ARIZONA_OUT5LMIX_INPUT_4_SOURCE 0x6C6
361#define ARIZONA_OUT5LMIX_INPUT_4_VOLUME 0x6C7
362#define ARIZONA_OUT5RMIX_INPUT_1_SOURCE 0x6C8
363#define ARIZONA_OUT5RMIX_INPUT_1_VOLUME 0x6C9
364#define ARIZONA_OUT5RMIX_INPUT_2_SOURCE 0x6CA
365#define ARIZONA_OUT5RMIX_INPUT_2_VOLUME 0x6CB
366#define ARIZONA_OUT5RMIX_INPUT_3_SOURCE 0x6CC
367#define ARIZONA_OUT5RMIX_INPUT_3_VOLUME 0x6CD
368#define ARIZONA_OUT5RMIX_INPUT_4_SOURCE 0x6CE
369#define ARIZONA_OUT5RMIX_INPUT_4_VOLUME 0x6CF
370#define ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE 0x700
371#define ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME 0x701
372#define ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE 0x702
373#define ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME 0x703
374#define ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE 0x704
375#define ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME 0x705
376#define ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE 0x706
377#define ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME 0x707
378#define ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE 0x708
379#define ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME 0x709
380#define ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE 0x70A
381#define ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME 0x70B
382#define ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE 0x70C
383#define ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME 0x70D
384#define ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE 0x70E
385#define ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME 0x70F
386#define ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE 0x710
387#define ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME 0x711
388#define ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE 0x712
389#define ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME 0x713
390#define ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE 0x714
391#define ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME 0x715
392#define ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE 0x716
393#define ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME 0x717
394#define ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE 0x718
395#define ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME 0x719
396#define ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE 0x71A
397#define ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME 0x71B
398#define ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE 0x71C
399#define ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME 0x71D
400#define ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE 0x71E
401#define ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME 0x71F
402#define ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE 0x720
403#define ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME 0x721
404#define ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE 0x722
405#define ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME 0x723
406#define ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE 0x724
407#define ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME 0x725
408#define ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE 0x726
409#define ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME 0x727
410#define ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE 0x728
411#define ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME 0x729
412#define ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE 0x72A
413#define ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME 0x72B
414#define ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE 0x72C
415#define ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME 0x72D
416#define ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE 0x72E
417#define ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME 0x72F
418#define ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE 0x730
419#define ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME 0x731
420#define ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE 0x732
421#define ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME 0x733
422#define ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE 0x734
423#define ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME 0x735
424#define ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE 0x736
425#define ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME 0x737
426#define ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE 0x738
427#define ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME 0x739
428#define ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE 0x73A
429#define ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME 0x73B
430#define ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE 0x73C
431#define ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME 0x73D
432#define ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE 0x73E
433#define ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME 0x73F
434#define ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE 0x740
435#define ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME 0x741
436#define ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE 0x742
437#define ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME 0x743
438#define ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE 0x744
439#define ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME 0x745
440#define ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE 0x746
441#define ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME 0x747
442#define ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE 0x748
443#define ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME 0x749
444#define ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE 0x74A
445#define ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME 0x74B
446#define ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE 0x74C
447#define ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME 0x74D
448#define ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE 0x74E
449#define ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME 0x74F
450#define ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE 0x780
451#define ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME 0x781
452#define ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE 0x782
453#define ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME 0x783
454#define ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE 0x784
455#define ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME 0x785
456#define ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE 0x786
457#define ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME 0x787
458#define ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE 0x788
459#define ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME 0x789
460#define ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE 0x78A
461#define ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME 0x78B
462#define ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE 0x78C
463#define ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME 0x78D
464#define ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE 0x78E
465#define ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME 0x78F
466#define ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE 0x7C0
467#define ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME 0x7C1
468#define ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE 0x7C2
469#define ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME 0x7C3
470#define ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE 0x7C4
471#define ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME 0x7C5
472#define ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE 0x7C6
473#define ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME 0x7C7
474#define ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE 0x7C8
475#define ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME 0x7C9
476#define ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE 0x7CA
477#define ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME 0x7CB
478#define ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE 0x7CC
479#define ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME 0x7CD
480#define ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE 0x7CE
481#define ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME 0x7CF
482#define ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE 0x7D0
483#define ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME 0x7D1
484#define ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE 0x7D2
485#define ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME 0x7D3
486#define ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE 0x7D4
487#define ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME 0x7D5
488#define ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE 0x7D6
489#define ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME 0x7D7
490#define ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE 0x7D8
491#define ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME 0x7D9
492#define ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE 0x7DA
493#define ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME 0x7DB
494#define ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE 0x7DC
495#define ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME 0x7DD
496#define ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE 0x7DE
497#define ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME 0x7DF
498#define ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE 0x7E0
499#define ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME 0x7E1
500#define ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE 0x7E2
501#define ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME 0x7E3
502#define ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE 0x7E4
503#define ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME 0x7E5
504#define ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE 0x7E6
505#define ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME 0x7E7
506#define ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE 0x7E8
507#define ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME 0x7E9
508#define ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE 0x7EA
509#define ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME 0x7EB
510#define ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE 0x7EC
511#define ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME 0x7ED
512#define ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE 0x7EE
513#define ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME 0x7EF
514#define ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE 0x7F0
515#define ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME 0x7F1
516#define ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE 0x7F2
517#define ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME 0x7F3
518#define ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE 0x7F4
519#define ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME 0x7F5
520#define ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE 0x7F6
521#define ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME 0x7F7
522#define ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE 0x7F8
523#define ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME 0x7F9
524#define ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE 0x7FA
525#define ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME 0x7FB
526#define ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE 0x7FC
527#define ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME 0x7FD
528#define ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE 0x7FE
529#define ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME 0x7FF
530#define ARIZONA_EQ1MIX_INPUT_1_SOURCE 0x880
531#define ARIZONA_EQ1MIX_INPUT_1_VOLUME 0x881
532#define ARIZONA_EQ1MIX_INPUT_2_SOURCE 0x882
533#define ARIZONA_EQ1MIX_INPUT_2_VOLUME 0x883
534#define ARIZONA_EQ1MIX_INPUT_3_SOURCE 0x884
535#define ARIZONA_EQ1MIX_INPUT_3_VOLUME 0x885
536#define ARIZONA_EQ1MIX_INPUT_4_SOURCE 0x886
537#define ARIZONA_EQ1MIX_INPUT_4_VOLUME 0x887
538#define ARIZONA_EQ2MIX_INPUT_1_SOURCE 0x888
539#define ARIZONA_EQ2MIX_INPUT_1_VOLUME 0x889
540#define ARIZONA_EQ2MIX_INPUT_2_SOURCE 0x88A
541#define ARIZONA_EQ2MIX_INPUT_2_VOLUME 0x88B
542#define ARIZONA_EQ2MIX_INPUT_3_SOURCE 0x88C
543#define ARIZONA_EQ2MIX_INPUT_3_VOLUME 0x88D
544#define ARIZONA_EQ2MIX_INPUT_4_SOURCE 0x88E
545#define ARIZONA_EQ2MIX_INPUT_4_VOLUME 0x88F
546#define ARIZONA_EQ3MIX_INPUT_1_SOURCE 0x890
547#define ARIZONA_EQ3MIX_INPUT_1_VOLUME 0x891
548#define ARIZONA_EQ3MIX_INPUT_2_SOURCE 0x892
549#define ARIZONA_EQ3MIX_INPUT_2_VOLUME 0x893
550#define ARIZONA_EQ3MIX_INPUT_3_SOURCE 0x894
551#define ARIZONA_EQ3MIX_INPUT_3_VOLUME 0x895
552#define ARIZONA_EQ3MIX_INPUT_4_SOURCE 0x896
553#define ARIZONA_EQ3MIX_INPUT_4_VOLUME 0x897
554#define ARIZONA_EQ4MIX_INPUT_1_SOURCE 0x898
555#define ARIZONA_EQ4MIX_INPUT_1_VOLUME 0x899
556#define ARIZONA_EQ4MIX_INPUT_2_SOURCE 0x89A
557#define ARIZONA_EQ4MIX_INPUT_2_VOLUME 0x89B
558#define ARIZONA_EQ4MIX_INPUT_3_SOURCE 0x89C
559#define ARIZONA_EQ4MIX_INPUT_3_VOLUME 0x89D
560#define ARIZONA_EQ4MIX_INPUT_4_SOURCE 0x89E
561#define ARIZONA_EQ4MIX_INPUT_4_VOLUME 0x89F
562#define ARIZONA_DRC1LMIX_INPUT_1_SOURCE 0x8C0
563#define ARIZONA_DRC1LMIX_INPUT_1_VOLUME 0x8C1
564#define ARIZONA_DRC1LMIX_INPUT_2_SOURCE 0x8C2
565#define ARIZONA_DRC1LMIX_INPUT_2_VOLUME 0x8C3
566#define ARIZONA_DRC1LMIX_INPUT_3_SOURCE 0x8C4
567#define ARIZONA_DRC1LMIX_INPUT_3_VOLUME 0x8C5
568#define ARIZONA_DRC1LMIX_INPUT_4_SOURCE 0x8C6
569#define ARIZONA_DRC1LMIX_INPUT_4_VOLUME 0x8C7
570#define ARIZONA_DRC1RMIX_INPUT_1_SOURCE 0x8C8
571#define ARIZONA_DRC1RMIX_INPUT_1_VOLUME 0x8C9
572#define ARIZONA_DRC1RMIX_INPUT_2_SOURCE 0x8CA
573#define ARIZONA_DRC1RMIX_INPUT_2_VOLUME 0x8CB
574#define ARIZONA_DRC1RMIX_INPUT_3_SOURCE 0x8CC
575#define ARIZONA_DRC1RMIX_INPUT_3_VOLUME 0x8CD
576#define ARIZONA_DRC1RMIX_INPUT_4_SOURCE 0x8CE
577#define ARIZONA_DRC1RMIX_INPUT_4_VOLUME 0x8CF
578#define ARIZONA_DRC2LMIX_INPUT_1_SOURCE 0x8D0
579#define ARIZONA_DRC2LMIX_INPUT_1_VOLUME 0x8D1
580#define ARIZONA_DRC2LMIX_INPUT_2_SOURCE 0x8D2
581#define ARIZONA_DRC2LMIX_INPUT_2_VOLUME 0x8D3
582#define ARIZONA_DRC2LMIX_INPUT_3_SOURCE 0x8D4
583#define ARIZONA_DRC2LMIX_INPUT_3_VOLUME 0x8D5
584#define ARIZONA_DRC2LMIX_INPUT_4_SOURCE 0x8D6
585#define ARIZONA_DRC2LMIX_INPUT_4_VOLUME 0x8D7
586#define ARIZONA_DRC2RMIX_INPUT_1_SOURCE 0x8D8
587#define ARIZONA_DRC2RMIX_INPUT_1_VOLUME 0x8D9
588#define ARIZONA_DRC2RMIX_INPUT_2_SOURCE 0x8DA
589#define ARIZONA_DRC2RMIX_INPUT_2_VOLUME 0x8DB
590#define ARIZONA_DRC2RMIX_INPUT_3_SOURCE 0x8DC
591#define ARIZONA_DRC2RMIX_INPUT_3_VOLUME 0x8DD
592#define ARIZONA_DRC2RMIX_INPUT_4_SOURCE 0x8DE
593#define ARIZONA_DRC2RMIX_INPUT_4_VOLUME 0x8DF
594#define ARIZONA_HPLP1MIX_INPUT_1_SOURCE 0x900
595#define ARIZONA_HPLP1MIX_INPUT_1_VOLUME 0x901
596#define ARIZONA_HPLP1MIX_INPUT_2_SOURCE 0x902
597#define ARIZONA_HPLP1MIX_INPUT_2_VOLUME 0x903
598#define ARIZONA_HPLP1MIX_INPUT_3_SOURCE 0x904
599#define ARIZONA_HPLP1MIX_INPUT_3_VOLUME 0x905
600#define ARIZONA_HPLP1MIX_INPUT_4_SOURCE 0x906
601#define ARIZONA_HPLP1MIX_INPUT_4_VOLUME 0x907
602#define ARIZONA_HPLP2MIX_INPUT_1_SOURCE 0x908
603#define ARIZONA_HPLP2MIX_INPUT_1_VOLUME 0x909
604#define ARIZONA_HPLP2MIX_INPUT_2_SOURCE 0x90A
605#define ARIZONA_HPLP2MIX_INPUT_2_VOLUME 0x90B
606#define ARIZONA_HPLP2MIX_INPUT_3_SOURCE 0x90C
607#define ARIZONA_HPLP2MIX_INPUT_3_VOLUME 0x90D
608#define ARIZONA_HPLP2MIX_INPUT_4_SOURCE 0x90E
609#define ARIZONA_HPLP2MIX_INPUT_4_VOLUME 0x90F
610#define ARIZONA_HPLP3MIX_INPUT_1_SOURCE 0x910
611#define ARIZONA_HPLP3MIX_INPUT_1_VOLUME 0x911
612#define ARIZONA_HPLP3MIX_INPUT_2_SOURCE 0x912
613#define ARIZONA_HPLP3MIX_INPUT_2_VOLUME 0x913
614#define ARIZONA_HPLP3MIX_INPUT_3_SOURCE 0x914
615#define ARIZONA_HPLP3MIX_INPUT_3_VOLUME 0x915
616#define ARIZONA_HPLP3MIX_INPUT_4_SOURCE 0x916
617#define ARIZONA_HPLP3MIX_INPUT_4_VOLUME 0x917
618#define ARIZONA_HPLP4MIX_INPUT_1_SOURCE 0x918
619#define ARIZONA_HPLP4MIX_INPUT_1_VOLUME 0x919
620#define ARIZONA_HPLP4MIX_INPUT_2_SOURCE 0x91A
621#define ARIZONA_HPLP4MIX_INPUT_2_VOLUME 0x91B
622#define ARIZONA_HPLP4MIX_INPUT_3_SOURCE 0x91C
623#define ARIZONA_HPLP4MIX_INPUT_3_VOLUME 0x91D
624#define ARIZONA_HPLP4MIX_INPUT_4_SOURCE 0x91E
625#define ARIZONA_HPLP4MIX_INPUT_4_VOLUME 0x91F
626#define ARIZONA_DSP1LMIX_INPUT_1_SOURCE 0x940
627#define ARIZONA_DSP1LMIX_INPUT_1_VOLUME 0x941
628#define ARIZONA_DSP1LMIX_INPUT_2_SOURCE 0x942
629#define ARIZONA_DSP1LMIX_INPUT_2_VOLUME 0x943
630#define ARIZONA_DSP1LMIX_INPUT_3_SOURCE 0x944
631#define ARIZONA_DSP1LMIX_INPUT_3_VOLUME 0x945
632#define ARIZONA_DSP1LMIX_INPUT_4_SOURCE 0x946
633#define ARIZONA_DSP1LMIX_INPUT_4_VOLUME 0x947
634#define ARIZONA_DSP1RMIX_INPUT_1_SOURCE 0x948
635#define ARIZONA_DSP1RMIX_INPUT_1_VOLUME 0x949
636#define ARIZONA_DSP1RMIX_INPUT_2_SOURCE 0x94A
637#define ARIZONA_DSP1RMIX_INPUT_2_VOLUME 0x94B
638#define ARIZONA_DSP1RMIX_INPUT_3_SOURCE 0x94C
639#define ARIZONA_DSP1RMIX_INPUT_3_VOLUME 0x94D
640#define ARIZONA_DSP1RMIX_INPUT_4_SOURCE 0x94E
641#define ARIZONA_DSP1RMIX_INPUT_4_VOLUME 0x94F
642#define ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE 0x950
643#define ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE 0x958
644#define ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE 0x960
645#define ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE 0x968
646#define ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE 0x970
647#define ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE 0x978
648#define ARIZONA_ASRC1LMIX_INPUT_1_SOURCE 0xA80
649#define ARIZONA_ASRC1RMIX_INPUT_1_SOURCE 0xA88
650#define ARIZONA_ASRC2LMIX_INPUT_1_SOURCE 0xA90
651#define ARIZONA_ASRC2RMIX_INPUT_1_SOURCE 0xA98
652#define ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00
653#define ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08
654#define ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20
655#define ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28
656#define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40
657#define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48
658#define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60
659#define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68
660#define ARIZONA_GPIO1_CTRL 0xC00
661#define ARIZONA_GPIO2_CTRL 0xC01
662#define ARIZONA_GPIO3_CTRL 0xC02
663#define ARIZONA_GPIO4_CTRL 0xC03
664#define ARIZONA_GPIO5_CTRL 0xC04
665#define ARIZONA_IRQ_CTRL_1 0xC0F
666#define ARIZONA_GPIO_DEBOUNCE_CONFIG 0xC10
667#define ARIZONA_MISC_PAD_CTRL_1 0xC20
668#define ARIZONA_MISC_PAD_CTRL_2 0xC21
669#define ARIZONA_MISC_PAD_CTRL_3 0xC22
670#define ARIZONA_MISC_PAD_CTRL_4 0xC23
671#define ARIZONA_MISC_PAD_CTRL_5 0xC24
672#define ARIZONA_MISC_PAD_CTRL_6 0xC25
673#define ARIZONA_INTERRUPT_STATUS_1 0xD00
674#define ARIZONA_INTERRUPT_STATUS_2 0xD01
675#define ARIZONA_INTERRUPT_STATUS_3 0xD02
676#define ARIZONA_INTERRUPT_STATUS_4 0xD03
677#define ARIZONA_INTERRUPT_STATUS_5 0xD04
678#define ARIZONA_INTERRUPT_STATUS_1_MASK 0xD08
679#define ARIZONA_INTERRUPT_STATUS_2_MASK 0xD09
680#define ARIZONA_INTERRUPT_STATUS_3_MASK 0xD0A
681#define ARIZONA_INTERRUPT_STATUS_4_MASK 0xD0B
682#define ARIZONA_INTERRUPT_STATUS_5_MASK 0xD0C
683#define ARIZONA_INTERRUPT_CONTROL 0xD0F
684#define ARIZONA_IRQ2_STATUS_1 0xD10
685#define ARIZONA_IRQ2_STATUS_2 0xD11
686#define ARIZONA_IRQ2_STATUS_3 0xD12
687#define ARIZONA_IRQ2_STATUS_4 0xD13
688#define ARIZONA_IRQ2_STATUS_5 0xD14
689#define ARIZONA_IRQ2_STATUS_1_MASK 0xD18
690#define ARIZONA_IRQ2_STATUS_2_MASK 0xD19
691#define ARIZONA_IRQ2_STATUS_3_MASK 0xD1A
692#define ARIZONA_IRQ2_STATUS_4_MASK 0xD1B
693#define ARIZONA_IRQ2_STATUS_5_MASK 0xD1C
694#define ARIZONA_IRQ2_CONTROL 0xD1F
695#define ARIZONA_INTERRUPT_RAW_STATUS_2 0xD20
696#define ARIZONA_INTERRUPT_RAW_STATUS_3 0xD21
697#define ARIZONA_INTERRUPT_RAW_STATUS_4 0xD22
698#define ARIZONA_INTERRUPT_RAW_STATUS_5 0xD23
699#define ARIZONA_INTERRUPT_RAW_STATUS_6 0xD24
700#define ARIZONA_INTERRUPT_RAW_STATUS_7 0xD25
701#define ARIZONA_INTERRUPT_RAW_STATUS_8 0xD26
702#define ARIZONA_IRQ_PIN_STATUS 0xD40
703#define ARIZONA_ADSP2_IRQ0 0xD41
704#define ARIZONA_AOD_WKUP_AND_TRIG 0xD50
705#define ARIZONA_AOD_IRQ1 0xD51
706#define ARIZONA_AOD_IRQ2 0xD52
707#define ARIZONA_AOD_IRQ_MASK_IRQ1 0xD53
708#define ARIZONA_AOD_IRQ_MASK_IRQ2 0xD54
709#define ARIZONA_AOD_IRQ_RAW_STATUS 0xD55
710#define ARIZONA_JACK_DETECT_DEBOUNCE 0xD56
711#define ARIZONA_FX_CTRL1 0xE00
712#define ARIZONA_FX_CTRL2 0xE01
713#define ARIZONA_EQ1_1 0xE10
714#define ARIZONA_EQ1_2 0xE11
715#define ARIZONA_EQ1_3 0xE12
716#define ARIZONA_EQ1_4 0xE13
717#define ARIZONA_EQ1_5 0xE14
718#define ARIZONA_EQ1_6 0xE15
719#define ARIZONA_EQ1_7 0xE16
720#define ARIZONA_EQ1_8 0xE17
721#define ARIZONA_EQ1_9 0xE18
722#define ARIZONA_EQ1_10 0xE19
723#define ARIZONA_EQ1_11 0xE1A
724#define ARIZONA_EQ1_12 0xE1B
725#define ARIZONA_EQ1_13 0xE1C
726#define ARIZONA_EQ1_14 0xE1D
727#define ARIZONA_EQ1_15 0xE1E
728#define ARIZONA_EQ1_16 0xE1F
729#define ARIZONA_EQ1_17 0xE20
730#define ARIZONA_EQ1_18 0xE21
731#define ARIZONA_EQ1_19 0xE22
732#define ARIZONA_EQ1_20 0xE23
733#define ARIZONA_EQ1_21 0xE24
734#define ARIZONA_EQ2_1 0xE26
735#define ARIZONA_EQ2_2 0xE27
736#define ARIZONA_EQ2_3 0xE28
737#define ARIZONA_EQ2_4 0xE29
738#define ARIZONA_EQ2_5 0xE2A
739#define ARIZONA_EQ2_6 0xE2B
740#define ARIZONA_EQ2_7 0xE2C
741#define ARIZONA_EQ2_8 0xE2D
742#define ARIZONA_EQ2_9 0xE2E
743#define ARIZONA_EQ2_10 0xE2F
744#define ARIZONA_EQ2_11 0xE30
745#define ARIZONA_EQ2_12 0xE31
746#define ARIZONA_EQ2_13 0xE32
747#define ARIZONA_EQ2_14 0xE33
748#define ARIZONA_EQ2_15 0xE34
749#define ARIZONA_EQ2_16 0xE35
750#define ARIZONA_EQ2_17 0xE36
751#define ARIZONA_EQ2_18 0xE37
752#define ARIZONA_EQ2_19 0xE38
753#define ARIZONA_EQ2_20 0xE39
754#define ARIZONA_EQ2_21 0xE3A
755#define ARIZONA_EQ3_1 0xE3C
756#define ARIZONA_EQ3_2 0xE3D
757#define ARIZONA_EQ3_3 0xE3E
758#define ARIZONA_EQ3_4 0xE3F
759#define ARIZONA_EQ3_5 0xE40
760#define ARIZONA_EQ3_6 0xE41
761#define ARIZONA_EQ3_7 0xE42
762#define ARIZONA_EQ3_8 0xE43
763#define ARIZONA_EQ3_9 0xE44
764#define ARIZONA_EQ3_10 0xE45
765#define ARIZONA_EQ3_11 0xE46
766#define ARIZONA_EQ3_12 0xE47
767#define ARIZONA_EQ3_13 0xE48
768#define ARIZONA_EQ3_14 0xE49
769#define ARIZONA_EQ3_15 0xE4A
770#define ARIZONA_EQ3_16 0xE4B
771#define ARIZONA_EQ3_17 0xE4C
772#define ARIZONA_EQ3_18 0xE4D
773#define ARIZONA_EQ3_19 0xE4E
774#define ARIZONA_EQ3_20 0xE4F
775#define ARIZONA_EQ3_21 0xE50
776#define ARIZONA_EQ4_1 0xE52
777#define ARIZONA_EQ4_2 0xE53
778#define ARIZONA_EQ4_3 0xE54
779#define ARIZONA_EQ4_4 0xE55
780#define ARIZONA_EQ4_5 0xE56
781#define ARIZONA_EQ4_6 0xE57
782#define ARIZONA_EQ4_7 0xE58
783#define ARIZONA_EQ4_8 0xE59
784#define ARIZONA_EQ4_9 0xE5A
785#define ARIZONA_EQ4_10 0xE5B
786#define ARIZONA_EQ4_11 0xE5C
787#define ARIZONA_EQ4_12 0xE5D
788#define ARIZONA_EQ4_13 0xE5E
789#define ARIZONA_EQ4_14 0xE5F
790#define ARIZONA_EQ4_15 0xE60
791#define ARIZONA_EQ4_16 0xE61
792#define ARIZONA_EQ4_17 0xE62
793#define ARIZONA_EQ4_18 0xE63
794#define ARIZONA_EQ4_19 0xE64
795#define ARIZONA_EQ4_20 0xE65
796#define ARIZONA_EQ4_21 0xE66
797#define ARIZONA_DRC1_CTRL1 0xE80
798#define ARIZONA_DRC1_CTRL2 0xE81
799#define ARIZONA_DRC1_CTRL3 0xE82
800#define ARIZONA_DRC1_CTRL4 0xE83
801#define ARIZONA_DRC1_CTRL5 0xE84
802#define ARIZONA_DRC2_CTRL1 0xE89
803#define ARIZONA_DRC2_CTRL2 0xE8A
804#define ARIZONA_DRC2_CTRL3 0xE8B
805#define ARIZONA_DRC2_CTRL4 0xE8C
806#define ARIZONA_DRC2_CTRL5 0xE8D
807#define ARIZONA_HPLPF1_1 0xEC0
808#define ARIZONA_HPLPF1_2 0xEC1
809#define ARIZONA_HPLPF2_1 0xEC4
810#define ARIZONA_HPLPF2_2 0xEC5
811#define ARIZONA_HPLPF3_1 0xEC8
812#define ARIZONA_HPLPF3_2 0xEC9
813#define ARIZONA_HPLPF4_1 0xECC
814#define ARIZONA_HPLPF4_2 0xECD
815#define ARIZONA_ASRC_ENABLE 0xEE0
816#define ARIZONA_ASRC_RATE1 0xEE2
817#define ARIZONA_ASRC_RATE2 0xEE3
818#define ARIZONA_ISRC_1_CTRL_1 0xEF0
819#define ARIZONA_ISRC_1_CTRL_2 0xEF1
820#define ARIZONA_ISRC_1_CTRL_3 0xEF2
821#define ARIZONA_ISRC_2_CTRL_1 0xEF3
822#define ARIZONA_ISRC_2_CTRL_2 0xEF4
823#define ARIZONA_ISRC_2_CTRL_3 0xEF5
824#define ARIZONA_ISRC_3_CTRL_1 0xEF6
825#define ARIZONA_ISRC_3_CTRL_2 0xEF7
826#define ARIZONA_ISRC_3_CTRL_3 0xEF8
827#define ARIZONA_DSP1_CONTROL_1 0x1100
828#define ARIZONA_DSP1_CLOCKING_1 0x1101
829#define ARIZONA_DSP1_STATUS_1 0x1104
830#define ARIZONA_DSP1_STATUS_2 0x1105
831
832/*
833 * Field Definitions.
834 */
835
836/*
837 * R0 (0x00) - software reset
838 */
839#define ARIZONA_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
840#define ARIZONA_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
841#define ARIZONA_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
842
843/*
844 * R1 (0x01) - Device Revision
845 */
846#define ARIZONA_DEVICE_REVISION_MASK 0x00FF /* DEVICE_REVISION - [7:0] */
847#define ARIZONA_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [7:0] */
848#define ARIZONA_DEVICE_REVISION_WIDTH 8 /* DEVICE_REVISION - [7:0] */
849
850/*
851 * R8 (0x08) - Ctrl IF SPI CFG 1
852 */
853#define ARIZONA_SPI_CFG 0x0010 /* SPI_CFG */
854#define ARIZONA_SPI_CFG_MASK 0x0010 /* SPI_CFG */
855#define ARIZONA_SPI_CFG_SHIFT 4 /* SPI_CFG */
856#define ARIZONA_SPI_CFG_WIDTH 1 /* SPI_CFG */
857#define ARIZONA_SPI_4WIRE 0x0008 /* SPI_4WIRE */
858#define ARIZONA_SPI_4WIRE_MASK 0x0008 /* SPI_4WIRE */
859#define ARIZONA_SPI_4WIRE_SHIFT 3 /* SPI_4WIRE */
860#define ARIZONA_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
861#define ARIZONA_SPI_AUTO_INC_MASK 0x0003 /* SPI_AUTO_INC - [1:0] */
862#define ARIZONA_SPI_AUTO_INC_SHIFT 0 /* SPI_AUTO_INC - [1:0] */
863#define ARIZONA_SPI_AUTO_INC_WIDTH 2 /* SPI_AUTO_INC - [1:0] */
864
865/*
866 * R9 (0x09) - Ctrl IF I2C1 CFG 1
867 */
868#define ARIZONA_I2C1_AUTO_INC_MASK 0x0003 /* I2C1_AUTO_INC - [1:0] */
869#define ARIZONA_I2C1_AUTO_INC_SHIFT 0 /* I2C1_AUTO_INC - [1:0] */
870#define ARIZONA_I2C1_AUTO_INC_WIDTH 2 /* I2C1_AUTO_INC - [1:0] */
871
872/*
873 * R13 (0x0D) - Ctrl IF Status 1
874 */
875#define ARIZONA_I2C1_BUSY 0x0020 /* I2C1_BUSY */
876#define ARIZONA_I2C1_BUSY_MASK 0x0020 /* I2C1_BUSY */
877#define ARIZONA_I2C1_BUSY_SHIFT 5 /* I2C1_BUSY */
878#define ARIZONA_I2C1_BUSY_WIDTH 1 /* I2C1_BUSY */
879#define ARIZONA_SPI_BUSY 0x0010 /* SPI_BUSY */
880#define ARIZONA_SPI_BUSY_MASK 0x0010 /* SPI_BUSY */
881#define ARIZONA_SPI_BUSY_SHIFT 4 /* SPI_BUSY */
882#define ARIZONA_SPI_BUSY_WIDTH 1 /* SPI_BUSY */
883
884/*
885 * R22 (0x16) - Write Sequencer Ctrl 0
886 */
887#define ARIZONA_WSEQ_ABORT 0x0800 /* WSEQ_ABORT */
888#define ARIZONA_WSEQ_ABORT_MASK 0x0800 /* WSEQ_ABORT */
889#define ARIZONA_WSEQ_ABORT_SHIFT 11 /* WSEQ_ABORT */
890#define ARIZONA_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
891#define ARIZONA_WSEQ_START 0x0400 /* WSEQ_START */
892#define ARIZONA_WSEQ_START_MASK 0x0400 /* WSEQ_START */
893#define ARIZONA_WSEQ_START_SHIFT 10 /* WSEQ_START */
894#define ARIZONA_WSEQ_START_WIDTH 1 /* WSEQ_START */
895#define ARIZONA_WSEQ_ENA 0x0200 /* WSEQ_ENA */
896#define ARIZONA_WSEQ_ENA_MASK 0x0200 /* WSEQ_ENA */
897#define ARIZONA_WSEQ_ENA_SHIFT 9 /* WSEQ_ENA */
898#define ARIZONA_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
899#define ARIZONA_WSEQ_START_INDEX_MASK 0x01FF /* WSEQ_START_INDEX - [8:0] */
900#define ARIZONA_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [8:0] */
901#define ARIZONA_WSEQ_START_INDEX_WIDTH 9 /* WSEQ_START_INDEX - [8:0] */
902
903/*
904 * R23 (0x17) - Write Sequencer Ctrl 1
905 */
906#define ARIZONA_WSEQ_BUSY 0x0200 /* WSEQ_BUSY */
907#define ARIZONA_WSEQ_BUSY_MASK 0x0200 /* WSEQ_BUSY */
908#define ARIZONA_WSEQ_BUSY_SHIFT 9 /* WSEQ_BUSY */
909#define ARIZONA_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
910#define ARIZONA_WSEQ_CURRENT_INDEX_MASK 0x01FF /* WSEQ_CURRENT_INDEX - [8:0] */
911#define ARIZONA_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [8:0] */
912#define ARIZONA_WSEQ_CURRENT_INDEX_WIDTH 9 /* WSEQ_CURRENT_INDEX - [8:0] */
913
914/*
915 * R24 (0x18) - Write Sequencer Ctrl 2
916 */
917#define ARIZONA_LOAD_DEFAULTS 0x0002 /* LOAD_DEFAULTS */
918#define ARIZONA_LOAD_DEFAULTS_MASK 0x0002 /* LOAD_DEFAULTS */
919#define ARIZONA_LOAD_DEFAULTS_SHIFT 1 /* LOAD_DEFAULTS */
920#define ARIZONA_LOAD_DEFAULTS_WIDTH 1 /* LOAD_DEFAULTS */
921#define ARIZONA_WSEQ_LOAD_MEM 0x0001 /* WSEQ_LOAD_MEM */
922#define ARIZONA_WSEQ_LOAD_MEM_MASK 0x0001 /* WSEQ_LOAD_MEM */
923#define ARIZONA_WSEQ_LOAD_MEM_SHIFT 0 /* WSEQ_LOAD_MEM */
924#define ARIZONA_WSEQ_LOAD_MEM_WIDTH 1 /* WSEQ_LOAD_MEM */
925
926/*
927 * R26 (0x1A) - Write Sequencer PROM
928 */
929#define ARIZONA_WSEQ_OTP_WRITE 0x0001 /* WSEQ_OTP_WRITE */
930#define ARIZONA_WSEQ_OTP_WRITE_MASK 0x0001 /* WSEQ_OTP_WRITE */
931#define ARIZONA_WSEQ_OTP_WRITE_SHIFT 0 /* WSEQ_OTP_WRITE */
932#define ARIZONA_WSEQ_OTP_WRITE_WIDTH 1 /* WSEQ_OTP_WRITE */
933
934/*
935 * R32 (0x20) - Tone Generator 1
936 */
937#define ARIZONA_TONE_RATE_MASK 0x7800 /* TONE_RATE - [14:11] */
938#define ARIZONA_TONE_RATE_SHIFT 11 /* TONE_RATE - [14:11] */
939#define ARIZONA_TONE_RATE_WIDTH 4 /* TONE_RATE - [14:11] */
940#define ARIZONA_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */
941#define ARIZONA_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */
942#define ARIZONA_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */
943#define ARIZONA_TONE2_OVD 0x0020 /* TONE2_OVD */
944#define ARIZONA_TONE2_OVD_MASK 0x0020 /* TONE2_OVD */
945#define ARIZONA_TONE2_OVD_SHIFT 5 /* TONE2_OVD */
946#define ARIZONA_TONE2_OVD_WIDTH 1 /* TONE2_OVD */
947#define ARIZONA_TONE1_OVD 0x0010 /* TONE1_OVD */
948#define ARIZONA_TONE1_OVD_MASK 0x0010 /* TONE1_OVD */
949#define ARIZONA_TONE1_OVD_SHIFT 4 /* TONE1_OVD */
950#define ARIZONA_TONE1_OVD_WIDTH 1 /* TONE1_OVD */
951#define ARIZONA_TONE2_ENA 0x0002 /* TONE2_ENA */
952#define ARIZONA_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */
953#define ARIZONA_TONE2_ENA_SHIFT 1 /* TONE2_ENA */
954#define ARIZONA_TONE2_ENA_WIDTH 1 /* TONE2_ENA */
955#define ARIZONA_TONE1_ENA 0x0001 /* TONE1_ENA */
956#define ARIZONA_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */
957#define ARIZONA_TONE1_ENA_SHIFT 0 /* TONE1_ENA */
958#define ARIZONA_TONE1_ENA_WIDTH 1 /* TONE1_ENA */
959
960/*
961 * R33 (0x21) - Tone Generator 2
962 */
963#define ARIZONA_TONE1_LVL_0_MASK 0xFFFF /* TONE1_LVL - [15:0] */
964#define ARIZONA_TONE1_LVL_0_SHIFT 0 /* TONE1_LVL - [15:0] */
965#define ARIZONA_TONE1_LVL_0_WIDTH 16 /* TONE1_LVL - [15:0] */
966
967/*
968 * R34 (0x22) - Tone Generator 3
969 */
970#define ARIZONA_TONE1_LVL_MASK 0x00FF /* TONE1_LVL - [7:0] */
971#define ARIZONA_TONE1_LVL_SHIFT 0 /* TONE1_LVL - [7:0] */
972#define ARIZONA_TONE1_LVL_WIDTH 8 /* TONE1_LVL - [7:0] */
973
974/*
975 * R35 (0x23) - Tone Generator 4
976 */
977#define ARIZONA_TONE2_LVL_0_MASK 0xFFFF /* TONE2_LVL - [15:0] */
978#define ARIZONA_TONE2_LVL_0_SHIFT 0 /* TONE2_LVL - [15:0] */
979#define ARIZONA_TONE2_LVL_0_WIDTH 16 /* TONE2_LVL - [15:0] */
980
981/*
982 * R36 (0x24) - Tone Generator 5
983 */
984#define ARIZONA_TONE2_LVL_MASK 0x00FF /* TONE2_LVL - [7:0] */
985#define ARIZONA_TONE2_LVL_SHIFT 0 /* TONE2_LVL - [7:0] */
986#define ARIZONA_TONE2_LVL_WIDTH 8 /* TONE2_LVL - [7:0] */
987
988/*
989 * R48 (0x30) - PWM Drive 1
990 */
991#define ARIZONA_PWM_RATE_MASK 0x7800 /* PWM_RATE - [14:11] */
992#define ARIZONA_PWM_RATE_SHIFT 11 /* PWM_RATE - [14:11] */
993#define ARIZONA_PWM_RATE_WIDTH 4 /* PWM_RATE - [14:11] */
994#define ARIZONA_PWM_CLK_SEL_MASK 0x0700 /* PWM_CLK_SEL - [10:8] */
995#define ARIZONA_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [10:8] */
996#define ARIZONA_PWM_CLK_SEL_WIDTH 3 /* PWM_CLK_SEL - [10:8] */
997#define ARIZONA_PWM2_OVD 0x0020 /* PWM2_OVD */
998#define ARIZONA_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */
999#define ARIZONA_PWM2_OVD_SHIFT 5 /* PWM2_OVD */
1000#define ARIZONA_PWM2_OVD_WIDTH 1 /* PWM2_OVD */
1001#define ARIZONA_PWM1_OVD 0x0010 /* PWM1_OVD */
1002#define ARIZONA_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */
1003#define ARIZONA_PWM1_OVD_SHIFT 4 /* PWM1_OVD */
1004#define ARIZONA_PWM1_OVD_WIDTH 1 /* PWM1_OVD */
1005#define ARIZONA_PWM2_ENA 0x0002 /* PWM2_ENA */
1006#define ARIZONA_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */
1007#define ARIZONA_PWM2_ENA_SHIFT 1 /* PWM2_ENA */
1008#define ARIZONA_PWM2_ENA_WIDTH 1 /* PWM2_ENA */
1009#define ARIZONA_PWM1_ENA 0x0001 /* PWM1_ENA */
1010#define ARIZONA_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */
1011#define ARIZONA_PWM1_ENA_SHIFT 0 /* PWM1_ENA */
1012#define ARIZONA_PWM1_ENA_WIDTH 1 /* PWM1_ENA */
1013
1014/*
1015 * R49 (0x31) - PWM Drive 2
1016 */
1017#define ARIZONA_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */
1018#define ARIZONA_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */
1019#define ARIZONA_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */
1020
1021/*
1022 * R50 (0x32) - PWM Drive 3
1023 */
1024#define ARIZONA_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */
1025#define ARIZONA_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */
1026#define ARIZONA_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */
1027
1028/*
1029 * R64 (0x40) - Wake control
1030 */
1031#define ARIZONA_WKUP_GP5_FALL 0x0020 /* WKUP_GP5_FALL */
1032#define ARIZONA_WKUP_GP5_FALL_MASK 0x0020 /* WKUP_GP5_FALL */
1033#define ARIZONA_WKUP_GP5_FALL_SHIFT 5 /* WKUP_GP5_FALL */
1034#define ARIZONA_WKUP_GP5_FALL_WIDTH 1 /* WKUP_GP5_FALL */
1035#define ARIZONA_WKUP_GP5_RISE 0x0010 /* WKUP_GP5_RISE */
1036#define ARIZONA_WKUP_GP5_RISE_MASK 0x0010 /* WKUP_GP5_RISE */
1037#define ARIZONA_WKUP_GP5_RISE_SHIFT 4 /* WKUP_GP5_RISE */
1038#define ARIZONA_WKUP_GP5_RISE_WIDTH 1 /* WKUP_GP5_RISE */
1039#define ARIZONA_WKUP_JD1_FALL 0x0008 /* WKUP_JD1_FALL */
1040#define ARIZONA_WKUP_JD1_FALL_MASK 0x0008 /* WKUP_JD1_FALL */
1041#define ARIZONA_WKUP_JD1_FALL_SHIFT 3 /* WKUP_JD1_FALL */
1042#define ARIZONA_WKUP_JD1_FALL_WIDTH 1 /* WKUP_JD1_FALL */
1043#define ARIZONA_WKUP_JD1_RISE 0x0004 /* WKUP_JD1_RISE */
1044#define ARIZONA_WKUP_JD1_RISE_MASK 0x0004 /* WKUP_JD1_RISE */
1045#define ARIZONA_WKUP_JD1_RISE_SHIFT 2 /* WKUP_JD1_RISE */
1046#define ARIZONA_WKUP_JD1_RISE_WIDTH 1 /* WKUP_JD1_RISE */
1047#define ARIZONA_WKUP_JD2_FALL 0x0002 /* WKUP_JD2_FALL */
1048#define ARIZONA_WKUP_JD2_FALL_MASK 0x0002 /* WKUP_JD2_FALL */
1049#define ARIZONA_WKUP_JD2_FALL_SHIFT 1 /* WKUP_JD2_FALL */
1050#define ARIZONA_WKUP_JD2_FALL_WIDTH 1 /* WKUP_JD2_FALL */
1051#define ARIZONA_WKUP_JD2_RISE 0x0001 /* WKUP_JD2_RISE */
1052#define ARIZONA_WKUP_JD2_RISE_MASK 0x0001 /* WKUP_JD2_RISE */
1053#define ARIZONA_WKUP_JD2_RISE_SHIFT 0 /* WKUP_JD2_RISE */
1054#define ARIZONA_WKUP_JD2_RISE_WIDTH 1 /* WKUP_JD2_RISE */
1055
1056/*
1057 * R65 (0x41) - Sequence control
1058 */
1059#define ARIZONA_WSEQ_ENA_GP5_FALL 0x0020 /* WSEQ_ENA_GP5_FALL */
1060#define ARIZONA_WSEQ_ENA_GP5_FALL_MASK 0x0020 /* WSEQ_ENA_GP5_FALL */
1061#define ARIZONA_WSEQ_ENA_GP5_FALL_SHIFT 5 /* WSEQ_ENA_GP5_FALL */
1062#define ARIZONA_WSEQ_ENA_GP5_FALL_WIDTH 1 /* WSEQ_ENA_GP5_FALL */
1063#define ARIZONA_WSEQ_ENA_GP5_RISE 0x0010 /* WSEQ_ENA_GP5_RISE */
1064#define ARIZONA_WSEQ_ENA_GP5_RISE_MASK 0x0010 /* WSEQ_ENA_GP5_RISE */
1065#define ARIZONA_WSEQ_ENA_GP5_RISE_SHIFT 4 /* WSEQ_ENA_GP5_RISE */
1066#define ARIZONA_WSEQ_ENA_GP5_RISE_WIDTH 1 /* WSEQ_ENA_GP5_RISE */
1067#define ARIZONA_WSEQ_ENA_JD1_FALL 0x0008 /* WSEQ_ENA_JD1_FALL */
1068#define ARIZONA_WSEQ_ENA_JD1_FALL_MASK 0x0008 /* WSEQ_ENA_JD1_FALL */
1069#define ARIZONA_WSEQ_ENA_JD1_FALL_SHIFT 3 /* WSEQ_ENA_JD1_FALL */
1070#define ARIZONA_WSEQ_ENA_JD1_FALL_WIDTH 1 /* WSEQ_ENA_JD1_FALL */
1071#define ARIZONA_WSEQ_ENA_JD1_RISE 0x0004 /* WSEQ_ENA_JD1_RISE */
1072#define ARIZONA_WSEQ_ENA_JD1_RISE_MASK 0x0004 /* WSEQ_ENA_JD1_RISE */
1073#define ARIZONA_WSEQ_ENA_JD1_RISE_SHIFT 2 /* WSEQ_ENA_JD1_RISE */
1074#define ARIZONA_WSEQ_ENA_JD1_RISE_WIDTH 1 /* WSEQ_ENA_JD1_RISE */
1075#define ARIZONA_WSEQ_ENA_JD2_FALL 0x0002 /* WSEQ_ENA_JD2_FALL */
1076#define ARIZONA_WSEQ_ENA_JD2_FALL_MASK 0x0002 /* WSEQ_ENA_JD2_FALL */
1077#define ARIZONA_WSEQ_ENA_JD2_FALL_SHIFT 1 /* WSEQ_ENA_JD2_FALL */
1078#define ARIZONA_WSEQ_ENA_JD2_FALL_WIDTH 1 /* WSEQ_ENA_JD2_FALL */
1079#define ARIZONA_WSEQ_ENA_JD2_RISE 0x0001 /* WSEQ_ENA_JD2_RISE */
1080#define ARIZONA_WSEQ_ENA_JD2_RISE_MASK 0x0001 /* WSEQ_ENA_JD2_RISE */
1081#define ARIZONA_WSEQ_ENA_JD2_RISE_SHIFT 0 /* WSEQ_ENA_JD2_RISE */
1082#define ARIZONA_WSEQ_ENA_JD2_RISE_WIDTH 1 /* WSEQ_ENA_JD2_RISE */
1083
1084/*
1085 * R97 (0x61) - Sample Rate Sequence Select 1
1086 */
1087#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
1088#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
1089#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
1090
1091/*
1092 * R98 (0x62) - Sample Rate Sequence Select 2
1093 */
1094#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
1095#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
1096#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
1097
1098/*
1099 * R99 (0x63) - Sample Rate Sequence Select 3
1100 */
1101#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
1102#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
1103#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
1104
1105/*
1106 * R100 (0x64) - Sample Rate Sequence Select 4
1107 */
1108#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
1109#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
1110#define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
1111
1112/*
1113 * R104 (0x68) - Always On Triggers Sequence Select 1
1114 */
1115#define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
1116#define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
1117#define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
1118
1119/*
1120 * R105 (0x69) - Always On Triggers Sequence Select 2
1121 */
1122#define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
1123#define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
1124#define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
1125
1126/*
1127 * R106 (0x6A) - Always On Triggers Sequence Select 3
1128 */
1129#define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
1130#define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
1131#define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
1132
1133/*
1134 * R107 (0x6B) - Always On Triggers Sequence Select 4
1135 */
1136#define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
1137#define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
1138#define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
1139
1140/*
1141 * R108 (0x6C) - Always On Triggers Sequence Select 5
1142 */
1143#define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
1144#define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
1145#define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
1146
1147/*
1148 * R109 (0x6D) - Always On Triggers Sequence Select 6
1149 */
1150#define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
1151#define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
1152#define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
1153
1154/*
1155 * R112 (0x70) - Comfort Noise Generator
1156 */
1157#define ARIZONA_NOISE_GEN_RATE_MASK 0x7800 /* NOISE_GEN_RATE - [14:11] */
1158#define ARIZONA_NOISE_GEN_RATE_SHIFT 11 /* NOISE_GEN_RATE - [14:11] */
1159#define ARIZONA_NOISE_GEN_RATE_WIDTH 4 /* NOISE_GEN_RATE - [14:11] */
1160#define ARIZONA_NOISE_GEN_ENA 0x0020 /* NOISE_GEN_ENA */
1161#define ARIZONA_NOISE_GEN_ENA_MASK 0x0020 /* NOISE_GEN_ENA */
1162#define ARIZONA_NOISE_GEN_ENA_SHIFT 5 /* NOISE_GEN_ENA */
1163#define ARIZONA_NOISE_GEN_ENA_WIDTH 1 /* NOISE_GEN_ENA */
1164#define ARIZONA_NOISE_GEN_GAIN_MASK 0x001F /* NOISE_GEN_GAIN - [4:0] */
1165#define ARIZONA_NOISE_GEN_GAIN_SHIFT 0 /* NOISE_GEN_GAIN - [4:0] */
1166#define ARIZONA_NOISE_GEN_GAIN_WIDTH 5 /* NOISE_GEN_GAIN - [4:0] */
1167
1168/*
1169 * R144 (0x90) - Haptics Control 1
1170 */
1171#define ARIZONA_HAP_RATE_MASK 0x7800 /* HAP_RATE - [14:11] */
1172#define ARIZONA_HAP_RATE_SHIFT 11 /* HAP_RATE - [14:11] */
1173#define ARIZONA_HAP_RATE_WIDTH 4 /* HAP_RATE - [14:11] */
1174#define ARIZONA_ONESHOT_TRIG 0x0010 /* ONESHOT_TRIG */
1175#define ARIZONA_ONESHOT_TRIG_MASK 0x0010 /* ONESHOT_TRIG */
1176#define ARIZONA_ONESHOT_TRIG_SHIFT 4 /* ONESHOT_TRIG */
1177#define ARIZONA_ONESHOT_TRIG_WIDTH 1 /* ONESHOT_TRIG */
1178#define ARIZONA_HAP_CTRL_MASK 0x000C /* HAP_CTRL - [3:2] */
1179#define ARIZONA_HAP_CTRL_SHIFT 2 /* HAP_CTRL - [3:2] */
1180#define ARIZONA_HAP_CTRL_WIDTH 2 /* HAP_CTRL - [3:2] */
1181#define ARIZONA_HAP_ACT 0x0002 /* HAP_ACT */
1182#define ARIZONA_HAP_ACT_MASK 0x0002 /* HAP_ACT */
1183#define ARIZONA_HAP_ACT_SHIFT 1 /* HAP_ACT */
1184#define ARIZONA_HAP_ACT_WIDTH 1 /* HAP_ACT */
1185
1186/*
1187 * R145 (0x91) - Haptics Control 2
1188 */
1189#define ARIZONA_LRA_FREQ_MASK 0x7FFF /* LRA_FREQ - [14:0] */
1190#define ARIZONA_LRA_FREQ_SHIFT 0 /* LRA_FREQ - [14:0] */
1191#define ARIZONA_LRA_FREQ_WIDTH 15 /* LRA_FREQ - [14:0] */
1192
1193/*
1194 * R146 (0x92) - Haptics phase 1 intensity
1195 */
1196#define ARIZONA_PHASE1_INTENSITY_MASK 0x00FF /* PHASE1_INTENSITY - [7:0] */
1197#define ARIZONA_PHASE1_INTENSITY_SHIFT 0 /* PHASE1_INTENSITY - [7:0] */
1198#define ARIZONA_PHASE1_INTENSITY_WIDTH 8 /* PHASE1_INTENSITY - [7:0] */
1199
1200/*
1201 * R147 (0x93) - Haptics phase 1 duration
1202 */
1203#define ARIZONA_PHASE1_DURATION_MASK 0x01FF /* PHASE1_DURATION - [8:0] */
1204#define ARIZONA_PHASE1_DURATION_SHIFT 0 /* PHASE1_DURATION - [8:0] */
1205#define ARIZONA_PHASE1_DURATION_WIDTH 9 /* PHASE1_DURATION - [8:0] */
1206
1207/*
1208 * R148 (0x94) - Haptics phase 2 intensity
1209 */
1210#define ARIZONA_PHASE2_INTENSITY_MASK 0x00FF /* PHASE2_INTENSITY - [7:0] */
1211#define ARIZONA_PHASE2_INTENSITY_SHIFT 0 /* PHASE2_INTENSITY - [7:0] */
1212#define ARIZONA_PHASE2_INTENSITY_WIDTH 8 /* PHASE2_INTENSITY - [7:0] */
1213
1214/*
1215 * R149 (0x95) - Haptics phase 2 duration
1216 */
1217#define ARIZONA_PHASE2_DURATION_MASK 0x07FF /* PHASE2_DURATION - [10:0] */
1218#define ARIZONA_PHASE2_DURATION_SHIFT 0 /* PHASE2_DURATION - [10:0] */
1219#define ARIZONA_PHASE2_DURATION_WIDTH 11 /* PHASE2_DURATION - [10:0] */
1220
1221/*
1222 * R150 (0x96) - Haptics phase 3 intensity
1223 */
1224#define ARIZONA_PHASE3_INTENSITY_MASK 0x00FF /* PHASE3_INTENSITY - [7:0] */
1225#define ARIZONA_PHASE3_INTENSITY_SHIFT 0 /* PHASE3_INTENSITY - [7:0] */
1226#define ARIZONA_PHASE3_INTENSITY_WIDTH 8 /* PHASE3_INTENSITY - [7:0] */
1227
1228/*
1229 * R151 (0x97) - Haptics phase 3 duration
1230 */
1231#define ARIZONA_PHASE3_DURATION_MASK 0x01FF /* PHASE3_DURATION - [8:0] */
1232#define ARIZONA_PHASE3_DURATION_SHIFT 0 /* PHASE3_DURATION - [8:0] */
1233#define ARIZONA_PHASE3_DURATION_WIDTH 9 /* PHASE3_DURATION - [8:0] */
1234
1235/*
1236 * R152 (0x98) - Haptics Status
1237 */
1238#define ARIZONA_ONESHOT_STS 0x0001 /* ONESHOT_STS */
1239#define ARIZONA_ONESHOT_STS_MASK 0x0001 /* ONESHOT_STS */
1240#define ARIZONA_ONESHOT_STS_SHIFT 0 /* ONESHOT_STS */
1241#define ARIZONA_ONESHOT_STS_WIDTH 1 /* ONESHOT_STS */
1242
1243/*
1244 * R256 (0x100) - Clock 32k 1
1245 */
1246#define ARIZONA_CLK_32K_ENA 0x0040 /* CLK_32K_ENA */
1247#define ARIZONA_CLK_32K_ENA_MASK 0x0040 /* CLK_32K_ENA */
1248#define ARIZONA_CLK_32K_ENA_SHIFT 6 /* CLK_32K_ENA */
1249#define ARIZONA_CLK_32K_ENA_WIDTH 1 /* CLK_32K_ENA */
1250#define ARIZONA_CLK_32K_SRC_MASK 0x0003 /* CLK_32K_SRC - [1:0] */
1251#define ARIZONA_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [1:0] */
1252#define ARIZONA_CLK_32K_SRC_WIDTH 2 /* CLK_32K_SRC - [1:0] */
1253
1254/*
1255 * R257 (0x101) - System Clock 1
1256 */
1257#define ARIZONA_SYSCLK_FRAC 0x8000 /* SYSCLK_FRAC */
1258#define ARIZONA_SYSCLK_FRAC_MASK 0x8000 /* SYSCLK_FRAC */
1259#define ARIZONA_SYSCLK_FRAC_SHIFT 15 /* SYSCLK_FRAC */
1260#define ARIZONA_SYSCLK_FRAC_WIDTH 1 /* SYSCLK_FRAC */
1261#define ARIZONA_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */
1262#define ARIZONA_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */
1263#define ARIZONA_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */
1264#define ARIZONA_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */
1265#define ARIZONA_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */
1266#define ARIZONA_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */
1267#define ARIZONA_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
1268#define ARIZONA_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */
1269#define ARIZONA_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */
1270#define ARIZONA_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */
1271
1272/*
1273 * R258 (0x102) - Sample rate 1
1274 */
1275#define ARIZONA_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */
1276#define ARIZONA_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */
1277#define ARIZONA_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */
1278
1279/*
1280 * R259 (0x103) - Sample rate 2
1281 */
1282#define ARIZONA_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */
1283#define ARIZONA_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */
1284#define ARIZONA_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */
1285
1286/*
1287 * R260 (0x104) - Sample rate 3
1288 */
1289#define ARIZONA_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */
1290#define ARIZONA_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */
1291#define ARIZONA_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */
1292
1293/*
1294 * R266 (0x10A) - Sample rate 1 status
1295 */
1296#define ARIZONA_SAMPLE_RATE_1_STS_MASK 0x001F /* SAMPLE_RATE_1_STS - [4:0] */
1297#define ARIZONA_SAMPLE_RATE_1_STS_SHIFT 0 /* SAMPLE_RATE_1_STS - [4:0] */
1298#define ARIZONA_SAMPLE_RATE_1_STS_WIDTH 5 /* SAMPLE_RATE_1_STS - [4:0] */
1299
1300/*
1301 * R267 (0x10B) - Sample rate 2 status
1302 */
1303#define ARIZONA_SAMPLE_RATE_2_STS_MASK 0x001F /* SAMPLE_RATE_2_STS - [4:0] */
1304#define ARIZONA_SAMPLE_RATE_2_STS_SHIFT 0 /* SAMPLE_RATE_2_STS - [4:0] */
1305#define ARIZONA_SAMPLE_RATE_2_STS_WIDTH 5 /* SAMPLE_RATE_2_STS - [4:0] */
1306
1307/*
1308 * R268 (0x10C) - Sample rate 3 status
1309 */
1310#define ARIZONA_SAMPLE_RATE_3_STS_MASK 0x001F /* SAMPLE_RATE_3_STS - [4:0] */
1311#define ARIZONA_SAMPLE_RATE_3_STS_SHIFT 0 /* SAMPLE_RATE_3_STS - [4:0] */
1312#define ARIZONA_SAMPLE_RATE_3_STS_WIDTH 5 /* SAMPLE_RATE_3_STS - [4:0] */
1313
1314/*
1315 * R274 (0x112) - Async clock 1
1316 */
1317#define ARIZONA_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */
1318#define ARIZONA_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */
1319#define ARIZONA_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */
1320#define ARIZONA_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */
1321#define ARIZONA_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */
1322#define ARIZONA_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */
1323#define ARIZONA_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */
1324#define ARIZONA_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */
1325#define ARIZONA_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */
1326#define ARIZONA_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */
1327
1328/*
1329 * R275 (0x113) - Async sample rate 1
1330 */
1331#define ARIZONA_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */
1332#define ARIZONA_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */
1333#define ARIZONA_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */
1334
1335/*
1336 * R283 (0x11B) - Async sample rate 1 status
1337 */
1338#define ARIZONA_ASYNC_SAMPLE_RATE_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_STS - [4:0] */
1339#define ARIZONA_ASYNC_SAMPLE_RATE_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_STS - [4:0] */
1340#define ARIZONA_ASYNC_SAMPLE_RATE_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_STS - [4:0] */
1341
1342/*
1343 * R329 (0x149) - Output system clock
1344 */
1345#define ARIZONA_OPCLK_ENA 0x8000 /* OPCLK_ENA */
1346#define ARIZONA_OPCLK_ENA_MASK 0x8000 /* OPCLK_ENA */
1347#define ARIZONA_OPCLK_ENA_SHIFT 15 /* OPCLK_ENA */
1348#define ARIZONA_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
1349#define ARIZONA_OPCLK_DIV_MASK 0x00F8 /* OPCLK_DIV - [7:3] */
1350#define ARIZONA_OPCLK_DIV_SHIFT 3 /* OPCLK_DIV - [7:3] */
1351#define ARIZONA_OPCLK_DIV_WIDTH 5 /* OPCLK_DIV - [7:3] */
1352#define ARIZONA_OPCLK_SEL_MASK 0x0007 /* OPCLK_SEL - [2:0] */
1353#define ARIZONA_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [2:0] */
1354#define ARIZONA_OPCLK_SEL_WIDTH 3 /* OPCLK_SEL - [2:0] */
1355
1356/*
1357 * R330 (0x14A) - Output async clock
1358 */
1359#define ARIZONA_OPCLK_ASYNC_ENA 0x8000 /* OPCLK_ASYNC_ENA */
1360#define ARIZONA_OPCLK_ASYNC_ENA_MASK 0x8000 /* OPCLK_ASYNC_ENA */
1361#define ARIZONA_OPCLK_ASYNC_ENA_SHIFT 15 /* OPCLK_ASYNC_ENA */
1362#define ARIZONA_OPCLK_ASYNC_ENA_WIDTH 1 /* OPCLK_ASYNC_ENA */
1363#define ARIZONA_OPCLK_ASYNC_DIV_MASK 0x00F8 /* OPCLK_ASYNC_DIV - [7:3] */
1364#define ARIZONA_OPCLK_ASYNC_DIV_SHIFT 3 /* OPCLK_ASYNC_DIV - [7:3] */
1365#define ARIZONA_OPCLK_ASYNC_DIV_WIDTH 5 /* OPCLK_ASYNC_DIV - [7:3] */
1366#define ARIZONA_OPCLK_ASYNC_SEL_MASK 0x0007 /* OPCLK_ASYNC_SEL - [2:0] */
1367#define ARIZONA_OPCLK_ASYNC_SEL_SHIFT 0 /* OPCLK_ASYNC_SEL - [2:0] */
1368#define ARIZONA_OPCLK_ASYNC_SEL_WIDTH 3 /* OPCLK_ASYNC_SEL - [2:0] */
1369
1370/*
1371 * R338 (0x152) - Rate Estimator 1
1372 */
1373#define ARIZONA_TRIG_ON_STARTUP 0x0010 /* TRIG_ON_STARTUP */
1374#define ARIZONA_TRIG_ON_STARTUP_MASK 0x0010 /* TRIG_ON_STARTUP */
1375#define ARIZONA_TRIG_ON_STARTUP_SHIFT 4 /* TRIG_ON_STARTUP */
1376#define ARIZONA_TRIG_ON_STARTUP_WIDTH 1 /* TRIG_ON_STARTUP */
1377#define ARIZONA_LRCLK_SRC_MASK 0x000E /* LRCLK_SRC - [3:1] */
1378#define ARIZONA_LRCLK_SRC_SHIFT 1 /* LRCLK_SRC - [3:1] */
1379#define ARIZONA_LRCLK_SRC_WIDTH 3 /* LRCLK_SRC - [3:1] */
1380#define ARIZONA_RATE_EST_ENA 0x0001 /* RATE_EST_ENA */
1381#define ARIZONA_RATE_EST_ENA_MASK 0x0001 /* RATE_EST_ENA */
1382#define ARIZONA_RATE_EST_ENA_SHIFT 0 /* RATE_EST_ENA */
1383#define ARIZONA_RATE_EST_ENA_WIDTH 1 /* RATE_EST_ENA */
1384
1385/*
1386 * R339 (0x153) - Rate Estimator 2
1387 */
1388#define ARIZONA_SAMPLE_RATE_DETECT_A_MASK 0x001F /* SAMPLE_RATE_DETECT_A - [4:0] */
1389#define ARIZONA_SAMPLE_RATE_DETECT_A_SHIFT 0 /* SAMPLE_RATE_DETECT_A - [4:0] */
1390#define ARIZONA_SAMPLE_RATE_DETECT_A_WIDTH 5 /* SAMPLE_RATE_DETECT_A - [4:0] */
1391
1392/*
1393 * R340 (0x154) - Rate Estimator 3
1394 */
1395#define ARIZONA_SAMPLE_RATE_DETECT_B_MASK 0x001F /* SAMPLE_RATE_DETECT_B - [4:0] */
1396#define ARIZONA_SAMPLE_RATE_DETECT_B_SHIFT 0 /* SAMPLE_RATE_DETECT_B - [4:0] */
1397#define ARIZONA_SAMPLE_RATE_DETECT_B_WIDTH 5 /* SAMPLE_RATE_DETECT_B - [4:0] */
1398
1399/*
1400 * R341 (0x155) - Rate Estimator 4
1401 */
1402#define ARIZONA_SAMPLE_RATE_DETECT_C_MASK 0x001F /* SAMPLE_RATE_DETECT_C - [4:0] */
1403#define ARIZONA_SAMPLE_RATE_DETECT_C_SHIFT 0 /* SAMPLE_RATE_DETECT_C - [4:0] */
1404#define ARIZONA_SAMPLE_RATE_DETECT_C_WIDTH 5 /* SAMPLE_RATE_DETECT_C - [4:0] */
1405
1406/*
1407 * R342 (0x156) - Rate Estimator 5
1408 */
1409#define ARIZONA_SAMPLE_RATE_DETECT_D_MASK 0x001F /* SAMPLE_RATE_DETECT_D - [4:0] */
1410#define ARIZONA_SAMPLE_RATE_DETECT_D_SHIFT 0 /* SAMPLE_RATE_DETECT_D - [4:0] */
1411#define ARIZONA_SAMPLE_RATE_DETECT_D_WIDTH 5 /* SAMPLE_RATE_DETECT_D - [4:0] */
1412
1413/*
1414 * R369 (0x171) - FLL1 Control 1
1415 */
1416#define ARIZONA_FLL1_FREERUN 0x0002 /* FLL1_FREERUN */
1417#define ARIZONA_FLL1_FREERUN_MASK 0x0002 /* FLL1_FREERUN */
1418#define ARIZONA_FLL1_FREERUN_SHIFT 1 /* FLL1_FREERUN */
1419#define ARIZONA_FLL1_FREERUN_WIDTH 1 /* FLL1_FREERUN */
1420#define ARIZONA_FLL1_ENA 0x0001 /* FLL1_ENA */
1421#define ARIZONA_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
1422#define ARIZONA_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
1423#define ARIZONA_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
1424
1425/*
1426 * R370 (0x172) - FLL1 Control 2
1427 */
1428#define ARIZONA_FLL1_CTRL_UPD 0x8000 /* FLL1_CTRL_UPD */
1429#define ARIZONA_FLL1_CTRL_UPD_MASK 0x8000 /* FLL1_CTRL_UPD */
1430#define ARIZONA_FLL1_CTRL_UPD_SHIFT 15 /* FLL1_CTRL_UPD */
1431#define ARIZONA_FLL1_CTRL_UPD_WIDTH 1 /* FLL1_CTRL_UPD */
1432#define ARIZONA_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */
1433#define ARIZONA_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */
1434#define ARIZONA_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */
1435
1436/*
1437 * R371 (0x173) - FLL1 Control 3
1438 */
1439#define ARIZONA_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */
1440#define ARIZONA_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */
1441#define ARIZONA_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */
1442
1443/*
1444 * R372 (0x174) - FLL1 Control 4
1445 */
1446#define ARIZONA_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */
1447#define ARIZONA_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */
1448#define ARIZONA_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */
1449
1450/*
1451 * R373 (0x175) - FLL1 Control 5
1452 */
1453#define ARIZONA_FLL1_FRATIO_MASK 0x0700 /* FLL1_FRATIO - [10:8] */
1454#define ARIZONA_FLL1_FRATIO_SHIFT 8 /* FLL1_FRATIO - [10:8] */
1455#define ARIZONA_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [10:8] */
1456#define ARIZONA_FLL1_OUTDIV_MASK 0x000E /* FLL1_OUTDIV - [3:1] */
1457#define ARIZONA_FLL1_OUTDIV_SHIFT 1 /* FLL1_OUTDIV - [3:1] */
1458#define ARIZONA_FLL1_OUTDIV_WIDTH 3 /* FLL1_OUTDIV - [3:1] */
1459
1460/*
1461 * R374 (0x176) - FLL1 Control 6
1462 */
1463#define ARIZONA_FLL1_CLK_REF_DIV_MASK 0x00C0 /* FLL1_CLK_REF_DIV - [7:6] */
1464#define ARIZONA_FLL1_CLK_REF_DIV_SHIFT 6 /* FLL1_CLK_REF_DIV - [7:6] */
1465#define ARIZONA_FLL1_CLK_REF_DIV_WIDTH 2 /* FLL1_CLK_REF_DIV - [7:6] */
1466#define ARIZONA_FLL1_CLK_REF_SRC_MASK 0x000F /* FLL1_CLK_REF_SRC - [3:0] */
1467#define ARIZONA_FLL1_CLK_REF_SRC_SHIFT 0 /* FLL1_CLK_REF_SRC - [3:0] */
1468#define ARIZONA_FLL1_CLK_REF_SRC_WIDTH 4 /* FLL1_CLK_REF_SRC - [3:0] */
1469
1470/*
1471 * R375 (0x177) - FLL1 Loop Filter Test 1
1472 */
1473#define ARIZONA_FLL1_FRC_INTEG_UPD 0x8000 /* FLL1_FRC_INTEG_UPD */
1474#define ARIZONA_FLL1_FRC_INTEG_UPD_MASK 0x8000 /* FLL1_FRC_INTEG_UPD */
1475#define ARIZONA_FLL1_FRC_INTEG_UPD_SHIFT 15 /* FLL1_FRC_INTEG_UPD */
1476#define ARIZONA_FLL1_FRC_INTEG_UPD_WIDTH 1 /* FLL1_FRC_INTEG_UPD */
1477#define ARIZONA_FLL1_FRC_INTEG_VAL_MASK 0x0FFF /* FLL1_FRC_INTEG_VAL - [11:0] */
1478#define ARIZONA_FLL1_FRC_INTEG_VAL_SHIFT 0 /* FLL1_FRC_INTEG_VAL - [11:0] */
1479#define ARIZONA_FLL1_FRC_INTEG_VAL_WIDTH 12 /* FLL1_FRC_INTEG_VAL - [11:0] */
1480
1481/*
1482 * R385 (0x181) - FLL1 Synchroniser 1
1483 */
1484#define ARIZONA_FLL1_SYNC_ENA 0x0001 /* FLL1_SYNC_ENA */
1485#define ARIZONA_FLL1_SYNC_ENA_MASK 0x0001 /* FLL1_SYNC_ENA */
1486#define ARIZONA_FLL1_SYNC_ENA_SHIFT 0 /* FLL1_SYNC_ENA */
1487#define ARIZONA_FLL1_SYNC_ENA_WIDTH 1 /* FLL1_SYNC_ENA */
1488
1489/*
1490 * R386 (0x182) - FLL1 Synchroniser 2
1491 */
1492#define ARIZONA_FLL1_SYNC_N_MASK 0x03FF /* FLL1_SYNC_N - [9:0] */
1493#define ARIZONA_FLL1_SYNC_N_SHIFT 0 /* FLL1_SYNC_N - [9:0] */
1494#define ARIZONA_FLL1_SYNC_N_WIDTH 10 /* FLL1_SYNC_N - [9:0] */
1495
1496/*
1497 * R387 (0x183) - FLL1 Synchroniser 3
1498 */
1499#define ARIZONA_FLL1_SYNC_THETA_MASK 0xFFFF /* FLL1_SYNC_THETA - [15:0] */
1500#define ARIZONA_FLL1_SYNC_THETA_SHIFT 0 /* FLL1_SYNC_THETA - [15:0] */
1501#define ARIZONA_FLL1_SYNC_THETA_WIDTH 16 /* FLL1_SYNC_THETA - [15:0] */
1502
1503/*
1504 * R388 (0x184) - FLL1 Synchroniser 4
1505 */
1506#define ARIZONA_FLL1_SYNC_LAMBDA_MASK 0xFFFF /* FLL1_SYNC_LAMBDA - [15:0] */
1507#define ARIZONA_FLL1_SYNC_LAMBDA_SHIFT 0 /* FLL1_SYNC_LAMBDA - [15:0] */
1508#define ARIZONA_FLL1_SYNC_LAMBDA_WIDTH 16 /* FLL1_SYNC_LAMBDA - [15:0] */
1509
1510/*
1511 * R389 (0x185) - FLL1 Synchroniser 5
1512 */
1513#define ARIZONA_FLL1_SYNC_FRATIO_MASK 0x0700 /* FLL1_SYNC_FRATIO - [10:8] */
1514#define ARIZONA_FLL1_SYNC_FRATIO_SHIFT 8 /* FLL1_SYNC_FRATIO - [10:8] */
1515#define ARIZONA_FLL1_SYNC_FRATIO_WIDTH 3 /* FLL1_SYNC_FRATIO - [10:8] */
1516
1517/*
1518 * R390 (0x186) - FLL1 Synchroniser 6
1519 */
1520#define ARIZONA_FLL1_CLK_SYNC_DIV_MASK 0x00C0 /* FLL1_CLK_SYNC_DIV - [7:6] */
1521#define ARIZONA_FLL1_CLK_SYNC_DIV_SHIFT 6 /* FLL1_CLK_SYNC_DIV - [7:6] */
1522#define ARIZONA_FLL1_CLK_SYNC_DIV_WIDTH 2 /* FLL1_CLK_SYNC_DIV - [7:6] */
1523#define ARIZONA_FLL1_CLK_SYNC_SRC_MASK 0x000F /* FLL1_CLK_SYNC_SRC - [3:0] */
1524#define ARIZONA_FLL1_CLK_SYNC_SRC_SHIFT 0 /* FLL1_CLK_SYNC_SRC - [3:0] */
1525#define ARIZONA_FLL1_CLK_SYNC_SRC_WIDTH 4 /* FLL1_CLK_SYNC_SRC - [3:0] */
1526
1527/*
1528 * R393 (0x189) - FLL1 Spread Spectrum
1529 */
1530#define ARIZONA_FLL1_SS_AMPL_MASK 0x0030 /* FLL1_SS_AMPL - [5:4] */
1531#define ARIZONA_FLL1_SS_AMPL_SHIFT 4 /* FLL1_SS_AMPL - [5:4] */
1532#define ARIZONA_FLL1_SS_AMPL_WIDTH 2 /* FLL1_SS_AMPL - [5:4] */
1533#define ARIZONA_FLL1_SS_FREQ_MASK 0x000C /* FLL1_SS_FREQ - [3:2] */
1534#define ARIZONA_FLL1_SS_FREQ_SHIFT 2 /* FLL1_SS_FREQ - [3:2] */
1535#define ARIZONA_FLL1_SS_FREQ_WIDTH 2 /* FLL1_SS_FREQ - [3:2] */
1536#define ARIZONA_FLL1_SS_SEL_MASK 0x0003 /* FLL1_SS_SEL - [1:0] */
1537#define ARIZONA_FLL1_SS_SEL_SHIFT 0 /* FLL1_SS_SEL - [1:0] */
1538#define ARIZONA_FLL1_SS_SEL_WIDTH 2 /* FLL1_SS_SEL - [1:0] */
1539
1540/*
1541 * R394 (0x18A) - FLL1 GPIO Clock
1542 */
1543#define ARIZONA_FLL1_GPDIV_MASK 0x00FE /* FLL1_GPDIV - [7:1] */
1544#define ARIZONA_FLL1_GPDIV_SHIFT 1 /* FLL1_GPDIV - [7:1] */
1545#define ARIZONA_FLL1_GPDIV_WIDTH 7 /* FLL1_GPDIV - [7:1] */
1546#define ARIZONA_FLL1_GPDIV_ENA 0x0001 /* FLL1_GPDIV_ENA */
1547#define ARIZONA_FLL1_GPDIV_ENA_MASK 0x0001 /* FLL1_GPDIV_ENA */
1548#define ARIZONA_FLL1_GPDIV_ENA_SHIFT 0 /* FLL1_GPDIV_ENA */
1549#define ARIZONA_FLL1_GPDIV_ENA_WIDTH 1 /* FLL1_GPDIV_ENA */
1550
1551/*
1552 * R401 (0x191) - FLL2 Control 1
1553 */
1554#define ARIZONA_FLL2_FREERUN 0x0002 /* FLL2_FREERUN */
1555#define ARIZONA_FLL2_FREERUN_MASK 0x0002 /* FLL2_FREERUN */
1556#define ARIZONA_FLL2_FREERUN_SHIFT 1 /* FLL2_FREERUN */
1557#define ARIZONA_FLL2_FREERUN_WIDTH 1 /* FLL2_FREERUN */
1558#define ARIZONA_FLL2_ENA 0x0001 /* FLL2_ENA */
1559#define ARIZONA_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
1560#define ARIZONA_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
1561#define ARIZONA_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
1562
1563/*
1564 * R402 (0x192) - FLL2 Control 2
1565 */
1566#define ARIZONA_FLL2_CTRL_UPD 0x8000 /* FLL2_CTRL_UPD */
1567#define ARIZONA_FLL2_CTRL_UPD_MASK 0x8000 /* FLL2_CTRL_UPD */
1568#define ARIZONA_FLL2_CTRL_UPD_SHIFT 15 /* FLL2_CTRL_UPD */
1569#define ARIZONA_FLL2_CTRL_UPD_WIDTH 1 /* FLL2_CTRL_UPD */
1570#define ARIZONA_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */
1571#define ARIZONA_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */
1572#define ARIZONA_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */
1573
1574/*
1575 * R403 (0x193) - FLL2 Control 3
1576 */
1577#define ARIZONA_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */
1578#define ARIZONA_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */
1579#define ARIZONA_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */
1580
1581/*
1582 * R404 (0x194) - FLL2 Control 4
1583 */
1584#define ARIZONA_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */
1585#define ARIZONA_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */
1586#define ARIZONA_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */
1587
1588/*
1589 * R405 (0x195) - FLL2 Control 5
1590 */
1591#define ARIZONA_FLL2_FRATIO_MASK 0x0700 /* FLL2_FRATIO - [10:8] */
1592#define ARIZONA_FLL2_FRATIO_SHIFT 8 /* FLL2_FRATIO - [10:8] */
1593#define ARIZONA_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [10:8] */
1594#define ARIZONA_FLL2_OUTDIV_MASK 0x000E /* FLL2_OUTDIV - [3:1] */
1595#define ARIZONA_FLL2_OUTDIV_SHIFT 1 /* FLL2_OUTDIV - [3:1] */
1596#define ARIZONA_FLL2_OUTDIV_WIDTH 3 /* FLL2_OUTDIV - [3:1] */
1597
1598/*
1599 * R406 (0x196) - FLL2 Control 6
1600 */
1601#define ARIZONA_FLL2_CLK_REF_DIV_MASK 0x00C0 /* FLL2_CLK_REF_DIV - [7:6] */
1602#define ARIZONA_FLL2_CLK_REF_DIV_SHIFT 6 /* FLL2_CLK_REF_DIV - [7:6] */
1603#define ARIZONA_FLL2_CLK_REF_DIV_WIDTH 2 /* FLL2_CLK_REF_DIV - [7:6] */
1604#define ARIZONA_FLL2_CLK_REF_SRC_MASK 0x000F /* FLL2_CLK_REF_SRC - [3:0] */
1605#define ARIZONA_FLL2_CLK_REF_SRC_SHIFT 0 /* FLL2_CLK_REF_SRC - [3:0] */
1606#define ARIZONA_FLL2_CLK_REF_SRC_WIDTH 4 /* FLL2_CLK_REF_SRC - [3:0] */
1607
1608/*
1609 * R407 (0x197) - FLL2 Loop Filter Test 1
1610 */
1611#define ARIZONA_FLL2_FRC_INTEG_UPD 0x8000 /* FLL2_FRC_INTEG_UPD */
1612#define ARIZONA_FLL2_FRC_INTEG_UPD_MASK 0x8000 /* FLL2_FRC_INTEG_UPD */
1613#define ARIZONA_FLL2_FRC_INTEG_UPD_SHIFT 15 /* FLL2_FRC_INTEG_UPD */
1614#define ARIZONA_FLL2_FRC_INTEG_UPD_WIDTH 1 /* FLL2_FRC_INTEG_UPD */
1615#define ARIZONA_FLL2_FRC_INTEG_VAL_MASK 0x0FFF /* FLL2_FRC_INTEG_VAL - [11:0] */
1616#define ARIZONA_FLL2_FRC_INTEG_VAL_SHIFT 0 /* FLL2_FRC_INTEG_VAL - [11:0] */
1617#define ARIZONA_FLL2_FRC_INTEG_VAL_WIDTH 12 /* FLL2_FRC_INTEG_VAL - [11:0] */
1618
1619/*
1620 * R417 (0x1A1) - FLL2 Synchroniser 1
1621 */
1622#define ARIZONA_FLL2_SYNC_ENA 0x0001 /* FLL2_SYNC_ENA */
1623#define ARIZONA_FLL2_SYNC_ENA_MASK 0x0001 /* FLL2_SYNC_ENA */
1624#define ARIZONA_FLL2_SYNC_ENA_SHIFT 0 /* FLL2_SYNC_ENA */
1625#define ARIZONA_FLL2_SYNC_ENA_WIDTH 1 /* FLL2_SYNC_ENA */
1626
1627/*
1628 * R418 (0x1A2) - FLL2 Synchroniser 2
1629 */
1630#define ARIZONA_FLL2_SYNC_N_MASK 0x03FF /* FLL2_SYNC_N - [9:0] */
1631#define ARIZONA_FLL2_SYNC_N_SHIFT 0 /* FLL2_SYNC_N - [9:0] */
1632#define ARIZONA_FLL2_SYNC_N_WIDTH 10 /* FLL2_SYNC_N - [9:0] */
1633
1634/*
1635 * R419 (0x1A3) - FLL2 Synchroniser 3
1636 */
1637#define ARIZONA_FLL2_SYNC_THETA_MASK 0xFFFF /* FLL2_SYNC_THETA - [15:0] */
1638#define ARIZONA_FLL2_SYNC_THETA_SHIFT 0 /* FLL2_SYNC_THETA - [15:0] */
1639#define ARIZONA_FLL2_SYNC_THETA_WIDTH 16 /* FLL2_SYNC_THETA - [15:0] */
1640
1641/*
1642 * R420 (0x1A4) - FLL2 Synchroniser 4
1643 */
1644#define ARIZONA_FLL2_SYNC_LAMBDA_MASK 0xFFFF /* FLL2_SYNC_LAMBDA - [15:0] */
1645#define ARIZONA_FLL2_SYNC_LAMBDA_SHIFT 0 /* FLL2_SYNC_LAMBDA - [15:0] */
1646#define ARIZONA_FLL2_SYNC_LAMBDA_WIDTH 16 /* FLL2_SYNC_LAMBDA - [15:0] */
1647
1648/*
1649 * R421 (0x1A5) - FLL2 Synchroniser 5
1650 */
1651#define ARIZONA_FLL2_SYNC_FRATIO_MASK 0x0700 /* FLL2_SYNC_FRATIO - [10:8] */
1652#define ARIZONA_FLL2_SYNC_FRATIO_SHIFT 8 /* FLL2_SYNC_FRATIO - [10:8] */
1653#define ARIZONA_FLL2_SYNC_FRATIO_WIDTH 3 /* FLL2_SYNC_FRATIO - [10:8] */
1654
1655/*
1656 * R422 (0x1A6) - FLL2 Synchroniser 6
1657 */
1658#define ARIZONA_FLL2_CLK_SYNC_DIV_MASK 0x00C0 /* FLL2_CLK_SYNC_DIV - [7:6] */
1659#define ARIZONA_FLL2_CLK_SYNC_DIV_SHIFT 6 /* FLL2_CLK_SYNC_DIV - [7:6] */
1660#define ARIZONA_FLL2_CLK_SYNC_DIV_WIDTH 2 /* FLL2_CLK_SYNC_DIV - [7:6] */
1661#define ARIZONA_FLL2_CLK_SYNC_SRC_MASK 0x000F /* FLL2_CLK_SYNC_SRC - [3:0] */
1662#define ARIZONA_FLL2_CLK_SYNC_SRC_SHIFT 0 /* FLL2_CLK_SYNC_SRC - [3:0] */
1663#define ARIZONA_FLL2_CLK_SYNC_SRC_WIDTH 4 /* FLL2_CLK_SYNC_SRC - [3:0] */
1664
1665/*
1666 * R425 (0x1A9) - FLL2 Spread Spectrum
1667 */
1668#define ARIZONA_FLL2_SS_AMPL_MASK 0x0030 /* FLL2_SS_AMPL - [5:4] */
1669#define ARIZONA_FLL2_SS_AMPL_SHIFT 4 /* FLL2_SS_AMPL - [5:4] */
1670#define ARIZONA_FLL2_SS_AMPL_WIDTH 2 /* FLL2_SS_AMPL - [5:4] */
1671#define ARIZONA_FLL2_SS_FREQ_MASK 0x000C /* FLL2_SS_FREQ - [3:2] */
1672#define ARIZONA_FLL2_SS_FREQ_SHIFT 2 /* FLL2_SS_FREQ - [3:2] */
1673#define ARIZONA_FLL2_SS_FREQ_WIDTH 2 /* FLL2_SS_FREQ - [3:2] */
1674#define ARIZONA_FLL2_SS_SEL_MASK 0x0003 /* FLL2_SS_SEL - [1:0] */
1675#define ARIZONA_FLL2_SS_SEL_SHIFT 0 /* FLL2_SS_SEL - [1:0] */
1676#define ARIZONA_FLL2_SS_SEL_WIDTH 2 /* FLL2_SS_SEL - [1:0] */
1677
1678/*
1679 * R426 (0x1AA) - FLL2 GPIO Clock
1680 */
1681#define ARIZONA_FLL2_GPDIV_MASK 0x00FE /* FLL2_GPDIV - [7:1] */
1682#define ARIZONA_FLL2_GPDIV_SHIFT 1 /* FLL2_GPDIV - [7:1] */
1683#define ARIZONA_FLL2_GPDIV_WIDTH 7 /* FLL2_GPDIV - [7:1] */
1684#define ARIZONA_FLL2_GPDIV_ENA 0x0001 /* FLL2_GPDIV_ENA */
1685#define ARIZONA_FLL2_GPDIV_ENA_MASK 0x0001 /* FLL2_GPDIV_ENA */
1686#define ARIZONA_FLL2_GPDIV_ENA_SHIFT 0 /* FLL2_GPDIV_ENA */
1687#define ARIZONA_FLL2_GPDIV_ENA_WIDTH 1 /* FLL2_GPDIV_ENA */
1688
1689/*
1690 * R512 (0x200) - Mic Charge Pump 1
1691 */
1692#define ARIZONA_CPMIC_DISCH 0x0004 /* CPMIC_DISCH */
1693#define ARIZONA_CPMIC_DISCH_MASK 0x0004 /* CPMIC_DISCH */
1694#define ARIZONA_CPMIC_DISCH_SHIFT 2 /* CPMIC_DISCH */
1695#define ARIZONA_CPMIC_DISCH_WIDTH 1 /* CPMIC_DISCH */
1696#define ARIZONA_CPMIC_BYPASS 0x0002 /* CPMIC_BYPASS */
1697#define ARIZONA_CPMIC_BYPASS_MASK 0x0002 /* CPMIC_BYPASS */
1698#define ARIZONA_CPMIC_BYPASS_SHIFT 1 /* CPMIC_BYPASS */
1699#define ARIZONA_CPMIC_BYPASS_WIDTH 1 /* CPMIC_BYPASS */
1700#define ARIZONA_CPMIC_ENA 0x0001 /* CPMIC_ENA */
1701#define ARIZONA_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */
1702#define ARIZONA_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */
1703#define ARIZONA_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */
1704
1705/*
1706 * R528 (0x210) - LDO1 Control 1
1707 */
1708#define ARIZONA_LDO1_VSEL_MASK 0x07E0 /* LDO1_VSEL - [10:5] */
1709#define ARIZONA_LDO1_VSEL_SHIFT 5 /* LDO1_VSEL - [10:5] */
1710#define ARIZONA_LDO1_VSEL_WIDTH 6 /* LDO1_VSEL - [10:5] */
1711#define ARIZONA_LDO1_FAST 0x0010 /* LDO1_FAST */
1712#define ARIZONA_LDO1_FAST_MASK 0x0010 /* LDO1_FAST */
1713#define ARIZONA_LDO1_FAST_SHIFT 4 /* LDO1_FAST */
1714#define ARIZONA_LDO1_FAST_WIDTH 1 /* LDO1_FAST */
1715#define ARIZONA_LDO1_DISCH 0x0004 /* LDO1_DISCH */
1716#define ARIZONA_LDO1_DISCH_MASK 0x0004 /* LDO1_DISCH */
1717#define ARIZONA_LDO1_DISCH_SHIFT 2 /* LDO1_DISCH */
1718#define ARIZONA_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
1719#define ARIZONA_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */
1720#define ARIZONA_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */
1721#define ARIZONA_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */
1722#define ARIZONA_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */
1723#define ARIZONA_LDO1_ENA 0x0001 /* LDO1_ENA */
1724#define ARIZONA_LDO1_ENA_MASK 0x0001 /* LDO1_ENA */
1725#define ARIZONA_LDO1_ENA_SHIFT 0 /* LDO1_ENA */
1726#define ARIZONA_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
1727
1728/*
1729 * R531 (0x213) - LDO2 Control 1
1730 */
1731#define ARIZONA_LDO2_VSEL_MASK 0x07E0 /* LDO2_VSEL - [10:5] */
1732#define ARIZONA_LDO2_VSEL_SHIFT 5 /* LDO2_VSEL - [10:5] */
1733#define ARIZONA_LDO2_VSEL_WIDTH 6 /* LDO2_VSEL - [10:5] */
1734#define ARIZONA_LDO2_FAST 0x0010 /* LDO2_FAST */
1735#define ARIZONA_LDO2_FAST_MASK 0x0010 /* LDO2_FAST */
1736#define ARIZONA_LDO2_FAST_SHIFT 4 /* LDO2_FAST */
1737#define ARIZONA_LDO2_FAST_WIDTH 1 /* LDO2_FAST */
1738#define ARIZONA_LDO2_DISCH 0x0004 /* LDO2_DISCH */
1739#define ARIZONA_LDO2_DISCH_MASK 0x0004 /* LDO2_DISCH */
1740#define ARIZONA_LDO2_DISCH_SHIFT 2 /* LDO2_DISCH */
1741#define ARIZONA_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
1742#define ARIZONA_LDO2_BYPASS 0x0002 /* LDO2_BYPASS */
1743#define ARIZONA_LDO2_BYPASS_MASK 0x0002 /* LDO2_BYPASS */
1744#define ARIZONA_LDO2_BYPASS_SHIFT 1 /* LDO2_BYPASS */
1745#define ARIZONA_LDO2_BYPASS_WIDTH 1 /* LDO2_BYPASS */
1746#define ARIZONA_LDO2_ENA 0x0001 /* LDO2_ENA */
1747#define ARIZONA_LDO2_ENA_MASK 0x0001 /* LDO2_ENA */
1748#define ARIZONA_LDO2_ENA_SHIFT 0 /* LDO2_ENA */
1749#define ARIZONA_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
1750
1751/*
1752 * R536 (0x218) - Mic Bias Ctrl 1
1753 */
1754#define ARIZONA_MICB1_EXT_CAP 0x8000 /* MICB1_EXT_CAP */
1755#define ARIZONA_MICB1_EXT_CAP_MASK 0x8000 /* MICB1_EXT_CAP */
1756#define ARIZONA_MICB1_EXT_CAP_SHIFT 15 /* MICB1_EXT_CAP */
1757#define ARIZONA_MICB1_EXT_CAP_WIDTH 1 /* MICB1_EXT_CAP */
1758#define ARIZONA_MICB1_LVL_MASK 0x01E0 /* MICB1_LVL - [8:5] */
1759#define ARIZONA_MICB1_LVL_SHIFT 5 /* MICB1_LVL - [8:5] */
1760#define ARIZONA_MICB1_LVL_WIDTH 4 /* MICB1_LVL - [8:5] */
1761#define ARIZONA_MICB1_FAST 0x0010 /* MICB1_FAST */
1762#define ARIZONA_MICB1_FAST_MASK 0x0010 /* MICB1_FAST */
1763#define ARIZONA_MICB1_FAST_SHIFT 4 /* MICB1_FAST */
1764#define ARIZONA_MICB1_FAST_WIDTH 1 /* MICB1_FAST */
1765#define ARIZONA_MICB1_RATE 0x0008 /* MICB1_RATE */
1766#define ARIZONA_MICB1_RATE_MASK 0x0008 /* MICB1_RATE */
1767#define ARIZONA_MICB1_RATE_SHIFT 3 /* MICB1_RATE */
1768#define ARIZONA_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
1769#define ARIZONA_MICB1_DISCH 0x0004 /* MICB1_DISCH */
1770#define ARIZONA_MICB1_DISCH_MASK 0x0004 /* MICB1_DISCH */
1771#define ARIZONA_MICB1_DISCH_SHIFT 2 /* MICB1_DISCH */
1772#define ARIZONA_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
1773#define ARIZONA_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */
1774#define ARIZONA_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */
1775#define ARIZONA_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */
1776#define ARIZONA_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */
1777#define ARIZONA_MICB1_ENA 0x0001 /* MICB1_ENA */
1778#define ARIZONA_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */
1779#define ARIZONA_MICB1_ENA_SHIFT 0 /* MICB1_ENA */
1780#define ARIZONA_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
1781
1782/*
1783 * R537 (0x219) - Mic Bias Ctrl 2
1784 */
1785#define ARIZONA_MICB2_EXT_CAP 0x8000 /* MICB2_EXT_CAP */
1786#define ARIZONA_MICB2_EXT_CAP_MASK 0x8000 /* MICB2_EXT_CAP */
1787#define ARIZONA_MICB2_EXT_CAP_SHIFT 15 /* MICB2_EXT_CAP */
1788#define ARIZONA_MICB2_EXT_CAP_WIDTH 1 /* MICB2_EXT_CAP */
1789#define ARIZONA_MICB2_LVL_MASK 0x01E0 /* MICB2_LVL - [8:5] */
1790#define ARIZONA_MICB2_LVL_SHIFT 5 /* MICB2_LVL - [8:5] */
1791#define ARIZONA_MICB2_LVL_WIDTH 4 /* MICB2_LVL - [8:5] */
1792#define ARIZONA_MICB2_FAST 0x0010 /* MICB2_FAST */
1793#define ARIZONA_MICB2_FAST_MASK 0x0010 /* MICB2_FAST */
1794#define ARIZONA_MICB2_FAST_SHIFT 4 /* MICB2_FAST */
1795#define ARIZONA_MICB2_FAST_WIDTH 1 /* MICB2_FAST */
1796#define ARIZONA_MICB2_RATE 0x0008 /* MICB2_RATE */
1797#define ARIZONA_MICB2_RATE_MASK 0x0008 /* MICB2_RATE */
1798#define ARIZONA_MICB2_RATE_SHIFT 3 /* MICB2_RATE */
1799#define ARIZONA_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
1800#define ARIZONA_MICB2_DISCH 0x0004 /* MICB2_DISCH */
1801#define ARIZONA_MICB2_DISCH_MASK 0x0004 /* MICB2_DISCH */
1802#define ARIZONA_MICB2_DISCH_SHIFT 2 /* MICB2_DISCH */
1803#define ARIZONA_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
1804#define ARIZONA_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */
1805#define ARIZONA_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */
1806#define ARIZONA_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */
1807#define ARIZONA_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */
1808#define ARIZONA_MICB2_ENA 0x0001 /* MICB2_ENA */
1809#define ARIZONA_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */
1810#define ARIZONA_MICB2_ENA_SHIFT 0 /* MICB2_ENA */
1811#define ARIZONA_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
1812
1813/*
1814 * R538 (0x21A) - Mic Bias Ctrl 3
1815 */
1816#define ARIZONA_MICB3_EXT_CAP 0x8000 /* MICB3_EXT_CAP */
1817#define ARIZONA_MICB3_EXT_CAP_MASK 0x8000 /* MICB3_EXT_CAP */
1818#define ARIZONA_MICB3_EXT_CAP_SHIFT 15 /* MICB3_EXT_CAP */
1819#define ARIZONA_MICB3_EXT_CAP_WIDTH 1 /* MICB3_EXT_CAP */
1820#define ARIZONA_MICB3_LVL_MASK 0x01E0 /* MICB3_LVL - [8:5] */
1821#define ARIZONA_MICB3_LVL_SHIFT 5 /* MICB3_LVL - [8:5] */
1822#define ARIZONA_MICB3_LVL_WIDTH 4 /* MICB3_LVL - [8:5] */
1823#define ARIZONA_MICB3_FAST 0x0010 /* MICB3_FAST */
1824#define ARIZONA_MICB3_FAST_MASK 0x0010 /* MICB3_FAST */
1825#define ARIZONA_MICB3_FAST_SHIFT 4 /* MICB3_FAST */
1826#define ARIZONA_MICB3_FAST_WIDTH 1 /* MICB3_FAST */
1827#define ARIZONA_MICB3_RATE 0x0008 /* MICB3_RATE */
1828#define ARIZONA_MICB3_RATE_MASK 0x0008 /* MICB3_RATE */
1829#define ARIZONA_MICB3_RATE_SHIFT 3 /* MICB3_RATE */
1830#define ARIZONA_MICB3_RATE_WIDTH 1 /* MICB3_RATE */
1831#define ARIZONA_MICB3_DISCH 0x0004 /* MICB3_DISCH */
1832#define ARIZONA_MICB3_DISCH_MASK 0x0004 /* MICB3_DISCH */
1833#define ARIZONA_MICB3_DISCH_SHIFT 2 /* MICB3_DISCH */
1834#define ARIZONA_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */
1835#define ARIZONA_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */
1836#define ARIZONA_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */
1837#define ARIZONA_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */
1838#define ARIZONA_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */
1839#define ARIZONA_MICB3_ENA 0x0001 /* MICB3_ENA */
1840#define ARIZONA_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */
1841#define ARIZONA_MICB3_ENA_SHIFT 0 /* MICB3_ENA */
1842#define ARIZONA_MICB3_ENA_WIDTH 1 /* MICB3_ENA */
1843
1844/*
1845 * R659 (0x293) - Accessory Detect Mode 1
1846 */
1847#define ARIZONA_ACCDET_SRC 0x2000 /* ACCDET_SRC */
1848#define ARIZONA_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */
1849#define ARIZONA_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */
1850#define ARIZONA_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */
1851#define ARIZONA_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */
1852#define ARIZONA_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */
1853#define ARIZONA_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */
1854
1855/*
1856 * R667 (0x29B) - Headphone Detect 1
1857 */
1858#define ARIZONA_HP_STEP_SIZE 0x0100 /* HP_STEP_SIZE */
1859#define ARIZONA_HP_STEP_SIZE_MASK 0x0100 /* HP_STEP_SIZE */
1860#define ARIZONA_HP_STEP_SIZE_SHIFT 8 /* HP_STEP_SIZE */
1861#define ARIZONA_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */
1862#define ARIZONA_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */
1863#define ARIZONA_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */
1864#define ARIZONA_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */
1865#define ARIZONA_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */
1866#define ARIZONA_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */
1867#define ARIZONA_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */
1868#define ARIZONA_HP_IDAC_STEER 0x0004 /* HP_IDAC_STEER */
1869#define ARIZONA_HP_IDAC_STEER_MASK 0x0004 /* HP_IDAC_STEER */
1870#define ARIZONA_HP_IDAC_STEER_SHIFT 2 /* HP_IDAC_STEER */
1871#define ARIZONA_HP_IDAC_STEER_WIDTH 1 /* HP_IDAC_STEER */
1872#define ARIZONA_HP_RATE 0x0002 /* HP_RATE */
1873#define ARIZONA_HP_RATE_MASK 0x0002 /* HP_RATE */
1874#define ARIZONA_HP_RATE_SHIFT 1 /* HP_RATE */
1875#define ARIZONA_HP_RATE_WIDTH 1 /* HP_RATE */
1876#define ARIZONA_HP_POLL 0x0001 /* HP_POLL */
1877#define ARIZONA_HP_POLL_MASK 0x0001 /* HP_POLL */
1878#define ARIZONA_HP_POLL_SHIFT 0 /* HP_POLL */
1879#define ARIZONA_HP_POLL_WIDTH 1 /* HP_POLL */
1880
1881/*
1882 * R668 (0x29C) - Headphone Detect 2
1883 */
1884#define ARIZONA_HP_DONE 0x0080 /* HP_DONE */
1885#define ARIZONA_HP_DONE_MASK 0x0080 /* HP_DONE */
1886#define ARIZONA_HP_DONE_SHIFT 7 /* HP_DONE */
1887#define ARIZONA_HP_DONE_WIDTH 1 /* HP_DONE */
1888#define ARIZONA_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
1889#define ARIZONA_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
1890#define ARIZONA_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
1891
1892/*
1893 * R675 (0x2A3) - Mic Detect 1
1894 */
1895#define ARIZONA_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */
1896#define ARIZONA_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */
1897#define ARIZONA_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */
1898#define ARIZONA_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */
1899#define ARIZONA_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */
1900#define ARIZONA_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */
1901#define ARIZONA_MICD_BIAS_SRC_MASK 0x0030 /* MICD_BIAS_SRC - [5:4] */
1902#define ARIZONA_MICD_BIAS_SRC_SHIFT 4 /* MICD_BIAS_SRC - [5:4] */
1903#define ARIZONA_MICD_BIAS_SRC_WIDTH 2 /* MICD_BIAS_SRC - [5:4] */
1904#define ARIZONA_MICD_DBTIME 0x0002 /* MICD_DBTIME */
1905#define ARIZONA_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
1906#define ARIZONA_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
1907#define ARIZONA_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
1908#define ARIZONA_MICD_ENA 0x0001 /* MICD_ENA */
1909#define ARIZONA_MICD_ENA_MASK 0x0001 /* MICD_ENA */
1910#define ARIZONA_MICD_ENA_SHIFT 0 /* MICD_ENA */
1911#define ARIZONA_MICD_ENA_WIDTH 1 /* MICD_ENA */
1912
1913/*
1914 * R676 (0x2A4) - Mic Detect 2
1915 */
1916#define ARIZONA_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */
1917#define ARIZONA_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */
1918#define ARIZONA_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */
1919
1920/*
1921 * R677 (0x2A5) - Mic Detect 3
1922 */
1923#define ARIZONA_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */
1924#define ARIZONA_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */
1925#define ARIZONA_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */
1926#define ARIZONA_MICD_VALID 0x0002 /* MICD_VALID */
1927#define ARIZONA_MICD_VALID_MASK 0x0002 /* MICD_VALID */
1928#define ARIZONA_MICD_VALID_SHIFT 1 /* MICD_VALID */
1929#define ARIZONA_MICD_VALID_WIDTH 1 /* MICD_VALID */
1930#define ARIZONA_MICD_STS 0x0001 /* MICD_STS */
1931#define ARIZONA_MICD_STS_MASK 0x0001 /* MICD_STS */
1932#define ARIZONA_MICD_STS_SHIFT 0 /* MICD_STS */
1933#define ARIZONA_MICD_STS_WIDTH 1 /* MICD_STS */
1934
1935/*
1936 * R707 (0x2C3) - Mic noise mix control 1
1937 */
1938#define ARIZONA_MICMUTE_RATE_MASK 0x7800 /* MICMUTE_RATE - [14:11] */
1939#define ARIZONA_MICMUTE_RATE_SHIFT 11 /* MICMUTE_RATE - [14:11] */
1940#define ARIZONA_MICMUTE_RATE_WIDTH 4 /* MICMUTE_RATE - [14:11] */
1941#define ARIZONA_MICMUTE_MIX_ENA 0x0040 /* MICMUTE_MIX_ENA */
1942#define ARIZONA_MICMUTE_MIX_ENA_MASK 0x0040 /* MICMUTE_MIX_ENA */
1943#define ARIZONA_MICMUTE_MIX_ENA_SHIFT 6 /* MICMUTE_MIX_ENA */
1944#define ARIZONA_MICMUTE_MIX_ENA_WIDTH 1 /* MICMUTE_MIX_ENA */
1945
1946/*
1947 * R715 (0x2CB) - Isolation control
1948 */
1949#define ARIZONA_ISOLATE_DCVDD1 0x0001 /* ISOLATE_DCVDD1 */
1950#define ARIZONA_ISOLATE_DCVDD1_MASK 0x0001 /* ISOLATE_DCVDD1 */
1951#define ARIZONA_ISOLATE_DCVDD1_SHIFT 0 /* ISOLATE_DCVDD1 */
1952#define ARIZONA_ISOLATE_DCVDD1_WIDTH 1 /* ISOLATE_DCVDD1 */
1953
1954/*
1955 * R723 (0x2D3) - Jack detect analogue
1956 */
1957#define ARIZONA_JD2_ENA 0x0002 /* JD2_ENA */
1958#define ARIZONA_JD2_ENA_MASK 0x0002 /* JD2_ENA */
1959#define ARIZONA_JD2_ENA_SHIFT 1 /* JD2_ENA */
1960#define ARIZONA_JD2_ENA_WIDTH 1 /* JD2_ENA */
1961#define ARIZONA_JD1_ENA 0x0001 /* JD1_ENA */
1962#define ARIZONA_JD1_ENA_MASK 0x0001 /* JD1_ENA */
1963#define ARIZONA_JD1_ENA_SHIFT 0 /* JD1_ENA */
1964#define ARIZONA_JD1_ENA_WIDTH 1 /* JD1_ENA */
1965
1966/*
1967 * R768 (0x300) - Input Enables
1968 */
1969#define ARIZONA_IN3L_ENA 0x0020 /* IN3L_ENA */
1970#define ARIZONA_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */
1971#define ARIZONA_IN3L_ENA_SHIFT 5 /* IN3L_ENA */
1972#define ARIZONA_IN3L_ENA_WIDTH 1 /* IN3L_ENA */
1973#define ARIZONA_IN3R_ENA 0x0010 /* IN3R_ENA */
1974#define ARIZONA_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */
1975#define ARIZONA_IN3R_ENA_SHIFT 4 /* IN3R_ENA */
1976#define ARIZONA_IN3R_ENA_WIDTH 1 /* IN3R_ENA */
1977#define ARIZONA_IN2L_ENA 0x0008 /* IN2L_ENA */
1978#define ARIZONA_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */
1979#define ARIZONA_IN2L_ENA_SHIFT 3 /* IN2L_ENA */
1980#define ARIZONA_IN2L_ENA_WIDTH 1 /* IN2L_ENA */
1981#define ARIZONA_IN2R_ENA 0x0004 /* IN2R_ENA */
1982#define ARIZONA_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */
1983#define ARIZONA_IN2R_ENA_SHIFT 2 /* IN2R_ENA */
1984#define ARIZONA_IN2R_ENA_WIDTH 1 /* IN2R_ENA */
1985#define ARIZONA_IN1L_ENA 0x0002 /* IN1L_ENA */
1986#define ARIZONA_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */
1987#define ARIZONA_IN1L_ENA_SHIFT 1 /* IN1L_ENA */
1988#define ARIZONA_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
1989#define ARIZONA_IN1R_ENA 0x0001 /* IN1R_ENA */
1990#define ARIZONA_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */
1991#define ARIZONA_IN1R_ENA_SHIFT 0 /* IN1R_ENA */
1992#define ARIZONA_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
1993
1994/*
1995 * R776 (0x308) - Input Rate
1996 */
1997#define ARIZONA_IN_RATE_MASK 0x7800 /* IN_RATE - [14:11] */
1998#define ARIZONA_IN_RATE_SHIFT 11 /* IN_RATE - [14:11] */
1999#define ARIZONA_IN_RATE_WIDTH 4 /* IN_RATE - [14:11] */
2000
2001/*
2002 * R777 (0x309) - Input Volume Ramp
2003 */
2004#define ARIZONA_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */
2005#define ARIZONA_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */
2006#define ARIZONA_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */
2007#define ARIZONA_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */
2008#define ARIZONA_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */
2009#define ARIZONA_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */
2010
2011/*
2012 * R784 (0x310) - IN1L Control
2013 */
2014#define ARIZONA_IN1_OSR_MASK 0x6000 /* IN1_OSR - [14:13] */
2015#define ARIZONA_IN1_OSR_SHIFT 13 /* IN1_OSR - [14:13] */
2016#define ARIZONA_IN1_OSR_WIDTH 2 /* IN1_OSR - [14:13] */
2017#define ARIZONA_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */
2018#define ARIZONA_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */
2019#define ARIZONA_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */
2020#define ARIZONA_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */
2021#define ARIZONA_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */
2022#define ARIZONA_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */
2023#define ARIZONA_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */
2024#define ARIZONA_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */
2025#define ARIZONA_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */
2026
2027/*
2028 * R785 (0x311) - ADC Digital Volume 1L
2029 */
2030#define ARIZONA_IN_VU 0x0200 /* IN_VU */
2031#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2032#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2033#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2034#define ARIZONA_IN1L_MUTE 0x0100 /* IN1L_MUTE */
2035#define ARIZONA_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */
2036#define ARIZONA_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */
2037#define ARIZONA_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */
2038#define ARIZONA_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */
2039#define ARIZONA_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */
2040#define ARIZONA_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */
2041
2042/*
2043 * R786 (0x312) - DMIC1L Control
2044 */
2045#define ARIZONA_IN1_DMICL_DLY_MASK 0x003F /* IN1_DMICL_DLY - [5:0] */
2046#define ARIZONA_IN1_DMICL_DLY_SHIFT 0 /* IN1_DMICL_DLY - [5:0] */
2047#define ARIZONA_IN1_DMICL_DLY_WIDTH 6 /* IN1_DMICL_DLY - [5:0] */
2048
2049/*
2050 * R788 (0x314) - IN1R Control
2051 */
2052#define ARIZONA_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */
2053#define ARIZONA_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */
2054#define ARIZONA_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */
2055
2056/*
2057 * R789 (0x315) - ADC Digital Volume 1R
2058 */
2059#define ARIZONA_IN_VU 0x0200 /* IN_VU */
2060#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2061#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2062#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2063#define ARIZONA_IN1R_MUTE 0x0100 /* IN1R_MUTE */
2064#define ARIZONA_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */
2065#define ARIZONA_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */
2066#define ARIZONA_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */
2067#define ARIZONA_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */
2068#define ARIZONA_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */
2069#define ARIZONA_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */
2070
2071/*
2072 * R790 (0x316) - DMIC1R Control
2073 */
2074#define ARIZONA_IN1_DMICR_DLY_MASK 0x003F /* IN1_DMICR_DLY - [5:0] */
2075#define ARIZONA_IN1_DMICR_DLY_SHIFT 0 /* IN1_DMICR_DLY - [5:0] */
2076#define ARIZONA_IN1_DMICR_DLY_WIDTH 6 /* IN1_DMICR_DLY - [5:0] */
2077
2078/*
2079 * R792 (0x318) - IN2L Control
2080 */
2081#define ARIZONA_IN2_OSR_MASK 0x6000 /* IN2_OSR - [14:13] */
2082#define ARIZONA_IN2_OSR_SHIFT 13 /* IN2_OSR - [14:13] */
2083#define ARIZONA_IN2_OSR_WIDTH 2 /* IN2_OSR - [14:13] */
2084#define ARIZONA_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */
2085#define ARIZONA_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */
2086#define ARIZONA_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */
2087#define ARIZONA_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */
2088#define ARIZONA_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */
2089#define ARIZONA_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */
2090#define ARIZONA_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */
2091#define ARIZONA_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */
2092#define ARIZONA_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */
2093
2094/*
2095 * R793 (0x319) - ADC Digital Volume 2L
2096 */
2097#define ARIZONA_IN_VU 0x0200 /* IN_VU */
2098#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2099#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2100#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2101#define ARIZONA_IN2L_MUTE 0x0100 /* IN2L_MUTE */
2102#define ARIZONA_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */
2103#define ARIZONA_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */
2104#define ARIZONA_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */
2105#define ARIZONA_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */
2106#define ARIZONA_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */
2107#define ARIZONA_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */
2108
2109/*
2110 * R794 (0x31A) - DMIC2L Control
2111 */
2112#define ARIZONA_IN2_DMICL_DLY_MASK 0x003F /* IN2_DMICL_DLY - [5:0] */
2113#define ARIZONA_IN2_DMICL_DLY_SHIFT 0 /* IN2_DMICL_DLY - [5:0] */
2114#define ARIZONA_IN2_DMICL_DLY_WIDTH 6 /* IN2_DMICL_DLY - [5:0] */
2115
2116/*
2117 * R796 (0x31C) - IN2R Control
2118 */
2119#define ARIZONA_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */
2120#define ARIZONA_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */
2121#define ARIZONA_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */
2122
2123/*
2124 * R797 (0x31D) - ADC Digital Volume 2R
2125 */
2126#define ARIZONA_IN_VU 0x0200 /* IN_VU */
2127#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2128#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2129#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2130#define ARIZONA_IN2R_MUTE 0x0100 /* IN2R_MUTE */
2131#define ARIZONA_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */
2132#define ARIZONA_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */
2133#define ARIZONA_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */
2134#define ARIZONA_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */
2135#define ARIZONA_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */
2136#define ARIZONA_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */
2137
2138/*
2139 * R798 (0x31E) - DMIC2R Control
2140 */
2141#define ARIZONA_IN2_DMICR_DLY_MASK 0x003F /* IN2_DMICR_DLY - [5:0] */
2142#define ARIZONA_IN2_DMICR_DLY_SHIFT 0 /* IN2_DMICR_DLY - [5:0] */
2143#define ARIZONA_IN2_DMICR_DLY_WIDTH 6 /* IN2_DMICR_DLY - [5:0] */
2144
2145/*
2146 * R800 (0x320) - IN3L Control
2147 */
2148#define ARIZONA_IN3_OSR_MASK 0x6000 /* IN3_OSR - [14:13] */
2149#define ARIZONA_IN3_OSR_SHIFT 13 /* IN3_OSR - [14:13] */
2150#define ARIZONA_IN3_OSR_WIDTH 2 /* IN3_OSR - [14:13] */
2151#define ARIZONA_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */
2152#define ARIZONA_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */
2153#define ARIZONA_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */
2154#define ARIZONA_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */
2155#define ARIZONA_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */
2156#define ARIZONA_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */
2157#define ARIZONA_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */
2158#define ARIZONA_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */
2159#define ARIZONA_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */
2160
2161/*
2162 * R801 (0x321) - ADC Digital Volume 3L
2163 */
2164#define ARIZONA_IN_VU 0x0200 /* IN_VU */
2165#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2166#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2167#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2168#define ARIZONA_IN3L_MUTE 0x0100 /* IN3L_MUTE */
2169#define ARIZONA_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */
2170#define ARIZONA_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */
2171#define ARIZONA_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */
2172#define ARIZONA_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */
2173#define ARIZONA_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */
2174#define ARIZONA_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */
2175
2176/*
2177 * R802 (0x322) - DMIC3L Control
2178 */
2179#define ARIZONA_IN3_DMICL_DLY_MASK 0x003F /* IN3_DMICL_DLY - [5:0] */
2180#define ARIZONA_IN3_DMICL_DLY_SHIFT 0 /* IN3_DMICL_DLY - [5:0] */
2181#define ARIZONA_IN3_DMICL_DLY_WIDTH 6 /* IN3_DMICL_DLY - [5:0] */
2182
2183/*
2184 * R804 (0x324) - IN3R Control
2185 */
2186#define ARIZONA_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */
2187#define ARIZONA_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */
2188#define ARIZONA_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */
2189
2190/*
2191 * R805 (0x325) - ADC Digital Volume 3R
2192 */
2193#define ARIZONA_IN_VU 0x0200 /* IN_VU */
2194#define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2195#define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2196#define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2197#define ARIZONA_IN3R_MUTE 0x0100 /* IN3R_MUTE */
2198#define ARIZONA_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */
2199#define ARIZONA_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */
2200#define ARIZONA_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */
2201#define ARIZONA_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */
2202#define ARIZONA_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */
2203#define ARIZONA_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */
2204
2205/*
2206 * R806 (0x326) - DMIC3R Control
2207 */
2208#define ARIZONA_IN3_DMICR_DLY_MASK 0x003F /* IN3_DMICR_DLY - [5:0] */
2209#define ARIZONA_IN3_DMICR_DLY_SHIFT 0 /* IN3_DMICR_DLY - [5:0] */
2210#define ARIZONA_IN3_DMICR_DLY_WIDTH 6 /* IN3_DMICR_DLY - [5:0] */
2211
2212/*
2213 * R1024 (0x400) - Output Enables 1
2214 */
2215#define ARIZONA_OUT5L_ENA 0x0200 /* OUT5L_ENA */
2216#define ARIZONA_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */
2217#define ARIZONA_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */
2218#define ARIZONA_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */
2219#define ARIZONA_OUT5R_ENA 0x0100 /* OUT5R_ENA */
2220#define ARIZONA_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */
2221#define ARIZONA_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */
2222#define ARIZONA_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */
2223#define ARIZONA_OUT4L_ENA 0x0080 /* OUT4L_ENA */
2224#define ARIZONA_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */
2225#define ARIZONA_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */
2226#define ARIZONA_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */
2227#define ARIZONA_OUT4R_ENA 0x0040 /* OUT4R_ENA */
2228#define ARIZONA_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */
2229#define ARIZONA_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */
2230#define ARIZONA_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */
2231#define ARIZONA_OUT3L_ENA 0x0020 /* OUT3L_ENA */
2232#define ARIZONA_OUT3L_ENA_MASK 0x0020 /* OUT3L_ENA */
2233#define ARIZONA_OUT3L_ENA_SHIFT 5 /* OUT3L_ENA */
2234#define ARIZONA_OUT3L_ENA_WIDTH 1 /* OUT3L_ENA */
2235#define ARIZONA_OUT3R_ENA 0x0010 /* OUT3R_ENA */
2236#define ARIZONA_OUT3R_ENA_MASK 0x0010 /* OUT3R_ENA */
2237#define ARIZONA_OUT3R_ENA_SHIFT 4 /* OUT3R_ENA */
2238#define ARIZONA_OUT3R_ENA_WIDTH 1 /* OUT3R_ENA */
2239#define ARIZONA_OUT2L_ENA 0x0008 /* OUT2L_ENA */
2240#define ARIZONA_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */
2241#define ARIZONA_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */
2242#define ARIZONA_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */
2243#define ARIZONA_OUT2R_ENA 0x0004 /* OUT2R_ENA */
2244#define ARIZONA_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */
2245#define ARIZONA_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */
2246#define ARIZONA_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */
2247#define ARIZONA_OUT1L_ENA 0x0002 /* OUT1L_ENA */
2248#define ARIZONA_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */
2249#define ARIZONA_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */
2250#define ARIZONA_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */
2251#define ARIZONA_OUT1R_ENA 0x0001 /* OUT1R_ENA */
2252#define ARIZONA_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */
2253#define ARIZONA_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */
2254#define ARIZONA_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */
2255
2256/*
2257 * R1025 (0x401) - Output Status 1
2258 */
2259#define ARIZONA_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */
2260#define ARIZONA_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */
2261#define ARIZONA_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */
2262#define ARIZONA_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */
2263#define ARIZONA_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */
2264#define ARIZONA_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */
2265#define ARIZONA_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */
2266#define ARIZONA_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */
2267#define ARIZONA_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */
2268#define ARIZONA_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */
2269#define ARIZONA_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */
2270#define ARIZONA_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */
2271#define ARIZONA_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */
2272#define ARIZONA_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */
2273#define ARIZONA_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */
2274#define ARIZONA_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */
2275#define ARIZONA_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */
2276#define ARIZONA_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */
2277#define ARIZONA_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */
2278#define ARIZONA_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */
2279#define ARIZONA_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */
2280#define ARIZONA_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */
2281#define ARIZONA_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */
2282#define ARIZONA_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */
2283
2284/*
2285 * R1032 (0x408) - Output Rate 1
2286 */
2287#define ARIZONA_OUT_RATE_MASK 0x7800 /* OUT_RATE - [14:11] */
2288#define ARIZONA_OUT_RATE_SHIFT 11 /* OUT_RATE - [14:11] */
2289#define ARIZONA_OUT_RATE_WIDTH 4 /* OUT_RATE - [14:11] */
2290
2291/*
2292 * R1033 (0x409) - Output Volume Ramp
2293 */
2294#define ARIZONA_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */
2295#define ARIZONA_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */
2296#define ARIZONA_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */
2297#define ARIZONA_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */
2298#define ARIZONA_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */
2299#define ARIZONA_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */
2300
2301/*
2302 * R1040 (0x410) - Output Path Config 1L
2303 */
2304#define ARIZONA_OUT1_LP_MODE 0x8000 /* OUT1_LP_MODE */
2305#define ARIZONA_OUT1_LP_MODE_MASK 0x8000 /* OUT1_LP_MODE */
2306#define ARIZONA_OUT1_LP_MODE_SHIFT 15 /* OUT1_LP_MODE */
2307#define ARIZONA_OUT1_LP_MODE_WIDTH 1 /* OUT1_LP_MODE */
2308#define ARIZONA_OUT1_OSR 0x2000 /* OUT1_OSR */
2309#define ARIZONA_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */
2310#define ARIZONA_OUT1_OSR_SHIFT 13 /* OUT1_OSR */
2311#define ARIZONA_OUT1_OSR_WIDTH 1 /* OUT1_OSR */
2312#define ARIZONA_OUT1_MONO 0x1000 /* OUT1_MONO */
2313#define ARIZONA_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */
2314#define ARIZONA_OUT1_MONO_SHIFT 12 /* OUT1_MONO */
2315#define ARIZONA_OUT1_MONO_WIDTH 1 /* OUT1_MONO */
2316#define ARIZONA_OUT1L_ANC_SRC_MASK 0x0C00 /* OUT1L_ANC_SRC - [11:10] */
2317#define ARIZONA_OUT1L_ANC_SRC_SHIFT 10 /* OUT1L_ANC_SRC - [11:10] */
2318#define ARIZONA_OUT1L_ANC_SRC_WIDTH 2 /* OUT1L_ANC_SRC - [11:10] */
2319#define ARIZONA_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */
2320#define ARIZONA_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */
2321#define ARIZONA_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */
2322
2323/*
2324 * R1041 (0x411) - DAC Digital Volume 1L
2325 */
2326#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2327#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2328#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2329#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2330#define ARIZONA_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */
2331#define ARIZONA_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */
2332#define ARIZONA_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */
2333#define ARIZONA_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */
2334#define ARIZONA_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */
2335#define ARIZONA_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */
2336#define ARIZONA_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */
2337
2338/*
2339 * R1042 (0x412) - DAC Volume Limit 1L
2340 */
2341#define ARIZONA_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */
2342#define ARIZONA_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */
2343#define ARIZONA_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */
2344
2345/*
2346 * R1043 (0x413) - Noise Gate Select 1L
2347 */
2348#define ARIZONA_OUT1L_NGATE_SRC_MASK 0x0FFF /* OUT1L_NGATE_SRC - [11:0] */
2349#define ARIZONA_OUT1L_NGATE_SRC_SHIFT 0 /* OUT1L_NGATE_SRC - [11:0] */
2350#define ARIZONA_OUT1L_NGATE_SRC_WIDTH 12 /* OUT1L_NGATE_SRC - [11:0] */
2351
2352/*
2353 * R1044 (0x414) - Output Path Config 1R
2354 */
2355#define ARIZONA_OUT1R_ANC_SRC_MASK 0x0C00 /* OUT1R_ANC_SRC - [11:10] */
2356#define ARIZONA_OUT1R_ANC_SRC_SHIFT 10 /* OUT1R_ANC_SRC - [11:10] */
2357#define ARIZONA_OUT1R_ANC_SRC_WIDTH 2 /* OUT1R_ANC_SRC - [11:10] */
2358#define ARIZONA_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */
2359#define ARIZONA_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */
2360#define ARIZONA_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */
2361
2362/*
2363 * R1045 (0x415) - DAC Digital Volume 1R
2364 */
2365#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2366#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2367#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2368#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2369#define ARIZONA_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */
2370#define ARIZONA_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */
2371#define ARIZONA_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */
2372#define ARIZONA_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */
2373#define ARIZONA_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */
2374#define ARIZONA_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */
2375#define ARIZONA_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */
2376
2377/*
2378 * R1046 (0x416) - DAC Volume Limit 1R
2379 */
2380#define ARIZONA_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */
2381#define ARIZONA_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */
2382#define ARIZONA_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */
2383
2384/*
2385 * R1047 (0x417) - Noise Gate Select 1R
2386 */
2387#define ARIZONA_OUT1R_NGATE_SRC_MASK 0x0FFF /* OUT1R_NGATE_SRC - [11:0] */
2388#define ARIZONA_OUT1R_NGATE_SRC_SHIFT 0 /* OUT1R_NGATE_SRC - [11:0] */
2389#define ARIZONA_OUT1R_NGATE_SRC_WIDTH 12 /* OUT1R_NGATE_SRC - [11:0] */
2390
2391/*
2392 * R1048 (0x418) - Output Path Config 2L
2393 */
2394#define ARIZONA_OUT2_LP_MODE 0x8000 /* OUT2_LP_MODE */
2395#define ARIZONA_OUT2_LP_MODE_MASK 0x8000 /* OUT2_LP_MODE */
2396#define ARIZONA_OUT2_LP_MODE_SHIFT 15 /* OUT2_LP_MODE */
2397#define ARIZONA_OUT2_LP_MODE_WIDTH 1 /* OUT2_LP_MODE */
2398#define ARIZONA_OUT2_OSR 0x2000 /* OUT2_OSR */
2399#define ARIZONA_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */
2400#define ARIZONA_OUT2_OSR_SHIFT 13 /* OUT2_OSR */
2401#define ARIZONA_OUT2_OSR_WIDTH 1 /* OUT2_OSR */
2402#define ARIZONA_OUT2_MONO 0x1000 /* OUT2_MONO */
2403#define ARIZONA_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */
2404#define ARIZONA_OUT2_MONO_SHIFT 12 /* OUT2_MONO */
2405#define ARIZONA_OUT2_MONO_WIDTH 1 /* OUT2_MONO */
2406#define ARIZONA_OUT2L_ANC_SRC_MASK 0x0C00 /* OUT2L_ANC_SRC - [11:10] */
2407#define ARIZONA_OUT2L_ANC_SRC_SHIFT 10 /* OUT2L_ANC_SRC - [11:10] */
2408#define ARIZONA_OUT2L_ANC_SRC_WIDTH 2 /* OUT2L_ANC_SRC - [11:10] */
2409#define ARIZONA_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */
2410#define ARIZONA_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */
2411#define ARIZONA_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */
2412
2413/*
2414 * R1049 (0x419) - DAC Digital Volume 2L
2415 */
2416#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2417#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2418#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2419#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2420#define ARIZONA_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */
2421#define ARIZONA_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */
2422#define ARIZONA_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */
2423#define ARIZONA_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */
2424#define ARIZONA_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */
2425#define ARIZONA_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */
2426#define ARIZONA_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */
2427
2428/*
2429 * R1050 (0x41A) - DAC Volume Limit 2L
2430 */
2431#define ARIZONA_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */
2432#define ARIZONA_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */
2433#define ARIZONA_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */
2434
2435/*
2436 * R1051 (0x41B) - Noise Gate Select 2L
2437 */
2438#define ARIZONA_OUT2L_NGATE_SRC_MASK 0x0FFF /* OUT2L_NGATE_SRC - [11:0] */
2439#define ARIZONA_OUT2L_NGATE_SRC_SHIFT 0 /* OUT2L_NGATE_SRC - [11:0] */
2440#define ARIZONA_OUT2L_NGATE_SRC_WIDTH 12 /* OUT2L_NGATE_SRC - [11:0] */
2441
2442/*
2443 * R1052 (0x41C) - Output Path Config 2R
2444 */
2445#define ARIZONA_OUT2R_ANC_SRC_MASK 0x0C00 /* OUT2R_ANC_SRC - [11:10] */
2446#define ARIZONA_OUT2R_ANC_SRC_SHIFT 10 /* OUT2R_ANC_SRC - [11:10] */
2447#define ARIZONA_OUT2R_ANC_SRC_WIDTH 2 /* OUT2R_ANC_SRC - [11:10] */
2448#define ARIZONA_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */
2449#define ARIZONA_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */
2450#define ARIZONA_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */
2451
2452/*
2453 * R1053 (0x41D) - DAC Digital Volume 2R
2454 */
2455#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2456#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2457#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2458#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2459#define ARIZONA_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */
2460#define ARIZONA_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */
2461#define ARIZONA_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */
2462#define ARIZONA_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */
2463#define ARIZONA_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */
2464#define ARIZONA_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */
2465#define ARIZONA_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */
2466
2467/*
2468 * R1054 (0x41E) - DAC Volume Limit 2R
2469 */
2470#define ARIZONA_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */
2471#define ARIZONA_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */
2472#define ARIZONA_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */
2473
2474/*
2475 * R1055 (0x41F) - Noise Gate Select 2R
2476 */
2477#define ARIZONA_OUT2R_NGATE_SRC_MASK 0x0FFF /* OUT2R_NGATE_SRC - [11:0] */
2478#define ARIZONA_OUT2R_NGATE_SRC_SHIFT 0 /* OUT2R_NGATE_SRC - [11:0] */
2479#define ARIZONA_OUT2R_NGATE_SRC_WIDTH 12 /* OUT2R_NGATE_SRC - [11:0] */
2480
2481/*
2482 * R1056 (0x420) - Output Path Config 3L
2483 */
2484#define ARIZONA_OUT3_LP_MODE 0x8000 /* OUT3_LP_MODE */
2485#define ARIZONA_OUT3_LP_MODE_MASK 0x8000 /* OUT3_LP_MODE */
2486#define ARIZONA_OUT3_LP_MODE_SHIFT 15 /* OUT3_LP_MODE */
2487#define ARIZONA_OUT3_LP_MODE_WIDTH 1 /* OUT3_LP_MODE */
2488#define ARIZONA_OUT3_OSR 0x2000 /* OUT3_OSR */
2489#define ARIZONA_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */
2490#define ARIZONA_OUT3_OSR_SHIFT 13 /* OUT3_OSR */
2491#define ARIZONA_OUT3_OSR_WIDTH 1 /* OUT3_OSR */
2492#define ARIZONA_OUT3_MONO 0x1000 /* OUT3_MONO */
2493#define ARIZONA_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */
2494#define ARIZONA_OUT3_MONO_SHIFT 12 /* OUT3_MONO */
2495#define ARIZONA_OUT3_MONO_WIDTH 1 /* OUT3_MONO */
2496#define ARIZONA_OUT3L_ANC_SRC_MASK 0x0C00 /* OUT3L_ANC_SRC - [11:10] */
2497#define ARIZONA_OUT3L_ANC_SRC_SHIFT 10 /* OUT3L_ANC_SRC - [11:10] */
2498#define ARIZONA_OUT3L_ANC_SRC_WIDTH 2 /* OUT3L_ANC_SRC - [11:10] */
2499#define ARIZONA_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */
2500#define ARIZONA_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */
2501#define ARIZONA_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */
2502
2503/*
2504 * R1057 (0x421) - DAC Digital Volume 3L
2505 */
2506#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2507#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2508#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2509#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2510#define ARIZONA_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */
2511#define ARIZONA_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */
2512#define ARIZONA_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */
2513#define ARIZONA_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */
2514#define ARIZONA_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */
2515#define ARIZONA_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */
2516#define ARIZONA_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */
2517
2518/*
2519 * R1058 (0x422) - DAC Volume Limit 3L
2520 */
2521#define ARIZONA_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */
2522#define ARIZONA_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */
2523#define ARIZONA_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */
2524
2525/*
2526 * R1059 (0x423) - Noise Gate Select 3L
2527 */
2528#define ARIZONA_OUT3_NGATE_SRC_MASK 0x0FFF /* OUT3_NGATE_SRC - [11:0] */
2529#define ARIZONA_OUT3_NGATE_SRC_SHIFT 0 /* OUT3_NGATE_SRC - [11:0] */
2530#define ARIZONA_OUT3_NGATE_SRC_WIDTH 12 /* OUT3_NGATE_SRC - [11:0] */
2531
2532/*
2533 * R1060 (0x424) - Output Path Config 3R
2534 */
2535#define ARIZONA_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */
2536#define ARIZONA_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */
2537#define ARIZONA_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */
2538
2539/*
2540 * R1061 (0x425) - DAC Digital Volume 3R
2541 */
2542#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2543#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2544#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2545#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2546#define ARIZONA_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */
2547#define ARIZONA_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */
2548#define ARIZONA_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */
2549#define ARIZONA_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */
2550#define ARIZONA_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */
2551#define ARIZONA_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */
2552#define ARIZONA_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */
2553
2554/*
2555 * R1062 (0x426) - DAC Volume Limit 3R
2556 */
2557#define ARIZONA_OUT3R_ANC_SRC_MASK 0x0C00 /* OUT3R_ANC_SRC - [11:10] */
2558#define ARIZONA_OUT3R_ANC_SRC_SHIFT 10 /* OUT3R_ANC_SRC - [11:10] */
2559#define ARIZONA_OUT3R_ANC_SRC_WIDTH 2 /* OUT3R_ANC_SRC - [11:10] */
2560#define ARIZONA_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */
2561#define ARIZONA_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */
2562#define ARIZONA_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */
2563
2564/*
2565 * R1064 (0x428) - Output Path Config 4L
2566 */
2567#define ARIZONA_OUT4_OSR 0x2000 /* OUT4_OSR */
2568#define ARIZONA_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */
2569#define ARIZONA_OUT4_OSR_SHIFT 13 /* OUT4_OSR */
2570#define ARIZONA_OUT4_OSR_WIDTH 1 /* OUT4_OSR */
2571#define ARIZONA_OUT4L_ANC_SRC_MASK 0x0C00 /* OUT4L_ANC_SRC - [11:10] */
2572#define ARIZONA_OUT4L_ANC_SRC_SHIFT 10 /* OUT4L_ANC_SRC - [11:10] */
2573#define ARIZONA_OUT4L_ANC_SRC_WIDTH 2 /* OUT4L_ANC_SRC - [11:10] */
2574
2575/*
2576 * R1065 (0x429) - DAC Digital Volume 4L
2577 */
2578#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2579#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2580#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2581#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2582#define ARIZONA_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */
2583#define ARIZONA_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */
2584#define ARIZONA_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */
2585#define ARIZONA_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */
2586#define ARIZONA_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */
2587#define ARIZONA_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */
2588#define ARIZONA_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */
2589
2590/*
2591 * R1066 (0x42A) - Out Volume 4L
2592 */
2593#define ARIZONA_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */
2594#define ARIZONA_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */
2595#define ARIZONA_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */
2596
2597/*
2598 * R1067 (0x42B) - Noise Gate Select 4L
2599 */
2600#define ARIZONA_OUT4L_NGATE_SRC_MASK 0x0FFF /* OUT4L_NGATE_SRC - [11:0] */
2601#define ARIZONA_OUT4L_NGATE_SRC_SHIFT 0 /* OUT4L_NGATE_SRC - [11:0] */
2602#define ARIZONA_OUT4L_NGATE_SRC_WIDTH 12 /* OUT4L_NGATE_SRC - [11:0] */
2603
2604/*
2605 * R1068 (0x42C) - Output Path Config 4R
2606 */
2607#define ARIZONA_OUT4R_ANC_SRC_MASK 0x0C00 /* OUT4R_ANC_SRC - [11:10] */
2608#define ARIZONA_OUT4R_ANC_SRC_SHIFT 10 /* OUT4R_ANC_SRC - [11:10] */
2609#define ARIZONA_OUT4R_ANC_SRC_WIDTH 2 /* OUT4R_ANC_SRC - [11:10] */
2610
2611/*
2612 * R1069 (0x42D) - DAC Digital Volume 4R
2613 */
2614#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2615#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2616#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2617#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2618#define ARIZONA_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */
2619#define ARIZONA_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */
2620#define ARIZONA_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */
2621#define ARIZONA_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */
2622#define ARIZONA_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */
2623#define ARIZONA_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */
2624#define ARIZONA_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */
2625
2626/*
2627 * R1070 (0x42E) - Out Volume 4R
2628 */
2629#define ARIZONA_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */
2630#define ARIZONA_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */
2631#define ARIZONA_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */
2632
2633/*
2634 * R1071 (0x42F) - Noise Gate Select 4R
2635 */
2636#define ARIZONA_OUT4R_NGATE_SRC_MASK 0x0FFF /* OUT4R_NGATE_SRC - [11:0] */
2637#define ARIZONA_OUT4R_NGATE_SRC_SHIFT 0 /* OUT4R_NGATE_SRC - [11:0] */
2638#define ARIZONA_OUT4R_NGATE_SRC_WIDTH 12 /* OUT4R_NGATE_SRC - [11:0] */
2639
2640/*
2641 * R1072 (0x430) - Output Path Config 5L
2642 */
2643#define ARIZONA_OUT5_OSR 0x2000 /* OUT5_OSR */
2644#define ARIZONA_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */
2645#define ARIZONA_OUT5_OSR_SHIFT 13 /* OUT5_OSR */
2646#define ARIZONA_OUT5_OSR_WIDTH 1 /* OUT5_OSR */
2647#define ARIZONA_OUT5L_ANC_SRC_MASK 0x0C00 /* OUT5L_ANC_SRC - [11:10] */
2648#define ARIZONA_OUT5L_ANC_SRC_SHIFT 10 /* OUT5L_ANC_SRC - [11:10] */
2649#define ARIZONA_OUT5L_ANC_SRC_WIDTH 2 /* OUT5L_ANC_SRC - [11:10] */
2650
2651/*
2652 * R1073 (0x431) - DAC Digital Volume 5L
2653 */
2654#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2655#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2656#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2657#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2658#define ARIZONA_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */
2659#define ARIZONA_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */
2660#define ARIZONA_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */
2661#define ARIZONA_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */
2662#define ARIZONA_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */
2663#define ARIZONA_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */
2664#define ARIZONA_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */
2665
2666/*
2667 * R1074 (0x432) - DAC Volume Limit 5L
2668 */
2669#define ARIZONA_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */
2670#define ARIZONA_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */
2671#define ARIZONA_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */
2672
2673/*
2674 * R1075 (0x433) - Noise Gate Select 5L
2675 */
2676#define ARIZONA_OUT5L_NGATE_SRC_MASK 0x0FFF /* OUT5L_NGATE_SRC - [11:0] */
2677#define ARIZONA_OUT5L_NGATE_SRC_SHIFT 0 /* OUT5L_NGATE_SRC - [11:0] */
2678#define ARIZONA_OUT5L_NGATE_SRC_WIDTH 12 /* OUT5L_NGATE_SRC - [11:0] */
2679
2680/*
2681 * R1076 (0x434) - Output Path Config 5R
2682 */
2683#define ARIZONA_OUT5R_ANC_SRC_MASK 0x0C00 /* OUT5R_ANC_SRC - [11:10] */
2684#define ARIZONA_OUT5R_ANC_SRC_SHIFT 10 /* OUT5R_ANC_SRC - [11:10] */
2685#define ARIZONA_OUT5R_ANC_SRC_WIDTH 2 /* OUT5R_ANC_SRC - [11:10] */
2686
2687/*
2688 * R1077 (0x435) - DAC Digital Volume 5R
2689 */
2690#define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2691#define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2692#define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2693#define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2694#define ARIZONA_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */
2695#define ARIZONA_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */
2696#define ARIZONA_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */
2697#define ARIZONA_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */
2698#define ARIZONA_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */
2699#define ARIZONA_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */
2700#define ARIZONA_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */
2701
2702/*
2703 * R1078 (0x436) - DAC Volume Limit 5R
2704 */
2705#define ARIZONA_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */
2706#define ARIZONA_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */
2707#define ARIZONA_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */
2708
2709/*
2710 * R1079 (0x437) - Noise Gate Select 5R
2711 */
2712#define ARIZONA_OUT5R_NGATE_SRC_MASK 0x0FFF /* OUT5R_NGATE_SRC - [11:0] */
2713#define ARIZONA_OUT5R_NGATE_SRC_SHIFT 0 /* OUT5R_NGATE_SRC - [11:0] */
2714#define ARIZONA_OUT5R_NGATE_SRC_WIDTH 12 /* OUT5R_NGATE_SRC - [11:0] */
2715
2716/*
2717 * R1104 (0x450) - DAC AEC Control 1
2718 */
2719#define ARIZONA_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */
2720#define ARIZONA_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */
2721#define ARIZONA_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */
2722#define ARIZONA_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */
2723#define ARIZONA_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */
2724#define ARIZONA_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */
2725#define ARIZONA_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */
2726#define ARIZONA_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */
2727#define ARIZONA_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */
2728#define ARIZONA_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */
2729#define ARIZONA_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */
2730
2731/*
2732 * R1112 (0x458) - Noise Gate Control
2733 */
2734#define ARIZONA_NGATE_HOLD_MASK 0x0030 /* NGATE_HOLD - [5:4] */
2735#define ARIZONA_NGATE_HOLD_SHIFT 4 /* NGATE_HOLD - [5:4] */
2736#define ARIZONA_NGATE_HOLD_WIDTH 2 /* NGATE_HOLD - [5:4] */
2737#define ARIZONA_NGATE_THR_MASK 0x000E /* NGATE_THR - [3:1] */
2738#define ARIZONA_NGATE_THR_SHIFT 1 /* NGATE_THR - [3:1] */
2739#define ARIZONA_NGATE_THR_WIDTH 3 /* NGATE_THR - [3:1] */
2740#define ARIZONA_NGATE_ENA 0x0001 /* NGATE_ENA */
2741#define ARIZONA_NGATE_ENA_MASK 0x0001 /* NGATE_ENA */
2742#define ARIZONA_NGATE_ENA_SHIFT 0 /* NGATE_ENA */
2743#define ARIZONA_NGATE_ENA_WIDTH 1 /* NGATE_ENA */
2744
2745/*
2746 * R1168 (0x490) - PDM SPK1 CTRL 1
2747 */
2748#define ARIZONA_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */
2749#define ARIZONA_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */
2750#define ARIZONA_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */
2751#define ARIZONA_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
2752#define ARIZONA_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */
2753#define ARIZONA_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */
2754#define ARIZONA_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */
2755#define ARIZONA_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
2756#define ARIZONA_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */
2757#define ARIZONA_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */
2758#define ARIZONA_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */
2759#define ARIZONA_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */
2760#define ARIZONA_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */
2761#define ARIZONA_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */
2762#define ARIZONA_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */
2763
2764/*
2765 * R1169 (0x491) - PDM SPK1 CTRL 2
2766 */
2767#define ARIZONA_SPK1_FMT 0x0001 /* SPK1_FMT */
2768#define ARIZONA_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */
2769#define ARIZONA_SPK1_FMT_SHIFT 0 /* SPK1_FMT */
2770#define ARIZONA_SPK1_FMT_WIDTH 1 /* SPK1_FMT */
2771
2772/*
2773 * R1244 (0x4DC) - DAC comp 1
2774 */
2775#define ARIZONA_OUT_COMP_COEFF_MASK 0xFFFF /* OUT_COMP_COEFF - [15:0] */
2776#define ARIZONA_OUT_COMP_COEFF_SHIFT 0 /* OUT_COMP_COEFF - [15:0] */
2777#define ARIZONA_OUT_COMP_COEFF_WIDTH 16 /* OUT_COMP_COEFF - [15:0] */
2778
2779/*
2780 * R1245 (0x4DD) - DAC comp 2
2781 */
2782#define ARIZONA_OUT_COMP_COEFF_1 0x0002 /* OUT_COMP_COEFF */
2783#define ARIZONA_OUT_COMP_COEFF_1_MASK 0x0002 /* OUT_COMP_COEFF */
2784#define ARIZONA_OUT_COMP_COEFF_1_SHIFT 1 /* OUT_COMP_COEFF */
2785#define ARIZONA_OUT_COMP_COEFF_1_WIDTH 1 /* OUT_COMP_COEFF */
2786#define ARIZONA_OUT_COMP_COEFF_SEL 0x0001 /* OUT_COMP_COEFF_SEL */
2787#define ARIZONA_OUT_COMP_COEFF_SEL_MASK 0x0001 /* OUT_COMP_COEFF_SEL */
2788#define ARIZONA_OUT_COMP_COEFF_SEL_SHIFT 0 /* OUT_COMP_COEFF_SEL */
2789#define ARIZONA_OUT_COMP_COEFF_SEL_WIDTH 1 /* OUT_COMP_COEFF_SEL */
2790
2791/*
2792 * R1246 (0x4DE) - DAC comp 3
2793 */
2794#define ARIZONA_AEC_COMP_COEFF_MASK 0xFFFF /* AEC_COMP_COEFF - [15:0] */
2795#define ARIZONA_AEC_COMP_COEFF_SHIFT 0 /* AEC_COMP_COEFF - [15:0] */
2796#define ARIZONA_AEC_COMP_COEFF_WIDTH 16 /* AEC_COMP_COEFF - [15:0] */
2797
2798/*
2799 * R1247 (0x4DF) - DAC comp 4
2800 */
2801#define ARIZONA_AEC_COMP_COEFF_1 0x0002 /* AEC_COMP_COEFF */
2802#define ARIZONA_AEC_COMP_COEFF_1_MASK 0x0002 /* AEC_COMP_COEFF */
2803#define ARIZONA_AEC_COMP_COEFF_1_SHIFT 1 /* AEC_COMP_COEFF */
2804#define ARIZONA_AEC_COMP_COEFF_1_WIDTH 1 /* AEC_COMP_COEFF */
2805#define ARIZONA_AEC_COMP_COEFF_SEL 0x0001 /* AEC_COMP_COEFF_SEL */
2806#define ARIZONA_AEC_COMP_COEFF_SEL_MASK 0x0001 /* AEC_COMP_COEFF_SEL */
2807#define ARIZONA_AEC_COMP_COEFF_SEL_SHIFT 0 /* AEC_COMP_COEFF_SEL */
2808#define ARIZONA_AEC_COMP_COEFF_SEL_WIDTH 1 /* AEC_COMP_COEFF_SEL */
2809
2810/*
2811 * R1280 (0x500) - AIF1 BCLK Ctrl
2812 */
2813#define ARIZONA_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */
2814#define ARIZONA_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */
2815#define ARIZONA_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */
2816#define ARIZONA_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
2817#define ARIZONA_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */
2818#define ARIZONA_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */
2819#define ARIZONA_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */
2820#define ARIZONA_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */
2821#define ARIZONA_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */
2822#define ARIZONA_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */
2823#define ARIZONA_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */
2824#define ARIZONA_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */
2825#define ARIZONA_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */
2826#define ARIZONA_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */
2827#define ARIZONA_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */
2828
2829/*
2830 * R1281 (0x501) - AIF1 Tx Pin Ctrl
2831 */
2832#define ARIZONA_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */
2833#define ARIZONA_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */
2834#define ARIZONA_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */
2835#define ARIZONA_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */
2836#define ARIZONA_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */
2837#define ARIZONA_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */
2838#define ARIZONA_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */
2839#define ARIZONA_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */
2840#define ARIZONA_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */
2841#define ARIZONA_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */
2842#define ARIZONA_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */
2843#define ARIZONA_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */
2844#define ARIZONA_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */
2845#define ARIZONA_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */
2846#define ARIZONA_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */
2847#define ARIZONA_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */
2848#define ARIZONA_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
2849#define ARIZONA_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
2850#define ARIZONA_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */
2851#define ARIZONA_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */
2852
2853/*
2854 * R1282 (0x502) - AIF1 Rx Pin Ctrl
2855 */
2856#define ARIZONA_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */
2857#define ARIZONA_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */
2858#define ARIZONA_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */
2859#define ARIZONA_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */
2860#define ARIZONA_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */
2861#define ARIZONA_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */
2862#define ARIZONA_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */
2863#define ARIZONA_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */
2864#define ARIZONA_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
2865#define ARIZONA_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
2866#define ARIZONA_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */
2867#define ARIZONA_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */
2868
2869/*
2870 * R1283 (0x503) - AIF1 Rate Ctrl
2871 */
2872#define ARIZONA_AIF1_RATE_MASK 0x7800 /* AIF1_RATE - [14:11] */
2873#define ARIZONA_AIF1_RATE_SHIFT 11 /* AIF1_RATE - [14:11] */
2874#define ARIZONA_AIF1_RATE_WIDTH 4 /* AIF1_RATE - [14:11] */
2875#define ARIZONA_AIF1_TRI 0x0040 /* AIF1_TRI */
2876#define ARIZONA_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */
2877#define ARIZONA_AIF1_TRI_SHIFT 6 /* AIF1_TRI */
2878#define ARIZONA_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
2879
2880/*
2881 * R1284 (0x504) - AIF1 Format
2882 */
2883#define ARIZONA_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */
2884#define ARIZONA_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */
2885#define ARIZONA_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */
2886
2887/*
2888 * R1285 (0x505) - AIF1 Tx BCLK Rate
2889 */
2890#define ARIZONA_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */
2891#define ARIZONA_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */
2892#define ARIZONA_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */
2893
2894/*
2895 * R1286 (0x506) - AIF1 Rx BCLK Rate
2896 */
2897#define ARIZONA_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */
2898#define ARIZONA_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */
2899#define ARIZONA_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */
2900
2901/*
2902 * R1287 (0x507) - AIF1 Frame Ctrl 1
2903 */
2904#define ARIZONA_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */
2905#define ARIZONA_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */
2906#define ARIZONA_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */
2907#define ARIZONA_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */
2908#define ARIZONA_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */
2909#define ARIZONA_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */
2910
2911/*
2912 * R1288 (0x508) - AIF1 Frame Ctrl 2
2913 */
2914#define ARIZONA_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */
2915#define ARIZONA_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */
2916#define ARIZONA_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */
2917#define ARIZONA_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */
2918#define ARIZONA_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */
2919#define ARIZONA_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */
2920
2921/*
2922 * R1289 (0x509) - AIF1 Frame Ctrl 3
2923 */
2924#define ARIZONA_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */
2925#define ARIZONA_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */
2926#define ARIZONA_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */
2927
2928/*
2929 * R1290 (0x50A) - AIF1 Frame Ctrl 4
2930 */
2931#define ARIZONA_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */
2932#define ARIZONA_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */
2933#define ARIZONA_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */
2934
2935/*
2936 * R1291 (0x50B) - AIF1 Frame Ctrl 5
2937 */
2938#define ARIZONA_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */
2939#define ARIZONA_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */
2940#define ARIZONA_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */
2941
2942/*
2943 * R1292 (0x50C) - AIF1 Frame Ctrl 6
2944 */
2945#define ARIZONA_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */
2946#define ARIZONA_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */
2947#define ARIZONA_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */
2948
2949/*
2950 * R1293 (0x50D) - AIF1 Frame Ctrl 7
2951 */
2952#define ARIZONA_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */
2953#define ARIZONA_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */
2954#define ARIZONA_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */
2955
2956/*
2957 * R1294 (0x50E) - AIF1 Frame Ctrl 8
2958 */
2959#define ARIZONA_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */
2960#define ARIZONA_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */
2961#define ARIZONA_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */
2962
2963/*
2964 * R1295 (0x50F) - AIF1 Frame Ctrl 9
2965 */
2966#define ARIZONA_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */
2967#define ARIZONA_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */
2968#define ARIZONA_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */
2969
2970/*
2971 * R1296 (0x510) - AIF1 Frame Ctrl 10
2972 */
2973#define ARIZONA_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */
2974#define ARIZONA_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */
2975#define ARIZONA_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */
2976
2977/*
2978 * R1297 (0x511) - AIF1 Frame Ctrl 11
2979 */
2980#define ARIZONA_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */
2981#define ARIZONA_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */
2982#define ARIZONA_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */
2983
2984/*
2985 * R1298 (0x512) - AIF1 Frame Ctrl 12
2986 */
2987#define ARIZONA_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */
2988#define ARIZONA_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */
2989#define ARIZONA_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */
2990
2991/*
2992 * R1299 (0x513) - AIF1 Frame Ctrl 13
2993 */
2994#define ARIZONA_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */
2995#define ARIZONA_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */
2996#define ARIZONA_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */
2997
2998/*
2999 * R1300 (0x514) - AIF1 Frame Ctrl 14
3000 */
3001#define ARIZONA_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */
3002#define ARIZONA_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */
3003#define ARIZONA_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */
3004
3005/*
3006 * R1301 (0x515) - AIF1 Frame Ctrl 15
3007 */
3008#define ARIZONA_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */
3009#define ARIZONA_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */
3010#define ARIZONA_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */
3011
3012/*
3013 * R1302 (0x516) - AIF1 Frame Ctrl 16
3014 */
3015#define ARIZONA_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */
3016#define ARIZONA_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */
3017#define ARIZONA_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */
3018
3019/*
3020 * R1303 (0x517) - AIF1 Frame Ctrl 17
3021 */
3022#define ARIZONA_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */
3023#define ARIZONA_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */
3024#define ARIZONA_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */
3025
3026/*
3027 * R1304 (0x518) - AIF1 Frame Ctrl 18
3028 */
3029#define ARIZONA_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */
3030#define ARIZONA_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */
3031#define ARIZONA_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */
3032
3033/*
3034 * R1305 (0x519) - AIF1 Tx Enables
3035 */
3036#define ARIZONA_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */
3037#define ARIZONA_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */
3038#define ARIZONA_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */
3039#define ARIZONA_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */
3040#define ARIZONA_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */
3041#define ARIZONA_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */
3042#define ARIZONA_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */
3043#define ARIZONA_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */
3044#define ARIZONA_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */
3045#define ARIZONA_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */
3046#define ARIZONA_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */
3047#define ARIZONA_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */
3048#define ARIZONA_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */
3049#define ARIZONA_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */
3050#define ARIZONA_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */
3051#define ARIZONA_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */
3052#define ARIZONA_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */
3053#define ARIZONA_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */
3054#define ARIZONA_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */
3055#define ARIZONA_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */
3056#define ARIZONA_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */
3057#define ARIZONA_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */
3058#define ARIZONA_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */
3059#define ARIZONA_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */
3060#define ARIZONA_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */
3061#define ARIZONA_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */
3062#define ARIZONA_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */
3063#define ARIZONA_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */
3064#define ARIZONA_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */
3065#define ARIZONA_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */
3066#define ARIZONA_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */
3067#define ARIZONA_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */
3068
3069/*
3070 * R1306 (0x51A) - AIF1 Rx Enables
3071 */
3072#define ARIZONA_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */
3073#define ARIZONA_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */
3074#define ARIZONA_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */
3075#define ARIZONA_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */
3076#define ARIZONA_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */
3077#define ARIZONA_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */
3078#define ARIZONA_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */
3079#define ARIZONA_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */
3080#define ARIZONA_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */
3081#define ARIZONA_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */
3082#define ARIZONA_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */
3083#define ARIZONA_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */
3084#define ARIZONA_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */
3085#define ARIZONA_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */
3086#define ARIZONA_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */
3087#define ARIZONA_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */
3088#define ARIZONA_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */
3089#define ARIZONA_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */
3090#define ARIZONA_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */
3091#define ARIZONA_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */
3092#define ARIZONA_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */
3093#define ARIZONA_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */
3094#define ARIZONA_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */
3095#define ARIZONA_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */
3096#define ARIZONA_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */
3097#define ARIZONA_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */
3098#define ARIZONA_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */
3099#define ARIZONA_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */
3100#define ARIZONA_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */
3101#define ARIZONA_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */
3102#define ARIZONA_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */
3103#define ARIZONA_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */
3104
3105/*
3106 * R1307 (0x51B) - AIF1 Force Write
3107 */
3108#define ARIZONA_AIF1_FRC_WR 0x0001 /* AIF1_FRC_WR */
3109#define ARIZONA_AIF1_FRC_WR_MASK 0x0001 /* AIF1_FRC_WR */
3110#define ARIZONA_AIF1_FRC_WR_SHIFT 0 /* AIF1_FRC_WR */
3111#define ARIZONA_AIF1_FRC_WR_WIDTH 1 /* AIF1_FRC_WR */
3112
3113/*
3114 * R1344 (0x540) - AIF2 BCLK Ctrl
3115 */
3116#define ARIZONA_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */
3117#define ARIZONA_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */
3118#define ARIZONA_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */
3119#define ARIZONA_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
3120#define ARIZONA_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */
3121#define ARIZONA_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */
3122#define ARIZONA_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */
3123#define ARIZONA_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */
3124#define ARIZONA_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */
3125#define ARIZONA_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */
3126#define ARIZONA_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */
3127#define ARIZONA_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */
3128#define ARIZONA_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */
3129#define ARIZONA_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */
3130#define ARIZONA_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */
3131
3132/*
3133 * R1345 (0x541) - AIF2 Tx Pin Ctrl
3134 */
3135#define ARIZONA_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */
3136#define ARIZONA_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */
3137#define ARIZONA_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */
3138#define ARIZONA_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */
3139#define ARIZONA_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */
3140#define ARIZONA_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */
3141#define ARIZONA_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */
3142#define ARIZONA_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */
3143#define ARIZONA_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */
3144#define ARIZONA_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */
3145#define ARIZONA_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */
3146#define ARIZONA_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */
3147#define ARIZONA_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */
3148#define ARIZONA_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */
3149#define ARIZONA_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */
3150#define ARIZONA_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */
3151#define ARIZONA_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */
3152#define ARIZONA_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */
3153#define ARIZONA_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */
3154#define ARIZONA_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */
3155
3156/*
3157 * R1346 (0x542) - AIF2 Rx Pin Ctrl
3158 */
3159#define ARIZONA_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */
3160#define ARIZONA_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */
3161#define ARIZONA_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */
3162#define ARIZONA_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */
3163#define ARIZONA_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */
3164#define ARIZONA_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */
3165#define ARIZONA_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */
3166#define ARIZONA_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */
3167#define ARIZONA_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */
3168#define ARIZONA_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */
3169#define ARIZONA_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */
3170#define ARIZONA_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */
3171
3172/*
3173 * R1347 (0x543) - AIF2 Rate Ctrl
3174 */
3175#define ARIZONA_AIF2_RATE_MASK 0x7800 /* AIF2_RATE - [14:11] */
3176#define ARIZONA_AIF2_RATE_SHIFT 11 /* AIF2_RATE - [14:11] */
3177#define ARIZONA_AIF2_RATE_WIDTH 4 /* AIF2_RATE - [14:11] */
3178#define ARIZONA_AIF2_TRI 0x0040 /* AIF2_TRI */
3179#define ARIZONA_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */
3180#define ARIZONA_AIF2_TRI_SHIFT 6 /* AIF2_TRI */
3181#define ARIZONA_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
3182
3183/*
3184 * R1348 (0x544) - AIF2 Format
3185 */
3186#define ARIZONA_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */
3187#define ARIZONA_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */
3188#define ARIZONA_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */
3189
3190/*
3191 * R1349 (0x545) - AIF2 Tx BCLK Rate
3192 */
3193#define ARIZONA_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */
3194#define ARIZONA_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */
3195#define ARIZONA_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */
3196
3197/*
3198 * R1350 (0x546) - AIF2 Rx BCLK Rate
3199 */
3200#define ARIZONA_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */
3201#define ARIZONA_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */
3202#define ARIZONA_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */
3203
3204/*
3205 * R1351 (0x547) - AIF2 Frame Ctrl 1
3206 */
3207#define ARIZONA_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */
3208#define ARIZONA_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */
3209#define ARIZONA_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */
3210#define ARIZONA_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */
3211#define ARIZONA_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */
3212#define ARIZONA_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */
3213
3214/*
3215 * R1352 (0x548) - AIF2 Frame Ctrl 2
3216 */
3217#define ARIZONA_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */
3218#define ARIZONA_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */
3219#define ARIZONA_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */
3220#define ARIZONA_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */
3221#define ARIZONA_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */
3222#define ARIZONA_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */
3223
3224/*
3225 * R1353 (0x549) - AIF2 Frame Ctrl 3
3226 */
3227#define ARIZONA_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */
3228#define ARIZONA_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */
3229#define ARIZONA_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */
3230
3231/*
3232 * R1354 (0x54A) - AIF2 Frame Ctrl 4
3233 */
3234#define ARIZONA_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */
3235#define ARIZONA_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */
3236#define ARIZONA_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */
3237
3238/*
3239 * R1361 (0x551) - AIF2 Frame Ctrl 11
3240 */
3241#define ARIZONA_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */
3242#define ARIZONA_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */
3243#define ARIZONA_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */
3244
3245/*
3246 * R1362 (0x552) - AIF2 Frame Ctrl 12
3247 */
3248#define ARIZONA_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */
3249#define ARIZONA_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */
3250#define ARIZONA_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */
3251
3252/*
3253 * R1369 (0x559) - AIF2 Tx Enables
3254 */
3255#define ARIZONA_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */
3256#define ARIZONA_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */
3257#define ARIZONA_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */
3258#define ARIZONA_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */
3259#define ARIZONA_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */
3260#define ARIZONA_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */
3261#define ARIZONA_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */
3262#define ARIZONA_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */
3263
3264/*
3265 * R1370 (0x55A) - AIF2 Rx Enables
3266 */
3267#define ARIZONA_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */
3268#define ARIZONA_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */
3269#define ARIZONA_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */
3270#define ARIZONA_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */
3271#define ARIZONA_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */
3272#define ARIZONA_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */
3273#define ARIZONA_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */
3274#define ARIZONA_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */
3275
3276/*
3277 * R1371 (0x55B) - AIF2 Force Write
3278 */
3279#define ARIZONA_AIF2_FRC_WR 0x0001 /* AIF2_FRC_WR */
3280#define ARIZONA_AIF2_FRC_WR_MASK 0x0001 /* AIF2_FRC_WR */
3281#define ARIZONA_AIF2_FRC_WR_SHIFT 0 /* AIF2_FRC_WR */
3282#define ARIZONA_AIF2_FRC_WR_WIDTH 1 /* AIF2_FRC_WR */
3283
3284/*
3285 * R1408 (0x580) - AIF3 BCLK Ctrl
3286 */
3287#define ARIZONA_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */
3288#define ARIZONA_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */
3289#define ARIZONA_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */
3290#define ARIZONA_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */
3291#define ARIZONA_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */
3292#define ARIZONA_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */
3293#define ARIZONA_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */
3294#define ARIZONA_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */
3295#define ARIZONA_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */
3296#define ARIZONA_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */
3297#define ARIZONA_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */
3298#define ARIZONA_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */
3299#define ARIZONA_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */
3300#define ARIZONA_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */
3301#define ARIZONA_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */
3302
3303/*
3304 * R1409 (0x581) - AIF3 Tx Pin Ctrl
3305 */
3306#define ARIZONA_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */
3307#define ARIZONA_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */
3308#define ARIZONA_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */
3309#define ARIZONA_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */
3310#define ARIZONA_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */
3311#define ARIZONA_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */
3312#define ARIZONA_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */
3313#define ARIZONA_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */
3314#define ARIZONA_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */
3315#define ARIZONA_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */
3316#define ARIZONA_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */
3317#define ARIZONA_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */
3318#define ARIZONA_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */
3319#define ARIZONA_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */
3320#define ARIZONA_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */
3321#define ARIZONA_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */
3322#define ARIZONA_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */
3323#define ARIZONA_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */
3324#define ARIZONA_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */
3325#define ARIZONA_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */
3326
3327/*
3328 * R1410 (0x582) - AIF3 Rx Pin Ctrl
3329 */
3330#define ARIZONA_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */
3331#define ARIZONA_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */
3332#define ARIZONA_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */
3333#define ARIZONA_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */
3334#define ARIZONA_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */
3335#define ARIZONA_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */
3336#define ARIZONA_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */
3337#define ARIZONA_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */
3338#define ARIZONA_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */
3339#define ARIZONA_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */
3340#define ARIZONA_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */
3341#define ARIZONA_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */
3342
3343/*
3344 * R1411 (0x583) - AIF3 Rate Ctrl
3345 */
3346#define ARIZONA_AIF3_RATE_MASK 0x7800 /* AIF3_RATE - [14:11] */
3347#define ARIZONA_AIF3_RATE_SHIFT 11 /* AIF3_RATE - [14:11] */
3348#define ARIZONA_AIF3_RATE_WIDTH 4 /* AIF3_RATE - [14:11] */
3349#define ARIZONA_AIF3_TRI 0x0040 /* AIF3_TRI */
3350#define ARIZONA_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */
3351#define ARIZONA_AIF3_TRI_SHIFT 6 /* AIF3_TRI */
3352#define ARIZONA_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
3353
3354/*
3355 * R1412 (0x584) - AIF3 Format
3356 */
3357#define ARIZONA_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */
3358#define ARIZONA_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */
3359#define ARIZONA_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */
3360
3361/*
3362 * R1413 (0x585) - AIF3 Tx BCLK Rate
3363 */
3364#define ARIZONA_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */
3365#define ARIZONA_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */
3366#define ARIZONA_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */
3367
3368/*
3369 * R1414 (0x586) - AIF3 Rx BCLK Rate
3370 */
3371#define ARIZONA_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */
3372#define ARIZONA_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */
3373#define ARIZONA_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */
3374
3375/*
3376 * R1415 (0x587) - AIF3 Frame Ctrl 1
3377 */
3378#define ARIZONA_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */
3379#define ARIZONA_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */
3380#define ARIZONA_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */
3381#define ARIZONA_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */
3382#define ARIZONA_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */
3383#define ARIZONA_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */
3384
3385/*
3386 * R1416 (0x588) - AIF3 Frame Ctrl 2
3387 */
3388#define ARIZONA_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */
3389#define ARIZONA_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */
3390#define ARIZONA_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */
3391#define ARIZONA_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */
3392#define ARIZONA_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */
3393#define ARIZONA_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */
3394
3395/*
3396 * R1417 (0x589) - AIF3 Frame Ctrl 3
3397 */
3398#define ARIZONA_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */
3399#define ARIZONA_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */
3400#define ARIZONA_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */
3401
3402/*
3403 * R1418 (0x58A) - AIF3 Frame Ctrl 4
3404 */
3405#define ARIZONA_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */
3406#define ARIZONA_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */
3407#define ARIZONA_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */
3408
3409/*
3410 * R1425 (0x591) - AIF3 Frame Ctrl 11
3411 */
3412#define ARIZONA_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */
3413#define ARIZONA_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */
3414#define ARIZONA_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */
3415
3416/*
3417 * R1426 (0x592) - AIF3 Frame Ctrl 12
3418 */
3419#define ARIZONA_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */
3420#define ARIZONA_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */
3421#define ARIZONA_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */
3422
3423/*
3424 * R1433 (0x599) - AIF3 Tx Enables
3425 */
3426#define ARIZONA_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */
3427#define ARIZONA_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */
3428#define ARIZONA_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */
3429#define ARIZONA_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */
3430#define ARIZONA_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */
3431#define ARIZONA_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */
3432#define ARIZONA_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */
3433#define ARIZONA_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */
3434
3435/*
3436 * R1434 (0x59A) - AIF3 Rx Enables
3437 */
3438#define ARIZONA_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */
3439#define ARIZONA_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */
3440#define ARIZONA_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */
3441#define ARIZONA_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */
3442#define ARIZONA_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */
3443#define ARIZONA_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */
3444#define ARIZONA_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */
3445#define ARIZONA_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */
3446
3447/*
3448 * R1435 (0x59B) - AIF3 Force Write
3449 */
3450#define ARIZONA_AIF3_FRC_WR 0x0001 /* AIF3_FRC_WR */
3451#define ARIZONA_AIF3_FRC_WR_MASK 0x0001 /* AIF3_FRC_WR */
3452#define ARIZONA_AIF3_FRC_WR_SHIFT 0 /* AIF3_FRC_WR */
3453#define ARIZONA_AIF3_FRC_WR_WIDTH 1 /* AIF3_FRC_WR */
3454
3455/*
3456 * R1507 (0x5E3) - SLIMbus Framer Ref Gear
3457 */
3458#define ARIZONA_SLIMCLK_SRC 0x0010 /* SLIMCLK_SRC */
3459#define ARIZONA_SLIMCLK_SRC_MASK 0x0010 /* SLIMCLK_SRC */
3460#define ARIZONA_SLIMCLK_SRC_SHIFT 4 /* SLIMCLK_SRC */
3461#define ARIZONA_SLIMCLK_SRC_WIDTH 1 /* SLIMCLK_SRC */
3462#define ARIZONA_FRAMER_REF_GEAR_MASK 0x000F /* FRAMER_REF_GEAR - [3:0] */
3463#define ARIZONA_FRAMER_REF_GEAR_SHIFT 0 /* FRAMER_REF_GEAR - [3:0] */
3464#define ARIZONA_FRAMER_REF_GEAR_WIDTH 4 /* FRAMER_REF_GEAR - [3:0] */
3465
3466/*
3467 * R1509 (0x5E5) - SLIMbus Rates 1
3468 */
3469#define ARIZONA_SLIMRX2_RATE_MASK 0x7800 /* SLIMRX2_RATE - [14:11] */
3470#define ARIZONA_SLIMRX2_RATE_SHIFT 11 /* SLIMRX2_RATE - [14:11] */
3471#define ARIZONA_SLIMRX2_RATE_WIDTH 4 /* SLIMRX2_RATE - [14:11] */
3472#define ARIZONA_SLIMRX1_RATE_MASK 0x0078 /* SLIMRX1_RATE - [6:3] */
3473#define ARIZONA_SLIMRX1_RATE_SHIFT 3 /* SLIMRX1_RATE - [6:3] */
3474#define ARIZONA_SLIMRX1_RATE_WIDTH 4 /* SLIMRX1_RATE - [6:3] */
3475
3476/*
3477 * R1510 (0x5E6) - SLIMbus Rates 2
3478 */
3479#define ARIZONA_SLIMRX4_RATE_MASK 0x7800 /* SLIMRX4_RATE - [14:11] */
3480#define ARIZONA_SLIMRX4_RATE_SHIFT 11 /* SLIMRX4_RATE - [14:11] */
3481#define ARIZONA_SLIMRX4_RATE_WIDTH 4 /* SLIMRX4_RATE - [14:11] */
3482#define ARIZONA_SLIMRX3_RATE_MASK 0x0078 /* SLIMRX3_RATE - [6:3] */
3483#define ARIZONA_SLIMRX3_RATE_SHIFT 3 /* SLIMRX3_RATE - [6:3] */
3484#define ARIZONA_SLIMRX3_RATE_WIDTH 4 /* SLIMRX3_RATE - [6:3] */
3485
3486/*
3487 * R1511 (0x5E7) - SLIMbus Rates 3
3488 */
3489#define ARIZONA_SLIMRX6_RATE_MASK 0x7800 /* SLIMRX6_RATE - [14:11] */
3490#define ARIZONA_SLIMRX6_RATE_SHIFT 11 /* SLIMRX6_RATE - [14:11] */
3491#define ARIZONA_SLIMRX6_RATE_WIDTH 4 /* SLIMRX6_RATE - [14:11] */
3492#define ARIZONA_SLIMRX5_RATE_MASK 0x0078 /* SLIMRX5_RATE - [6:3] */
3493#define ARIZONA_SLIMRX5_RATE_SHIFT 3 /* SLIMRX5_RATE - [6:3] */
3494#define ARIZONA_SLIMRX5_RATE_WIDTH 4 /* SLIMRX5_RATE - [6:3] */
3495
3496/*
3497 * R1512 (0x5E8) - SLIMbus Rates 4
3498 */
3499#define ARIZONA_SLIMRX8_RATE_MASK 0x7800 /* SLIMRX8_RATE - [14:11] */
3500#define ARIZONA_SLIMRX8_RATE_SHIFT 11 /* SLIMRX8_RATE - [14:11] */
3501#define ARIZONA_SLIMRX8_RATE_WIDTH 4 /* SLIMRX8_RATE - [14:11] */
3502#define ARIZONA_SLIMRX7_RATE_MASK 0x0078 /* SLIMRX7_RATE - [6:3] */
3503#define ARIZONA_SLIMRX7_RATE_SHIFT 3 /* SLIMRX7_RATE - [6:3] */
3504#define ARIZONA_SLIMRX7_RATE_WIDTH 4 /* SLIMRX7_RATE - [6:3] */
3505
3506/*
3507 * R1513 (0x5E9) - SLIMbus Rates 5
3508 */
3509#define ARIZONA_SLIMTX2_RATE_MASK 0x7800 /* SLIMTX2_RATE - [14:11] */
3510#define ARIZONA_SLIMTX2_RATE_SHIFT 11 /* SLIMTX2_RATE - [14:11] */
3511#define ARIZONA_SLIMTX2_RATE_WIDTH 4 /* SLIMTX2_RATE - [14:11] */
3512#define ARIZONA_SLIMTX1_RATE_MASK 0x0078 /* SLIMTX1_RATE - [6:3] */
3513#define ARIZONA_SLIMTX1_RATE_SHIFT 3 /* SLIMTX1_RATE - [6:3] */
3514#define ARIZONA_SLIMTX1_RATE_WIDTH 4 /* SLIMTX1_RATE - [6:3] */
3515
3516/*
3517 * R1514 (0x5EA) - SLIMbus Rates 6
3518 */
3519#define ARIZONA_SLIMTX4_RATE_MASK 0x7800 /* SLIMTX4_RATE - [14:11] */
3520#define ARIZONA_SLIMTX4_RATE_SHIFT 11 /* SLIMTX4_RATE - [14:11] */
3521#define ARIZONA_SLIMTX4_RATE_WIDTH 4 /* SLIMTX4_RATE - [14:11] */
3522#define ARIZONA_SLIMTX3_RATE_MASK 0x0078 /* SLIMTX3_RATE - [6:3] */
3523#define ARIZONA_SLIMTX3_RATE_SHIFT 3 /* SLIMTX3_RATE - [6:3] */
3524#define ARIZONA_SLIMTX3_RATE_WIDTH 4 /* SLIMTX3_RATE - [6:3] */
3525
3526/*
3527 * R1515 (0x5EB) - SLIMbus Rates 7
3528 */
3529#define ARIZONA_SLIMTX6_RATE_MASK 0x7800 /* SLIMTX6_RATE - [14:11] */
3530#define ARIZONA_SLIMTX6_RATE_SHIFT 11 /* SLIMTX6_RATE - [14:11] */
3531#define ARIZONA_SLIMTX6_RATE_WIDTH 4 /* SLIMTX6_RATE - [14:11] */
3532#define ARIZONA_SLIMTX5_RATE_MASK 0x0078 /* SLIMTX5_RATE - [6:3] */
3533#define ARIZONA_SLIMTX5_RATE_SHIFT 3 /* SLIMTX5_RATE - [6:3] */
3534#define ARIZONA_SLIMTX5_RATE_WIDTH 4 /* SLIMTX5_RATE - [6:3] */
3535
3536/*
3537 * R1516 (0x5EC) - SLIMbus Rates 8
3538 */
3539#define ARIZONA_SLIMTX8_RATE_MASK 0x7800 /* SLIMTX8_RATE - [14:11] */
3540#define ARIZONA_SLIMTX8_RATE_SHIFT 11 /* SLIMTX8_RATE - [14:11] */
3541#define ARIZONA_SLIMTX8_RATE_WIDTH 4 /* SLIMTX8_RATE - [14:11] */
3542#define ARIZONA_SLIMTX7_RATE_MASK 0x0078 /* SLIMTX7_RATE - [6:3] */
3543#define ARIZONA_SLIMTX7_RATE_SHIFT 3 /* SLIMTX7_RATE - [6:3] */
3544#define ARIZONA_SLIMTX7_RATE_WIDTH 4 /* SLIMTX7_RATE - [6:3] */
3545
3546/*
3547 * R1525 (0x5F5) - SLIMbus RX Channel Enable
3548 */
3549#define ARIZONA_SLIMRX8_ENA 0x0080 /* SLIMRX8_ENA */
3550#define ARIZONA_SLIMRX8_ENA_MASK 0x0080 /* SLIMRX8_ENA */
3551#define ARIZONA_SLIMRX8_ENA_SHIFT 7 /* SLIMRX8_ENA */
3552#define ARIZONA_SLIMRX8_ENA_WIDTH 1 /* SLIMRX8_ENA */
3553#define ARIZONA_SLIMRX7_ENA 0x0040 /* SLIMRX7_ENA */
3554#define ARIZONA_SLIMRX7_ENA_MASK 0x0040 /* SLIMRX7_ENA */
3555#define ARIZONA_SLIMRX7_ENA_SHIFT 6 /* SLIMRX7_ENA */
3556#define ARIZONA_SLIMRX7_ENA_WIDTH 1 /* SLIMRX7_ENA */
3557#define ARIZONA_SLIMRX6_ENA 0x0020 /* SLIMRX6_ENA */
3558#define ARIZONA_SLIMRX6_ENA_MASK 0x0020 /* SLIMRX6_ENA */
3559#define ARIZONA_SLIMRX6_ENA_SHIFT 5 /* SLIMRX6_ENA */
3560#define ARIZONA_SLIMRX6_ENA_WIDTH 1 /* SLIMRX6_ENA */
3561#define ARIZONA_SLIMRX5_ENA 0x0010 /* SLIMRX5_ENA */
3562#define ARIZONA_SLIMRX5_ENA_MASK 0x0010 /* SLIMRX5_ENA */
3563#define ARIZONA_SLIMRX5_ENA_SHIFT 4 /* SLIMRX5_ENA */
3564#define ARIZONA_SLIMRX5_ENA_WIDTH 1 /* SLIMRX5_ENA */
3565#define ARIZONA_SLIMRX4_ENA 0x0008 /* SLIMRX4_ENA */
3566#define ARIZONA_SLIMRX4_ENA_MASK 0x0008 /* SLIMRX4_ENA */
3567#define ARIZONA_SLIMRX4_ENA_SHIFT 3 /* SLIMRX4_ENA */
3568#define ARIZONA_SLIMRX4_ENA_WIDTH 1 /* SLIMRX4_ENA */
3569#define ARIZONA_SLIMRX3_ENA 0x0004 /* SLIMRX3_ENA */
3570#define ARIZONA_SLIMRX3_ENA_MASK 0x0004 /* SLIMRX3_ENA */
3571#define ARIZONA_SLIMRX3_ENA_SHIFT 2 /* SLIMRX3_ENA */
3572#define ARIZONA_SLIMRX3_ENA_WIDTH 1 /* SLIMRX3_ENA */
3573#define ARIZONA_SLIMRX2_ENA 0x0002 /* SLIMRX2_ENA */
3574#define ARIZONA_SLIMRX2_ENA_MASK 0x0002 /* SLIMRX2_ENA */
3575#define ARIZONA_SLIMRX2_ENA_SHIFT 1 /* SLIMRX2_ENA */
3576#define ARIZONA_SLIMRX2_ENA_WIDTH 1 /* SLIMRX2_ENA */
3577#define ARIZONA_SLIMRX1_ENA 0x0001 /* SLIMRX1_ENA */
3578#define ARIZONA_SLIMRX1_ENA_MASK 0x0001 /* SLIMRX1_ENA */
3579#define ARIZONA_SLIMRX1_ENA_SHIFT 0 /* SLIMRX1_ENA */
3580#define ARIZONA_SLIMRX1_ENA_WIDTH 1 /* SLIMRX1_ENA */
3581
3582/*
3583 * R1526 (0x5F6) - SLIMbus TX Channel Enable
3584 */
3585#define ARIZONA_SLIMTX8_ENA 0x0080 /* SLIMTX8_ENA */
3586#define ARIZONA_SLIMTX8_ENA_MASK 0x0080 /* SLIMTX8_ENA */
3587#define ARIZONA_SLIMTX8_ENA_SHIFT 7 /* SLIMTX8_ENA */
3588#define ARIZONA_SLIMTX8_ENA_WIDTH 1 /* SLIMTX8_ENA */
3589#define ARIZONA_SLIMTX7_ENA 0x0040 /* SLIMTX7_ENA */
3590#define ARIZONA_SLIMTX7_ENA_MASK 0x0040 /* SLIMTX7_ENA */
3591#define ARIZONA_SLIMTX7_ENA_SHIFT 6 /* SLIMTX7_ENA */
3592#define ARIZONA_SLIMTX7_ENA_WIDTH 1 /* SLIMTX7_ENA */
3593#define ARIZONA_SLIMTX6_ENA 0x0020 /* SLIMTX6_ENA */
3594#define ARIZONA_SLIMTX6_ENA_MASK 0x0020 /* SLIMTX6_ENA */
3595#define ARIZONA_SLIMTX6_ENA_SHIFT 5 /* SLIMTX6_ENA */
3596#define ARIZONA_SLIMTX6_ENA_WIDTH 1 /* SLIMTX6_ENA */
3597#define ARIZONA_SLIMTX5_ENA 0x0010 /* SLIMTX5_ENA */
3598#define ARIZONA_SLIMTX5_ENA_MASK 0x0010 /* SLIMTX5_ENA */
3599#define ARIZONA_SLIMTX5_ENA_SHIFT 4 /* SLIMTX5_ENA */
3600#define ARIZONA_SLIMTX5_ENA_WIDTH 1 /* SLIMTX5_ENA */
3601#define ARIZONA_SLIMTX4_ENA 0x0008 /* SLIMTX4_ENA */
3602#define ARIZONA_SLIMTX4_ENA_MASK 0x0008 /* SLIMTX4_ENA */
3603#define ARIZONA_SLIMTX4_ENA_SHIFT 3 /* SLIMTX4_ENA */
3604#define ARIZONA_SLIMTX4_ENA_WIDTH 1 /* SLIMTX4_ENA */
3605#define ARIZONA_SLIMTX3_ENA 0x0004 /* SLIMTX3_ENA */
3606#define ARIZONA_SLIMTX3_ENA_MASK 0x0004 /* SLIMTX3_ENA */
3607#define ARIZONA_SLIMTX3_ENA_SHIFT 2 /* SLIMTX3_ENA */
3608#define ARIZONA_SLIMTX3_ENA_WIDTH 1 /* SLIMTX3_ENA */
3609#define ARIZONA_SLIMTX2_ENA 0x0002 /* SLIMTX2_ENA */
3610#define ARIZONA_SLIMTX2_ENA_MASK 0x0002 /* SLIMTX2_ENA */
3611#define ARIZONA_SLIMTX2_ENA_SHIFT 1 /* SLIMTX2_ENA */
3612#define ARIZONA_SLIMTX2_ENA_WIDTH 1 /* SLIMTX2_ENA */
3613#define ARIZONA_SLIMTX1_ENA 0x0001 /* SLIMTX1_ENA */
3614#define ARIZONA_SLIMTX1_ENA_MASK 0x0001 /* SLIMTX1_ENA */
3615#define ARIZONA_SLIMTX1_ENA_SHIFT 0 /* SLIMTX1_ENA */
3616#define ARIZONA_SLIMTX1_ENA_WIDTH 1 /* SLIMTX1_ENA */
3617
3618/*
3619 * R1527 (0x5F7) - SLIMbus RX Port Status
3620 */
3621#define ARIZONA_SLIMRX8_PORT_STS 0x0080 /* SLIMRX8_PORT_STS */
3622#define ARIZONA_SLIMRX8_PORT_STS_MASK 0x0080 /* SLIMRX8_PORT_STS */
3623#define ARIZONA_SLIMRX8_PORT_STS_SHIFT 7 /* SLIMRX8_PORT_STS */
3624#define ARIZONA_SLIMRX8_PORT_STS_WIDTH 1 /* SLIMRX8_PORT_STS */
3625#define ARIZONA_SLIMRX7_PORT_STS 0x0040 /* SLIMRX7_PORT_STS */
3626#define ARIZONA_SLIMRX7_PORT_STS_MASK 0x0040 /* SLIMRX7_PORT_STS */
3627#define ARIZONA_SLIMRX7_PORT_STS_SHIFT 6 /* SLIMRX7_PORT_STS */
3628#define ARIZONA_SLIMRX7_PORT_STS_WIDTH 1 /* SLIMRX7_PORT_STS */
3629#define ARIZONA_SLIMRX6_PORT_STS 0x0020 /* SLIMRX6_PORT_STS */
3630#define ARIZONA_SLIMRX6_PORT_STS_MASK 0x0020 /* SLIMRX6_PORT_STS */
3631#define ARIZONA_SLIMRX6_PORT_STS_SHIFT 5 /* SLIMRX6_PORT_STS */
3632#define ARIZONA_SLIMRX6_PORT_STS_WIDTH 1 /* SLIMRX6_PORT_STS */
3633#define ARIZONA_SLIMRX5_PORT_STS 0x0010 /* SLIMRX5_PORT_STS */
3634#define ARIZONA_SLIMRX5_PORT_STS_MASK 0x0010 /* SLIMRX5_PORT_STS */
3635#define ARIZONA_SLIMRX5_PORT_STS_SHIFT 4 /* SLIMRX5_PORT_STS */
3636#define ARIZONA_SLIMRX5_PORT_STS_WIDTH 1 /* SLIMRX5_PORT_STS */
3637#define ARIZONA_SLIMRX4_PORT_STS 0x0008 /* SLIMRX4_PORT_STS */
3638#define ARIZONA_SLIMRX4_PORT_STS_MASK 0x0008 /* SLIMRX4_PORT_STS */
3639#define ARIZONA_SLIMRX4_PORT_STS_SHIFT 3 /* SLIMRX4_PORT_STS */
3640#define ARIZONA_SLIMRX4_PORT_STS_WIDTH 1 /* SLIMRX4_PORT_STS */
3641#define ARIZONA_SLIMRX3_PORT_STS 0x0004 /* SLIMRX3_PORT_STS */
3642#define ARIZONA_SLIMRX3_PORT_STS_MASK 0x0004 /* SLIMRX3_PORT_STS */
3643#define ARIZONA_SLIMRX3_PORT_STS_SHIFT 2 /* SLIMRX3_PORT_STS */
3644#define ARIZONA_SLIMRX3_PORT_STS_WIDTH 1 /* SLIMRX3_PORT_STS */
3645#define ARIZONA_SLIMRX2_PORT_STS 0x0002 /* SLIMRX2_PORT_STS */
3646#define ARIZONA_SLIMRX2_PORT_STS_MASK 0x0002 /* SLIMRX2_PORT_STS */
3647#define ARIZONA_SLIMRX2_PORT_STS_SHIFT 1 /* SLIMRX2_PORT_STS */
3648#define ARIZONA_SLIMRX2_PORT_STS_WIDTH 1 /* SLIMRX2_PORT_STS */
3649#define ARIZONA_SLIMRX1_PORT_STS 0x0001 /* SLIMRX1_PORT_STS */
3650#define ARIZONA_SLIMRX1_PORT_STS_MASK 0x0001 /* SLIMRX1_PORT_STS */
3651#define ARIZONA_SLIMRX1_PORT_STS_SHIFT 0 /* SLIMRX1_PORT_STS */
3652#define ARIZONA_SLIMRX1_PORT_STS_WIDTH 1 /* SLIMRX1_PORT_STS */
3653
3654/*
3655 * R1528 (0x5F8) - SLIMbus TX Port Status
3656 */
3657#define ARIZONA_SLIMTX8_PORT_STS 0x0080 /* SLIMTX8_PORT_STS */
3658#define ARIZONA_SLIMTX8_PORT_STS_MASK 0x0080 /* SLIMTX8_PORT_STS */
3659#define ARIZONA_SLIMTX8_PORT_STS_SHIFT 7 /* SLIMTX8_PORT_STS */
3660#define ARIZONA_SLIMTX8_PORT_STS_WIDTH 1 /* SLIMTX8_PORT_STS */
3661#define ARIZONA_SLIMTX7_PORT_STS 0x0040 /* SLIMTX7_PORT_STS */
3662#define ARIZONA_SLIMTX7_PORT_STS_MASK 0x0040 /* SLIMTX7_PORT_STS */
3663#define ARIZONA_SLIMTX7_PORT_STS_SHIFT 6 /* SLIMTX7_PORT_STS */
3664#define ARIZONA_SLIMTX7_PORT_STS_WIDTH 1 /* SLIMTX7_PORT_STS */
3665#define ARIZONA_SLIMTX6_PORT_STS 0x0020 /* SLIMTX6_PORT_STS */
3666#define ARIZONA_SLIMTX6_PORT_STS_MASK 0x0020 /* SLIMTX6_PORT_STS */
3667#define ARIZONA_SLIMTX6_PORT_STS_SHIFT 5 /* SLIMTX6_PORT_STS */
3668#define ARIZONA_SLIMTX6_PORT_STS_WIDTH 1 /* SLIMTX6_PORT_STS */
3669#define ARIZONA_SLIMTX5_PORT_STS 0x0010 /* SLIMTX5_PORT_STS */
3670#define ARIZONA_SLIMTX5_PORT_STS_MASK 0x0010 /* SLIMTX5_PORT_STS */
3671#define ARIZONA_SLIMTX5_PORT_STS_SHIFT 4 /* SLIMTX5_PORT_STS */
3672#define ARIZONA_SLIMTX5_PORT_STS_WIDTH 1 /* SLIMTX5_PORT_STS */
3673#define ARIZONA_SLIMTX4_PORT_STS 0x0008 /* SLIMTX4_PORT_STS */
3674#define ARIZONA_SLIMTX4_PORT_STS_MASK 0x0008 /* SLIMTX4_PORT_STS */
3675#define ARIZONA_SLIMTX4_PORT_STS_SHIFT 3 /* SLIMTX4_PORT_STS */
3676#define ARIZONA_SLIMTX4_PORT_STS_WIDTH 1 /* SLIMTX4_PORT_STS */
3677#define ARIZONA_SLIMTX3_PORT_STS 0x0004 /* SLIMTX3_PORT_STS */
3678#define ARIZONA_SLIMTX3_PORT_STS_MASK 0x0004 /* SLIMTX3_PORT_STS */
3679#define ARIZONA_SLIMTX3_PORT_STS_SHIFT 2 /* SLIMTX3_PORT_STS */
3680#define ARIZONA_SLIMTX3_PORT_STS_WIDTH 1 /* SLIMTX3_PORT_STS */
3681#define ARIZONA_SLIMTX2_PORT_STS 0x0002 /* SLIMTX2_PORT_STS */
3682#define ARIZONA_SLIMTX2_PORT_STS_MASK 0x0002 /* SLIMTX2_PORT_STS */
3683#define ARIZONA_SLIMTX2_PORT_STS_SHIFT 1 /* SLIMTX2_PORT_STS */
3684#define ARIZONA_SLIMTX2_PORT_STS_WIDTH 1 /* SLIMTX2_PORT_STS */
3685#define ARIZONA_SLIMTX1_PORT_STS 0x0001 /* SLIMTX1_PORT_STS */
3686#define ARIZONA_SLIMTX1_PORT_STS_MASK 0x0001 /* SLIMTX1_PORT_STS */
3687#define ARIZONA_SLIMTX1_PORT_STS_SHIFT 0 /* SLIMTX1_PORT_STS */
3688#define ARIZONA_SLIMTX1_PORT_STS_WIDTH 1 /* SLIMTX1_PORT_STS */
3689
3690/*
3691 * R3087 (0xC0F) - IRQ CTRL 1
3692 */
3693#define ARIZONA_IRQ_POL 0x0400 /* IRQ_POL */
3694#define ARIZONA_IRQ_POL_MASK 0x0400 /* IRQ_POL */
3695#define ARIZONA_IRQ_POL_SHIFT 10 /* IRQ_POL */
3696#define ARIZONA_IRQ_POL_WIDTH 1 /* IRQ_POL */
3697#define ARIZONA_IRQ_OP_CFG 0x0200 /* IRQ_OP_CFG */
3698#define ARIZONA_IRQ_OP_CFG_MASK 0x0200 /* IRQ_OP_CFG */
3699#define ARIZONA_IRQ_OP_CFG_SHIFT 9 /* IRQ_OP_CFG */
3700#define ARIZONA_IRQ_OP_CFG_WIDTH 1 /* IRQ_OP_CFG */
3701
3702/*
3703 * R3088 (0xC10) - GPIO Debounce Config
3704 */
3705#define ARIZONA_GP_DBTIME_MASK 0xF000 /* GP_DBTIME - [15:12] */
3706#define ARIZONA_GP_DBTIME_SHIFT 12 /* GP_DBTIME - [15:12] */
3707#define ARIZONA_GP_DBTIME_WIDTH 4 /* GP_DBTIME - [15:12] */
3708
3709/*
3710 * R3104 (0xC20) - Misc Pad Ctrl 1
3711 */
3712#define ARIZONA_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */
3713#define ARIZONA_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */
3714#define ARIZONA_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */
3715#define ARIZONA_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
3716#define ARIZONA_MCLK2_PD 0x2000 /* MCLK2_PD */
3717#define ARIZONA_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */
3718#define ARIZONA_MCLK2_PD_SHIFT 13 /* MCLK2_PD */
3719#define ARIZONA_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
3720#define ARIZONA_RSTB_PU 0x0002 /* RSTB_PU */
3721#define ARIZONA_RSTB_PU_MASK 0x0002 /* RSTB_PU */
3722#define ARIZONA_RSTB_PU_SHIFT 1 /* RSTB_PU */
3723#define ARIZONA_RSTB_PU_WIDTH 1 /* RSTB_PU */
3724
3725/*
3726 * R3105 (0xC21) - Misc Pad Ctrl 2
3727 */
3728#define ARIZONA_MCLK1_PD 0x1000 /* MCLK1_PD */
3729#define ARIZONA_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */
3730#define ARIZONA_MCLK1_PD_SHIFT 12 /* MCLK1_PD */
3731#define ARIZONA_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
3732#define ARIZONA_MICD_PD 0x0100 /* MICD_PD */
3733#define ARIZONA_MICD_PD_MASK 0x0100 /* MICD_PD */
3734#define ARIZONA_MICD_PD_SHIFT 8 /* MICD_PD */
3735#define ARIZONA_MICD_PD_WIDTH 1 /* MICD_PD */
3736#define ARIZONA_ADDR_PD 0x0001 /* ADDR_PD */
3737#define ARIZONA_ADDR_PD_MASK 0x0001 /* ADDR_PD */
3738#define ARIZONA_ADDR_PD_SHIFT 0 /* ADDR_PD */
3739#define ARIZONA_ADDR_PD_WIDTH 1 /* ADDR_PD */
3740
3741/*
3742 * R3106 (0xC22) - Misc Pad Ctrl 3
3743 */
3744#define ARIZONA_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */
3745#define ARIZONA_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */
3746#define ARIZONA_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */
3747#define ARIZONA_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */
3748#define ARIZONA_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */
3749#define ARIZONA_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */
3750#define ARIZONA_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */
3751#define ARIZONA_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
3752#define ARIZONA_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */
3753#define ARIZONA_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */
3754#define ARIZONA_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */
3755#define ARIZONA_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
3756#define ARIZONA_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */
3757#define ARIZONA_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */
3758#define ARIZONA_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */
3759#define ARIZONA_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
3760
3761/*
3762 * R3107 (0xC23) - Misc Pad Ctrl 4
3763 */
3764#define ARIZONA_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */
3765#define ARIZONA_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */
3766#define ARIZONA_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */
3767#define ARIZONA_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */
3768#define ARIZONA_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */
3769#define ARIZONA_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */
3770#define ARIZONA_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */
3771#define ARIZONA_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */
3772#define ARIZONA_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */
3773#define ARIZONA_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */
3774#define ARIZONA_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */
3775#define ARIZONA_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */
3776#define ARIZONA_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */
3777#define ARIZONA_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */
3778#define ARIZONA_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */
3779#define ARIZONA_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */
3780#define ARIZONA_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */
3781#define ARIZONA_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */
3782#define ARIZONA_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */
3783#define ARIZONA_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */
3784#define ARIZONA_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */
3785#define ARIZONA_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */
3786#define ARIZONA_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */
3787#define ARIZONA_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */
3788
3789/*
3790 * R3108 (0xC24) - Misc Pad Ctrl 5
3791 */
3792#define ARIZONA_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */
3793#define ARIZONA_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */
3794#define ARIZONA_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */
3795#define ARIZONA_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */
3796#define ARIZONA_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */
3797#define ARIZONA_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */
3798#define ARIZONA_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */
3799#define ARIZONA_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */
3800#define ARIZONA_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */
3801#define ARIZONA_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */
3802#define ARIZONA_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */
3803#define ARIZONA_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */
3804#define ARIZONA_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */
3805#define ARIZONA_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */
3806#define ARIZONA_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */
3807#define ARIZONA_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */
3808#define ARIZONA_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */
3809#define ARIZONA_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */
3810#define ARIZONA_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */
3811#define ARIZONA_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */
3812#define ARIZONA_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */
3813#define ARIZONA_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */
3814#define ARIZONA_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */
3815#define ARIZONA_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */
3816
3817/*
3818 * R3109 (0xC25) - Misc Pad Ctrl 6
3819 */
3820#define ARIZONA_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */
3821#define ARIZONA_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */
3822#define ARIZONA_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */
3823#define ARIZONA_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */
3824#define ARIZONA_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */
3825#define ARIZONA_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */
3826#define ARIZONA_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */
3827#define ARIZONA_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */
3828#define ARIZONA_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */
3829#define ARIZONA_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */
3830#define ARIZONA_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */
3831#define ARIZONA_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */
3832#define ARIZONA_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */
3833#define ARIZONA_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */
3834#define ARIZONA_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */
3835#define ARIZONA_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */
3836#define ARIZONA_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */
3837#define ARIZONA_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */
3838#define ARIZONA_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */
3839#define ARIZONA_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */
3840#define ARIZONA_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */
3841#define ARIZONA_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */
3842#define ARIZONA_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */
3843#define ARIZONA_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */
3844
3845/*
3846 * R3328 (0xD00) - Interrupt Status 1
3847 */
3848#define ARIZONA_GP4_EINT1 0x0008 /* GP4_EINT1 */
3849#define ARIZONA_GP4_EINT1_MASK 0x0008 /* GP4_EINT1 */
3850#define ARIZONA_GP4_EINT1_SHIFT 3 /* GP4_EINT1 */
3851#define ARIZONA_GP4_EINT1_WIDTH 1 /* GP4_EINT1 */
3852#define ARIZONA_GP3_EINT1 0x0004 /* GP3_EINT1 */
3853#define ARIZONA_GP3_EINT1_MASK 0x0004 /* GP3_EINT1 */
3854#define ARIZONA_GP3_EINT1_SHIFT 2 /* GP3_EINT1 */
3855#define ARIZONA_GP3_EINT1_WIDTH 1 /* GP3_EINT1 */
3856#define ARIZONA_GP2_EINT1 0x0002 /* GP2_EINT1 */
3857#define ARIZONA_GP2_EINT1_MASK 0x0002 /* GP2_EINT1 */
3858#define ARIZONA_GP2_EINT1_SHIFT 1 /* GP2_EINT1 */
3859#define ARIZONA_GP2_EINT1_WIDTH 1 /* GP2_EINT1 */
3860#define ARIZONA_GP1_EINT1 0x0001 /* GP1_EINT1 */
3861#define ARIZONA_GP1_EINT1_MASK 0x0001 /* GP1_EINT1 */
3862#define ARIZONA_GP1_EINT1_SHIFT 0 /* GP1_EINT1 */
3863#define ARIZONA_GP1_EINT1_WIDTH 1 /* GP1_EINT1 */
3864
3865/*
3866 * R3329 (0xD01) - Interrupt Status 2
3867 */
3868#define ARIZONA_DSP1_RAM_RDY_EINT1 0x0100 /* DSP1_RAM_RDY_EINT1 */
3869#define ARIZONA_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* DSP1_RAM_RDY_EINT1 */
3870#define ARIZONA_DSP1_RAM_RDY_EINT1_SHIFT 8 /* DSP1_RAM_RDY_EINT1 */
3871#define ARIZONA_DSP1_RAM_RDY_EINT1_WIDTH 1 /* DSP1_RAM_RDY_EINT1 */
3872#define ARIZONA_DSP_IRQ2_EINT1 0x0002 /* DSP_IRQ2_EINT1 */
3873#define ARIZONA_DSP_IRQ2_EINT1_MASK 0x0002 /* DSP_IRQ2_EINT1 */
3874#define ARIZONA_DSP_IRQ2_EINT1_SHIFT 1 /* DSP_IRQ2_EINT1 */
3875#define ARIZONA_DSP_IRQ2_EINT1_WIDTH 1 /* DSP_IRQ2_EINT1 */
3876#define ARIZONA_DSP_IRQ1_EINT1 0x0001 /* DSP_IRQ1_EINT1 */
3877#define ARIZONA_DSP_IRQ1_EINT1_MASK 0x0001 /* DSP_IRQ1_EINT1 */
3878#define ARIZONA_DSP_IRQ1_EINT1_SHIFT 0 /* DSP_IRQ1_EINT1 */
3879#define ARIZONA_DSP_IRQ1_EINT1_WIDTH 1 /* DSP_IRQ1_EINT1 */
3880
3881/*
3882 * R3330 (0xD02) - Interrupt Status 3
3883 */
3884#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */
3885#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */
3886#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT1 */
3887#define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT1 */
3888#define ARIZONA_SPK_SHUTDOWN_EINT1 0x4000 /* SPK_SHUTDOWN_EINT1 */
3889#define ARIZONA_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* SPK_SHUTDOWN_EINT1 */
3890#define ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT 14 /* SPK_SHUTDOWN_EINT1 */
3891#define ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_EINT1 */
3892#define ARIZONA_HPDET_EINT1 0x2000 /* HPDET_EINT1 */
3893#define ARIZONA_HPDET_EINT1_MASK 0x2000 /* HPDET_EINT1 */
3894#define ARIZONA_HPDET_EINT1_SHIFT 13 /* HPDET_EINT1 */
3895#define ARIZONA_HPDET_EINT1_WIDTH 1 /* HPDET_EINT1 */
3896#define ARIZONA_MICDET_EINT1 0x1000 /* MICDET_EINT1 */
3897#define ARIZONA_MICDET_EINT1_MASK 0x1000 /* MICDET_EINT1 */
3898#define ARIZONA_MICDET_EINT1_SHIFT 12 /* MICDET_EINT1 */
3899#define ARIZONA_MICDET_EINT1_WIDTH 1 /* MICDET_EINT1 */
3900#define ARIZONA_WSEQ_DONE_EINT1 0x0800 /* WSEQ_DONE_EINT1 */
3901#define ARIZONA_WSEQ_DONE_EINT1_MASK 0x0800 /* WSEQ_DONE_EINT1 */
3902#define ARIZONA_WSEQ_DONE_EINT1_SHIFT 11 /* WSEQ_DONE_EINT1 */
3903#define ARIZONA_WSEQ_DONE_EINT1_WIDTH 1 /* WSEQ_DONE_EINT1 */
3904#define ARIZONA_DRC2_SIG_DET_EINT1 0x0400 /* DRC2_SIG_DET_EINT1 */
3905#define ARIZONA_DRC2_SIG_DET_EINT1_MASK 0x0400 /* DRC2_SIG_DET_EINT1 */
3906#define ARIZONA_DRC2_SIG_DET_EINT1_SHIFT 10 /* DRC2_SIG_DET_EINT1 */
3907#define ARIZONA_DRC2_SIG_DET_EINT1_WIDTH 1 /* DRC2_SIG_DET_EINT1 */
3908#define ARIZONA_DRC1_SIG_DET_EINT1 0x0200 /* DRC1_SIG_DET_EINT1 */
3909#define ARIZONA_DRC1_SIG_DET_EINT1_MASK 0x0200 /* DRC1_SIG_DET_EINT1 */
3910#define ARIZONA_DRC1_SIG_DET_EINT1_SHIFT 9 /* DRC1_SIG_DET_EINT1 */
3911#define ARIZONA_DRC1_SIG_DET_EINT1_WIDTH 1 /* DRC1_SIG_DET_EINT1 */
3912#define ARIZONA_ASRC2_LOCK_EINT1 0x0100 /* ASRC2_LOCK_EINT1 */
3913#define ARIZONA_ASRC2_LOCK_EINT1_MASK 0x0100 /* ASRC2_LOCK_EINT1 */
3914#define ARIZONA_ASRC2_LOCK_EINT1_SHIFT 8 /* ASRC2_LOCK_EINT1 */
3915#define ARIZONA_ASRC2_LOCK_EINT1_WIDTH 1 /* ASRC2_LOCK_EINT1 */
3916#define ARIZONA_ASRC1_LOCK_EINT1 0x0080 /* ASRC1_LOCK_EINT1 */
3917#define ARIZONA_ASRC1_LOCK_EINT1_MASK 0x0080 /* ASRC1_LOCK_EINT1 */
3918#define ARIZONA_ASRC1_LOCK_EINT1_SHIFT 7 /* ASRC1_LOCK_EINT1 */
3919#define ARIZONA_ASRC1_LOCK_EINT1_WIDTH 1 /* ASRC1_LOCK_EINT1 */
3920#define ARIZONA_UNDERCLOCKED_EINT1 0x0040 /* UNDERCLOCKED_EINT1 */
3921#define ARIZONA_UNDERCLOCKED_EINT1_MASK 0x0040 /* UNDERCLOCKED_EINT1 */
3922#define ARIZONA_UNDERCLOCKED_EINT1_SHIFT 6 /* UNDERCLOCKED_EINT1 */
3923#define ARIZONA_UNDERCLOCKED_EINT1_WIDTH 1 /* UNDERCLOCKED_EINT1 */
3924#define ARIZONA_OVERCLOCKED_EINT1 0x0020 /* OVERCLOCKED_EINT1 */
3925#define ARIZONA_OVERCLOCKED_EINT1_MASK 0x0020 /* OVERCLOCKED_EINT1 */
3926#define ARIZONA_OVERCLOCKED_EINT1_SHIFT 5 /* OVERCLOCKED_EINT1 */
3927#define ARIZONA_OVERCLOCKED_EINT1_WIDTH 1 /* OVERCLOCKED_EINT1 */
3928#define ARIZONA_FLL2_LOCK_EINT1 0x0008 /* FLL2_LOCK_EINT1 */
3929#define ARIZONA_FLL2_LOCK_EINT1_MASK 0x0008 /* FLL2_LOCK_EINT1 */
3930#define ARIZONA_FLL2_LOCK_EINT1_SHIFT 3 /* FLL2_LOCK_EINT1 */
3931#define ARIZONA_FLL2_LOCK_EINT1_WIDTH 1 /* FLL2_LOCK_EINT1 */
3932#define ARIZONA_FLL1_LOCK_EINT1 0x0004 /* FLL1_LOCK_EINT1 */
3933#define ARIZONA_FLL1_LOCK_EINT1_MASK 0x0004 /* FLL1_LOCK_EINT1 */
3934#define ARIZONA_FLL1_LOCK_EINT1_SHIFT 2 /* FLL1_LOCK_EINT1 */
3935#define ARIZONA_FLL1_LOCK_EINT1_WIDTH 1 /* FLL1_LOCK_EINT1 */
3936#define ARIZONA_CLKGEN_ERR_EINT1 0x0002 /* CLKGEN_ERR_EINT1 */
3937#define ARIZONA_CLKGEN_ERR_EINT1_MASK 0x0002 /* CLKGEN_ERR_EINT1 */
3938#define ARIZONA_CLKGEN_ERR_EINT1_SHIFT 1 /* CLKGEN_ERR_EINT1 */
3939#define ARIZONA_CLKGEN_ERR_EINT1_WIDTH 1 /* CLKGEN_ERR_EINT1 */
3940#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */
3941#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */
3942#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT1 */
3943#define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT1 */
3944
3945/*
3946 * R3331 (0xD03) - Interrupt Status 4
3947 */
3948#define ARIZONA_ASRC_CFG_ERR_EINT1 0x8000 /* ASRC_CFG_ERR_EINT1 */
3949#define ARIZONA_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* ASRC_CFG_ERR_EINT1 */
3950#define ARIZONA_ASRC_CFG_ERR_EINT1_SHIFT 15 /* ASRC_CFG_ERR_EINT1 */
3951#define ARIZONA_ASRC_CFG_ERR_EINT1_WIDTH 1 /* ASRC_CFG_ERR_EINT1 */
3952#define ARIZONA_AIF3_ERR_EINT1 0x4000 /* AIF3_ERR_EINT1 */
3953#define ARIZONA_AIF3_ERR_EINT1_MASK 0x4000 /* AIF3_ERR_EINT1 */
3954#define ARIZONA_AIF3_ERR_EINT1_SHIFT 14 /* AIF3_ERR_EINT1 */
3955#define ARIZONA_AIF3_ERR_EINT1_WIDTH 1 /* AIF3_ERR_EINT1 */
3956#define ARIZONA_AIF2_ERR_EINT1 0x2000 /* AIF2_ERR_EINT1 */
3957#define ARIZONA_AIF2_ERR_EINT1_MASK 0x2000 /* AIF2_ERR_EINT1 */
3958#define ARIZONA_AIF2_ERR_EINT1_SHIFT 13 /* AIF2_ERR_EINT1 */
3959#define ARIZONA_AIF2_ERR_EINT1_WIDTH 1 /* AIF2_ERR_EINT1 */
3960#define ARIZONA_AIF1_ERR_EINT1 0x1000 /* AIF1_ERR_EINT1 */
3961#define ARIZONA_AIF1_ERR_EINT1_MASK 0x1000 /* AIF1_ERR_EINT1 */
3962#define ARIZONA_AIF1_ERR_EINT1_SHIFT 12 /* AIF1_ERR_EINT1 */
3963#define ARIZONA_AIF1_ERR_EINT1_WIDTH 1 /* AIF1_ERR_EINT1 */
3964#define ARIZONA_CTRLIF_ERR_EINT1 0x0800 /* CTRLIF_ERR_EINT1 */
3965#define ARIZONA_CTRLIF_ERR_EINT1_MASK 0x0800 /* CTRLIF_ERR_EINT1 */
3966#define ARIZONA_CTRLIF_ERR_EINT1_SHIFT 11 /* CTRLIF_ERR_EINT1 */
3967#define ARIZONA_CTRLIF_ERR_EINT1_WIDTH 1 /* CTRLIF_ERR_EINT1 */
3968#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */
3969#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */
3970#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT1 */
3971#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT1 */
3972#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */
3973#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */
3974#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT1 */
3975#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT1 */
3976#define ARIZONA_SYSCLK_ENA_LOW_EINT1 0x0100 /* SYSCLK_ENA_LOW_EINT1 */
3977#define ARIZONA_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT1 */
3978#define ARIZONA_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* SYSCLK_ENA_LOW_EINT1 */
3979#define ARIZONA_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* SYSCLK_ENA_LOW_EINT1 */
3980#define ARIZONA_ISRC1_CFG_ERR_EINT1 0x0080 /* ISRC1_CFG_ERR_EINT1 */
3981#define ARIZONA_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* ISRC1_CFG_ERR_EINT1 */
3982#define ARIZONA_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* ISRC1_CFG_ERR_EINT1 */
3983#define ARIZONA_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* ISRC1_CFG_ERR_EINT1 */
3984#define ARIZONA_ISRC2_CFG_ERR_EINT1 0x0040 /* ISRC2_CFG_ERR_EINT1 */
3985#define ARIZONA_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* ISRC2_CFG_ERR_EINT1 */
3986#define ARIZONA_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* ISRC2_CFG_ERR_EINT1 */
3987#define ARIZONA_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* ISRC2_CFG_ERR_EINT1 */
3988
3989/*
3990 * R3332 (0xD04) - Interrupt Status 5
3991 */
3992#define ARIZONA_BOOT_DONE_EINT1 0x0100 /* BOOT_DONE_EINT1 */
3993#define ARIZONA_BOOT_DONE_EINT1_MASK 0x0100 /* BOOT_DONE_EINT1 */
3994#define ARIZONA_BOOT_DONE_EINT1_SHIFT 8 /* BOOT_DONE_EINT1 */
3995#define ARIZONA_BOOT_DONE_EINT1_WIDTH 1 /* BOOT_DONE_EINT1 */
3996#define ARIZONA_DCS_DAC_DONE_EINT1 0x0080 /* DCS_DAC_DONE_EINT1 */
3997#define ARIZONA_DCS_DAC_DONE_EINT1_MASK 0x0080 /* DCS_DAC_DONE_EINT1 */
3998#define ARIZONA_DCS_DAC_DONE_EINT1_SHIFT 7 /* DCS_DAC_DONE_EINT1 */
3999#define ARIZONA_DCS_DAC_DONE_EINT1_WIDTH 1 /* DCS_DAC_DONE_EINT1 */
4000#define ARIZONA_DCS_HP_DONE_EINT1 0x0040 /* DCS_HP_DONE_EINT1 */
4001#define ARIZONA_DCS_HP_DONE_EINT1_MASK 0x0040 /* DCS_HP_DONE_EINT1 */
4002#define ARIZONA_DCS_HP_DONE_EINT1_SHIFT 6 /* DCS_HP_DONE_EINT1 */
4003#define ARIZONA_DCS_HP_DONE_EINT1_WIDTH 1 /* DCS_HP_DONE_EINT1 */
4004#define ARIZONA_FLL2_CLOCK_OK_EINT1 0x0002 /* FLL2_CLOCK_OK_EINT1 */
4005#define ARIZONA_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* FLL2_CLOCK_OK_EINT1 */
4006#define ARIZONA_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* FLL2_CLOCK_OK_EINT1 */
4007#define ARIZONA_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* FLL2_CLOCK_OK_EINT1 */
4008#define ARIZONA_FLL1_CLOCK_OK_EINT1 0x0001 /* FLL1_CLOCK_OK_EINT1 */
4009#define ARIZONA_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* FLL1_CLOCK_OK_EINT1 */
4010#define ARIZONA_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* FLL1_CLOCK_OK_EINT1 */
4011#define ARIZONA_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* FLL1_CLOCK_OK_EINT1 */
4012
4013/*
4014 * R3336 (0xD08) - Interrupt Status 1 Mask
4015 */
4016#define ARIZONA_IM_GP4_EINT1 0x0008 /* IM_GP4_EINT1 */
4017#define ARIZONA_IM_GP4_EINT1_MASK 0x0008 /* IM_GP4_EINT1 */
4018#define ARIZONA_IM_GP4_EINT1_SHIFT 3 /* IM_GP4_EINT1 */
4019#define ARIZONA_IM_GP4_EINT1_WIDTH 1 /* IM_GP4_EINT1 */
4020#define ARIZONA_IM_GP3_EINT1 0x0004 /* IM_GP3_EINT1 */
4021#define ARIZONA_IM_GP3_EINT1_MASK 0x0004 /* IM_GP3_EINT1 */
4022#define ARIZONA_IM_GP3_EINT1_SHIFT 2 /* IM_GP3_EINT1 */
4023#define ARIZONA_IM_GP3_EINT1_WIDTH 1 /* IM_GP3_EINT1 */
4024#define ARIZONA_IM_GP2_EINT1 0x0002 /* IM_GP2_EINT1 */
4025#define ARIZONA_IM_GP2_EINT1_MASK 0x0002 /* IM_GP2_EINT1 */
4026#define ARIZONA_IM_GP2_EINT1_SHIFT 1 /* IM_GP2_EINT1 */
4027#define ARIZONA_IM_GP2_EINT1_WIDTH 1 /* IM_GP2_EINT1 */
4028#define ARIZONA_IM_GP1_EINT1 0x0001 /* IM_GP1_EINT1 */
4029#define ARIZONA_IM_GP1_EINT1_MASK 0x0001 /* IM_GP1_EINT1 */
4030#define ARIZONA_IM_GP1_EINT1_SHIFT 0 /* IM_GP1_EINT1 */
4031#define ARIZONA_IM_GP1_EINT1_WIDTH 1 /* IM_GP1_EINT1 */
4032
4033/*
4034 * R3337 (0xD09) - Interrupt Status 2 Mask
4035 */
4036#define ARIZONA_IM_DSP1_RAM_RDY_EINT1 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */
4037#define ARIZONA_IM_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */
4038#define ARIZONA_IM_DSP1_RAM_RDY_EINT1_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT1 */
4039#define ARIZONA_IM_DSP1_RAM_RDY_EINT1_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT1 */
4040#define ARIZONA_IM_DSP_IRQ2_EINT1 0x0002 /* IM_DSP_IRQ2_EINT1 */
4041#define ARIZONA_IM_DSP_IRQ2_EINT1_MASK 0x0002 /* IM_DSP_IRQ2_EINT1 */
4042#define ARIZONA_IM_DSP_IRQ2_EINT1_SHIFT 1 /* IM_DSP_IRQ2_EINT1 */
4043#define ARIZONA_IM_DSP_IRQ2_EINT1_WIDTH 1 /* IM_DSP_IRQ2_EINT1 */
4044#define ARIZONA_IM_DSP_IRQ1_EINT1 0x0001 /* IM_DSP_IRQ1_EINT1 */
4045#define ARIZONA_IM_DSP_IRQ1_EINT1_MASK 0x0001 /* IM_DSP_IRQ1_EINT1 */
4046#define ARIZONA_IM_DSP_IRQ1_EINT1_SHIFT 0 /* IM_DSP_IRQ1_EINT1 */
4047#define ARIZONA_IM_DSP_IRQ1_EINT1_WIDTH 1 /* IM_DSP_IRQ1_EINT1 */
4048
4049/*
4050 * R3338 (0xD0A) - Interrupt Status 3 Mask
4051 */
4052#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
4053#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
4054#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
4055#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
4056#define ARIZONA_IM_SPK_SHUTDOWN_EINT1 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
4057#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
4058#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT1 */
4059#define ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT1 */
4060#define ARIZONA_IM_HPDET_EINT1 0x2000 /* IM_HPDET_EINT1 */
4061#define ARIZONA_IM_HPDET_EINT1_MASK 0x2000 /* IM_HPDET_EINT1 */
4062#define ARIZONA_IM_HPDET_EINT1_SHIFT 13 /* IM_HPDET_EINT1 */
4063#define ARIZONA_IM_HPDET_EINT1_WIDTH 1 /* IM_HPDET_EINT1 */
4064#define ARIZONA_IM_MICDET_EINT1 0x1000 /* IM_MICDET_EINT1 */
4065#define ARIZONA_IM_MICDET_EINT1_MASK 0x1000 /* IM_MICDET_EINT1 */
4066#define ARIZONA_IM_MICDET_EINT1_SHIFT 12 /* IM_MICDET_EINT1 */
4067#define ARIZONA_IM_MICDET_EINT1_WIDTH 1 /* IM_MICDET_EINT1 */
4068#define ARIZONA_IM_WSEQ_DONE_EINT1 0x0800 /* IM_WSEQ_DONE_EINT1 */
4069#define ARIZONA_IM_WSEQ_DONE_EINT1_MASK 0x0800 /* IM_WSEQ_DONE_EINT1 */
4070#define ARIZONA_IM_WSEQ_DONE_EINT1_SHIFT 11 /* IM_WSEQ_DONE_EINT1 */
4071#define ARIZONA_IM_WSEQ_DONE_EINT1_WIDTH 1 /* IM_WSEQ_DONE_EINT1 */
4072#define ARIZONA_IM_DRC2_SIG_DET_EINT1 0x0400 /* IM_DRC2_SIG_DET_EINT1 */
4073#define ARIZONA_IM_DRC2_SIG_DET_EINT1_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT1 */
4074#define ARIZONA_IM_DRC2_SIG_DET_EINT1_SHIFT 10 /* IM_DRC2_SIG_DET_EINT1 */
4075#define ARIZONA_IM_DRC2_SIG_DET_EINT1_WIDTH 1 /* IM_DRC2_SIG_DET_EINT1 */
4076#define ARIZONA_IM_DRC1_SIG_DET_EINT1 0x0200 /* IM_DRC1_SIG_DET_EINT1 */
4077#define ARIZONA_IM_DRC1_SIG_DET_EINT1_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT1 */
4078#define ARIZONA_IM_DRC1_SIG_DET_EINT1_SHIFT 9 /* IM_DRC1_SIG_DET_EINT1 */
4079#define ARIZONA_IM_DRC1_SIG_DET_EINT1_WIDTH 1 /* IM_DRC1_SIG_DET_EINT1 */
4080#define ARIZONA_IM_ASRC2_LOCK_EINT1 0x0100 /* IM_ASRC2_LOCK_EINT1 */
4081#define ARIZONA_IM_ASRC2_LOCK_EINT1_MASK 0x0100 /* IM_ASRC2_LOCK_EINT1 */
4082#define ARIZONA_IM_ASRC2_LOCK_EINT1_SHIFT 8 /* IM_ASRC2_LOCK_EINT1 */
4083#define ARIZONA_IM_ASRC2_LOCK_EINT1_WIDTH 1 /* IM_ASRC2_LOCK_EINT1 */
4084#define ARIZONA_IM_ASRC1_LOCK_EINT1 0x0080 /* IM_ASRC1_LOCK_EINT1 */
4085#define ARIZONA_IM_ASRC1_LOCK_EINT1_MASK 0x0080 /* IM_ASRC1_LOCK_EINT1 */
4086#define ARIZONA_IM_ASRC1_LOCK_EINT1_SHIFT 7 /* IM_ASRC1_LOCK_EINT1 */
4087#define ARIZONA_IM_ASRC1_LOCK_EINT1_WIDTH 1 /* IM_ASRC1_LOCK_EINT1 */
4088#define ARIZONA_IM_UNDERCLOCKED_EINT1 0x0040 /* IM_UNDERCLOCKED_EINT1 */
4089#define ARIZONA_IM_UNDERCLOCKED_EINT1_MASK 0x0040 /* IM_UNDERCLOCKED_EINT1 */
4090#define ARIZONA_IM_UNDERCLOCKED_EINT1_SHIFT 6 /* IM_UNDERCLOCKED_EINT1 */
4091#define ARIZONA_IM_UNDERCLOCKED_EINT1_WIDTH 1 /* IM_UNDERCLOCKED_EINT1 */
4092#define ARIZONA_IM_OVERCLOCKED_EINT1 0x0020 /* IM_OVERCLOCKED_EINT1 */
4093#define ARIZONA_IM_OVERCLOCKED_EINT1_MASK 0x0020 /* IM_OVERCLOCKED_EINT1 */
4094#define ARIZONA_IM_OVERCLOCKED_EINT1_SHIFT 5 /* IM_OVERCLOCKED_EINT1 */
4095#define ARIZONA_IM_OVERCLOCKED_EINT1_WIDTH 1 /* IM_OVERCLOCKED_EINT1 */
4096#define ARIZONA_IM_FLL2_LOCK_EINT1 0x0008 /* IM_FLL2_LOCK_EINT1 */
4097#define ARIZONA_IM_FLL2_LOCK_EINT1_MASK 0x0008 /* IM_FLL2_LOCK_EINT1 */
4098#define ARIZONA_IM_FLL2_LOCK_EINT1_SHIFT 3 /* IM_FLL2_LOCK_EINT1 */
4099#define ARIZONA_IM_FLL2_LOCK_EINT1_WIDTH 1 /* IM_FLL2_LOCK_EINT1 */
4100#define ARIZONA_IM_FLL1_LOCK_EINT1 0x0004 /* IM_FLL1_LOCK_EINT1 */
4101#define ARIZONA_IM_FLL1_LOCK_EINT1_MASK 0x0004 /* IM_FLL1_LOCK_EINT1 */
4102#define ARIZONA_IM_FLL1_LOCK_EINT1_SHIFT 2 /* IM_FLL1_LOCK_EINT1 */
4103#define ARIZONA_IM_FLL1_LOCK_EINT1_WIDTH 1 /* IM_FLL1_LOCK_EINT1 */
4104#define ARIZONA_IM_CLKGEN_ERR_EINT1 0x0002 /* IM_CLKGEN_ERR_EINT1 */
4105#define ARIZONA_IM_CLKGEN_ERR_EINT1_MASK 0x0002 /* IM_CLKGEN_ERR_EINT1 */
4106#define ARIZONA_IM_CLKGEN_ERR_EINT1_SHIFT 1 /* IM_CLKGEN_ERR_EINT1 */
4107#define ARIZONA_IM_CLKGEN_ERR_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_EINT1 */
4108#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
4109#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
4110#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
4111#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
4112
4113/*
4114 * R3339 (0xD0B) - Interrupt Status 4 Mask
4115 */
4116#define ARIZONA_IM_ASRC_CFG_ERR_EINT1 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */
4117#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */
4118#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT1 */
4119#define ARIZONA_IM_ASRC_CFG_ERR_EINT1_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT1 */
4120#define ARIZONA_IM_AIF3_ERR_EINT1 0x4000 /* IM_AIF3_ERR_EINT1 */
4121#define ARIZONA_IM_AIF3_ERR_EINT1_MASK 0x4000 /* IM_AIF3_ERR_EINT1 */
4122#define ARIZONA_IM_AIF3_ERR_EINT1_SHIFT 14 /* IM_AIF3_ERR_EINT1 */
4123#define ARIZONA_IM_AIF3_ERR_EINT1_WIDTH 1 /* IM_AIF3_ERR_EINT1 */
4124#define ARIZONA_IM_AIF2_ERR_EINT1 0x2000 /* IM_AIF2_ERR_EINT1 */
4125#define ARIZONA_IM_AIF2_ERR_EINT1_MASK 0x2000 /* IM_AIF2_ERR_EINT1 */
4126#define ARIZONA_IM_AIF2_ERR_EINT1_SHIFT 13 /* IM_AIF2_ERR_EINT1 */
4127#define ARIZONA_IM_AIF2_ERR_EINT1_WIDTH 1 /* IM_AIF2_ERR_EINT1 */
4128#define ARIZONA_IM_AIF1_ERR_EINT1 0x1000 /* IM_AIF1_ERR_EINT1 */
4129#define ARIZONA_IM_AIF1_ERR_EINT1_MASK 0x1000 /* IM_AIF1_ERR_EINT1 */
4130#define ARIZONA_IM_AIF1_ERR_EINT1_SHIFT 12 /* IM_AIF1_ERR_EINT1 */
4131#define ARIZONA_IM_AIF1_ERR_EINT1_WIDTH 1 /* IM_AIF1_ERR_EINT1 */
4132#define ARIZONA_IM_CTRLIF_ERR_EINT1 0x0800 /* IM_CTRLIF_ERR_EINT1 */
4133#define ARIZONA_IM_CTRLIF_ERR_EINT1_MASK 0x0800 /* IM_CTRLIF_ERR_EINT1 */
4134#define ARIZONA_IM_CTRLIF_ERR_EINT1_SHIFT 11 /* IM_CTRLIF_ERR_EINT1 */
4135#define ARIZONA_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */
4136#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
4137#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
4138#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
4139#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
4140#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
4141#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
4142#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
4143#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
4144#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */
4145#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */
4146#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT1 */
4147#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT1 */
4148#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */
4149#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */
4150#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT1 */
4151#define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT1 */
4152#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */
4153#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */
4154#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT1 */
4155#define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */
4156
4157/*
4158 * R3340 (0xD0C) - Interrupt Status 5 Mask
4159 */
4160#define ARIZONA_IM_BOOT_DONE_EINT1 0x0100 /* IM_BOOT_DONE_EINT1 */
4161#define ARIZONA_IM_BOOT_DONE_EINT1_MASK 0x0100 /* IM_BOOT_DONE_EINT1 */
4162#define ARIZONA_IM_BOOT_DONE_EINT1_SHIFT 8 /* IM_BOOT_DONE_EINT1 */
4163#define ARIZONA_IM_BOOT_DONE_EINT1_WIDTH 1 /* IM_BOOT_DONE_EINT1 */
4164#define ARIZONA_IM_DCS_DAC_DONE_EINT1 0x0080 /* IM_DCS_DAC_DONE_EINT1 */
4165#define ARIZONA_IM_DCS_DAC_DONE_EINT1_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT1 */
4166#define ARIZONA_IM_DCS_DAC_DONE_EINT1_SHIFT 7 /* IM_DCS_DAC_DONE_EINT1 */
4167#define ARIZONA_IM_DCS_DAC_DONE_EINT1_WIDTH 1 /* IM_DCS_DAC_DONE_EINT1 */
4168#define ARIZONA_IM_DCS_HP_DONE_EINT1 0x0040 /* IM_DCS_HP_DONE_EINT1 */
4169#define ARIZONA_IM_DCS_HP_DONE_EINT1_MASK 0x0040 /* IM_DCS_HP_DONE_EINT1 */
4170#define ARIZONA_IM_DCS_HP_DONE_EINT1_SHIFT 6 /* IM_DCS_HP_DONE_EINT1 */
4171#define ARIZONA_IM_DCS_HP_DONE_EINT1_WIDTH 1 /* IM_DCS_HP_DONE_EINT1 */
4172#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */
4173#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */
4174#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT1 */
4175#define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT1 */
4176#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */
4177#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */
4178#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT1 */
4179#define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT1 */
4180
4181/*
4182 * R3343 (0xD0F) - Interrupt Control
4183 */
4184#define ARIZONA_IM_IRQ1 0x0001 /* IM_IRQ1 */
4185#define ARIZONA_IM_IRQ1_MASK 0x0001 /* IM_IRQ1 */
4186#define ARIZONA_IM_IRQ1_SHIFT 0 /* IM_IRQ1 */
4187#define ARIZONA_IM_IRQ1_WIDTH 1 /* IM_IRQ1 */
4188
4189/*
4190 * R3344 (0xD10) - IRQ2 Status 1
4191 */
4192#define ARIZONA_GP4_EINT2 0x0008 /* GP4_EINT2 */
4193#define ARIZONA_GP4_EINT2_MASK 0x0008 /* GP4_EINT2 */
4194#define ARIZONA_GP4_EINT2_SHIFT 3 /* GP4_EINT2 */
4195#define ARIZONA_GP4_EINT2_WIDTH 1 /* GP4_EINT2 */
4196#define ARIZONA_GP3_EINT2 0x0004 /* GP3_EINT2 */
4197#define ARIZONA_GP3_EINT2_MASK 0x0004 /* GP3_EINT2 */
4198#define ARIZONA_GP3_EINT2_SHIFT 2 /* GP3_EINT2 */
4199#define ARIZONA_GP3_EINT2_WIDTH 1 /* GP3_EINT2 */
4200#define ARIZONA_GP2_EINT2 0x0002 /* GP2_EINT2 */
4201#define ARIZONA_GP2_EINT2_MASK 0x0002 /* GP2_EINT2 */
4202#define ARIZONA_GP2_EINT2_SHIFT 1 /* GP2_EINT2 */
4203#define ARIZONA_GP2_EINT2_WIDTH 1 /* GP2_EINT2 */
4204#define ARIZONA_GP1_EINT2 0x0001 /* GP1_EINT2 */
4205#define ARIZONA_GP1_EINT2_MASK 0x0001 /* GP1_EINT2 */
4206#define ARIZONA_GP1_EINT2_SHIFT 0 /* GP1_EINT2 */
4207#define ARIZONA_GP1_EINT2_WIDTH 1 /* GP1_EINT2 */
4208
4209/*
4210 * R3345 (0xD11) - IRQ2 Status 2
4211 */
4212#define ARIZONA_DSP1_RAM_RDY_EINT2 0x0100 /* DSP1_RAM_RDY_EINT2 */
4213#define ARIZONA_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* DSP1_RAM_RDY_EINT2 */
4214#define ARIZONA_DSP1_RAM_RDY_EINT2_SHIFT 8 /* DSP1_RAM_RDY_EINT2 */
4215#define ARIZONA_DSP1_RAM_RDY_EINT2_WIDTH 1 /* DSP1_RAM_RDY_EINT2 */
4216#define ARIZONA_DSP_IRQ2_EINT2 0x0002 /* DSP_IRQ2_EINT2 */
4217#define ARIZONA_DSP_IRQ2_EINT2_MASK 0x0002 /* DSP_IRQ2_EINT2 */
4218#define ARIZONA_DSP_IRQ2_EINT2_SHIFT 1 /* DSP_IRQ2_EINT2 */
4219#define ARIZONA_DSP_IRQ2_EINT2_WIDTH 1 /* DSP_IRQ2_EINT2 */
4220#define ARIZONA_DSP_IRQ1_EINT2 0x0001 /* DSP_IRQ1_EINT2 */
4221#define ARIZONA_DSP_IRQ1_EINT2_MASK 0x0001 /* DSP_IRQ1_EINT2 */
4222#define ARIZONA_DSP_IRQ1_EINT2_SHIFT 0 /* DSP_IRQ1_EINT2 */
4223#define ARIZONA_DSP_IRQ1_EINT2_WIDTH 1 /* DSP_IRQ1_EINT2 */
4224
4225/*
4226 * R3346 (0xD12) - IRQ2 Status 3
4227 */
4228#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */
4229#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */
4230#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT2 */
4231#define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT2 */
4232#define ARIZONA_SPK_SHUTDOWN_EINT2 0x4000 /* SPK_SHUTDOWN_EINT2 */
4233#define ARIZONA_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* SPK_SHUTDOWN_EINT2 */
4234#define ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT 14 /* SPK_SHUTDOWN_EINT2 */
4235#define ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_EINT2 */
4236#define ARIZONA_HPDET_EINT2 0x2000 /* HPDET_EINT2 */
4237#define ARIZONA_HPDET_EINT2_MASK 0x2000 /* HPDET_EINT2 */
4238#define ARIZONA_HPDET_EINT2_SHIFT 13 /* HPDET_EINT2 */
4239#define ARIZONA_HPDET_EINT2_WIDTH 1 /* HPDET_EINT2 */
4240#define ARIZONA_MICDET_EINT2 0x1000 /* MICDET_EINT2 */
4241#define ARIZONA_MICDET_EINT2_MASK 0x1000 /* MICDET_EINT2 */
4242#define ARIZONA_MICDET_EINT2_SHIFT 12 /* MICDET_EINT2 */
4243#define ARIZONA_MICDET_EINT2_WIDTH 1 /* MICDET_EINT2 */
4244#define ARIZONA_WSEQ_DONE_EINT2 0x0800 /* WSEQ_DONE_EINT2 */
4245#define ARIZONA_WSEQ_DONE_EINT2_MASK 0x0800 /* WSEQ_DONE_EINT2 */
4246#define ARIZONA_WSEQ_DONE_EINT2_SHIFT 11 /* WSEQ_DONE_EINT2 */
4247#define ARIZONA_WSEQ_DONE_EINT2_WIDTH 1 /* WSEQ_DONE_EINT2 */
4248#define ARIZONA_DRC2_SIG_DET_EINT2 0x0400 /* DRC2_SIG_DET_EINT2 */
4249#define ARIZONA_DRC2_SIG_DET_EINT2_MASK 0x0400 /* DRC2_SIG_DET_EINT2 */
4250#define ARIZONA_DRC2_SIG_DET_EINT2_SHIFT 10 /* DRC2_SIG_DET_EINT2 */
4251#define ARIZONA_DRC2_SIG_DET_EINT2_WIDTH 1 /* DRC2_SIG_DET_EINT2 */
4252#define ARIZONA_DRC1_SIG_DET_EINT2 0x0200 /* DRC1_SIG_DET_EINT2 */
4253#define ARIZONA_DRC1_SIG_DET_EINT2_MASK 0x0200 /* DRC1_SIG_DET_EINT2 */
4254#define ARIZONA_DRC1_SIG_DET_EINT2_SHIFT 9 /* DRC1_SIG_DET_EINT2 */
4255#define ARIZONA_DRC1_SIG_DET_EINT2_WIDTH 1 /* DRC1_SIG_DET_EINT2 */
4256#define ARIZONA_ASRC2_LOCK_EINT2 0x0100 /* ASRC2_LOCK_EINT2 */
4257#define ARIZONA_ASRC2_LOCK_EINT2_MASK 0x0100 /* ASRC2_LOCK_EINT2 */
4258#define ARIZONA_ASRC2_LOCK_EINT2_SHIFT 8 /* ASRC2_LOCK_EINT2 */
4259#define ARIZONA_ASRC2_LOCK_EINT2_WIDTH 1 /* ASRC2_LOCK_EINT2 */
4260#define ARIZONA_ASRC1_LOCK_EINT2 0x0080 /* ASRC1_LOCK_EINT2 */
4261#define ARIZONA_ASRC1_LOCK_EINT2_MASK 0x0080 /* ASRC1_LOCK_EINT2 */
4262#define ARIZONA_ASRC1_LOCK_EINT2_SHIFT 7 /* ASRC1_LOCK_EINT2 */
4263#define ARIZONA_ASRC1_LOCK_EINT2_WIDTH 1 /* ASRC1_LOCK_EINT2 */
4264#define ARIZONA_UNDERCLOCKED_EINT2 0x0040 /* UNDERCLOCKED_EINT2 */
4265#define ARIZONA_UNDERCLOCKED_EINT2_MASK 0x0040 /* UNDERCLOCKED_EINT2 */
4266#define ARIZONA_UNDERCLOCKED_EINT2_SHIFT 6 /* UNDERCLOCKED_EINT2 */
4267#define ARIZONA_UNDERCLOCKED_EINT2_WIDTH 1 /* UNDERCLOCKED_EINT2 */
4268#define ARIZONA_OVERCLOCKED_EINT2 0x0020 /* OVERCLOCKED_EINT2 */
4269#define ARIZONA_OVERCLOCKED_EINT2_MASK 0x0020 /* OVERCLOCKED_EINT2 */
4270#define ARIZONA_OVERCLOCKED_EINT2_SHIFT 5 /* OVERCLOCKED_EINT2 */
4271#define ARIZONA_OVERCLOCKED_EINT2_WIDTH 1 /* OVERCLOCKED_EINT2 */
4272#define ARIZONA_FLL2_LOCK_EINT2 0x0008 /* FLL2_LOCK_EINT2 */
4273#define ARIZONA_FLL2_LOCK_EINT2_MASK 0x0008 /* FLL2_LOCK_EINT2 */
4274#define ARIZONA_FLL2_LOCK_EINT2_SHIFT 3 /* FLL2_LOCK_EINT2 */
4275#define ARIZONA_FLL2_LOCK_EINT2_WIDTH 1 /* FLL2_LOCK_EINT2 */
4276#define ARIZONA_FLL1_LOCK_EINT2 0x0004 /* FLL1_LOCK_EINT2 */
4277#define ARIZONA_FLL1_LOCK_EINT2_MASK 0x0004 /* FLL1_LOCK_EINT2 */
4278#define ARIZONA_FLL1_LOCK_EINT2_SHIFT 2 /* FLL1_LOCK_EINT2 */
4279#define ARIZONA_FLL1_LOCK_EINT2_WIDTH 1 /* FLL1_LOCK_EINT2 */
4280#define ARIZONA_CLKGEN_ERR_EINT2 0x0002 /* CLKGEN_ERR_EINT2 */
4281#define ARIZONA_CLKGEN_ERR_EINT2_MASK 0x0002 /* CLKGEN_ERR_EINT2 */
4282#define ARIZONA_CLKGEN_ERR_EINT2_SHIFT 1 /* CLKGEN_ERR_EINT2 */
4283#define ARIZONA_CLKGEN_ERR_EINT2_WIDTH 1 /* CLKGEN_ERR_EINT2 */
4284#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */
4285#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */
4286#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT2 */
4287#define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT2 */
4288
4289/*
4290 * R3347 (0xD13) - IRQ2 Status 4
4291 */
4292#define ARIZONA_ASRC_CFG_ERR_EINT2 0x8000 /* ASRC_CFG_ERR_EINT2 */
4293#define ARIZONA_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* ASRC_CFG_ERR_EINT2 */
4294#define ARIZONA_ASRC_CFG_ERR_EINT2_SHIFT 15 /* ASRC_CFG_ERR_EINT2 */
4295#define ARIZONA_ASRC_CFG_ERR_EINT2_WIDTH 1 /* ASRC_CFG_ERR_EINT2 */
4296#define ARIZONA_AIF3_ERR_EINT2 0x4000 /* AIF3_ERR_EINT2 */
4297#define ARIZONA_AIF3_ERR_EINT2_MASK 0x4000 /* AIF3_ERR_EINT2 */
4298#define ARIZONA_AIF3_ERR_EINT2_SHIFT 14 /* AIF3_ERR_EINT2 */
4299#define ARIZONA_AIF3_ERR_EINT2_WIDTH 1 /* AIF3_ERR_EINT2 */
4300#define ARIZONA_AIF2_ERR_EINT2 0x2000 /* AIF2_ERR_EINT2 */
4301#define ARIZONA_AIF2_ERR_EINT2_MASK 0x2000 /* AIF2_ERR_EINT2 */
4302#define ARIZONA_AIF2_ERR_EINT2_SHIFT 13 /* AIF2_ERR_EINT2 */
4303#define ARIZONA_AIF2_ERR_EINT2_WIDTH 1 /* AIF2_ERR_EINT2 */
4304#define ARIZONA_AIF1_ERR_EINT2 0x1000 /* AIF1_ERR_EINT2 */
4305#define ARIZONA_AIF1_ERR_EINT2_MASK 0x1000 /* AIF1_ERR_EINT2 */
4306#define ARIZONA_AIF1_ERR_EINT2_SHIFT 12 /* AIF1_ERR_EINT2 */
4307#define ARIZONA_AIF1_ERR_EINT2_WIDTH 1 /* AIF1_ERR_EINT2 */
4308#define ARIZONA_CTRLIF_ERR_EINT2 0x0800 /* CTRLIF_ERR_EINT2 */
4309#define ARIZONA_CTRLIF_ERR_EINT2_MASK 0x0800 /* CTRLIF_ERR_EINT2 */
4310#define ARIZONA_CTRLIF_ERR_EINT2_SHIFT 11 /* CTRLIF_ERR_EINT2 */
4311#define ARIZONA_CTRLIF_ERR_EINT2_WIDTH 1 /* CTRLIF_ERR_EINT2 */
4312#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */
4313#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */
4314#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT2 */
4315#define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT2 */
4316#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */
4317#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */
4318#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT2 */
4319#define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT2 */
4320#define ARIZONA_SYSCLK_ENA_LOW_EINT2 0x0100 /* SYSCLK_ENA_LOW_EINT2 */
4321#define ARIZONA_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT2 */
4322#define ARIZONA_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* SYSCLK_ENA_LOW_EINT2 */
4323#define ARIZONA_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* SYSCLK_ENA_LOW_EINT2 */
4324#define ARIZONA_ISRC1_CFG_ERR_EINT2 0x0080 /* ISRC1_CFG_ERR_EINT2 */
4325#define ARIZONA_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* ISRC1_CFG_ERR_EINT2 */
4326#define ARIZONA_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* ISRC1_CFG_ERR_EINT2 */
4327#define ARIZONA_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* ISRC1_CFG_ERR_EINT2 */
4328#define ARIZONA_ISRC2_CFG_ERR_EINT2 0x0040 /* ISRC2_CFG_ERR_EINT2 */
4329#define ARIZONA_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* ISRC2_CFG_ERR_EINT2 */
4330#define ARIZONA_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* ISRC2_CFG_ERR_EINT2 */
4331#define ARIZONA_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* ISRC2_CFG_ERR_EINT2 */
4332
4333/*
4334 * R3348 (0xD14) - IRQ2 Status 5
4335 */
4336#define ARIZONA_BOOT_DONE_EINT2 0x0100 /* BOOT_DONE_EINT2 */
4337#define ARIZONA_BOOT_DONE_EINT2_MASK 0x0100 /* BOOT_DONE_EINT2 */
4338#define ARIZONA_BOOT_DONE_EINT2_SHIFT 8 /* BOOT_DONE_EINT2 */
4339#define ARIZONA_BOOT_DONE_EINT2_WIDTH 1 /* BOOT_DONE_EINT2 */
4340#define ARIZONA_DCS_DAC_DONE_EINT2 0x0080 /* DCS_DAC_DONE_EINT2 */
4341#define ARIZONA_DCS_DAC_DONE_EINT2_MASK 0x0080 /* DCS_DAC_DONE_EINT2 */
4342#define ARIZONA_DCS_DAC_DONE_EINT2_SHIFT 7 /* DCS_DAC_DONE_EINT2 */
4343#define ARIZONA_DCS_DAC_DONE_EINT2_WIDTH 1 /* DCS_DAC_DONE_EINT2 */
4344#define ARIZONA_DCS_HP_DONE_EINT2 0x0040 /* DCS_HP_DONE_EINT2 */
4345#define ARIZONA_DCS_HP_DONE_EINT2_MASK 0x0040 /* DCS_HP_DONE_EINT2 */
4346#define ARIZONA_DCS_HP_DONE_EINT2_SHIFT 6 /* DCS_HP_DONE_EINT2 */
4347#define ARIZONA_DCS_HP_DONE_EINT2_WIDTH 1 /* DCS_HP_DONE_EINT2 */
4348#define ARIZONA_FLL2_CLOCK_OK_EINT2 0x0002 /* FLL2_CLOCK_OK_EINT2 */
4349#define ARIZONA_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* FLL2_CLOCK_OK_EINT2 */
4350#define ARIZONA_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* FLL2_CLOCK_OK_EINT2 */
4351#define ARIZONA_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* FLL2_CLOCK_OK_EINT2 */
4352#define ARIZONA_FLL1_CLOCK_OK_EINT2 0x0001 /* FLL1_CLOCK_OK_EINT2 */
4353#define ARIZONA_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* FLL1_CLOCK_OK_EINT2 */
4354#define ARIZONA_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* FLL1_CLOCK_OK_EINT2 */
4355#define ARIZONA_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* FLL1_CLOCK_OK_EINT2 */
4356
4357/*
4358 * R3352 (0xD18) - IRQ2 Status 1 Mask
4359 */
4360#define ARIZONA_IM_GP4_EINT2 0x0008 /* IM_GP4_EINT2 */
4361#define ARIZONA_IM_GP4_EINT2_MASK 0x0008 /* IM_GP4_EINT2 */
4362#define ARIZONA_IM_GP4_EINT2_SHIFT 3 /* IM_GP4_EINT2 */
4363#define ARIZONA_IM_GP4_EINT2_WIDTH 1 /* IM_GP4_EINT2 */
4364#define ARIZONA_IM_GP3_EINT2 0x0004 /* IM_GP3_EINT2 */
4365#define ARIZONA_IM_GP3_EINT2_MASK 0x0004 /* IM_GP3_EINT2 */
4366#define ARIZONA_IM_GP3_EINT2_SHIFT 2 /* IM_GP3_EINT2 */
4367#define ARIZONA_IM_GP3_EINT2_WIDTH 1 /* IM_GP3_EINT2 */
4368#define ARIZONA_IM_GP2_EINT2 0x0002 /* IM_GP2_EINT2 */
4369#define ARIZONA_IM_GP2_EINT2_MASK 0x0002 /* IM_GP2_EINT2 */
4370#define ARIZONA_IM_GP2_EINT2_SHIFT 1 /* IM_GP2_EINT2 */
4371#define ARIZONA_IM_GP2_EINT2_WIDTH 1 /* IM_GP2_EINT2 */
4372#define ARIZONA_IM_GP1_EINT2 0x0001 /* IM_GP1_EINT2 */
4373#define ARIZONA_IM_GP1_EINT2_MASK 0x0001 /* IM_GP1_EINT2 */
4374#define ARIZONA_IM_GP1_EINT2_SHIFT 0 /* IM_GP1_EINT2 */
4375#define ARIZONA_IM_GP1_EINT2_WIDTH 1 /* IM_GP1_EINT2 */
4376
4377/*
4378 * R3353 (0xD19) - IRQ2 Status 2 Mask
4379 */
4380#define ARIZONA_IM_DSP1_RAM_RDY_EINT2 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */
4381#define ARIZONA_IM_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */
4382#define ARIZONA_IM_DSP1_RAM_RDY_EINT2_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT2 */
4383#define ARIZONA_IM_DSP1_RAM_RDY_EINT2_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT2 */
4384#define ARIZONA_IM_DSP_IRQ2_EINT2 0x0002 /* IM_DSP_IRQ2_EINT2 */
4385#define ARIZONA_IM_DSP_IRQ2_EINT2_MASK 0x0002 /* IM_DSP_IRQ2_EINT2 */
4386#define ARIZONA_IM_DSP_IRQ2_EINT2_SHIFT 1 /* IM_DSP_IRQ2_EINT2 */
4387#define ARIZONA_IM_DSP_IRQ2_EINT2_WIDTH 1 /* IM_DSP_IRQ2_EINT2 */
4388#define ARIZONA_IM_DSP_IRQ1_EINT2 0x0001 /* IM_DSP_IRQ1_EINT2 */
4389#define ARIZONA_IM_DSP_IRQ1_EINT2_MASK 0x0001 /* IM_DSP_IRQ1_EINT2 */
4390#define ARIZONA_IM_DSP_IRQ1_EINT2_SHIFT 0 /* IM_DSP_IRQ1_EINT2 */
4391#define ARIZONA_IM_DSP_IRQ1_EINT2_WIDTH 1 /* IM_DSP_IRQ1_EINT2 */
4392
4393/*
4394 * R3354 (0xD1A) - IRQ2 Status 3 Mask
4395 */
4396#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
4397#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
4398#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
4399#define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
4400#define ARIZONA_IM_SPK_SHUTDOWN_EINT2 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
4401#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
4402#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT2 */
4403#define ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT2 */
4404#define ARIZONA_IM_HPDET_EINT2 0x2000 /* IM_HPDET_EINT2 */
4405#define ARIZONA_IM_HPDET_EINT2_MASK 0x2000 /* IM_HPDET_EINT2 */
4406#define ARIZONA_IM_HPDET_EINT2_SHIFT 13 /* IM_HPDET_EINT2 */
4407#define ARIZONA_IM_HPDET_EINT2_WIDTH 1 /* IM_HPDET_EINT2 */
4408#define ARIZONA_IM_MICDET_EINT2 0x1000 /* IM_MICDET_EINT2 */
4409#define ARIZONA_IM_MICDET_EINT2_MASK 0x1000 /* IM_MICDET_EINT2 */
4410#define ARIZONA_IM_MICDET_EINT2_SHIFT 12 /* IM_MICDET_EINT2 */
4411#define ARIZONA_IM_MICDET_EINT2_WIDTH 1 /* IM_MICDET_EINT2 */
4412#define ARIZONA_IM_WSEQ_DONE_EINT2 0x0800 /* IM_WSEQ_DONE_EINT2 */
4413#define ARIZONA_IM_WSEQ_DONE_EINT2_MASK 0x0800 /* IM_WSEQ_DONE_EINT2 */
4414#define ARIZONA_IM_WSEQ_DONE_EINT2_SHIFT 11 /* IM_WSEQ_DONE_EINT2 */
4415#define ARIZONA_IM_WSEQ_DONE_EINT2_WIDTH 1 /* IM_WSEQ_DONE_EINT2 */
4416#define ARIZONA_IM_DRC2_SIG_DET_EINT2 0x0400 /* IM_DRC2_SIG_DET_EINT2 */
4417#define ARIZONA_IM_DRC2_SIG_DET_EINT2_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT2 */
4418#define ARIZONA_IM_DRC2_SIG_DET_EINT2_SHIFT 10 /* IM_DRC2_SIG_DET_EINT2 */
4419#define ARIZONA_IM_DRC2_SIG_DET_EINT2_WIDTH 1 /* IM_DRC2_SIG_DET_EINT2 */
4420#define ARIZONA_IM_DRC1_SIG_DET_EINT2 0x0200 /* IM_DRC1_SIG_DET_EINT2 */
4421#define ARIZONA_IM_DRC1_SIG_DET_EINT2_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT2 */
4422#define ARIZONA_IM_DRC1_SIG_DET_EINT2_SHIFT 9 /* IM_DRC1_SIG_DET_EINT2 */
4423#define ARIZONA_IM_DRC1_SIG_DET_EINT2_WIDTH 1 /* IM_DRC1_SIG_DET_EINT2 */
4424#define ARIZONA_IM_ASRC2_LOCK_EINT2 0x0100 /* IM_ASRC2_LOCK_EINT2 */
4425#define ARIZONA_IM_ASRC2_LOCK_EINT2_MASK 0x0100 /* IM_ASRC2_LOCK_EINT2 */
4426#define ARIZONA_IM_ASRC2_LOCK_EINT2_SHIFT 8 /* IM_ASRC2_LOCK_EINT2 */
4427#define ARIZONA_IM_ASRC2_LOCK_EINT2_WIDTH 1 /* IM_ASRC2_LOCK_EINT2 */
4428#define ARIZONA_IM_ASRC1_LOCK_EINT2 0x0080 /* IM_ASRC1_LOCK_EINT2 */
4429#define ARIZONA_IM_ASRC1_LOCK_EINT2_MASK 0x0080 /* IM_ASRC1_LOCK_EINT2 */
4430#define ARIZONA_IM_ASRC1_LOCK_EINT2_SHIFT 7 /* IM_ASRC1_LOCK_EINT2 */
4431#define ARIZONA_IM_ASRC1_LOCK_EINT2_WIDTH 1 /* IM_ASRC1_LOCK_EINT2 */
4432#define ARIZONA_IM_UNDERCLOCKED_EINT2 0x0040 /* IM_UNDERCLOCKED_EINT2 */
4433#define ARIZONA_IM_UNDERCLOCKED_EINT2_MASK 0x0040 /* IM_UNDERCLOCKED_EINT2 */
4434#define ARIZONA_IM_UNDERCLOCKED_EINT2_SHIFT 6 /* IM_UNDERCLOCKED_EINT2 */
4435#define ARIZONA_IM_UNDERCLOCKED_EINT2_WIDTH 1 /* IM_UNDERCLOCKED_EINT2 */
4436#define ARIZONA_IM_OVERCLOCKED_EINT2 0x0020 /* IM_OVERCLOCKED_EINT2 */
4437#define ARIZONA_IM_OVERCLOCKED_EINT2_MASK 0x0020 /* IM_OVERCLOCKED_EINT2 */
4438#define ARIZONA_IM_OVERCLOCKED_EINT2_SHIFT 5 /* IM_OVERCLOCKED_EINT2 */
4439#define ARIZONA_IM_OVERCLOCKED_EINT2_WIDTH 1 /* IM_OVERCLOCKED_EINT2 */
4440#define ARIZONA_IM_FLL2_LOCK_EINT2 0x0008 /* IM_FLL2_LOCK_EINT2 */
4441#define ARIZONA_IM_FLL2_LOCK_EINT2_MASK 0x0008 /* IM_FLL2_LOCK_EINT2 */
4442#define ARIZONA_IM_FLL2_LOCK_EINT2_SHIFT 3 /* IM_FLL2_LOCK_EINT2 */
4443#define ARIZONA_IM_FLL2_LOCK_EINT2_WIDTH 1 /* IM_FLL2_LOCK_EINT2 */
4444#define ARIZONA_IM_FLL1_LOCK_EINT2 0x0004 /* IM_FLL1_LOCK_EINT2 */
4445#define ARIZONA_IM_FLL1_LOCK_EINT2_MASK 0x0004 /* IM_FLL1_LOCK_EINT2 */
4446#define ARIZONA_IM_FLL1_LOCK_EINT2_SHIFT 2 /* IM_FLL1_LOCK_EINT2 */
4447#define ARIZONA_IM_FLL1_LOCK_EINT2_WIDTH 1 /* IM_FLL1_LOCK_EINT2 */
4448#define ARIZONA_IM_CLKGEN_ERR_EINT2 0x0002 /* IM_CLKGEN_ERR_EINT2 */
4449#define ARIZONA_IM_CLKGEN_ERR_EINT2_MASK 0x0002 /* IM_CLKGEN_ERR_EINT2 */
4450#define ARIZONA_IM_CLKGEN_ERR_EINT2_SHIFT 1 /* IM_CLKGEN_ERR_EINT2 */
4451#define ARIZONA_IM_CLKGEN_ERR_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_EINT2 */
4452#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
4453#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
4454#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
4455#define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
4456
4457/*
4458 * R3355 (0xD1B) - IRQ2 Status 4 Mask
4459 */
4460#define ARIZONA_IM_ASRC_CFG_ERR_EINT2 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */
4461#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */
4462#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT2 */
4463#define ARIZONA_IM_ASRC_CFG_ERR_EINT2_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT2 */
4464#define ARIZONA_IM_AIF3_ERR_EINT2 0x4000 /* IM_AIF3_ERR_EINT2 */
4465#define ARIZONA_IM_AIF3_ERR_EINT2_MASK 0x4000 /* IM_AIF3_ERR_EINT2 */
4466#define ARIZONA_IM_AIF3_ERR_EINT2_SHIFT 14 /* IM_AIF3_ERR_EINT2 */
4467#define ARIZONA_IM_AIF3_ERR_EINT2_WIDTH 1 /* IM_AIF3_ERR_EINT2 */
4468#define ARIZONA_IM_AIF2_ERR_EINT2 0x2000 /* IM_AIF2_ERR_EINT2 */
4469#define ARIZONA_IM_AIF2_ERR_EINT2_MASK 0x2000 /* IM_AIF2_ERR_EINT2 */
4470#define ARIZONA_IM_AIF2_ERR_EINT2_SHIFT 13 /* IM_AIF2_ERR_EINT2 */
4471#define ARIZONA_IM_AIF2_ERR_EINT2_WIDTH 1 /* IM_AIF2_ERR_EINT2 */
4472#define ARIZONA_IM_AIF1_ERR_EINT2 0x1000 /* IM_AIF1_ERR_EINT2 */
4473#define ARIZONA_IM_AIF1_ERR_EINT2_MASK 0x1000 /* IM_AIF1_ERR_EINT2 */
4474#define ARIZONA_IM_AIF1_ERR_EINT2_SHIFT 12 /* IM_AIF1_ERR_EINT2 */
4475#define ARIZONA_IM_AIF1_ERR_EINT2_WIDTH 1 /* IM_AIF1_ERR_EINT2 */
4476#define ARIZONA_IM_CTRLIF_ERR_EINT2 0x0800 /* IM_CTRLIF_ERR_EINT2 */
4477#define ARIZONA_IM_CTRLIF_ERR_EINT2_MASK 0x0800 /* IM_CTRLIF_ERR_EINT2 */
4478#define ARIZONA_IM_CTRLIF_ERR_EINT2_SHIFT 11 /* IM_CTRLIF_ERR_EINT2 */
4479#define ARIZONA_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */
4480#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
4481#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
4482#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
4483#define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
4484#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
4485#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
4486#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
4487#define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
4488#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */
4489#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */
4490#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT2 */
4491#define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT2 */
4492#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */
4493#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */
4494#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT2 */
4495#define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT2 */
4496#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */
4497#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */
4498#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT2 */
4499#define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */
4500
4501/*
4502 * R3356 (0xD1C) - IRQ2 Status 5 Mask
4503 */
4504
4505#define ARIZONA_IM_BOOT_DONE_EINT2 0x0100 /* IM_BOOT_DONE_EINT2 */
4506#define ARIZONA_IM_BOOT_DONE_EINT2_MASK 0x0100 /* IM_BOOT_DONE_EINT2 */
4507#define ARIZONA_IM_BOOT_DONE_EINT2_SHIFT 8 /* IM_BOOT_DONE_EINT2 */
4508#define ARIZONA_IM_BOOT_DONE_EINT2_WIDTH 1 /* IM_BOOT_DONE_EINT2 */
4509#define ARIZONA_IM_DCS_DAC_DONE_EINT2 0x0080 /* IM_DCS_DAC_DONE_EINT2 */
4510#define ARIZONA_IM_DCS_DAC_DONE_EINT2_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT2 */
4511#define ARIZONA_IM_DCS_DAC_DONE_EINT2_SHIFT 7 /* IM_DCS_DAC_DONE_EINT2 */
4512#define ARIZONA_IM_DCS_DAC_DONE_EINT2_WIDTH 1 /* IM_DCS_DAC_DONE_EINT2 */
4513#define ARIZONA_IM_DCS_HP_DONE_EINT2 0x0040 /* IM_DCS_HP_DONE_EINT2 */
4514#define ARIZONA_IM_DCS_HP_DONE_EINT2_MASK 0x0040 /* IM_DCS_HP_DONE_EINT2 */
4515#define ARIZONA_IM_DCS_HP_DONE_EINT2_SHIFT 6 /* IM_DCS_HP_DONE_EINT2 */
4516#define ARIZONA_IM_DCS_HP_DONE_EINT2_WIDTH 1 /* IM_DCS_HP_DONE_EINT2 */
4517#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */
4518#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */
4519#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT2 */
4520#define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT2 */
4521#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */
4522#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */
4523#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT2 */
4524#define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT2 */
4525
4526/*
4527 * R3359 (0xD1F) - IRQ2 Control
4528 */
4529#define ARIZONA_IM_IRQ2 0x0001 /* IM_IRQ2 */
4530#define ARIZONA_IM_IRQ2_MASK 0x0001 /* IM_IRQ2 */
4531#define ARIZONA_IM_IRQ2_SHIFT 0 /* IM_IRQ2 */
4532#define ARIZONA_IM_IRQ2_WIDTH 1 /* IM_IRQ2 */
4533
4534/*
4535 * R3360 (0xD20) - Interrupt Raw Status 2
4536 */
4537#define ARIZONA_DSP1_RAM_RDY_STS 0x0100 /* DSP1_RAM_RDY_STS */
4538#define ARIZONA_DSP1_RAM_RDY_STS_MASK 0x0100 /* DSP1_RAM_RDY_STS */
4539#define ARIZONA_DSP1_RAM_RDY_STS_SHIFT 8 /* DSP1_RAM_RDY_STS */
4540#define ARIZONA_DSP1_RAM_RDY_STS_WIDTH 1 /* DSP1_RAM_RDY_STS */
4541#define ARIZONA_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */
4542#define ARIZONA_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */
4543#define ARIZONA_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */
4544#define ARIZONA_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */
4545#define ARIZONA_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */
4546#define ARIZONA_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */
4547#define ARIZONA_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */
4548#define ARIZONA_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */
4549
4550/*
4551 * R3361 (0xD21) - Interrupt Raw Status 3
4552 */
4553#define ARIZONA_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */
4554#define ARIZONA_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */
4555#define ARIZONA_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */
4556#define ARIZONA_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */
4557#define ARIZONA_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */
4558#define ARIZONA_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */
4559#define ARIZONA_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */
4560#define ARIZONA_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */
4561#define ARIZONA_HPDET_STS 0x2000 /* HPDET_STS */
4562#define ARIZONA_HPDET_STS_MASK 0x2000 /* HPDET_STS */
4563#define ARIZONA_HPDET_STS_SHIFT 13 /* HPDET_STS */
4564#define ARIZONA_HPDET_STS_WIDTH 1 /* HPDET_STS */
4565#define ARIZONA_MICDET_STS 0x1000 /* MICDET_STS */
4566#define ARIZONA_MICDET_STS_MASK 0x1000 /* MICDET_STS */
4567#define ARIZONA_MICDET_STS_SHIFT 12 /* MICDET_STS */
4568#define ARIZONA_MICDET_STS_WIDTH 1 /* MICDET_STS */
4569#define ARIZONA_WSEQ_DONE_STS 0x0800 /* WSEQ_DONE_STS */
4570#define ARIZONA_WSEQ_DONE_STS_MASK 0x0800 /* WSEQ_DONE_STS */
4571#define ARIZONA_WSEQ_DONE_STS_SHIFT 11 /* WSEQ_DONE_STS */
4572#define ARIZONA_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
4573#define ARIZONA_DRC2_SIG_DET_STS 0x0400 /* DRC2_SIG_DET_STS */
4574#define ARIZONA_DRC2_SIG_DET_STS_MASK 0x0400 /* DRC2_SIG_DET_STS */
4575#define ARIZONA_DRC2_SIG_DET_STS_SHIFT 10 /* DRC2_SIG_DET_STS */
4576#define ARIZONA_DRC2_SIG_DET_STS_WIDTH 1 /* DRC2_SIG_DET_STS */
4577#define ARIZONA_DRC1_SIG_DET_STS 0x0200 /* DRC1_SIG_DET_STS */
4578#define ARIZONA_DRC1_SIG_DET_STS_MASK 0x0200 /* DRC1_SIG_DET_STS */
4579#define ARIZONA_DRC1_SIG_DET_STS_SHIFT 9 /* DRC1_SIG_DET_STS */
4580#define ARIZONA_DRC1_SIG_DET_STS_WIDTH 1 /* DRC1_SIG_DET_STS */
4581#define ARIZONA_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */
4582#define ARIZONA_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */
4583#define ARIZONA_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */
4584#define ARIZONA_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */
4585#define ARIZONA_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */
4586#define ARIZONA_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */
4587#define ARIZONA_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */
4588#define ARIZONA_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */
4589#define ARIZONA_UNDERCLOCKED_STS 0x0040 /* UNDERCLOCKED_STS */
4590#define ARIZONA_UNDERCLOCKED_STS_MASK 0x0040 /* UNDERCLOCKED_STS */
4591#define ARIZONA_UNDERCLOCKED_STS_SHIFT 6 /* UNDERCLOCKED_STS */
4592#define ARIZONA_UNDERCLOCKED_STS_WIDTH 1 /* UNDERCLOCKED_STS */
4593#define ARIZONA_OVERCLOCKED_STS 0x0020 /* OVERCLOCKED_STS */
4594#define ARIZONA_OVERCLOCKED_STS_MASK 0x0020 /* OVERCLOCKED_STS */
4595#define ARIZONA_OVERCLOCKED_STS_SHIFT 5 /* OVERCLOCKED_STS */
4596#define ARIZONA_OVERCLOCKED_STS_WIDTH 1 /* OVERCLOCKED_STS */
4597#define ARIZONA_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */
4598#define ARIZONA_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */
4599#define ARIZONA_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */
4600#define ARIZONA_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
4601#define ARIZONA_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */
4602#define ARIZONA_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */
4603#define ARIZONA_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */
4604#define ARIZONA_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
4605#define ARIZONA_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */
4606#define ARIZONA_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */
4607#define ARIZONA_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */
4608#define ARIZONA_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */
4609#define ARIZONA_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */
4610#define ARIZONA_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */
4611#define ARIZONA_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */
4612#define ARIZONA_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */
4613
4614/*
4615 * R3362 (0xD22) - Interrupt Raw Status 4
4616 */
4617#define ARIZONA_ASRC_CFG_ERR_STS 0x8000 /* ASRC_CFG_ERR_STS */
4618#define ARIZONA_ASRC_CFG_ERR_STS_MASK 0x8000 /* ASRC_CFG_ERR_STS */
4619#define ARIZONA_ASRC_CFG_ERR_STS_SHIFT 15 /* ASRC_CFG_ERR_STS */
4620#define ARIZONA_ASRC_CFG_ERR_STS_WIDTH 1 /* ASRC_CFG_ERR_STS */
4621#define ARIZONA_AIF3_ERR_STS 0x4000 /* AIF3_ERR_STS */
4622#define ARIZONA_AIF3_ERR_STS_MASK 0x4000 /* AIF3_ERR_STS */
4623#define ARIZONA_AIF3_ERR_STS_SHIFT 14 /* AIF3_ERR_STS */
4624#define ARIZONA_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */
4625#define ARIZONA_AIF2_ERR_STS 0x2000 /* AIF2_ERR_STS */
4626#define ARIZONA_AIF2_ERR_STS_MASK 0x2000 /* AIF2_ERR_STS */
4627#define ARIZONA_AIF2_ERR_STS_SHIFT 13 /* AIF2_ERR_STS */
4628#define ARIZONA_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */
4629#define ARIZONA_AIF1_ERR_STS 0x1000 /* AIF1_ERR_STS */
4630#define ARIZONA_AIF1_ERR_STS_MASK 0x1000 /* AIF1_ERR_STS */
4631#define ARIZONA_AIF1_ERR_STS_SHIFT 12 /* AIF1_ERR_STS */
4632#define ARIZONA_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */
4633#define ARIZONA_CTRLIF_ERR_STS 0x0800 /* CTRLIF_ERR_STS */
4634#define ARIZONA_CTRLIF_ERR_STS_MASK 0x0800 /* CTRLIF_ERR_STS */
4635#define ARIZONA_CTRLIF_ERR_STS_SHIFT 11 /* CTRLIF_ERR_STS */
4636#define ARIZONA_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */
4637#define ARIZONA_MIXER_DROPPED_SAMPLE_STS 0x0400 /* MIXER_DROPPED_SAMPLE_STS */
4638#define ARIZONA_MIXER_DROPPED_SAMPLE_STS_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_STS */
4639#define ARIZONA_MIXER_DROPPED_SAMPLE_STS_SHIFT 10 /* MIXER_DROPPED_SAMPLE_STS */
4640#define ARIZONA_MIXER_DROPPED_SAMPLE_STS_WIDTH 1 /* MIXER_DROPPED_SAMPLE_STS */
4641#define ARIZONA_ASYNC_CLK_ENA_LOW_STS 0x0200 /* ASYNC_CLK_ENA_LOW_STS */
4642#define ARIZONA_ASYNC_CLK_ENA_LOW_STS_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_STS */
4643#define ARIZONA_ASYNC_CLK_ENA_LOW_STS_SHIFT 9 /* ASYNC_CLK_ENA_LOW_STS */
4644#define ARIZONA_ASYNC_CLK_ENA_LOW_STS_WIDTH 1 /* ASYNC_CLK_ENA_LOW_STS */
4645#define ARIZONA_SYSCLK_ENA_LOW_STS 0x0100 /* SYSCLK_ENA_LOW_STS */
4646#define ARIZONA_SYSCLK_ENA_LOW_STS_MASK 0x0100 /* SYSCLK_ENA_LOW_STS */
4647#define ARIZONA_SYSCLK_ENA_LOW_STS_SHIFT 8 /* SYSCLK_ENA_LOW_STS */
4648#define ARIZONA_SYSCLK_ENA_LOW_STS_WIDTH 1 /* SYSCLK_ENA_LOW_STS */
4649#define ARIZONA_ISRC1_CFG_ERR_STS 0x0080 /* ISRC1_CFG_ERR_STS */
4650#define ARIZONA_ISRC1_CFG_ERR_STS_MASK 0x0080 /* ISRC1_CFG_ERR_STS */
4651#define ARIZONA_ISRC1_CFG_ERR_STS_SHIFT 7 /* ISRC1_CFG_ERR_STS */
4652#define ARIZONA_ISRC1_CFG_ERR_STS_WIDTH 1 /* ISRC1_CFG_ERR_STS */
4653#define ARIZONA_ISRC2_CFG_ERR_STS 0x0040 /* ISRC2_CFG_ERR_STS */
4654#define ARIZONA_ISRC2_CFG_ERR_STS_MASK 0x0040 /* ISRC2_CFG_ERR_STS */
4655#define ARIZONA_ISRC2_CFG_ERR_STS_SHIFT 6 /* ISRC2_CFG_ERR_STS */
4656#define ARIZONA_ISRC2_CFG_ERR_STS_WIDTH 1 /* ISRC2_CFG_ERR_STS */
4657
4658/*
4659 * R3363 (0xD23) - Interrupt Raw Status 5
4660 */
4661#define ARIZONA_BOOT_DONE_STS 0x0100 /* BOOT_DONE_STS */
4662#define ARIZONA_BOOT_DONE_STS_MASK 0x0100 /* BOOT_DONE_STS */
4663#define ARIZONA_BOOT_DONE_STS_SHIFT 8 /* BOOT_DONE_STS */
4664#define ARIZONA_BOOT_DONE_STS_WIDTH 1 /* BOOT_DONE_STS */
4665#define ARIZONA_DCS_DAC_DONE_STS 0x0080 /* DCS_DAC_DONE_STS */
4666#define ARIZONA_DCS_DAC_DONE_STS_MASK 0x0080 /* DCS_DAC_DONE_STS */
4667#define ARIZONA_DCS_DAC_DONE_STS_SHIFT 7 /* DCS_DAC_DONE_STS */
4668#define ARIZONA_DCS_DAC_DONE_STS_WIDTH 1 /* DCS_DAC_DONE_STS */
4669#define ARIZONA_DCS_HP_DONE_STS 0x0040 /* DCS_HP_DONE_STS */
4670#define ARIZONA_DCS_HP_DONE_STS_MASK 0x0040 /* DCS_HP_DONE_STS */
4671#define ARIZONA_DCS_HP_DONE_STS_SHIFT 6 /* DCS_HP_DONE_STS */
4672#define ARIZONA_DCS_HP_DONE_STS_WIDTH 1 /* DCS_HP_DONE_STS */
4673#define ARIZONA_FLL2_CLOCK_OK_STS 0x0002 /* FLL2_CLOCK_OK_STS */
4674#define ARIZONA_FLL2_CLOCK_OK_STS_MASK 0x0002 /* FLL2_CLOCK_OK_STS */
4675#define ARIZONA_FLL2_CLOCK_OK_STS_SHIFT 1 /* FLL2_CLOCK_OK_STS */
4676#define ARIZONA_FLL2_CLOCK_OK_STS_WIDTH 1 /* FLL2_CLOCK_OK_STS */
4677#define ARIZONA_FLL1_CLOCK_OK_STS 0x0001 /* FLL1_CLOCK_OK_STS */
4678#define ARIZONA_FLL1_CLOCK_OK_STS_MASK 0x0001 /* FLL1_CLOCK_OK_STS */
4679#define ARIZONA_FLL1_CLOCK_OK_STS_SHIFT 0 /* FLL1_CLOCK_OK_STS */
4680#define ARIZONA_FLL1_CLOCK_OK_STS_WIDTH 1 /* FLL1_CLOCK_OK_STS */
4681
4682/*
4683 * R3364 (0xD24) - Interrupt Raw Status 6
4684 */
4685#define ARIZONA_PWM_OVERCLOCKED_STS 0x2000 /* PWM_OVERCLOCKED_STS */
4686#define ARIZONA_PWM_OVERCLOCKED_STS_MASK 0x2000 /* PWM_OVERCLOCKED_STS */
4687#define ARIZONA_PWM_OVERCLOCKED_STS_SHIFT 13 /* PWM_OVERCLOCKED_STS */
4688#define ARIZONA_PWM_OVERCLOCKED_STS_WIDTH 1 /* PWM_OVERCLOCKED_STS */
4689#define ARIZONA_FX_CORE_OVERCLOCKED_STS 0x1000 /* FX_CORE_OVERCLOCKED_STS */
4690#define ARIZONA_FX_CORE_OVERCLOCKED_STS_MASK 0x1000 /* FX_CORE_OVERCLOCKED_STS */
4691#define ARIZONA_FX_CORE_OVERCLOCKED_STS_SHIFT 12 /* FX_CORE_OVERCLOCKED_STS */
4692#define ARIZONA_FX_CORE_OVERCLOCKED_STS_WIDTH 1 /* FX_CORE_OVERCLOCKED_STS */
4693#define ARIZONA_DAC_SYS_OVERCLOCKED_STS 0x0400 /* DAC_SYS_OVERCLOCKED_STS */
4694#define ARIZONA_DAC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* DAC_SYS_OVERCLOCKED_STS */
4695#define ARIZONA_DAC_SYS_OVERCLOCKED_STS_SHIFT 10 /* DAC_SYS_OVERCLOCKED_STS */
4696#define ARIZONA_DAC_SYS_OVERCLOCKED_STS_WIDTH 1 /* DAC_SYS_OVERCLOCKED_STS */
4697#define ARIZONA_DAC_WARP_OVERCLOCKED_STS 0x0200 /* DAC_WARP_OVERCLOCKED_STS */
4698#define ARIZONA_DAC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* DAC_WARP_OVERCLOCKED_STS */
4699#define ARIZONA_DAC_WARP_OVERCLOCKED_STS_SHIFT 9 /* DAC_WARP_OVERCLOCKED_STS */
4700#define ARIZONA_DAC_WARP_OVERCLOCKED_STS_WIDTH 1 /* DAC_WARP_OVERCLOCKED_STS */
4701#define ARIZONA_ADC_OVERCLOCKED_STS 0x0100 /* ADC_OVERCLOCKED_STS */
4702#define ARIZONA_ADC_OVERCLOCKED_STS_MASK 0x0100 /* ADC_OVERCLOCKED_STS */
4703#define ARIZONA_ADC_OVERCLOCKED_STS_SHIFT 8 /* ADC_OVERCLOCKED_STS */
4704#define ARIZONA_ADC_OVERCLOCKED_STS_WIDTH 1 /* ADC_OVERCLOCKED_STS */
4705#define ARIZONA_MIXER_OVERCLOCKED_STS 0x0080 /* MIXER_OVERCLOCKED_STS */
4706#define ARIZONA_MIXER_OVERCLOCKED_STS_MASK 0x0080 /* MIXER_OVERCLOCKED_STS */
4707#define ARIZONA_MIXER_OVERCLOCKED_STS_SHIFT 7 /* MIXER_OVERCLOCKED_STS */
4708#define ARIZONA_MIXER_OVERCLOCKED_STS_WIDTH 1 /* MIXER_OVERCLOCKED_STS */
4709#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */
4710#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_MASK 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */
4711#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_SHIFT 6 /* AIF3_ASYNC_OVERCLOCKED_STS */
4712#define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_ASYNC_OVERCLOCKED_STS */
4713#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */
4714#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_MASK 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */
4715#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_SHIFT 5 /* AIF2_ASYNC_OVERCLOCKED_STS */
4716#define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_ASYNC_OVERCLOCKED_STS */
4717#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */
4718#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_MASK 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */
4719#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_SHIFT 4 /* AIF1_ASYNC_OVERCLOCKED_STS */
4720#define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_ASYNC_OVERCLOCKED_STS */
4721#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */
4722#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_MASK 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */
4723#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_SHIFT 3 /* AIF3_SYNC_OVERCLOCKED_STS */
4724#define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_SYNC_OVERCLOCKED_STS */
4725#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */
4726#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_MASK 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */
4727#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_SHIFT 2 /* AIF2_SYNC_OVERCLOCKED_STS */
4728#define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_SYNC_OVERCLOCKED_STS */
4729#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */
4730#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_MASK 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */
4731#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_SHIFT 1 /* AIF1_SYNC_OVERCLOCKED_STS */
4732#define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_SYNC_OVERCLOCKED_STS */
4733#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */
4734#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_MASK 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */
4735#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_SHIFT 0 /* PAD_CTRL_OVERCLOCKED_STS */
4736#define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_WIDTH 1 /* PAD_CTRL_OVERCLOCKED_STS */
4737
4738/*
4739 * R3365 (0xD25) - Interrupt Raw Status 7
4740 */
4741#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
4742#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_MASK 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
4743#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_SHIFT 15 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
4744#define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
4745#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
4746#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_MASK 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
4747#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_SHIFT 14 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
4748#define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
4749#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
4750#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_MASK 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
4751#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_SHIFT 13 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
4752#define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
4753#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
4754#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_MASK 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
4755#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_SHIFT 12 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
4756#define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
4757#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
4758#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_MASK 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
4759#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_SHIFT 11 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
4760#define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
4761#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
4762#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
4763#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_SHIFT 10 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
4764#define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
4765#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
4766#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
4767#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_SHIFT 9 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
4768#define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
4769#define ARIZONA_ADSP2_1_OVERCLOCKED_STS 0x0008 /* ADSP2_1_OVERCLOCKED_STS */
4770#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_MASK 0x0008 /* ADSP2_1_OVERCLOCKED_STS */
4771#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_SHIFT 3 /* ADSP2_1_OVERCLOCKED_STS */
4772#define ARIZONA_ADSP2_1_OVERCLOCKED_STS_WIDTH 1 /* ADSP2_1_OVERCLOCKED_STS */
4773#define ARIZONA_ISRC2_OVERCLOCKED_STS 0x0002 /* ISRC2_OVERCLOCKED_STS */
4774#define ARIZONA_ISRC2_OVERCLOCKED_STS_MASK 0x0002 /* ISRC2_OVERCLOCKED_STS */
4775#define ARIZONA_ISRC2_OVERCLOCKED_STS_SHIFT 1 /* ISRC2_OVERCLOCKED_STS */
4776#define ARIZONA_ISRC2_OVERCLOCKED_STS_WIDTH 1 /* ISRC2_OVERCLOCKED_STS */
4777#define ARIZONA_ISRC1_OVERCLOCKED_STS 0x0001 /* ISRC1_OVERCLOCKED_STS */
4778#define ARIZONA_ISRC1_OVERCLOCKED_STS_MASK 0x0001 /* ISRC1_OVERCLOCKED_STS */
4779#define ARIZONA_ISRC1_OVERCLOCKED_STS_SHIFT 0 /* ISRC1_OVERCLOCKED_STS */
4780#define ARIZONA_ISRC1_OVERCLOCKED_STS_WIDTH 1 /* ISRC1_OVERCLOCKED_STS */
4781
4782/*
4783 * R3366 (0xD26) - Interrupt Raw Status 8
4784 */
4785#define ARIZONA_AIF3_UNDERCLOCKED_STS 0x0400 /* AIF3_UNDERCLOCKED_STS */
4786#define ARIZONA_AIF3_UNDERCLOCKED_STS_MASK 0x0400 /* AIF3_UNDERCLOCKED_STS */
4787#define ARIZONA_AIF3_UNDERCLOCKED_STS_SHIFT 10 /* AIF3_UNDERCLOCKED_STS */
4788#define ARIZONA_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */
4789#define ARIZONA_AIF2_UNDERCLOCKED_STS 0x0200 /* AIF2_UNDERCLOCKED_STS */
4790#define ARIZONA_AIF2_UNDERCLOCKED_STS_MASK 0x0200 /* AIF2_UNDERCLOCKED_STS */
4791#define ARIZONA_AIF2_UNDERCLOCKED_STS_SHIFT 9 /* AIF2_UNDERCLOCKED_STS */
4792#define ARIZONA_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */
4793#define ARIZONA_AIF1_UNDERCLOCKED_STS 0x0100 /* AIF1_UNDERCLOCKED_STS */
4794#define ARIZONA_AIF1_UNDERCLOCKED_STS_MASK 0x0100 /* AIF1_UNDERCLOCKED_STS */
4795#define ARIZONA_AIF1_UNDERCLOCKED_STS_SHIFT 8 /* AIF1_UNDERCLOCKED_STS */
4796#define ARIZONA_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */
4797#define ARIZONA_ISRC2_UNDERCLOCKED_STS 0x0040 /* ISRC2_UNDERCLOCKED_STS */
4798#define ARIZONA_ISRC2_UNDERCLOCKED_STS_MASK 0x0040 /* ISRC2_UNDERCLOCKED_STS */
4799#define ARIZONA_ISRC2_UNDERCLOCKED_STS_SHIFT 6 /* ISRC2_UNDERCLOCKED_STS */
4800#define ARIZONA_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */
4801#define ARIZONA_ISRC1_UNDERCLOCKED_STS 0x0020 /* ISRC1_UNDERCLOCKED_STS */
4802#define ARIZONA_ISRC1_UNDERCLOCKED_STS_MASK 0x0020 /* ISRC1_UNDERCLOCKED_STS */
4803#define ARIZONA_ISRC1_UNDERCLOCKED_STS_SHIFT 5 /* ISRC1_UNDERCLOCKED_STS */
4804#define ARIZONA_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */
4805#define ARIZONA_FX_UNDERCLOCKED_STS 0x0010 /* FX_UNDERCLOCKED_STS */
4806#define ARIZONA_FX_UNDERCLOCKED_STS_MASK 0x0010 /* FX_UNDERCLOCKED_STS */
4807#define ARIZONA_FX_UNDERCLOCKED_STS_SHIFT 4 /* FX_UNDERCLOCKED_STS */
4808#define ARIZONA_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */
4809#define ARIZONA_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */
4810#define ARIZONA_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */
4811#define ARIZONA_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */
4812#define ARIZONA_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */
4813#define ARIZONA_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */
4814#define ARIZONA_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */
4815#define ARIZONA_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */
4816#define ARIZONA_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */
4817#define ARIZONA_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */
4818#define ARIZONA_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */
4819#define ARIZONA_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */
4820#define ARIZONA_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */
4821#define ARIZONA_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */
4822#define ARIZONA_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */
4823#define ARIZONA_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */
4824#define ARIZONA_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */
4825
4826/*
4827 * R3392 (0xD40) - IRQ Pin Status
4828 */
4829#define ARIZONA_IRQ2_STS 0x0002 /* IRQ2_STS */
4830#define ARIZONA_IRQ2_STS_MASK 0x0002 /* IRQ2_STS */
4831#define ARIZONA_IRQ2_STS_SHIFT 1 /* IRQ2_STS */
4832#define ARIZONA_IRQ2_STS_WIDTH 1 /* IRQ2_STS */
4833#define ARIZONA_IRQ1_STS 0x0001 /* IRQ1_STS */
4834#define ARIZONA_IRQ1_STS_MASK 0x0001 /* IRQ1_STS */
4835#define ARIZONA_IRQ1_STS_SHIFT 0 /* IRQ1_STS */
4836#define ARIZONA_IRQ1_STS_WIDTH 1 /* IRQ1_STS */
4837
4838/*
4839 * R3393 (0xD41) - ADSP2 IRQ0
4840 */
4841#define ARIZONA_DSP_IRQ2 0x0002 /* DSP_IRQ2 */
4842#define ARIZONA_DSP_IRQ2_MASK 0x0002 /* DSP_IRQ2 */
4843#define ARIZONA_DSP_IRQ2_SHIFT 1 /* DSP_IRQ2 */
4844#define ARIZONA_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */
4845#define ARIZONA_DSP_IRQ1 0x0001 /* DSP_IRQ1 */
4846#define ARIZONA_DSP_IRQ1_MASK 0x0001 /* DSP_IRQ1 */
4847#define ARIZONA_DSP_IRQ1_SHIFT 0 /* DSP_IRQ1 */
4848#define ARIZONA_DSP_IRQ1_WIDTH 1 /* DSP_IRQ1 */
4849
4850/*
4851 * R3408 (0xD50) - AOD wkup and trig
4852 */
4853#define ARIZONA_GP5_FALL_TRIG_STS 0x0020 /* GP5_FALL_TRIG_STS */
4854#define ARIZONA_GP5_FALL_TRIG_STS_MASK 0x0020 /* GP5_FALL_TRIG_STS */
4855#define ARIZONA_GP5_FALL_TRIG_STS_SHIFT 5 /* GP5_FALL_TRIG_STS */
4856#define ARIZONA_GP5_FALL_TRIG_STS_WIDTH 1 /* GP5_FALL_TRIG_STS */
4857#define ARIZONA_GP5_RISE_TRIG_STS 0x0010 /* GP5_RISE_TRIG_STS */
4858#define ARIZONA_GP5_RISE_TRIG_STS_MASK 0x0010 /* GP5_RISE_TRIG_STS */
4859#define ARIZONA_GP5_RISE_TRIG_STS_SHIFT 4 /* GP5_RISE_TRIG_STS */
4860#define ARIZONA_GP5_RISE_TRIG_STS_WIDTH 1 /* GP5_RISE_TRIG_STS */
4861#define ARIZONA_JD1_FALL_TRIG_STS 0x0008 /* JD1_FALL_TRIG_STS */
4862#define ARIZONA_JD1_FALL_TRIG_STS_MASK 0x0008 /* JD1_FALL_TRIG_STS */
4863#define ARIZONA_JD1_FALL_TRIG_STS_SHIFT 3 /* JD1_FALL_TRIG_STS */
4864#define ARIZONA_JD1_FALL_TRIG_STS_WIDTH 1 /* JD1_FALL_TRIG_STS */
4865#define ARIZONA_JD1_RISE_TRIG_STS 0x0004 /* JD1_RISE_TRIG_STS */
4866#define ARIZONA_JD1_RISE_TRIG_STS_MASK 0x0004 /* JD1_RISE_TRIG_STS */
4867#define ARIZONA_JD1_RISE_TRIG_STS_SHIFT 2 /* JD1_RISE_TRIG_STS */
4868#define ARIZONA_JD1_RISE_TRIG_STS_WIDTH 1 /* JD1_RISE_TRIG_STS */
4869#define ARIZONA_JD2_FALL_TRIG_STS 0x0002 /* JD2_FALL_TRIG_STS */
4870#define ARIZONA_JD2_FALL_TRIG_STS_MASK 0x0002 /* JD2_FALL_TRIG_STS */
4871#define ARIZONA_JD2_FALL_TRIG_STS_SHIFT 1 /* JD2_FALL_TRIG_STS */
4872#define ARIZONA_JD2_FALL_TRIG_STS_WIDTH 1 /* JD2_FALL_TRIG_STS */
4873#define ARIZONA_JD2_RISE_TRIG_STS 0x0001 /* JD2_RISE_TRIG_STS */
4874#define ARIZONA_JD2_RISE_TRIG_STS_MASK 0x0001 /* JD2_RISE_TRIG_STS */
4875#define ARIZONA_JD2_RISE_TRIG_STS_SHIFT 0 /* JD2_RISE_TRIG_STS */
4876#define ARIZONA_JD2_RISE_TRIG_STS_WIDTH 1 /* JD2_RISE_TRIG_STS */
4877
4878/*
4879 * R3409 (0xD51) - AOD IRQ1
4880 */
4881#define ARIZONA_GP5_FALL_EINT1 0x0020 /* GP5_FALL_EINT1 */
4882#define ARIZONA_GP5_FALL_EINT1_MASK 0x0020 /* GP5_FALL_EINT1 */
4883#define ARIZONA_GP5_FALL_EINT1_SHIFT 5 /* GP5_FALL_EINT1 */
4884#define ARIZONA_GP5_FALL_EINT1_WIDTH 1 /* GP5_FALL_EINT1 */
4885#define ARIZONA_GP5_RISE_EINT1 0x0010 /* GP5_RISE_EINT1 */
4886#define ARIZONA_GP5_RISE_EINT1_MASK 0x0010 /* GP5_RISE_EINT1 */
4887#define ARIZONA_GP5_RISE_EINT1_SHIFT 4 /* GP5_RISE_EINT1 */
4888#define ARIZONA_GP5_RISE_EINT1_WIDTH 1 /* GP5_RISE_EINT1 */
4889#define ARIZONA_JD1_FALL_EINT1 0x0008 /* JD1_FALL_EINT1 */
4890#define ARIZONA_JD1_FALL_EINT1_MASK 0x0008 /* JD1_FALL_EINT1 */
4891#define ARIZONA_JD1_FALL_EINT1_SHIFT 3 /* JD1_FALL_EINT1 */
4892#define ARIZONA_JD1_FALL_EINT1_WIDTH 1 /* JD1_FALL_EINT1 */
4893#define ARIZONA_JD1_RISE_EINT1 0x0004 /* JD1_RISE_EINT1 */
4894#define ARIZONA_JD1_RISE_EINT1_MASK 0x0004 /* JD1_RISE_EINT1 */
4895#define ARIZONA_JD1_RISE_EINT1_SHIFT 2 /* JD1_RISE_EINT1 */
4896#define ARIZONA_JD1_RISE_EINT1_WIDTH 1 /* JD1_RISE_EINT1 */
4897#define ARIZONA_JD2_FALL_EINT1 0x0002 /* JD2_FALL_EINT1 */
4898#define ARIZONA_JD2_FALL_EINT1_MASK 0x0002 /* JD2_FALL_EINT1 */
4899#define ARIZONA_JD2_FALL_EINT1_SHIFT 1 /* JD2_FALL_EINT1 */
4900#define ARIZONA_JD2_FALL_EINT1_WIDTH 1 /* JD2_FALL_EINT1 */
4901#define ARIZONA_JD2_RISE_EINT1 0x0001 /* JD2_RISE_EINT1 */
4902#define ARIZONA_JD2_RISE_EINT1_MASK 0x0001 /* JD2_RISE_EINT1 */
4903#define ARIZONA_JD2_RISE_EINT1_SHIFT 0 /* JD2_RISE_EINT1 */
4904#define ARIZONA_JD2_RISE_EINT1_WIDTH 1 /* JD2_RISE_EINT1 */
4905
4906/*
4907 * R3410 (0xD52) - AOD IRQ2
4908 */
4909#define ARIZONA_GP5_FALL_EINT2 0x0020 /* GP5_FALL_EINT2 */
4910#define ARIZONA_GP5_FALL_EINT2_MASK 0x0020 /* GP5_FALL_EINT2 */
4911#define ARIZONA_GP5_FALL_EINT2_SHIFT 5 /* GP5_FALL_EINT2 */
4912#define ARIZONA_GP5_FALL_EINT2_WIDTH 1 /* GP5_FALL_EINT2 */
4913#define ARIZONA_GP5_RISE_EINT2 0x0010 /* GP5_RISE_EINT2 */
4914#define ARIZONA_GP5_RISE_EINT2_MASK 0x0010 /* GP5_RISE_EINT2 */
4915#define ARIZONA_GP5_RISE_EINT2_SHIFT 4 /* GP5_RISE_EINT2 */
4916#define ARIZONA_GP5_RISE_EINT2_WIDTH 1 /* GP5_RISE_EINT2 */
4917#define ARIZONA_JD1_FALL_EINT2 0x0008 /* JD1_FALL_EINT2 */
4918#define ARIZONA_JD1_FALL_EINT2_MASK 0x0008 /* JD1_FALL_EINT2 */
4919#define ARIZONA_JD1_FALL_EINT2_SHIFT 3 /* JD1_FALL_EINT2 */
4920#define ARIZONA_JD1_FALL_EINT2_WIDTH 1 /* JD1_FALL_EINT2 */
4921#define ARIZONA_JD1_RISE_EINT2 0x0004 /* JD1_RISE_EINT2 */
4922#define ARIZONA_JD1_RISE_EINT2_MASK 0x0004 /* JD1_RISE_EINT2 */
4923#define ARIZONA_JD1_RISE_EINT2_SHIFT 2 /* JD1_RISE_EINT2 */
4924#define ARIZONA_JD1_RISE_EINT2_WIDTH 1 /* JD1_RISE_EINT2 */
4925#define ARIZONA_JD2_FALL_EINT2 0x0002 /* JD2_FALL_EINT2 */
4926#define ARIZONA_JD2_FALL_EINT2_MASK 0x0002 /* JD2_FALL_EINT2 */
4927#define ARIZONA_JD2_FALL_EINT2_SHIFT 1 /* JD2_FALL_EINT2 */
4928#define ARIZONA_JD2_FALL_EINT2_WIDTH 1 /* JD2_FALL_EINT2 */
4929#define ARIZONA_JD2_RISE_EINT2 0x0001 /* JD2_RISE_EINT2 */
4930#define ARIZONA_JD2_RISE_EINT2_MASK 0x0001 /* JD2_RISE_EINT2 */
4931#define ARIZONA_JD2_RISE_EINT2_SHIFT 0 /* JD2_RISE_EINT2 */
4932#define ARIZONA_JD2_RISE_EINT2_WIDTH 1 /* JD2_RISE_EINT2 */
4933
4934/*
4935 * R3411 (0xD53) - AOD IRQ Mask IRQ1
4936 */
4937#define ARIZONA_IM_GP5_FALL_EINT1 0x0020 /* IM_GP5_FALL_EINT1 */
4938#define ARIZONA_IM_GP5_FALL_EINT1_MASK 0x0020 /* IM_GP5_FALL_EINT1 */
4939#define ARIZONA_IM_GP5_FALL_EINT1_SHIFT 5 /* IM_GP5_FALL_EINT1 */
4940#define ARIZONA_IM_GP5_FALL_EINT1_WIDTH 1 /* IM_GP5_FALL_EINT1 */
4941#define ARIZONA_IM_GP5_RISE_EINT1 0x0010 /* IM_GP5_RISE_EINT1 */
4942#define ARIZONA_IM_GP5_RISE_EINT1_MASK 0x0010 /* IM_GP5_RISE_EINT1 */
4943#define ARIZONA_IM_GP5_RISE_EINT1_SHIFT 4 /* IM_GP5_RISE_EINT1 */
4944#define ARIZONA_IM_GP5_RISE_EINT1_WIDTH 1 /* IM_GP5_RISE_EINT1 */
4945#define ARIZONA_IM_JD1_FALL_EINT1 0x0008 /* IM_JD1_FALL_EINT1 */
4946#define ARIZONA_IM_JD1_FALL_EINT1_MASK 0x0008 /* IM_JD1_FALL_EINT1 */
4947#define ARIZONA_IM_JD1_FALL_EINT1_SHIFT 3 /* IM_JD1_FALL_EINT1 */
4948#define ARIZONA_IM_JD1_FALL_EINT1_WIDTH 1 /* IM_JD1_FALL_EINT1 */
4949#define ARIZONA_IM_JD1_RISE_EINT1 0x0004 /* IM_JD1_RISE_EINT1 */
4950#define ARIZONA_IM_JD1_RISE_EINT1_MASK 0x0004 /* IM_JD1_RISE_EINT1 */
4951#define ARIZONA_IM_JD1_RISE_EINT1_SHIFT 2 /* IM_JD1_RISE_EINT1 */
4952#define ARIZONA_IM_JD1_RISE_EINT1_WIDTH 1 /* IM_JD1_RISE_EINT1 */
4953#define ARIZONA_IM_JD2_FALL_EINT1 0x0002 /* IM_JD2_FALL_EINT1 */
4954#define ARIZONA_IM_JD2_FALL_EINT1_MASK 0x0002 /* IM_JD2_FALL_EINT1 */
4955#define ARIZONA_IM_JD2_FALL_EINT1_SHIFT 1 /* IM_JD2_FALL_EINT1 */
4956#define ARIZONA_IM_JD2_FALL_EINT1_WIDTH 1 /* IM_JD2_FALL_EINT1 */
4957#define ARIZONA_IM_JD2_RISE_EINT1 0x0001 /* IM_JD2_RISE_EINT1 */
4958#define ARIZONA_IM_JD2_RISE_EINT1_MASK 0x0001 /* IM_JD2_RISE_EINT1 */
4959#define ARIZONA_IM_JD2_RISE_EINT1_SHIFT 0 /* IM_JD2_RISE_EINT1 */
4960#define ARIZONA_IM_JD2_RISE_EINT1_WIDTH 1 /* IM_JD2_RISE_EINT1 */
4961
4962/*
4963 * R3412 (0xD54) - AOD IRQ Mask IRQ2
4964 */
4965#define ARIZONA_IM_GP5_FALL_EINT2 0x0020 /* IM_GP5_FALL_EINT2 */
4966#define ARIZONA_IM_GP5_FALL_EINT2_MASK 0x0020 /* IM_GP5_FALL_EINT2 */
4967#define ARIZONA_IM_GP5_FALL_EINT2_SHIFT 5 /* IM_GP5_FALL_EINT2 */
4968#define ARIZONA_IM_GP5_FALL_EINT2_WIDTH 1 /* IM_GP5_FALL_EINT2 */
4969#define ARIZONA_IM_GP5_RISE_EINT2 0x0010 /* IM_GP5_RISE_EINT2 */
4970#define ARIZONA_IM_GP5_RISE_EINT2_MASK 0x0010 /* IM_GP5_RISE_EINT2 */
4971#define ARIZONA_IM_GP5_RISE_EINT2_SHIFT 4 /* IM_GP5_RISE_EINT2 */
4972#define ARIZONA_IM_GP5_RISE_EINT2_WIDTH 1 /* IM_GP5_RISE_EINT2 */
4973#define ARIZONA_IM_JD1_FALL_EINT2 0x0008 /* IM_JD1_FALL_EINT2 */
4974#define ARIZONA_IM_JD1_FALL_EINT2_MASK 0x0008 /* IM_JD1_FALL_EINT2 */
4975#define ARIZONA_IM_JD1_FALL_EINT2_SHIFT 3 /* IM_JD1_FALL_EINT2 */
4976#define ARIZONA_IM_JD1_FALL_EINT2_WIDTH 1 /* IM_JD1_FALL_EINT2 */
4977#define ARIZONA_IM_JD1_RISE_EINT2 0x0004 /* IM_JD1_RISE_EINT2 */
4978#define ARIZONA_IM_JD1_RISE_EINT2_MASK 0x0004 /* IM_JD1_RISE_EINT2 */
4979#define ARIZONA_IM_JD1_RISE_EINT2_SHIFT 2 /* IM_JD1_RISE_EINT2 */
4980#define ARIZONA_IM_JD1_RISE_EINT2_WIDTH 1 /* IM_JD1_RISE_EINT2 */
4981#define ARIZONA_IM_JD2_FALL_EINT2 0x0002 /* IM_JD2_FALL_EINT2 */
4982#define ARIZONA_IM_JD2_FALL_EINT2_MASK 0x0002 /* IM_JD2_FALL_EINT2 */
4983#define ARIZONA_IM_JD2_FALL_EINT2_SHIFT 1 /* IM_JD2_FALL_EINT2 */
4984#define ARIZONA_IM_JD2_FALL_EINT2_WIDTH 1 /* IM_JD2_FALL_EINT2 */
4985#define ARIZONA_IM_JD2_RISE_EINT2 0x0001 /* IM_JD2_RISE_EINT2 */
4986#define ARIZONA_IM_JD2_RISE_EINT2_MASK 0x0001 /* IM_JD2_RISE_EINT2 */
4987#define ARIZONA_IM_JD2_RISE_EINT2_SHIFT 0 /* IM_JD2_RISE_EINT2 */
4988#define ARIZONA_IM_JD2_RISE_EINT2_WIDTH 1 /* IM_JD2_RISE_EINT2 */
4989
4990/*
4991 * R3413 (0xD55) - AOD IRQ Raw Status
4992 */
4993#define ARIZONA_GP5_STS 0x0004 /* GP5_STS */
4994#define ARIZONA_GP5_STS_MASK 0x0004 /* GP5_STS */
4995#define ARIZONA_GP5_STS_SHIFT 2 /* GP5_STS */
4996#define ARIZONA_GP5_STS_WIDTH 1 /* GP5_STS */
4997#define ARIZONA_JD2_STS 0x0002 /* JD2_STS */
4998#define ARIZONA_JD2_STS_MASK 0x0002 /* JD2_STS */
4999#define ARIZONA_JD2_STS_SHIFT 1 /* JD2_STS */
5000#define ARIZONA_JD2_STS_WIDTH 1 /* JD2_STS */
5001#define ARIZONA_JD1_STS 0x0001 /* JD1_STS */
5002#define ARIZONA_JD1_STS_MASK 0x0001 /* JD1_STS */
5003#define ARIZONA_JD1_STS_SHIFT 0 /* JD1_STS */
5004#define ARIZONA_JD1_STS_WIDTH 1 /* JD1_STS */
5005
5006/*
5007 * R3414 (0xD56) - Jack detect debounce
5008 */
5009#define ARIZONA_JD2_DB 0x0002 /* JD2_DB */
5010#define ARIZONA_JD2_DB_MASK 0x0002 /* JD2_DB */
5011#define ARIZONA_JD2_DB_SHIFT 1 /* JD2_DB */
5012#define ARIZONA_JD2_DB_WIDTH 1 /* JD2_DB */
5013#define ARIZONA_JD1_DB 0x0001 /* JD1_DB */
5014#define ARIZONA_JD1_DB_MASK 0x0001 /* JD1_DB */
5015#define ARIZONA_JD1_DB_SHIFT 0 /* JD1_DB */
5016#define ARIZONA_JD1_DB_WIDTH 1 /* JD1_DB */
5017
5018/*
5019 * R3584 (0xE00) - FX_Ctrl1
5020 */
5021#define ARIZONA_FX_RATE_MASK 0x7800 /* FX_RATE - [14:11] */
5022#define ARIZONA_FX_RATE_SHIFT 11 /* FX_RATE - [14:11] */
5023#define ARIZONA_FX_RATE_WIDTH 4 /* FX_RATE - [14:11] */
5024
5025/*
5026 * R3585 (0xE01) - FX_Ctrl2
5027 */
5028#define ARIZONA_FX_STS_MASK 0xFFF0 /* FX_STS - [15:4] */
5029#define ARIZONA_FX_STS_SHIFT 4 /* FX_STS - [15:4] */
5030#define ARIZONA_FX_STS_WIDTH 12 /* FX_STS - [15:4] */
5031
5032/*
5033 * R3600 (0xE10) - EQ1_1
5034 */
5035#define ARIZONA_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */
5036#define ARIZONA_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */
5037#define ARIZONA_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */
5038#define ARIZONA_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */
5039#define ARIZONA_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */
5040#define ARIZONA_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */
5041#define ARIZONA_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */
5042#define ARIZONA_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */
5043#define ARIZONA_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */
5044#define ARIZONA_EQ1_ENA 0x0001 /* EQ1_ENA */
5045#define ARIZONA_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */
5046#define ARIZONA_EQ1_ENA_SHIFT 0 /* EQ1_ENA */
5047#define ARIZONA_EQ1_ENA_WIDTH 1 /* EQ1_ENA */
5048
5049/*
5050 * R3601 (0xE11) - EQ1_2
5051 */
5052#define ARIZONA_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */
5053#define ARIZONA_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */
5054#define ARIZONA_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */
5055#define ARIZONA_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */
5056#define ARIZONA_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */
5057#define ARIZONA_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */
5058#define ARIZONA_EQ1_B1_MODE 0x0001 /* EQ1_B1_MODE */
5059#define ARIZONA_EQ1_B1_MODE_MASK 0x0001 /* EQ1_B1_MODE */
5060#define ARIZONA_EQ1_B1_MODE_SHIFT 0 /* EQ1_B1_MODE */
5061#define ARIZONA_EQ1_B1_MODE_WIDTH 1 /* EQ1_B1_MODE */
5062
5063/*
5064 * R3602 (0xE12) - EQ1_3
5065 */
5066#define ARIZONA_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */
5067#define ARIZONA_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */
5068#define ARIZONA_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */
5069
5070/*
5071 * R3603 (0xE13) - EQ1_4
5072 */
5073#define ARIZONA_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */
5074#define ARIZONA_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */
5075#define ARIZONA_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */
5076
5077/*
5078 * R3604 (0xE14) - EQ1_5
5079 */
5080#define ARIZONA_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */
5081#define ARIZONA_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */
5082#define ARIZONA_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */
5083
5084/*
5085 * R3605 (0xE15) - EQ1_6
5086 */
5087#define ARIZONA_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */
5088#define ARIZONA_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */
5089#define ARIZONA_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */
5090
5091/*
5092 * R3606 (0xE16) - EQ1_7
5093 */
5094#define ARIZONA_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */
5095#define ARIZONA_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */
5096#define ARIZONA_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */
5097
5098/*
5099 * R3607 (0xE17) - EQ1_8
5100 */
5101#define ARIZONA_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */
5102#define ARIZONA_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */
5103#define ARIZONA_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */
5104
5105/*
5106 * R3608 (0xE18) - EQ1_9
5107 */
5108#define ARIZONA_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */
5109#define ARIZONA_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */
5110#define ARIZONA_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */
5111
5112/*
5113 * R3609 (0xE19) - EQ1_10
5114 */
5115#define ARIZONA_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */
5116#define ARIZONA_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */
5117#define ARIZONA_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */
5118
5119/*
5120 * R3610 (0xE1A) - EQ1_11
5121 */
5122#define ARIZONA_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */
5123#define ARIZONA_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */
5124#define ARIZONA_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */
5125
5126/*
5127 * R3611 (0xE1B) - EQ1_12
5128 */
5129#define ARIZONA_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */
5130#define ARIZONA_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */
5131#define ARIZONA_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */
5132
5133/*
5134 * R3612 (0xE1C) - EQ1_13
5135 */
5136#define ARIZONA_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */
5137#define ARIZONA_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */
5138#define ARIZONA_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */
5139
5140/*
5141 * R3613 (0xE1D) - EQ1_14
5142 */
5143#define ARIZONA_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */
5144#define ARIZONA_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */
5145#define ARIZONA_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */
5146
5147/*
5148 * R3614 (0xE1E) - EQ1_15
5149 */
5150#define ARIZONA_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */
5151#define ARIZONA_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */
5152#define ARIZONA_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */
5153
5154/*
5155 * R3615 (0xE1F) - EQ1_16
5156 */
5157#define ARIZONA_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */
5158#define ARIZONA_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */
5159#define ARIZONA_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */
5160
5161/*
5162 * R3616 (0xE20) - EQ1_17
5163 */
5164#define ARIZONA_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */
5165#define ARIZONA_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */
5166#define ARIZONA_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */
5167
5168/*
5169 * R3617 (0xE21) - EQ1_18
5170 */
5171#define ARIZONA_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */
5172#define ARIZONA_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */
5173#define ARIZONA_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */
5174
5175/*
5176 * R3618 (0xE22) - EQ1_19
5177 */
5178#define ARIZONA_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */
5179#define ARIZONA_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */
5180#define ARIZONA_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */
5181
5182/*
5183 * R3619 (0xE23) - EQ1_20
5184 */
5185#define ARIZONA_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */
5186#define ARIZONA_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */
5187#define ARIZONA_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */
5188
5189/*
5190 * R3620 (0xE24) - EQ1_21
5191 */
5192#define ARIZONA_EQ1_B1_C_MASK 0xFFFF /* EQ1_B1_C - [15:0] */
5193#define ARIZONA_EQ1_B1_C_SHIFT 0 /* EQ1_B1_C - [15:0] */
5194#define ARIZONA_EQ1_B1_C_WIDTH 16 /* EQ1_B1_C - [15:0] */
5195
5196/*
5197 * R3622 (0xE26) - EQ2_1
5198 */
5199#define ARIZONA_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */
5200#define ARIZONA_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */
5201#define ARIZONA_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */
5202#define ARIZONA_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */
5203#define ARIZONA_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */
5204#define ARIZONA_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */
5205#define ARIZONA_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */
5206#define ARIZONA_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */
5207#define ARIZONA_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */
5208#define ARIZONA_EQ2_ENA 0x0001 /* EQ2_ENA */
5209#define ARIZONA_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */
5210#define ARIZONA_EQ2_ENA_SHIFT 0 /* EQ2_ENA */
5211#define ARIZONA_EQ2_ENA_WIDTH 1 /* EQ2_ENA */
5212
5213/*
5214 * R3623 (0xE27) - EQ2_2
5215 */
5216#define ARIZONA_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */
5217#define ARIZONA_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */
5218#define ARIZONA_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */
5219#define ARIZONA_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */
5220#define ARIZONA_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */
5221#define ARIZONA_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */
5222#define ARIZONA_EQ2_B1_MODE 0x0001 /* EQ2_B1_MODE */
5223#define ARIZONA_EQ2_B1_MODE_MASK 0x0001 /* EQ2_B1_MODE */
5224#define ARIZONA_EQ2_B1_MODE_SHIFT 0 /* EQ2_B1_MODE */
5225#define ARIZONA_EQ2_B1_MODE_WIDTH 1 /* EQ2_B1_MODE */
5226
5227/*
5228 * R3624 (0xE28) - EQ2_3
5229 */
5230#define ARIZONA_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */
5231#define ARIZONA_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */
5232#define ARIZONA_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */
5233
5234/*
5235 * R3625 (0xE29) - EQ2_4
5236 */
5237#define ARIZONA_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */
5238#define ARIZONA_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */
5239#define ARIZONA_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */
5240
5241/*
5242 * R3626 (0xE2A) - EQ2_5
5243 */
5244#define ARIZONA_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */
5245#define ARIZONA_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */
5246#define ARIZONA_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */
5247
5248/*
5249 * R3627 (0xE2B) - EQ2_6
5250 */
5251#define ARIZONA_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */
5252#define ARIZONA_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */
5253#define ARIZONA_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */
5254
5255/*
5256 * R3628 (0xE2C) - EQ2_7
5257 */
5258#define ARIZONA_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */
5259#define ARIZONA_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */
5260#define ARIZONA_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */
5261
5262/*
5263 * R3629 (0xE2D) - EQ2_8
5264 */
5265#define ARIZONA_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */
5266#define ARIZONA_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */
5267#define ARIZONA_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */
5268
5269/*
5270 * R3630 (0xE2E) - EQ2_9
5271 */
5272#define ARIZONA_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */
5273#define ARIZONA_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */
5274#define ARIZONA_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */
5275
5276/*
5277 * R3631 (0xE2F) - EQ2_10
5278 */
5279#define ARIZONA_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */
5280#define ARIZONA_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */
5281#define ARIZONA_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */
5282
5283/*
5284 * R3632 (0xE30) - EQ2_11
5285 */
5286#define ARIZONA_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */
5287#define ARIZONA_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */
5288#define ARIZONA_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */
5289
5290/*
5291 * R3633 (0xE31) - EQ2_12
5292 */
5293#define ARIZONA_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */
5294#define ARIZONA_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */
5295#define ARIZONA_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */
5296
5297/*
5298 * R3634 (0xE32) - EQ2_13
5299 */
5300#define ARIZONA_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */
5301#define ARIZONA_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */
5302#define ARIZONA_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */
5303
5304/*
5305 * R3635 (0xE33) - EQ2_14
5306 */
5307#define ARIZONA_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */
5308#define ARIZONA_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */
5309#define ARIZONA_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */
5310
5311/*
5312 * R3636 (0xE34) - EQ2_15
5313 */
5314#define ARIZONA_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */
5315#define ARIZONA_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */
5316#define ARIZONA_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */
5317
5318/*
5319 * R3637 (0xE35) - EQ2_16
5320 */
5321#define ARIZONA_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */
5322#define ARIZONA_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */
5323#define ARIZONA_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */
5324
5325/*
5326 * R3638 (0xE36) - EQ2_17
5327 */
5328#define ARIZONA_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */
5329#define ARIZONA_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */
5330#define ARIZONA_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */
5331
5332/*
5333 * R3639 (0xE37) - EQ2_18
5334 */
5335#define ARIZONA_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */
5336#define ARIZONA_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */
5337#define ARIZONA_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */
5338
5339/*
5340 * R3640 (0xE38) - EQ2_19
5341 */
5342#define ARIZONA_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */
5343#define ARIZONA_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */
5344#define ARIZONA_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */
5345
5346/*
5347 * R3641 (0xE39) - EQ2_20
5348 */
5349#define ARIZONA_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */
5350#define ARIZONA_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */
5351#define ARIZONA_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */
5352
5353/*
5354 * R3642 (0xE3A) - EQ2_21
5355 */
5356#define ARIZONA_EQ2_B1_C_MASK 0xFFFF /* EQ2_B1_C - [15:0] */
5357#define ARIZONA_EQ2_B1_C_SHIFT 0 /* EQ2_B1_C - [15:0] */
5358#define ARIZONA_EQ2_B1_C_WIDTH 16 /* EQ2_B1_C - [15:0] */
5359
5360/*
5361 * R3644 (0xE3C) - EQ3_1
5362 */
5363#define ARIZONA_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */
5364#define ARIZONA_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */
5365#define ARIZONA_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */
5366#define ARIZONA_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */
5367#define ARIZONA_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */
5368#define ARIZONA_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */
5369#define ARIZONA_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */
5370#define ARIZONA_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */
5371#define ARIZONA_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */
5372#define ARIZONA_EQ3_ENA 0x0001 /* EQ3_ENA */
5373#define ARIZONA_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */
5374#define ARIZONA_EQ3_ENA_SHIFT 0 /* EQ3_ENA */
5375#define ARIZONA_EQ3_ENA_WIDTH 1 /* EQ3_ENA */
5376
5377/*
5378 * R3645 (0xE3D) - EQ3_2
5379 */
5380#define ARIZONA_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */
5381#define ARIZONA_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */
5382#define ARIZONA_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */
5383#define ARIZONA_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */
5384#define ARIZONA_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */
5385#define ARIZONA_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */
5386#define ARIZONA_EQ3_B1_MODE 0x0001 /* EQ3_B1_MODE */
5387#define ARIZONA_EQ3_B1_MODE_MASK 0x0001 /* EQ3_B1_MODE */
5388#define ARIZONA_EQ3_B1_MODE_SHIFT 0 /* EQ3_B1_MODE */
5389#define ARIZONA_EQ3_B1_MODE_WIDTH 1 /* EQ3_B1_MODE */
5390
5391/*
5392 * R3646 (0xE3E) - EQ3_3
5393 */
5394#define ARIZONA_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */
5395#define ARIZONA_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */
5396#define ARIZONA_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */
5397
5398/*
5399 * R3647 (0xE3F) - EQ3_4
5400 */
5401#define ARIZONA_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */
5402#define ARIZONA_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */
5403#define ARIZONA_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */
5404
5405/*
5406 * R3648 (0xE40) - EQ3_5
5407 */
5408#define ARIZONA_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */
5409#define ARIZONA_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */
5410#define ARIZONA_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */
5411
5412/*
5413 * R3649 (0xE41) - EQ3_6
5414 */
5415#define ARIZONA_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */
5416#define ARIZONA_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */
5417#define ARIZONA_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */
5418
5419/*
5420 * R3650 (0xE42) - EQ3_7
5421 */
5422#define ARIZONA_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */
5423#define ARIZONA_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */
5424#define ARIZONA_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */
5425
5426/*
5427 * R3651 (0xE43) - EQ3_8
5428 */
5429#define ARIZONA_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */
5430#define ARIZONA_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */
5431#define ARIZONA_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */
5432
5433/*
5434 * R3652 (0xE44) - EQ3_9
5435 */
5436#define ARIZONA_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */
5437#define ARIZONA_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */
5438#define ARIZONA_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */
5439
5440/*
5441 * R3653 (0xE45) - EQ3_10
5442 */
5443#define ARIZONA_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */
5444#define ARIZONA_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */
5445#define ARIZONA_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */
5446
5447/*
5448 * R3654 (0xE46) - EQ3_11
5449 */
5450#define ARIZONA_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */
5451#define ARIZONA_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */
5452#define ARIZONA_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */
5453
5454/*
5455 * R3655 (0xE47) - EQ3_12
5456 */
5457#define ARIZONA_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */
5458#define ARIZONA_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */
5459#define ARIZONA_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */
5460
5461/*
5462 * R3656 (0xE48) - EQ3_13
5463 */
5464#define ARIZONA_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */
5465#define ARIZONA_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */
5466#define ARIZONA_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */
5467
5468/*
5469 * R3657 (0xE49) - EQ3_14
5470 */
5471#define ARIZONA_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */
5472#define ARIZONA_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */
5473#define ARIZONA_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */
5474
5475/*
5476 * R3658 (0xE4A) - EQ3_15
5477 */
5478#define ARIZONA_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */
5479#define ARIZONA_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */
5480#define ARIZONA_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */
5481
5482/*
5483 * R3659 (0xE4B) - EQ3_16
5484 */
5485#define ARIZONA_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */
5486#define ARIZONA_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */
5487#define ARIZONA_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */
5488
5489/*
5490 * R3660 (0xE4C) - EQ3_17
5491 */
5492#define ARIZONA_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */
5493#define ARIZONA_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */
5494#define ARIZONA_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */
5495
5496/*
5497 * R3661 (0xE4D) - EQ3_18
5498 */
5499#define ARIZONA_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */
5500#define ARIZONA_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */
5501#define ARIZONA_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */
5502
5503/*
5504 * R3662 (0xE4E) - EQ3_19
5505 */
5506#define ARIZONA_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */
5507#define ARIZONA_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */
5508#define ARIZONA_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */
5509
5510/*
5511 * R3663 (0xE4F) - EQ3_20
5512 */
5513#define ARIZONA_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */
5514#define ARIZONA_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */
5515#define ARIZONA_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */
5516
5517/*
5518 * R3664 (0xE50) - EQ3_21
5519 */
5520#define ARIZONA_EQ3_B1_C_MASK 0xFFFF /* EQ3_B1_C - [15:0] */
5521#define ARIZONA_EQ3_B1_C_SHIFT 0 /* EQ3_B1_C - [15:0] */
5522#define ARIZONA_EQ3_B1_C_WIDTH 16 /* EQ3_B1_C - [15:0] */
5523
5524/*
5525 * R3666 (0xE52) - EQ4_1
5526 */
5527#define ARIZONA_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */
5528#define ARIZONA_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */
5529#define ARIZONA_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */
5530#define ARIZONA_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */
5531#define ARIZONA_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */
5532#define ARIZONA_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */
5533#define ARIZONA_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */
5534#define ARIZONA_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */
5535#define ARIZONA_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */
5536#define ARIZONA_EQ4_ENA 0x0001 /* EQ4_ENA */
5537#define ARIZONA_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */
5538#define ARIZONA_EQ4_ENA_SHIFT 0 /* EQ4_ENA */
5539#define ARIZONA_EQ4_ENA_WIDTH 1 /* EQ4_ENA */
5540
5541/*
5542 * R3667 (0xE53) - EQ4_2
5543 */
5544#define ARIZONA_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */
5545#define ARIZONA_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */
5546#define ARIZONA_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */
5547#define ARIZONA_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */
5548#define ARIZONA_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */
5549#define ARIZONA_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */
5550#define ARIZONA_EQ4_B1_MODE 0x0001 /* EQ4_B1_MODE */
5551#define ARIZONA_EQ4_B1_MODE_MASK 0x0001 /* EQ4_B1_MODE */
5552#define ARIZONA_EQ4_B1_MODE_SHIFT 0 /* EQ4_B1_MODE */
5553#define ARIZONA_EQ4_B1_MODE_WIDTH 1 /* EQ4_B1_MODE */
5554
5555/*
5556 * R3668 (0xE54) - EQ4_3
5557 */
5558#define ARIZONA_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */
5559#define ARIZONA_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */
5560#define ARIZONA_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */
5561
5562/*
5563 * R3669 (0xE55) - EQ4_4
5564 */
5565#define ARIZONA_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */
5566#define ARIZONA_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */
5567#define ARIZONA_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */
5568
5569/*
5570 * R3670 (0xE56) - EQ4_5
5571 */
5572#define ARIZONA_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */
5573#define ARIZONA_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */
5574#define ARIZONA_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */
5575
5576/*
5577 * R3671 (0xE57) - EQ4_6
5578 */
5579#define ARIZONA_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */
5580#define ARIZONA_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */
5581#define ARIZONA_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */
5582
5583/*
5584 * R3672 (0xE58) - EQ4_7
5585 */
5586#define ARIZONA_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */
5587#define ARIZONA_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */
5588#define ARIZONA_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */
5589
5590/*
5591 * R3673 (0xE59) - EQ4_8
5592 */
5593#define ARIZONA_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */
5594#define ARIZONA_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */
5595#define ARIZONA_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */
5596
5597/*
5598 * R3674 (0xE5A) - EQ4_9
5599 */
5600#define ARIZONA_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */
5601#define ARIZONA_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */
5602#define ARIZONA_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */
5603
5604/*
5605 * R3675 (0xE5B) - EQ4_10
5606 */
5607#define ARIZONA_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */
5608#define ARIZONA_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */
5609#define ARIZONA_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */
5610
5611/*
5612 * R3676 (0xE5C) - EQ4_11
5613 */
5614#define ARIZONA_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */
5615#define ARIZONA_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */
5616#define ARIZONA_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */
5617
5618/*
5619 * R3677 (0xE5D) - EQ4_12
5620 */
5621#define ARIZONA_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */
5622#define ARIZONA_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */
5623#define ARIZONA_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */
5624
5625/*
5626 * R3678 (0xE5E) - EQ4_13
5627 */
5628#define ARIZONA_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */
5629#define ARIZONA_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */
5630#define ARIZONA_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */
5631
5632/*
5633 * R3679 (0xE5F) - EQ4_14
5634 */
5635#define ARIZONA_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */
5636#define ARIZONA_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */
5637#define ARIZONA_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */
5638
5639/*
5640 * R3680 (0xE60) - EQ4_15
5641 */
5642#define ARIZONA_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */
5643#define ARIZONA_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */
5644#define ARIZONA_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */
5645
5646/*
5647 * R3681 (0xE61) - EQ4_16
5648 */
5649#define ARIZONA_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */
5650#define ARIZONA_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */
5651#define ARIZONA_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */
5652
5653/*
5654 * R3682 (0xE62) - EQ4_17
5655 */
5656#define ARIZONA_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */
5657#define ARIZONA_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */
5658#define ARIZONA_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */
5659
5660/*
5661 * R3683 (0xE63) - EQ4_18
5662 */
5663#define ARIZONA_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */
5664#define ARIZONA_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */
5665#define ARIZONA_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */
5666
5667/*
5668 * R3684 (0xE64) - EQ4_19
5669 */
5670#define ARIZONA_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */
5671#define ARIZONA_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */
5672#define ARIZONA_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */
5673
5674/*
5675 * R3685 (0xE65) - EQ4_20
5676 */
5677#define ARIZONA_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */
5678#define ARIZONA_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */
5679#define ARIZONA_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */
5680
5681/*
5682 * R3686 (0xE66) - EQ4_21
5683 */
5684#define ARIZONA_EQ4_B1_C_MASK 0xFFFF /* EQ4_B1_C - [15:0] */
5685#define ARIZONA_EQ4_B1_C_SHIFT 0 /* EQ4_B1_C - [15:0] */
5686#define ARIZONA_EQ4_B1_C_WIDTH 16 /* EQ4_B1_C - [15:0] */
5687
5688/*
5689 * R3712 (0xE80) - DRC1 ctrl1
5690 */
5691#define ARIZONA_DRC1_SIG_DET_RMS_MASK 0xF800 /* DRC1_SIG_DET_RMS - [15:11] */
5692#define ARIZONA_DRC1_SIG_DET_RMS_SHIFT 11 /* DRC1_SIG_DET_RMS - [15:11] */
5693#define ARIZONA_DRC1_SIG_DET_RMS_WIDTH 5 /* DRC1_SIG_DET_RMS - [15:11] */
5694#define ARIZONA_DRC1_SIG_DET_PK_MASK 0x0600 /* DRC1_SIG_DET_PK - [10:9] */
5695#define ARIZONA_DRC1_SIG_DET_PK_SHIFT 9 /* DRC1_SIG_DET_PK - [10:9] */
5696#define ARIZONA_DRC1_SIG_DET_PK_WIDTH 2 /* DRC1_SIG_DET_PK - [10:9] */
5697#define ARIZONA_DRC1_NG_ENA 0x0100 /* DRC1_NG_ENA */
5698#define ARIZONA_DRC1_NG_ENA_MASK 0x0100 /* DRC1_NG_ENA */
5699#define ARIZONA_DRC1_NG_ENA_SHIFT 8 /* DRC1_NG_ENA */
5700#define ARIZONA_DRC1_NG_ENA_WIDTH 1 /* DRC1_NG_ENA */
5701#define ARIZONA_DRC1_SIG_DET_MODE 0x0080 /* DRC1_SIG_DET_MODE */
5702#define ARIZONA_DRC1_SIG_DET_MODE_MASK 0x0080 /* DRC1_SIG_DET_MODE */
5703#define ARIZONA_DRC1_SIG_DET_MODE_SHIFT 7 /* DRC1_SIG_DET_MODE */
5704#define ARIZONA_DRC1_SIG_DET_MODE_WIDTH 1 /* DRC1_SIG_DET_MODE */
5705#define ARIZONA_DRC1_SIG_DET 0x0040 /* DRC1_SIG_DET */
5706#define ARIZONA_DRC1_SIG_DET_MASK 0x0040 /* DRC1_SIG_DET */
5707#define ARIZONA_DRC1_SIG_DET_SHIFT 6 /* DRC1_SIG_DET */
5708#define ARIZONA_DRC1_SIG_DET_WIDTH 1 /* DRC1_SIG_DET */
5709#define ARIZONA_DRC1_KNEE2_OP_ENA 0x0020 /* DRC1_KNEE2_OP_ENA */
5710#define ARIZONA_DRC1_KNEE2_OP_ENA_MASK 0x0020 /* DRC1_KNEE2_OP_ENA */
5711#define ARIZONA_DRC1_KNEE2_OP_ENA_SHIFT 5 /* DRC1_KNEE2_OP_ENA */
5712#define ARIZONA_DRC1_KNEE2_OP_ENA_WIDTH 1 /* DRC1_KNEE2_OP_ENA */
5713#define ARIZONA_DRC1_QR 0x0010 /* DRC1_QR */
5714#define ARIZONA_DRC1_QR_MASK 0x0010 /* DRC1_QR */
5715#define ARIZONA_DRC1_QR_SHIFT 4 /* DRC1_QR */
5716#define ARIZONA_DRC1_QR_WIDTH 1 /* DRC1_QR */
5717#define ARIZONA_DRC1_ANTICLIP 0x0008 /* DRC1_ANTICLIP */
5718#define ARIZONA_DRC1_ANTICLIP_MASK 0x0008 /* DRC1_ANTICLIP */
5719#define ARIZONA_DRC1_ANTICLIP_SHIFT 3 /* DRC1_ANTICLIP */
5720#define ARIZONA_DRC1_ANTICLIP_WIDTH 1 /* DRC1_ANTICLIP */
5721#define ARIZONA_DRC1L_ENA 0x0002 /* DRC1L_ENA */
5722#define ARIZONA_DRC1L_ENA_MASK 0x0002 /* DRC1L_ENA */
5723#define ARIZONA_DRC1L_ENA_SHIFT 1 /* DRC1L_ENA */
5724#define ARIZONA_DRC1L_ENA_WIDTH 1 /* DRC1L_ENA */
5725#define ARIZONA_DRC1R_ENA 0x0001 /* DRC1R_ENA */
5726#define ARIZONA_DRC1R_ENA_MASK 0x0001 /* DRC1R_ENA */
5727#define ARIZONA_DRC1R_ENA_SHIFT 0 /* DRC1R_ENA */
5728#define ARIZONA_DRC1R_ENA_WIDTH 1 /* DRC1R_ENA */
5729
5730/*
5731 * R3713 (0xE81) - DRC1 ctrl2
5732 */
5733#define ARIZONA_DRC1_ATK_MASK 0x1E00 /* DRC1_ATK - [12:9] */
5734#define ARIZONA_DRC1_ATK_SHIFT 9 /* DRC1_ATK - [12:9] */
5735#define ARIZONA_DRC1_ATK_WIDTH 4 /* DRC1_ATK - [12:9] */
5736#define ARIZONA_DRC1_DCY_MASK 0x01E0 /* DRC1_DCY - [8:5] */
5737#define ARIZONA_DRC1_DCY_SHIFT 5 /* DRC1_DCY - [8:5] */
5738#define ARIZONA_DRC1_DCY_WIDTH 4 /* DRC1_DCY - [8:5] */
5739#define ARIZONA_DRC1_MINGAIN_MASK 0x001C /* DRC1_MINGAIN - [4:2] */
5740#define ARIZONA_DRC1_MINGAIN_SHIFT 2 /* DRC1_MINGAIN - [4:2] */
5741#define ARIZONA_DRC1_MINGAIN_WIDTH 3 /* DRC1_MINGAIN - [4:2] */
5742#define ARIZONA_DRC1_MAXGAIN_MASK 0x0003 /* DRC1_MAXGAIN - [1:0] */
5743#define ARIZONA_DRC1_MAXGAIN_SHIFT 0 /* DRC1_MAXGAIN - [1:0] */
5744#define ARIZONA_DRC1_MAXGAIN_WIDTH 2 /* DRC1_MAXGAIN - [1:0] */
5745
5746/*
5747 * R3714 (0xE82) - DRC1 ctrl3
5748 */
5749#define ARIZONA_DRC1_NG_MINGAIN_MASK 0xF000 /* DRC1_NG_MINGAIN - [15:12] */
5750#define ARIZONA_DRC1_NG_MINGAIN_SHIFT 12 /* DRC1_NG_MINGAIN - [15:12] */
5751#define ARIZONA_DRC1_NG_MINGAIN_WIDTH 4 /* DRC1_NG_MINGAIN - [15:12] */
5752#define ARIZONA_DRC1_NG_EXP_MASK 0x0C00 /* DRC1_NG_EXP - [11:10] */
5753#define ARIZONA_DRC1_NG_EXP_SHIFT 10 /* DRC1_NG_EXP - [11:10] */
5754#define ARIZONA_DRC1_NG_EXP_WIDTH 2 /* DRC1_NG_EXP - [11:10] */
5755#define ARIZONA_DRC1_QR_THR_MASK 0x0300 /* DRC1_QR_THR - [9:8] */
5756#define ARIZONA_DRC1_QR_THR_SHIFT 8 /* DRC1_QR_THR - [9:8] */
5757#define ARIZONA_DRC1_QR_THR_WIDTH 2 /* DRC1_QR_THR - [9:8] */
5758#define ARIZONA_DRC1_QR_DCY_MASK 0x00C0 /* DRC1_QR_DCY - [7:6] */
5759#define ARIZONA_DRC1_QR_DCY_SHIFT 6 /* DRC1_QR_DCY - [7:6] */
5760#define ARIZONA_DRC1_QR_DCY_WIDTH 2 /* DRC1_QR_DCY - [7:6] */
5761#define ARIZONA_DRC1_HI_COMP_MASK 0x0038 /* DRC1_HI_COMP - [5:3] */
5762#define ARIZONA_DRC1_HI_COMP_SHIFT 3 /* DRC1_HI_COMP - [5:3] */
5763#define ARIZONA_DRC1_HI_COMP_WIDTH 3 /* DRC1_HI_COMP - [5:3] */
5764#define ARIZONA_DRC1_LO_COMP_MASK 0x0007 /* DRC1_LO_COMP - [2:0] */
5765#define ARIZONA_DRC1_LO_COMP_SHIFT 0 /* DRC1_LO_COMP - [2:0] */
5766#define ARIZONA_DRC1_LO_COMP_WIDTH 3 /* DRC1_LO_COMP - [2:0] */
5767
5768/*
5769 * R3715 (0xE83) - DRC1 ctrl4
5770 */
5771#define ARIZONA_DRC1_KNEE_IP_MASK 0x07E0 /* DRC1_KNEE_IP - [10:5] */
5772#define ARIZONA_DRC1_KNEE_IP_SHIFT 5 /* DRC1_KNEE_IP - [10:5] */
5773#define ARIZONA_DRC1_KNEE_IP_WIDTH 6 /* DRC1_KNEE_IP - [10:5] */
5774#define ARIZONA_DRC1_KNEE_OP_MASK 0x001F /* DRC1_KNEE_OP - [4:0] */
5775#define ARIZONA_DRC1_KNEE_OP_SHIFT 0 /* DRC1_KNEE_OP - [4:0] */
5776#define ARIZONA_DRC1_KNEE_OP_WIDTH 5 /* DRC1_KNEE_OP - [4:0] */
5777
5778/*
5779 * R3716 (0xE84) - DRC1 ctrl5
5780 */
5781#define ARIZONA_DRC1_KNEE2_IP_MASK 0x03E0 /* DRC1_KNEE2_IP - [9:5] */
5782#define ARIZONA_DRC1_KNEE2_IP_SHIFT 5 /* DRC1_KNEE2_IP - [9:5] */
5783#define ARIZONA_DRC1_KNEE2_IP_WIDTH 5 /* DRC1_KNEE2_IP - [9:5] */
5784#define ARIZONA_DRC1_KNEE2_OP_MASK 0x001F /* DRC1_KNEE2_OP - [4:0] */
5785#define ARIZONA_DRC1_KNEE2_OP_SHIFT 0 /* DRC1_KNEE2_OP - [4:0] */
5786#define ARIZONA_DRC1_KNEE2_OP_WIDTH 5 /* DRC1_KNEE2_OP - [4:0] */
5787
5788/*
5789 * R3721 (0xE89) - DRC2 ctrl1
5790 */
5791#define ARIZONA_DRC2_SIG_DET_RMS_MASK 0xF800 /* DRC2_SIG_DET_RMS - [15:11] */
5792#define ARIZONA_DRC2_SIG_DET_RMS_SHIFT 11 /* DRC2_SIG_DET_RMS - [15:11] */
5793#define ARIZONA_DRC2_SIG_DET_RMS_WIDTH 5 /* DRC2_SIG_DET_RMS - [15:11] */
5794#define ARIZONA_DRC2_SIG_DET_PK_MASK 0x0600 /* DRC2_SIG_DET_PK - [10:9] */
5795#define ARIZONA_DRC2_SIG_DET_PK_SHIFT 9 /* DRC2_SIG_DET_PK - [10:9] */
5796#define ARIZONA_DRC2_SIG_DET_PK_WIDTH 2 /* DRC2_SIG_DET_PK - [10:9] */
5797#define ARIZONA_DRC2_NG_ENA 0x0100 /* DRC2_NG_ENA */
5798#define ARIZONA_DRC2_NG_ENA_MASK 0x0100 /* DRC2_NG_ENA */
5799#define ARIZONA_DRC2_NG_ENA_SHIFT 8 /* DRC2_NG_ENA */
5800#define ARIZONA_DRC2_NG_ENA_WIDTH 1 /* DRC2_NG_ENA */
5801#define ARIZONA_DRC2_SIG_DET_MODE 0x0080 /* DRC2_SIG_DET_MODE */
5802#define ARIZONA_DRC2_SIG_DET_MODE_MASK 0x0080 /* DRC2_SIG_DET_MODE */
5803#define ARIZONA_DRC2_SIG_DET_MODE_SHIFT 7 /* DRC2_SIG_DET_MODE */
5804#define ARIZONA_DRC2_SIG_DET_MODE_WIDTH 1 /* DRC2_SIG_DET_MODE */
5805#define ARIZONA_DRC2_SIG_DET 0x0040 /* DRC2_SIG_DET */
5806#define ARIZONA_DRC2_SIG_DET_MASK 0x0040 /* DRC2_SIG_DET */
5807#define ARIZONA_DRC2_SIG_DET_SHIFT 6 /* DRC2_SIG_DET */
5808#define ARIZONA_DRC2_SIG_DET_WIDTH 1 /* DRC2_SIG_DET */
5809#define ARIZONA_DRC2_KNEE2_OP_ENA 0x0020 /* DRC2_KNEE2_OP_ENA */
5810#define ARIZONA_DRC2_KNEE2_OP_ENA_MASK 0x0020 /* DRC2_KNEE2_OP_ENA */
5811#define ARIZONA_DRC2_KNEE2_OP_ENA_SHIFT 5 /* DRC2_KNEE2_OP_ENA */
5812#define ARIZONA_DRC2_KNEE2_OP_ENA_WIDTH 1 /* DRC2_KNEE2_OP_ENA */
5813#define ARIZONA_DRC2_QR 0x0010 /* DRC2_QR */
5814#define ARIZONA_DRC2_QR_MASK 0x0010 /* DRC2_QR */
5815#define ARIZONA_DRC2_QR_SHIFT 4 /* DRC2_QR */
5816#define ARIZONA_DRC2_QR_WIDTH 1 /* DRC2_QR */
5817#define ARIZONA_DRC2_ANTICLIP 0x0008 /* DRC2_ANTICLIP */
5818#define ARIZONA_DRC2_ANTICLIP_MASK 0x0008 /* DRC2_ANTICLIP */
5819#define ARIZONA_DRC2_ANTICLIP_SHIFT 3 /* DRC2_ANTICLIP */
5820#define ARIZONA_DRC2_ANTICLIP_WIDTH 1 /* DRC2_ANTICLIP */
5821#define ARIZONA_DRC2L_ENA 0x0002 /* DRC2L_ENA */
5822#define ARIZONA_DRC2L_ENA_MASK 0x0002 /* DRC2L_ENA */
5823#define ARIZONA_DRC2L_ENA_SHIFT 1 /* DRC2L_ENA */
5824#define ARIZONA_DRC2L_ENA_WIDTH 1 /* DRC2L_ENA */
5825#define ARIZONA_DRC2R_ENA 0x0001 /* DRC2R_ENA */
5826#define ARIZONA_DRC2R_ENA_MASK 0x0001 /* DRC2R_ENA */
5827#define ARIZONA_DRC2R_ENA_SHIFT 0 /* DRC2R_ENA */
5828#define ARIZONA_DRC2R_ENA_WIDTH 1 /* DRC2R_ENA */
5829
5830/*
5831 * R3722 (0xE8A) - DRC2 ctrl2
5832 */
5833#define ARIZONA_DRC2_ATK_MASK 0x1E00 /* DRC2_ATK - [12:9] */
5834#define ARIZONA_DRC2_ATK_SHIFT 9 /* DRC2_ATK - [12:9] */
5835#define ARIZONA_DRC2_ATK_WIDTH 4 /* DRC2_ATK - [12:9] */
5836#define ARIZONA_DRC2_DCY_MASK 0x01E0 /* DRC2_DCY - [8:5] */
5837#define ARIZONA_DRC2_DCY_SHIFT 5 /* DRC2_DCY - [8:5] */
5838#define ARIZONA_DRC2_DCY_WIDTH 4 /* DRC2_DCY - [8:5] */
5839#define ARIZONA_DRC2_MINGAIN_MASK 0x001C /* DRC2_MINGAIN - [4:2] */
5840#define ARIZONA_DRC2_MINGAIN_SHIFT 2 /* DRC2_MINGAIN - [4:2] */
5841#define ARIZONA_DRC2_MINGAIN_WIDTH 3 /* DRC2_MINGAIN - [4:2] */
5842#define ARIZONA_DRC2_MAXGAIN_MASK 0x0003 /* DRC2_MAXGAIN - [1:0] */
5843#define ARIZONA_DRC2_MAXGAIN_SHIFT 0 /* DRC2_MAXGAIN - [1:0] */
5844#define ARIZONA_DRC2_MAXGAIN_WIDTH 2 /* DRC2_MAXGAIN - [1:0] */
5845
5846/*
5847 * R3723 (0xE8B) - DRC2 ctrl3
5848 */
5849#define ARIZONA_DRC2_NG_MINGAIN_MASK 0xF000 /* DRC2_NG_MINGAIN - [15:12] */
5850#define ARIZONA_DRC2_NG_MINGAIN_SHIFT 12 /* DRC2_NG_MINGAIN - [15:12] */
5851#define ARIZONA_DRC2_NG_MINGAIN_WIDTH 4 /* DRC2_NG_MINGAIN - [15:12] */
5852#define ARIZONA_DRC2_NG_EXP_MASK 0x0C00 /* DRC2_NG_EXP - [11:10] */
5853#define ARIZONA_DRC2_NG_EXP_SHIFT 10 /* DRC2_NG_EXP - [11:10] */
5854#define ARIZONA_DRC2_NG_EXP_WIDTH 2 /* DRC2_NG_EXP - [11:10] */
5855#define ARIZONA_DRC2_QR_THR_MASK 0x0300 /* DRC2_QR_THR - [9:8] */
5856#define ARIZONA_DRC2_QR_THR_SHIFT 8 /* DRC2_QR_THR - [9:8] */
5857#define ARIZONA_DRC2_QR_THR_WIDTH 2 /* DRC2_QR_THR - [9:8] */
5858#define ARIZONA_DRC2_QR_DCY_MASK 0x00C0 /* DRC2_QR_DCY - [7:6] */
5859#define ARIZONA_DRC2_QR_DCY_SHIFT 6 /* DRC2_QR_DCY - [7:6] */
5860#define ARIZONA_DRC2_QR_DCY_WIDTH 2 /* DRC2_QR_DCY - [7:6] */
5861#define ARIZONA_DRC2_HI_COMP_MASK 0x0038 /* DRC2_HI_COMP - [5:3] */
5862#define ARIZONA_DRC2_HI_COMP_SHIFT 3 /* DRC2_HI_COMP - [5:3] */
5863#define ARIZONA_DRC2_HI_COMP_WIDTH 3 /* DRC2_HI_COMP - [5:3] */
5864#define ARIZONA_DRC2_LO_COMP_MASK 0x0007 /* DRC2_LO_COMP - [2:0] */
5865#define ARIZONA_DRC2_LO_COMP_SHIFT 0 /* DRC2_LO_COMP - [2:0] */
5866#define ARIZONA_DRC2_LO_COMP_WIDTH 3 /* DRC2_LO_COMP - [2:0] */
5867
5868/*
5869 * R3724 (0xE8C) - DRC2 ctrl4
5870 */
5871#define ARIZONA_DRC2_KNEE_IP_MASK 0x07E0 /* DRC2_KNEE_IP - [10:5] */
5872#define ARIZONA_DRC2_KNEE_IP_SHIFT 5 /* DRC2_KNEE_IP - [10:5] */
5873#define ARIZONA_DRC2_KNEE_IP_WIDTH 6 /* DRC2_KNEE_IP - [10:5] */
5874#define ARIZONA_DRC2_KNEE_OP_MASK 0x001F /* DRC2_KNEE_OP - [4:0] */
5875#define ARIZONA_DRC2_KNEE_OP_SHIFT 0 /* DRC2_KNEE_OP - [4:0] */
5876#define ARIZONA_DRC2_KNEE_OP_WIDTH 5 /* DRC2_KNEE_OP - [4:0] */
5877
5878/*
5879 * R3725 (0xE8D) - DRC2 ctrl5
5880 */
5881#define ARIZONA_DRC2_KNEE2_IP_MASK 0x03E0 /* DRC2_KNEE2_IP - [9:5] */
5882#define ARIZONA_DRC2_KNEE2_IP_SHIFT 5 /* DRC2_KNEE2_IP - [9:5] */
5883#define ARIZONA_DRC2_KNEE2_IP_WIDTH 5 /* DRC2_KNEE2_IP - [9:5] */
5884#define ARIZONA_DRC2_KNEE2_OP_MASK 0x001F /* DRC2_KNEE2_OP - [4:0] */
5885#define ARIZONA_DRC2_KNEE2_OP_SHIFT 0 /* DRC2_KNEE2_OP - [4:0] */
5886#define ARIZONA_DRC2_KNEE2_OP_WIDTH 5 /* DRC2_KNEE2_OP - [4:0] */
5887
5888/*
5889 * R3776 (0xEC0) - HPLPF1_1
5890 */
5891#define ARIZONA_LHPF1_MODE 0x0002 /* LHPF1_MODE */
5892#define ARIZONA_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */
5893#define ARIZONA_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */
5894#define ARIZONA_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */
5895#define ARIZONA_LHPF1_ENA 0x0001 /* LHPF1_ENA */
5896#define ARIZONA_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */
5897#define ARIZONA_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */
5898#define ARIZONA_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */
5899
5900/*
5901 * R3777 (0xEC1) - HPLPF1_2
5902 */
5903#define ARIZONA_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */
5904#define ARIZONA_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */
5905#define ARIZONA_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */
5906
5907/*
5908 * R3780 (0xEC4) - HPLPF2_1
5909 */
5910#define ARIZONA_LHPF2_MODE 0x0002 /* LHPF2_MODE */
5911#define ARIZONA_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */
5912#define ARIZONA_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */
5913#define ARIZONA_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */
5914#define ARIZONA_LHPF2_ENA 0x0001 /* LHPF2_ENA */
5915#define ARIZONA_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */
5916#define ARIZONA_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */
5917#define ARIZONA_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */
5918
5919/*
5920 * R3781 (0xEC5) - HPLPF2_2
5921 */
5922#define ARIZONA_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */
5923#define ARIZONA_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */
5924#define ARIZONA_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */
5925
5926/*
5927 * R3784 (0xEC8) - HPLPF3_1
5928 */
5929#define ARIZONA_LHPF3_MODE 0x0002 /* LHPF3_MODE */
5930#define ARIZONA_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */
5931#define ARIZONA_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */
5932#define ARIZONA_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */
5933#define ARIZONA_LHPF3_ENA 0x0001 /* LHPF3_ENA */
5934#define ARIZONA_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */
5935#define ARIZONA_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */
5936#define ARIZONA_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */
5937
5938/*
5939 * R3785 (0xEC9) - HPLPF3_2
5940 */
5941#define ARIZONA_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */
5942#define ARIZONA_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */
5943#define ARIZONA_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */
5944
5945/*
5946 * R3788 (0xECC) - HPLPF4_1
5947 */
5948#define ARIZONA_LHPF4_MODE 0x0002 /* LHPF4_MODE */
5949#define ARIZONA_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */
5950#define ARIZONA_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */
5951#define ARIZONA_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */
5952#define ARIZONA_LHPF4_ENA 0x0001 /* LHPF4_ENA */
5953#define ARIZONA_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */
5954#define ARIZONA_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */
5955#define ARIZONA_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */
5956
5957/*
5958 * R3789 (0xECD) - HPLPF4_2
5959 */
5960#define ARIZONA_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */
5961#define ARIZONA_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */
5962#define ARIZONA_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */
5963
5964/*
5965 * R3808 (0xEE0) - ASRC_ENABLE
5966 */
5967#define ARIZONA_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */
5968#define ARIZONA_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */
5969#define ARIZONA_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */
5970#define ARIZONA_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */
5971#define ARIZONA_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */
5972#define ARIZONA_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */
5973#define ARIZONA_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */
5974#define ARIZONA_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */
5975#define ARIZONA_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */
5976#define ARIZONA_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */
5977#define ARIZONA_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */
5978#define ARIZONA_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */
5979#define ARIZONA_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */
5980#define ARIZONA_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */
5981#define ARIZONA_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */
5982#define ARIZONA_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */
5983
5984/*
5985 * R3810 (0xEE2) - ASRC_RATE1
5986 */
5987#define ARIZONA_ASRC_RATE1_MASK 0x7800 /* ASRC_RATE1 - [14:11] */
5988#define ARIZONA_ASRC_RATE1_SHIFT 11 /* ASRC_RATE1 - [14:11] */
5989#define ARIZONA_ASRC_RATE1_WIDTH 4 /* ASRC_RATE1 - [14:11] */
5990
5991/*
5992 * R3811 (0xEE3) - ASRC_RATE2
5993 */
5994#define ARIZONA_ASRC_RATE2_MASK 0x7800 /* ASRC_RATE2 - [14:11] */
5995#define ARIZONA_ASRC_RATE2_SHIFT 11 /* ASRC_RATE2 - [14:11] */
5996#define ARIZONA_ASRC_RATE2_WIDTH 4 /* ASRC_RATE2 - [14:11] */
5997
5998/*
5999 * R3824 (0xEF0) - ISRC 1 CTRL 1
6000 */
6001#define ARIZONA_ISRC1_FSH_MASK 0x7800 /* ISRC1_FSH - [14:11] */
6002#define ARIZONA_ISRC1_FSH_SHIFT 11 /* ISRC1_FSH - [14:11] */
6003#define ARIZONA_ISRC1_FSH_WIDTH 4 /* ISRC1_FSH - [14:11] */
6004#define ARIZONA_ISRC1_CLK_SEL_MASK 0x0700 /* ISRC1_CLK_SEL - [10:8] */
6005#define ARIZONA_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [10:8] */
6006#define ARIZONA_ISRC1_CLK_SEL_WIDTH 3 /* ISRC1_CLK_SEL - [10:8] */
6007
6008/*
6009 * R3825 (0xEF1) - ISRC 1 CTRL 2
6010 */
6011#define ARIZONA_ISRC1_FSL_MASK 0x7800 /* ISRC1_FSL - [14:11] */
6012#define ARIZONA_ISRC1_FSL_SHIFT 11 /* ISRC1_FSL - [14:11] */
6013#define ARIZONA_ISRC1_FSL_WIDTH 4 /* ISRC1_FSL - [14:11] */
6014
6015/*
6016 * R3826 (0xEF2) - ISRC 1 CTRL 3
6017 */
6018#define ARIZONA_ISRC1_INT0_ENA 0x8000 /* ISRC1_INT0_ENA */
6019#define ARIZONA_ISRC1_INT0_ENA_MASK 0x8000 /* ISRC1_INT0_ENA */
6020#define ARIZONA_ISRC1_INT0_ENA_SHIFT 15 /* ISRC1_INT0_ENA */
6021#define ARIZONA_ISRC1_INT0_ENA_WIDTH 1 /* ISRC1_INT0_ENA */
6022#define ARIZONA_ISRC1_INT1_ENA 0x4000 /* ISRC1_INT1_ENA */
6023#define ARIZONA_ISRC1_INT1_ENA_MASK 0x4000 /* ISRC1_INT1_ENA */
6024#define ARIZONA_ISRC1_INT1_ENA_SHIFT 14 /* ISRC1_INT1_ENA */
6025#define ARIZONA_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */
6026#define ARIZONA_ISRC1_INT2_ENA 0x2000 /* ISRC1_INT2_ENA */
6027#define ARIZONA_ISRC1_INT2_ENA_MASK 0x2000 /* ISRC1_INT2_ENA */
6028#define ARIZONA_ISRC1_INT2_ENA_SHIFT 13 /* ISRC1_INT2_ENA */
6029#define ARIZONA_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */
6030#define ARIZONA_ISRC1_INT3_ENA 0x1000 /* ISRC1_INT3_ENA */
6031#define ARIZONA_ISRC1_INT3_ENA_MASK 0x1000 /* ISRC1_INT3_ENA */
6032#define ARIZONA_ISRC1_INT3_ENA_SHIFT 12 /* ISRC1_INT3_ENA */
6033#define ARIZONA_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */
6034#define ARIZONA_ISRC1_DEC0_ENA 0x0200 /* ISRC1_DEC0_ENA */
6035#define ARIZONA_ISRC1_DEC0_ENA_MASK 0x0200 /* ISRC1_DEC0_ENA */
6036#define ARIZONA_ISRC1_DEC0_ENA_SHIFT 9 /* ISRC1_DEC0_ENA */
6037#define ARIZONA_ISRC1_DEC0_ENA_WIDTH 1 /* ISRC1_DEC0_ENA */
6038#define ARIZONA_ISRC1_DEC1_ENA 0x0100 /* ISRC1_DEC1_ENA */
6039#define ARIZONA_ISRC1_DEC1_ENA_MASK 0x0100 /* ISRC1_DEC1_ENA */
6040#define ARIZONA_ISRC1_DEC1_ENA_SHIFT 8 /* ISRC1_DEC1_ENA */
6041#define ARIZONA_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */
6042#define ARIZONA_ISRC1_DEC2_ENA 0x0080 /* ISRC1_DEC2_ENA */
6043#define ARIZONA_ISRC1_DEC2_ENA_MASK 0x0080 /* ISRC1_DEC2_ENA */
6044#define ARIZONA_ISRC1_DEC2_ENA_SHIFT 7 /* ISRC1_DEC2_ENA */
6045#define ARIZONA_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */
6046#define ARIZONA_ISRC1_DEC3_ENA 0x0040 /* ISRC1_DEC3_ENA */
6047#define ARIZONA_ISRC1_DEC3_ENA_MASK 0x0040 /* ISRC1_DEC3_ENA */
6048#define ARIZONA_ISRC1_DEC3_ENA_SHIFT 6 /* ISRC1_DEC3_ENA */
6049#define ARIZONA_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */
6050#define ARIZONA_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */
6051#define ARIZONA_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */
6052#define ARIZONA_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */
6053#define ARIZONA_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */
6054
6055/*
6056 * R3827 (0xEF3) - ISRC 2 CTRL 1
6057 */
6058#define ARIZONA_ISRC2_FSH_MASK 0x7800 /* ISRC2_FSH - [14:11] */
6059#define ARIZONA_ISRC2_FSH_SHIFT 11 /* ISRC2_FSH - [14:11] */
6060#define ARIZONA_ISRC2_FSH_WIDTH 4 /* ISRC2_FSH - [14:11] */
6061#define ARIZONA_ISRC2_CLK_SEL_MASK 0x0700 /* ISRC2_CLK_SEL - [10:8] */
6062#define ARIZONA_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [10:8] */
6063#define ARIZONA_ISRC2_CLK_SEL_WIDTH 3 /* ISRC2_CLK_SEL - [10:8] */
6064
6065/*
6066 * R3828 (0xEF4) - ISRC 2 CTRL 2
6067 */
6068#define ARIZONA_ISRC2_FSL_MASK 0x7800 /* ISRC2_FSL - [14:11] */
6069#define ARIZONA_ISRC2_FSL_SHIFT 11 /* ISRC2_FSL - [14:11] */
6070#define ARIZONA_ISRC2_FSL_WIDTH 4 /* ISRC2_FSL - [14:11] */
6071
6072/*
6073 * R3829 (0xEF5) - ISRC 2 CTRL 3
6074 */
6075#define ARIZONA_ISRC2_INT0_ENA 0x8000 /* ISRC2_INT0_ENA */
6076#define ARIZONA_ISRC2_INT0_ENA_MASK 0x8000 /* ISRC2_INT0_ENA */
6077#define ARIZONA_ISRC2_INT0_ENA_SHIFT 15 /* ISRC2_INT0_ENA */
6078#define ARIZONA_ISRC2_INT0_ENA_WIDTH 1 /* ISRC2_INT0_ENA */
6079#define ARIZONA_ISRC2_INT1_ENA 0x4000 /* ISRC2_INT1_ENA */
6080#define ARIZONA_ISRC2_INT1_ENA_MASK 0x4000 /* ISRC2_INT1_ENA */
6081#define ARIZONA_ISRC2_INT1_ENA_SHIFT 14 /* ISRC2_INT1_ENA */
6082#define ARIZONA_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */
6083#define ARIZONA_ISRC2_INT2_ENA 0x2000 /* ISRC2_INT2_ENA */
6084#define ARIZONA_ISRC2_INT2_ENA_MASK 0x2000 /* ISRC2_INT2_ENA */
6085#define ARIZONA_ISRC2_INT2_ENA_SHIFT 13 /* ISRC2_INT2_ENA */
6086#define ARIZONA_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */
6087#define ARIZONA_ISRC2_INT3_ENA 0x1000 /* ISRC2_INT3_ENA */
6088#define ARIZONA_ISRC2_INT3_ENA_MASK 0x1000 /* ISRC2_INT3_ENA */
6089#define ARIZONA_ISRC2_INT3_ENA_SHIFT 12 /* ISRC2_INT3_ENA */
6090#define ARIZONA_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */
6091#define ARIZONA_ISRC2_DEC0_ENA 0x0200 /* ISRC2_DEC0_ENA */
6092#define ARIZONA_ISRC2_DEC0_ENA_MASK 0x0200 /* ISRC2_DEC0_ENA */
6093#define ARIZONA_ISRC2_DEC0_ENA_SHIFT 9 /* ISRC2_DEC0_ENA */
6094#define ARIZONA_ISRC2_DEC0_ENA_WIDTH 1 /* ISRC2_DEC0_ENA */
6095#define ARIZONA_ISRC2_DEC1_ENA 0x0100 /* ISRC2_DEC1_ENA */
6096#define ARIZONA_ISRC2_DEC1_ENA_MASK 0x0100 /* ISRC2_DEC1_ENA */
6097#define ARIZONA_ISRC2_DEC1_ENA_SHIFT 8 /* ISRC2_DEC1_ENA */
6098#define ARIZONA_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */
6099#define ARIZONA_ISRC2_DEC2_ENA 0x0080 /* ISRC2_DEC2_ENA */
6100#define ARIZONA_ISRC2_DEC2_ENA_MASK 0x0080 /* ISRC2_DEC2_ENA */
6101#define ARIZONA_ISRC2_DEC2_ENA_SHIFT 7 /* ISRC2_DEC2_ENA */
6102#define ARIZONA_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */
6103#define ARIZONA_ISRC2_DEC3_ENA 0x0040 /* ISRC2_DEC3_ENA */
6104#define ARIZONA_ISRC2_DEC3_ENA_MASK 0x0040 /* ISRC2_DEC3_ENA */
6105#define ARIZONA_ISRC2_DEC3_ENA_SHIFT 6 /* ISRC2_DEC3_ENA */
6106#define ARIZONA_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */
6107#define ARIZONA_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */
6108#define ARIZONA_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */
6109#define ARIZONA_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */
6110#define ARIZONA_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */
6111
6112/*
6113 * R3830 (0xEF6) - ISRC 3 CTRL 1
6114 */
6115#define ARIZONA_ISRC3_FSH_MASK 0x7800 /* ISRC3_FSH - [14:11] */
6116#define ARIZONA_ISRC3_FSH_SHIFT 11 /* ISRC3_FSH - [14:11] */
6117#define ARIZONA_ISRC3_FSH_WIDTH 4 /* ISRC3_FSH - [14:11] */
6118#define ARIZONA_ISRC3_CLK_SEL_MASK 0x0700 /* ISRC3_CLK_SEL - [10:8] */
6119#define ARIZONA_ISRC3_CLK_SEL_SHIFT 8 /* ISRC3_CLK_SEL - [10:8] */
6120#define ARIZONA_ISRC3_CLK_SEL_WIDTH 3 /* ISRC3_CLK_SEL - [10:8] */
6121
6122/*
6123 * R3831 (0xEF7) - ISRC 3 CTRL 2
6124 */
6125#define ARIZONA_ISRC3_FSL_MASK 0x7800 /* ISRC3_FSL - [14:11] */
6126#define ARIZONA_ISRC3_FSL_SHIFT 11 /* ISRC3_FSL - [14:11] */
6127#define ARIZONA_ISRC3_FSL_WIDTH 4 /* ISRC3_FSL - [14:11] */
6128
6129/*
6130 * R3832 (0xEF8) - ISRC 3 CTRL 3
6131 */
6132#define ARIZONA_ISRC3_INT0_ENA 0x8000 /* ISRC3_INT0_ENA */
6133#define ARIZONA_ISRC3_INT0_ENA_MASK 0x8000 /* ISRC3_INT0_ENA */
6134#define ARIZONA_ISRC3_INT0_ENA_SHIFT 15 /* ISRC3_INT0_ENA */
6135#define ARIZONA_ISRC3_INT0_ENA_WIDTH 1 /* ISRC3_INT0_ENA */
6136#define ARIZONA_ISRC3_INT1_ENA 0x4000 /* ISRC3_INT1_ENA */
6137#define ARIZONA_ISRC3_INT1_ENA_MASK 0x4000 /* ISRC3_INT1_ENA */
6138#define ARIZONA_ISRC3_INT1_ENA_SHIFT 14 /* ISRC3_INT1_ENA */
6139#define ARIZONA_ISRC3_INT1_ENA_WIDTH 1 /* ISRC3_INT1_ENA */
6140#define ARIZONA_ISRC3_INT2_ENA 0x2000 /* ISRC3_INT2_ENA */
6141#define ARIZONA_ISRC3_INT2_ENA_MASK 0x2000 /* ISRC3_INT2_ENA */
6142#define ARIZONA_ISRC3_INT2_ENA_SHIFT 13 /* ISRC3_INT2_ENA */
6143#define ARIZONA_ISRC3_INT2_ENA_WIDTH 1 /* ISRC3_INT2_ENA */
6144#define ARIZONA_ISRC3_INT3_ENA 0x1000 /* ISRC3_INT3_ENA */
6145#define ARIZONA_ISRC3_INT3_ENA_MASK 0x1000 /* ISRC3_INT3_ENA */
6146#define ARIZONA_ISRC3_INT3_ENA_SHIFT 12 /* ISRC3_INT3_ENA */
6147#define ARIZONA_ISRC3_INT3_ENA_WIDTH 1 /* ISRC3_INT3_ENA */
6148#define ARIZONA_ISRC3_DEC0_ENA 0x0200 /* ISRC3_DEC0_ENA */
6149#define ARIZONA_ISRC3_DEC0_ENA_MASK 0x0200 /* ISRC3_DEC0_ENA */
6150#define ARIZONA_ISRC3_DEC0_ENA_SHIFT 9 /* ISRC3_DEC0_ENA */
6151#define ARIZONA_ISRC3_DEC0_ENA_WIDTH 1 /* ISRC3_DEC0_ENA */
6152#define ARIZONA_ISRC3_DEC1_ENA 0x0100 /* ISRC3_DEC1_ENA */
6153#define ARIZONA_ISRC3_DEC1_ENA_MASK 0x0100 /* ISRC3_DEC1_ENA */
6154#define ARIZONA_ISRC3_DEC1_ENA_SHIFT 8 /* ISRC3_DEC1_ENA */
6155#define ARIZONA_ISRC3_DEC1_ENA_WIDTH 1 /* ISRC3_DEC1_ENA */
6156#define ARIZONA_ISRC3_DEC2_ENA 0x0080 /* ISRC3_DEC2_ENA */
6157#define ARIZONA_ISRC3_DEC2_ENA_MASK 0x0080 /* ISRC3_DEC2_ENA */
6158#define ARIZONA_ISRC3_DEC2_ENA_SHIFT 7 /* ISRC3_DEC2_ENA */
6159#define ARIZONA_ISRC3_DEC2_ENA_WIDTH 1 /* ISRC3_DEC2_ENA */
6160#define ARIZONA_ISRC3_DEC3_ENA 0x0040 /* ISRC3_DEC3_ENA */
6161#define ARIZONA_ISRC3_DEC3_ENA_MASK 0x0040 /* ISRC3_DEC3_ENA */
6162#define ARIZONA_ISRC3_DEC3_ENA_SHIFT 6 /* ISRC3_DEC3_ENA */
6163#define ARIZONA_ISRC3_DEC3_ENA_WIDTH 1 /* ISRC3_DEC3_ENA */
6164#define ARIZONA_ISRC3_NOTCH_ENA 0x0001 /* ISRC3_NOTCH_ENA */
6165#define ARIZONA_ISRC3_NOTCH_ENA_MASK 0x0001 /* ISRC3_NOTCH_ENA */
6166#define ARIZONA_ISRC3_NOTCH_ENA_SHIFT 0 /* ISRC3_NOTCH_ENA */
6167#define ARIZONA_ISRC3_NOTCH_ENA_WIDTH 1 /* ISRC3_NOTCH_ENA */
6168
6169/*
6170 * R4352 (0x1100) - DSP1 Control 1
6171 */
6172#define ARIZONA_DSP1_RATE_MASK 0x7800 /* DSP1_RATE - [14:11] */
6173#define ARIZONA_DSP1_RATE_SHIFT 11 /* DSP1_RATE - [14:11] */
6174#define ARIZONA_DSP1_RATE_WIDTH 4 /* DSP1_RATE - [14:11] */
6175#define ARIZONA_DSP1_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
6176#define ARIZONA_DSP1_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
6177#define ARIZONA_DSP1_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
6178#define ARIZONA_DSP1_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
6179#define ARIZONA_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
6180#define ARIZONA_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
6181#define ARIZONA_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
6182#define ARIZONA_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
6183#define ARIZONA_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
6184#define ARIZONA_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
6185#define ARIZONA_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
6186#define ARIZONA_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
6187#define ARIZONA_DSP1_START 0x0001 /* DSP1_START */
6188#define ARIZONA_DSP1_START_MASK 0x0001 /* DSP1_START */
6189#define ARIZONA_DSP1_START_SHIFT 0 /* DSP1_START */
6190#define ARIZONA_DSP1_START_WIDTH 1 /* DSP1_START */
6191
6192/*
6193 * R4353 (0x1101) - DSP1 Clocking 1
6194 */
6195#define ARIZONA_DSP1_CLK_SEL_MASK 0x0007 /* DSP1_CLK_SEL - [2:0] */
6196#define ARIZONA_DSP1_CLK_SEL_SHIFT 0 /* DSP1_CLK_SEL - [2:0] */
6197#define ARIZONA_DSP1_CLK_SEL_WIDTH 3 /* DSP1_CLK_SEL - [2:0] */
6198
6199/*
6200 * R4356 (0x1104) - DSP1 Status 1
6201 */
6202#define ARIZONA_DSP1_RAM_RDY 0x0001 /* DSP1_RAM_RDY */
6203#define ARIZONA_DSP1_RAM_RDY_MASK 0x0001 /* DSP1_RAM_RDY */
6204#define ARIZONA_DSP1_RAM_RDY_SHIFT 0 /* DSP1_RAM_RDY */
6205#define ARIZONA_DSP1_RAM_RDY_WIDTH 1 /* DSP1_RAM_RDY */
6206
6207/*
6208 * R4357 (0x1105) - DSP1 Status 2
6209 */
6210#define ARIZONA_DSP1_PING_FULL 0x8000 /* DSP1_PING_FULL */
6211#define ARIZONA_DSP1_PING_FULL_MASK 0x8000 /* DSP1_PING_FULL */
6212#define ARIZONA_DSP1_PING_FULL_SHIFT 15 /* DSP1_PING_FULL */
6213#define ARIZONA_DSP1_PING_FULL_WIDTH 1 /* DSP1_PING_FULL */
6214#define ARIZONA_DSP1_PONG_FULL 0x4000 /* DSP1_PONG_FULL */
6215#define ARIZONA_DSP1_PONG_FULL_MASK 0x4000 /* DSP1_PONG_FULL */
6216#define ARIZONA_DSP1_PONG_FULL_SHIFT 14 /* DSP1_PONG_FULL */
6217#define ARIZONA_DSP1_PONG_FULL_WIDTH 1 /* DSP1_PONG_FULL */
6218#define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
6219#define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
6220#define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
6221
6222#endif
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 56af22ec9aba..58ec0cba0ae6 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -219,6 +219,7 @@ struct regmap_irq {
219 * @status_base: Base status register address. 219 * @status_base: Base status register address.
220 * @mask_base: Base mask register address. 220 * @mask_base: Base mask register address.
221 * @ack_base: Base ack address. If zero then the chip is clear on read. 221 * @ack_base: Base ack address. If zero then the chip is clear on read.
222 * @wake_base: Base address for wake enables. If zero unsupported.
222 * @irq_reg_stride: Stride to use for chips where registers are not contiguous. 223 * @irq_reg_stride: Stride to use for chips where registers are not contiguous.
223 * 224 *
224 * @num_regs: Number of registers in each control bank. 225 * @num_regs: Number of registers in each control bank.
@@ -232,6 +233,7 @@ struct regmap_irq_chip {
232 unsigned int status_base; 233 unsigned int status_base;
233 unsigned int mask_base; 234 unsigned int mask_base;
234 unsigned int ack_base; 235 unsigned int ack_base;
236 unsigned int wake_base;
235 unsigned int irq_reg_stride; 237 unsigned int irq_reg_stride;
236 238
237 int num_regs; 239 int num_regs;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 14:11:31 -0500