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authorJoakim Tjernlund <joakim.tjernlund@transmode.se>2010-01-08 01:46:26 -0500
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2010-01-14 21:26:16 -0500
commit061ec9599f7ea515a3f08cd5cb74a03b2f9c56d2 (patch)
treeb078ad67594cc2794914e85e9fbbdb5642a0ff9d
parent3e7b484354c8f60c12119c1c5174ef354696c30d (diff)
powerpc/8xx: Fix user space TLB walk in dcbX fixup
The newly added fixup for buggy dcbX insn's has a bug that always trigger a kernel TLB walk so a user space dcbX insn will cause a Kernel Machine Check if it hits DTLB error. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
-rw-r--r--arch/powerpc/kernel/head_8xx.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index a2ed3422fa3d..3ef743fa5d7c 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -542,11 +542,11 @@ DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR
542FixupDAR:/* Entry point for dcbx workaround. */ 542FixupDAR:/* Entry point for dcbx workaround. */
543 /* fetch instruction from memory. */ 543 /* fetch instruction from memory. */
544 mfspr r10, SPRN_SRR0 544 mfspr r10, SPRN_SRR0
545 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
545 DO_8xx_CPU6(0x3780, r3) 546 DO_8xx_CPU6(0x3780, r3)
546 mtspr SPRN_MD_EPN, r10 547 mtspr SPRN_MD_EPN, r10
547 mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */ 548 mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */
548 cmplwi cr0, r11, 0x0800 549 beq- 3f /* Branch if user space */
549 blt- 3f /* Branch if user space */
550 lis r11, (swapper_pg_dir-PAGE_OFFSET)@h 550 lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
551 ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l 551 ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
552 rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */ 552 rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */