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authorRafał Miłecki <zajec5@gmail.com>2013-03-29 06:13:40 -0400
committerRafał Miłecki <zajec5@gmail.com>2013-04-23 06:27:57 -0400
commit04519dc6590baa83158316026ee35cde29e7be3c (patch)
tree8f929f09471e626cb6421addff7f528b562d0ce2
parentfb3bc67ed8e2ec6e18078e047e9e72254d1526d1 (diff)
b43: N-PHY: define missing registers
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Diffstat
-rw-r--r--drivers/net/wireless/b43/phy_n.c74
-rw-r--r--drivers/net/wireless/b43/phy_n.h146
2 files changed, 182 insertions, 38 deletions
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index 7b5c2af6a2f6..29a979671502 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -1974,10 +1974,8 @@ static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
1974 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040); 1974 b43_phy_set(dev, B43_NPHY_RXCTL, 0x0040);
1975 1975
1976 /* Set Clip 2 detect */ 1976 /* Set Clip 2 detect */
1977 b43_phy_set(dev, B43_NPHY_C1_CGAINI, 1977 b43_phy_set(dev, B43_NPHY_C1_CGAINI, B43_NPHY_C1_CGAINI_CL2DETECT);
1978 B43_NPHY_C1_CGAINI_CL2DETECT); 1978 b43_phy_set(dev, B43_NPHY_C2_CGAINI, B43_NPHY_C2_CGAINI_CL2DETECT);
1979 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
1980 B43_NPHY_C2_CGAINI_CL2DETECT);
1981 1979
1982 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC, 1980 b43_radio_write(dev, B2056_RX0 | B2056_RX_BIASPOLE_LNAG1_IDAC,
1983 0x17); 1981 0x17);
@@ -2011,22 +2009,22 @@ static void b43_nphy_gain_ctl_workarounds_rev3plus(struct b43_wldev *dev)
2011 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits); 2009 b43_ntab_write_bulk(dev, B43_NTAB8(2, 0x40), 6, lpf_bits);
2012 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits); 2010 b43_ntab_write_bulk(dev, B43_NTAB8(3, 0x40), 6, lpf_bits);
2013 2011
2014 b43_phy_write(dev, B43_NPHY_C1_INITGAIN, e->init_gain); 2012 b43_phy_write(dev, B43_NPHY_REV3_C1_INITGAIN_A, e->init_gain);
2015 b43_phy_write(dev, 0x2A7, e->init_gain); 2013 b43_phy_write(dev, B43_NPHY_REV3_C2_INITGAIN_A, e->init_gain);
2014
2016 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2, 2015 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x106), 2,
2017 e->rfseq_init); 2016 e->rfseq_init);
2018 2017
2019 /* TODO: check defines. Do not match variables names */ 2018 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_HIGAIN_A, e->cliphi_gain);
2020 b43_phy_write(dev, B43_NPHY_C1_CLIP1_MEDGAIN, e->cliphi_gain); 2019 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_HIGAIN_A, e->cliphi_gain);
2021 b43_phy_write(dev, 0x2A9, e->cliphi_gain); 2020 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_MEDGAIN_A, e->clipmd_gain);
2022 b43_phy_write(dev, B43_NPHY_C1_CLIP2_GAIN, e->clipmd_gain); 2021 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_MEDGAIN_A, e->clipmd_gain);
2023 b43_phy_write(dev, 0x2AB, e->clipmd_gain); 2022 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_A, e->cliplo_gain);
2024 b43_phy_write(dev, B43_NPHY_C2_CLIP1_HIGAIN, e->cliplo_gain); 2023 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_A, e->cliplo_gain);
2025 b43_phy_write(dev, 0x2AD, e->cliplo_gain); 2024
2026 2025 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWER0, 0xFF00, e->crsmin);
2027 b43_phy_maskset(dev, 0x27D, 0xFF00, e->crsmin); 2026 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERL0, 0xFF00, e->crsminl);
2028 b43_phy_maskset(dev, 0x280, 0xFF00, e->crsminl); 2027 b43_phy_maskset(dev, B43_NPHY_CRSMINPOWERU0, 0xFF00, e->crsminu);
2029 b43_phy_maskset(dev, 0x283, 0xFF00, e->crsminu);
2030 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip); 2028 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, e->nbclip);
2031 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip); 2029 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, e->nbclip);
2032 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES, 2030 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
@@ -2208,8 +2206,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2208 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000); 2206 b43_phy_maskset(dev, B43_NPHY_FREQGAIN7, 0x80FF, 0x4000);
2209 } 2207 }
2210 if (phy->rev <= 8) { 2208 if (phy->rev <= 8) {
2211 b43_phy_write(dev, 0x23F, 0x1B0); 2209 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1B0);
2212 b43_phy_write(dev, 0x240, 0x1B0); 2210 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1B0);
2213 } 2211 }
2214 if (phy->rev >= 8) 2212 if (phy->rev >= 8)
2215 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72); 2213 b43_phy_maskset(dev, B43_NPHY_TXTAILCNT, ~0xFF, 0x72);
@@ -2226,8 +2224,8 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2226 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa, 2224 b43_nphy_set_rf_sequence(dev, 0, rx2tx_events_ipa,
2227 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa)); 2225 rx2tx_delays_ipa, ARRAY_SIZE(rx2tx_events_ipa));
2228 2226
2229 b43_phy_maskset(dev, 0x299, 0x3FFF, 0x4000); 2227 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_0, 0x3FFF, 0x4000);
2230 b43_phy_maskset(dev, 0x29D, 0x3FFF, 0x4000); 2228 b43_phy_maskset(dev, B43_NPHY_EPS_OVERRIDEI_1, 0x3FFF, 0x4000);
2231 2229
2232 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154); 2230 lpf_20 = b43_nphy_read_lpf_ctl(dev, 0x154);
2233 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159); 2231 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
@@ -2494,8 +2492,8 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2494 u16 tmp16; 2492 u16 tmp16;
2495 u32 tmp32; 2493 u32 tmp32;
2496 2494
2497 b43_phy_write(dev, 0x23f, 0x1f8); 2495 b43_phy_write(dev, B43_NPHY_FORCEFRONT0, 0x1f8);
2498 b43_phy_write(dev, 0x240, 0x1f8); 2496 b43_phy_write(dev, B43_NPHY_FORCEFRONT1, 0x1f8);
2499 2497
2500 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0)); 2498 tmp32 = b43_ntab_read(dev, B43_NTAB32(30, 0));
2501 tmp32 &= 0xffffff; 2499 tmp32 &= 0xffffff;
@@ -2508,8 +2506,8 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2508 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD); 2506 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0x00CD);
2509 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020); 2507 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x0020);
2510 2508
2511 b43_phy_write(dev, B43_NPHY_C2_CLIP1_MEDGAIN, 0x000C); 2509 b43_phy_write(dev, B43_NPHY_REV3_C1_CLIP_LOGAIN_B, 0x000C);
2512 b43_phy_write(dev, 0x2AE, 0x000C); 2510 b43_phy_write(dev, B43_NPHY_REV3_C2_CLIP_LOGAIN_B, 0x000C);
2513 2511
2514 /* TX to RX */ 2512 /* TX to RX */
2515 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays, 2513 b43_nphy_set_rf_sequence(dev, 1, tx2rx_events, tx2rx_delays,
@@ -2534,7 +2532,7 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2534 0x2 : 0x9C40; 2532 0x2 : 0x9C40;
2535 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16); 2533 b43_phy_write(dev, B43_NPHY_ENDROP_TLEN, tmp16);
2536 2534
2537 b43_phy_maskset(dev, 0x294, 0xF0FF, 0x0700); 2535 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
2538 2536
2539 if (!dev->phy.is_40mhz) { 2537 if (!dev->phy.is_40mhz) {
2540 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); 2538 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
@@ -2586,18 +2584,18 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2586 } 2584 }
2587 2585
2588 /* Dropped probably-always-true condition */ 2586 /* Dropped probably-always-true condition */
2589 b43_phy_write(dev, 0x224, 0x03eb); 2587 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH0, 0x03eb);
2590 b43_phy_write(dev, 0x225, 0x03eb); 2588 b43_phy_write(dev, B43_NPHY_ED_CRS40ASSERTTHRESH1, 0x03eb);
2591 b43_phy_write(dev, 0x226, 0x0341); 2589 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2592 b43_phy_write(dev, 0x227, 0x0341); 2590 b43_phy_write(dev, B43_NPHY_ED_CRS40DEASSERTTHRESH1, 0x0341);
2593 b43_phy_write(dev, 0x228, 0x042b); 2591 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH0, 0x042b);
2594 b43_phy_write(dev, 0x229, 0x042b); 2592 b43_phy_write(dev, B43_NPHY_ED_CRS20LASSERTTHRESH1, 0x042b);
2595 b43_phy_write(dev, 0x22a, 0x0381); 2593 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH0, 0x0381);
2596 b43_phy_write(dev, 0x22b, 0x0381); 2594 b43_phy_write(dev, B43_NPHY_ED_CRS20LDEASSERTTHRESH1, 0x0381);
2597 b43_phy_write(dev, 0x22c, 0x042b); 2595 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH0, 0x042b);
2598 b43_phy_write(dev, 0x22d, 0x042b); 2596 b43_phy_write(dev, B43_NPHY_ED_CRS20UASSERTTHRESH1, 0x042b);
2599 b43_phy_write(dev, 0x22e, 0x0381); 2597 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH0, 0x0381);
2600 b43_phy_write(dev, 0x22f, 0x0381); 2598 b43_phy_write(dev, B43_NPHY_ED_CRS20UDEASSERTTHRESH1, 0x0381);
2601 2599
2602 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK) 2600 if (dev->phy.rev >= 6 && sprom->boardflags2_lo & B43_BFL2_SINGLEANT_CCK)
2603 ; /* TODO: 0x0080000000000000 HF */ 2601 ; /* TODO: 0x0080000000000000 HF */
diff --git a/drivers/net/wireless/b43/phy_n.h b/drivers/net/wireless/b43/phy_n.h
index 092c0140c249..9a5b6bc27d24 100644
--- a/drivers/net/wireless/b43/phy_n.h
+++ b/drivers/net/wireless/b43/phy_n.h
@@ -54,10 +54,15 @@
54#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7 54#define B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT 7
55#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */ 55#define B43_NPHY_C1_INITGAIN_TRRX 0x1000 /* TR RX index */
56#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */ 56#define B43_NPHY_C1_INITGAIN_TRTX 0x2000 /* TR TX index */
57#define B43_NPHY_REV3_C1_INITGAIN_A B43_PHY_N(0x020)
57#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */ 58#define B43_NPHY_C1_CLIP1_HIGAIN B43_PHY_N(0x021) /* Core 1 clip1 high gain code */
59#define B43_NPHY_REV3_C1_INITGAIN_B B43_PHY_N(0x021)
58#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */ 60#define B43_NPHY_C1_CLIP1_MEDGAIN B43_PHY_N(0x022) /* Core 1 clip1 medium gain code */
61#define B43_NPHY_REV3_C1_CLIP_HIGAIN_A B43_PHY_N(0x022)
59#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */ 62#define B43_NPHY_C1_CLIP1_LOGAIN B43_PHY_N(0x023) /* Core 1 clip1 low gain code */
63#define B43_NPHY_REV3_C1_CLIP_HIGAIN_B B43_PHY_N(0x023)
60#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */ 64#define B43_NPHY_C1_CLIP2_GAIN B43_PHY_N(0x024) /* Core 1 clip2 gain code */
65#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_A B43_PHY_N(0x024)
61#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */ 66#define B43_NPHY_C1_FILTERGAIN B43_PHY_N(0x025) /* Core 1 filter gain */
62#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */ 67#define B43_NPHY_C1_LPF_QHPF_BW B43_PHY_N(0x026) /* Core 1 LPF Q HP F bandwidth */
63#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */ 68#define B43_NPHY_C1_CLIPWBTHRES B43_PHY_N(0x027) /* Core 1 clip wideband threshold */
@@ -107,10 +112,15 @@
107#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7 112#define B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT 7
108#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */ 113#define B43_NPHY_C2_INITGAIN_TRRX 0x1000 /* TR RX index */
109#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */ 114#define B43_NPHY_C2_INITGAIN_TRTX 0x2000 /* TR TX index */
115#define B43_NPHY_REV3_C1_CLIP_MEDGAIN_B B43_PHY_N(0x036)
110#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */ 116#define B43_NPHY_C2_CLIP1_HIGAIN B43_PHY_N(0x037) /* Core 2 clip1 high gain code */
117#define B43_NPHY_REV3_C1_CLIP_LOGAIN_A B43_PHY_N(0x037)
111#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */ 118#define B43_NPHY_C2_CLIP1_MEDGAIN B43_PHY_N(0x038) /* Core 2 clip1 medium gain code */
119#define B43_NPHY_REV3_C1_CLIP_LOGAIN_B B43_PHY_N(0x038)
112#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */ 120#define B43_NPHY_C2_CLIP1_LOGAIN B43_PHY_N(0x039) /* Core 2 clip1 low gain code */
121#define B43_NPHY_REV3_C1_CLIP2_GAIN_A B43_PHY_N(0x039)
113#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */ 122#define B43_NPHY_C2_CLIP2_GAIN B43_PHY_N(0x03A) /* Core 2 clip2 gain code */
123#define B43_NPHY_REV3_C1_CLIP2_GAIN_B B43_PHY_N(0x03A)
114#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */ 124#define B43_NPHY_C2_FILTERGAIN B43_PHY_N(0x03B) /* Core 2 filter gain */
115#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */ 125#define B43_NPHY_C2_LPF_QHPF_BW B43_PHY_N(0x03C) /* Core 2 LPF Q HP F bandwidth */
116#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */ 126#define B43_NPHY_C2_CLIPWBTHRES B43_PHY_N(0x03D) /* Core 2 clip wideband threshold */
@@ -706,10 +716,146 @@
706#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */ 716#define B43_NPHY_TXPCTL_INIT B43_PHY_N(0x222) /* TX power control init */
707#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */ 717#define B43_NPHY_TXPCTL_INIT_PIDXI1 0x00FF /* Power index init 1 */
708#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0 718#define B43_NPHY_TXPCTL_INIT_PIDXI1_SHIFT 0
719#define B43_NPHY_ED_CRSEN B43_PHY_N(0x223)
720#define B43_NPHY_ED_CRS40ASSERTTHRESH0 B43_PHY_N(0x224)
721#define B43_NPHY_ED_CRS40ASSERTTHRESH1 B43_PHY_N(0x225)
722#define B43_NPHY_ED_CRS40DEASSERTTHRESH0 B43_PHY_N(0x226)
723#define B43_NPHY_ED_CRS40DEASSERTTHRESH1 B43_PHY_N(0x227)
724#define B43_NPHY_ED_CRS20LASSERTTHRESH0 B43_PHY_N(0x228)
725#define B43_NPHY_ED_CRS20LASSERTTHRESH1 B43_PHY_N(0x229)
726#define B43_NPHY_ED_CRS20LDEASSERTTHRESH0 B43_PHY_N(0x22A)
727#define B43_NPHY_ED_CRS20LDEASSERTTHRESH1 B43_PHY_N(0x22B)
728#define B43_NPHY_ED_CRS20UASSERTTHRESH0 B43_PHY_N(0x22C)
729#define B43_NPHY_ED_CRS20UASSERTTHRESH1 B43_PHY_N(0x22D)
730#define B43_NPHY_ED_CRS20UDEASSERTTHRESH0 B43_PHY_N(0x22E)
731#define B43_NPHY_ED_CRS20UDEASSERTTHRESH1 B43_PHY_N(0x22F)
732#define B43_NPHY_ED_CRS B43_PHY_N(0x230)
733#define B43_NPHY_TIMEOUTEN B43_PHY_N(0x231)
734#define B43_NPHY_OFDMPAYDECODETIMEOUTLEN B43_PHY_N(0x232)
735#define B43_NPHY_CCKPAYDECODETIMEOUTLEN B43_PHY_N(0x233)
736#define B43_NPHY_NONPAYDECODETIMEOUTLEN B43_PHY_N(0x234)
737#define B43_NPHY_TIMEOUTSTATUS B43_PHY_N(0x235)
738#define B43_NPHY_RFCTRLCORE0GPIO0 B43_PHY_N(0x236)
739#define B43_NPHY_RFCTRLCORE0GPIO1 B43_PHY_N(0x237)
740#define B43_NPHY_RFCTRLCORE0GPIO2 B43_PHY_N(0x238)
741#define B43_NPHY_RFCTRLCORE0GPIO3 B43_PHY_N(0x239)
742#define B43_NPHY_RFCTRLCORE1GPIO0 B43_PHY_N(0x23A)
743#define B43_NPHY_RFCTRLCORE1GPIO1 B43_PHY_N(0x23B)
744#define B43_NPHY_RFCTRLCORE1GPIO2 B43_PHY_N(0x23C)
745#define B43_NPHY_RFCTRLCORE1GPIO3 B43_PHY_N(0x23D)
746#define B43_NPHY_BPHYTESTCONTROL B43_PHY_N(0x23E)
747/* REV3+ */
748#define B43_NPHY_FORCEFRONT0 B43_PHY_N(0x23F)
749#define B43_NPHY_FORCEFRONT1 B43_PHY_N(0x240)
750#define B43_NPHY_NORMVARHYSTTH B43_PHY_N(0x241)
751#define B43_NPHY_TXCCKERROR B43_PHY_N(0x242)
752#define B43_NPHY_AFESEQINITDACGAIN B43_PHY_N(0x243)
753#define B43_NPHY_TXANTSWLUT B43_PHY_N(0x244)
754#define B43_NPHY_CORECONFIG B43_PHY_N(0x245)
755#define B43_NPHY_ANTENNADIVDWELLTIME B43_PHY_N(0x246)
756#define B43_NPHY_ANTENNACCKDIVDWELLTIME B43_PHY_N(0x247)
757#define B43_NPHY_ANTENNADIVBACKOFFGAIN B43_PHY_N(0x248)
758#define B43_NPHY_ANTENNADIVMINGAIN B43_PHY_N(0x249)
759#define B43_NPHY_BRDSEL_NORMVARHYSTTH B43_PHY_N(0x24A)
760#define B43_NPHY_RXANTSWITCHCTRL B43_PHY_N(0x24B)
761#define B43_NPHY_ENERGYDROPTIMEOUTLEN2 B43_PHY_N(0x24C)
762#define B43_NPHY_ML_LOG_TXEVM0 B43_PHY_N(0x250)
763#define B43_NPHY_ML_LOG_TXEVM1 B43_PHY_N(0x251)
764#define B43_NPHY_ML_LOG_TXEVM2 B43_PHY_N(0x252)
765#define B43_NPHY_ML_LOG_TXEVM3 B43_PHY_N(0x253)
766#define B43_NPHY_ML_LOG_TXEVM4 B43_PHY_N(0x254)
767#define B43_NPHY_ML_LOG_TXEVM5 B43_PHY_N(0x255)
768#define B43_NPHY_ML_LOG_TXEVM6 B43_PHY_N(0x256)
769#define B43_NPHY_ML_LOG_TXEVM7 B43_PHY_N(0x257)
770#define B43_NPHY_ML_SCALE_TWEAK B43_PHY_N(0x258)
771#define B43_NPHY_MLUA B43_PHY_N(0x259)
772#define B43_NPHY_ZFUA B43_PHY_N(0x25A)
773#define B43_NPHY_CHANUPSYM01 B43_PHY_N(0x25B)
774#define B43_NPHY_CHANUPSYM2 B43_PHY_N(0x25C)
775#define B43_NPHY_RXSTRNFILT20NUM00 B43_PHY_N(0x25D)
776#define B43_NPHY_RXSTRNFILT20NUM01 B43_PHY_N(0x25E)
777#define B43_NPHY_RXSTRNFILT20NUM02 B43_PHY_N(0x25F)
778#define B43_NPHY_RXSTRNFILT20DEN00 B43_PHY_N(0x260)
779#define B43_NPHY_RXSTRNFILT20DEN01 B43_PHY_N(0x261)
780#define B43_NPHY_RXSTRNFILT20NUM10 B43_PHY_N(0x262)
781#define B43_NPHY_RXSTRNFILT20NUM11 B43_PHY_N(0x263)
782#define B43_NPHY_RXSTRNFILT20NUM12 B43_PHY_N(0x264)
783#define B43_NPHY_RXSTRNFILT20DEN10 B43_PHY_N(0x265)
784#define B43_NPHY_RXSTRNFILT20DEN11 B43_PHY_N(0x266)
785#define B43_NPHY_RXSTRNFILT40NUM00 B43_PHY_N(0x267)
786#define B43_NPHY_RXSTRNFILT40NUM01 B43_PHY_N(0x268)
787#define B43_NPHY_RXSTRNFILT40NUM02 B43_PHY_N(0x269)
788#define B43_NPHY_RXSTRNFILT40DEN00 B43_PHY_N(0x26A)
789#define B43_NPHY_RXSTRNFILT40DEN01 B43_PHY_N(0x26B)
790#define B43_NPHY_RXSTRNFILT40NUM10 B43_PHY_N(0x26C)
791#define B43_NPHY_RXSTRNFILT40NUM11 B43_PHY_N(0x26D)
792#define B43_NPHY_RXSTRNFILT40NUM12 B43_PHY_N(0x26E)
793#define B43_NPHY_RXSTRNFILT40DEN10 B43_PHY_N(0x26F)
794#define B43_NPHY_RXSTRNFILT40DEN11 B43_PHY_N(0x270)
795#define B43_NPHY_CRSHIGHPOWTHRESHOLD1 B43_PHY_N(0x271)
796#define B43_NPHY_CRSHIGHPOWTHRESHOLD2 B43_PHY_N(0x272)
797#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLD B43_PHY_N(0x273)
798#define B43_NPHY_CRSHIGHPOWTHRESHOLD1L B43_PHY_N(0x274)
799#define B43_NPHY_CRSHIGHPOWTHRESHOLD2L B43_PHY_N(0x275)
800#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDL B43_PHY_N(0x276)
801#define B43_NPHY_CRSHIGHPOWTHRESHOLD1U B43_PHY_N(0x277)
802#define B43_NPHY_CRSHIGHPOWTHRESHOLD2U B43_PHY_N(0x278)
803#define B43_NPHY_CRSHIGHLOWPOWTHRESHOLDU B43_PHY_N(0x279)
804#define B43_NPHY_CRSACIDETECTTHRESH B43_PHY_N(0x27A)
805#define B43_NPHY_CRSACIDETECTTHRESHL B43_PHY_N(0x27B)
806#define B43_NPHY_CRSACIDETECTTHRESHU B43_PHY_N(0x27C)
807#define B43_NPHY_CRSMINPOWER0 B43_PHY_N(0x27D)
808#define B43_NPHY_CRSMINPOWER1 B43_PHY_N(0x27E)
809#define B43_NPHY_CRSMINPOWER2 B43_PHY_N(0x27F)
810#define B43_NPHY_CRSMINPOWERL0 B43_PHY_N(0x280)
811#define B43_NPHY_CRSMINPOWERL1 B43_PHY_N(0x281)
812#define B43_NPHY_CRSMINPOWERL2 B43_PHY_N(0x282)
813#define B43_NPHY_CRSMINPOWERU0 B43_PHY_N(0x283)
814#define B43_NPHY_CRSMINPOWERU1 B43_PHY_N(0x284)
815#define B43_NPHY_CRSMINPOWERU2 B43_PHY_N(0x285)
816#define B43_NPHY_STRPARAM B43_PHY_N(0x286)
817#define B43_NPHY_STRPARAML B43_PHY_N(0x287)
818#define B43_NPHY_STRPARAMU B43_PHY_N(0x288)
819#define B43_NPHY_BPHYCRSMINPOWER0 B43_PHY_N(0x289)
820#define B43_NPHY_BPHYCRSMINPOWER1 B43_PHY_N(0x28A)
821#define B43_NPHY_BPHYCRSMINPOWER2 B43_PHY_N(0x28B)
822#define B43_NPHY_BPHYFILTDEN0COEF B43_PHY_N(0x28C)
823#define B43_NPHY_BPHYFILTDEN1COEF B43_PHY_N(0x28D)
824#define B43_NPHY_BPHYFILTDEN2COEF B43_PHY_N(0x28E)
825#define B43_NPHY_BPHYFILTNUM0COEF B43_PHY_N(0x28F)
826#define B43_NPHY_BPHYFILTNUM1COEF B43_PHY_N(0x290)
827#define B43_NPHY_BPHYFILTNUM2COEF B43_PHY_N(0x291)
828#define B43_NPHY_BPHYFILTNUM01COEF2 B43_PHY_N(0x292)
829#define B43_NPHY_BPHYFILTBYPASS B43_PHY_N(0x293)
830#define B43_NPHY_SGILTRNOFFSET B43_PHY_N(0x294)
831#define B43_NPHY_RADAR_T2_MIN B43_PHY_N(0x295)
832#define B43_NPHY_TXPWRCTRLDAMPING B43_PHY_N(0x296)
709#define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */ 833#define B43_NPHY_PAPD_EN0 B43_PHY_N(0x297) /* PAPD Enable0 TBD */
710#define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */ 834#define B43_NPHY_EPS_TABLE_ADJ0 B43_PHY_N(0x298) /* EPS Table Adj0 TBD */
835#define B43_NPHY_EPS_OVERRIDEI_0 B43_PHY_N(0x299)
836#define B43_NPHY_EPS_OVERRIDEQ_0 B43_PHY_N(0x29A)
711#define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */ 837#define B43_NPHY_PAPD_EN1 B43_PHY_N(0x29B) /* PAPD Enable1 TBD */
712#define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */ 838#define B43_NPHY_EPS_TABLE_ADJ1 B43_PHY_N(0x29C) /* EPS Table Adj1 TBD */
839#define B43_NPHY_EPS_OVERRIDEI_1 B43_PHY_N(0x29D)
840#define B43_NPHY_EPS_OVERRIDEQ_1 B43_PHY_N(0x29E)
841#define B43_NPHY_PAPD_CAL_ADDRESS B43_PHY_N(0x29F)
842#define B43_NPHY_PAPD_CAL_YREFEPSILON B43_PHY_N(0x2A0)
843#define B43_NPHY_PAPD_CAL_SETTLE B43_PHY_N(0x2A1)
844#define B43_NPHY_PAPD_CAL_CORRELATE B43_PHY_N(0x2A2)
845#define B43_NPHY_PAPD_CAL_SHIFTS0 B43_PHY_N(0x2A3)
846#define B43_NPHY_PAPD_CAL_SHIFTS1 B43_PHY_N(0x2A4)
847#define B43_NPHY_SAMPLE_START_ADDR B43_PHY_N(0x2A5)
848#define B43_NPHY_RADAR_ADC_TO_DBM B43_PHY_N(0x2A6)
849#define B43_NPHY_REV3_C2_INITGAIN_A B43_PHY_N(0x2A7)
850#define B43_NPHY_REV3_C2_INITGAIN_B B43_PHY_N(0x2A8)
851#define B43_NPHY_REV3_C2_CLIP_HIGAIN_A B43_PHY_N(0x2A9)
852#define B43_NPHY_REV3_C2_CLIP_HIGAIN_B B43_PHY_N(0x2AA)
853#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_A B43_PHY_N(0x2AB)
854#define B43_NPHY_REV3_C2_CLIP_MEDGAIN_B B43_PHY_N(0x2AC)
855#define B43_NPHY_REV3_C2_CLIP_LOGAIN_A B43_PHY_N(0x2AD)
856#define B43_NPHY_REV3_C2_CLIP_LOGAIN_B B43_PHY_N(0x2AE)
857#define B43_NPHY_REV3_C2_CLIP2_GAIN_A B43_PHY_N(0x2AF)
858#define B43_NPHY_REV3_C2_CLIP2_GAIN_B B43_PHY_N(0x2B0)
713 859
714#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */ 860#define B43_PHY_B_BBCFG B43_PHY_N_BMODE(0x001) /* BB config */
715#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A) 861#define B43_PHY_B_TEST B43_PHY_N_BMODE(0x00A)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-17 14:11:41 -0400