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authorKever Yang <kever.yang@rock-chips.com>2014-10-15 13:23:05 -0400
committerHeiko Stuebner <heiko@sntech.de>2014-11-02 08:47:04 -0500
commit044542af535f949a28c6193c7f93a183b290681d (patch)
tree8dd9bcdc72f3c224d0321f6d43fcad9b78d1b1b3
parent1123d412bb52807e173930f1b6e915adad24d61e (diff)
ARM: dts: rockchip: add reset for CPU nodes
This patch add reset for CPU nodes to use the reset controller. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index e3b8b4dfc631..6ffd0fb18971 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -53,6 +53,7 @@
53 device_type = "cpu"; 53 device_type = "cpu";
54 compatible = "arm,cortex-a12"; 54 compatible = "arm,cortex-a12";
55 reg = <0x500>; 55 reg = <0x500>;
56 resets = <&cru SRST_CORE0>;
56 operating-points = < 57 operating-points = <
57 /* KHz uV */ 58 /* KHz uV */
58 1608000 1350000 59 1608000 1350000
@@ -75,16 +76,19 @@
75 device_type = "cpu"; 76 device_type = "cpu";
76 compatible = "arm,cortex-a12"; 77 compatible = "arm,cortex-a12";
77 reg = <0x501>; 78 reg = <0x501>;
79 resets = <&cru SRST_CORE1>;
78 }; 80 };
79 cpu@502 { 81 cpu@502 {
80 device_type = "cpu"; 82 device_type = "cpu";
81 compatible = "arm,cortex-a12"; 83 compatible = "arm,cortex-a12";
82 reg = <0x502>; 84 reg = <0x502>;
85 resets = <&cru SRST_CORE2>;
83 }; 86 };
84 cpu@503 { 87 cpu@503 {
85 device_type = "cpu"; 88 device_type = "cpu";
86 compatible = "arm,cortex-a12"; 89 compatible = "arm,cortex-a12";
87 reg = <0x503>; 90 reg = <0x503>;
91 resets = <&cru SRST_CORE3>;
88 }; 92 };
89 }; 93 };
90 94