mtd: m25p80: use the SPI nor framework

Use the new SPI nor framework, and rewrite the m25p80:
 (0) remove all the NOR comands.
 (1) change the m25p->command to an array.
 (2) implement the necessary hooks, such as m25p80_read/m25p80_write.

Tested with the m25p32.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
[Brian: rebased]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>

2 files changed, 106 insertions, 1199 deletions

diff --git a/drivers/mtd/devices/Kconfig b/drivers/mtd/devices/Kconfig
index 1210bc2923b7..48aa1aa5820b 100644
--- a/drivers/mtd/devices/Kconfig
+++ b/drivers/mtd/devices/Kconfig
@@ -80,7 +80,7 @@ config MTD_DATAFLASH_OTP
 
 config MTD_M25P80
         tristate "Support most SPI Flash chips (AT26DF, M25P, W25X, ...)"
-        depends on SPI_MASTER
+        depends on SPI_MASTER && MTD_SPI_NOR_BASE
         help
           This enables access to most modern SPI flash chips, used for
           program and data storage.   Series supported include Atmel AT26DF,
diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p80.c
index 524dab3ac938..4af6400ccd95 100644
--- a/drivers/mtd/devices/m25p80.c
+++ b/drivers/mtd/devices/m25p80.c
@@ -19,485 +19,98 @@
 #include <linux/errno.h>
 #include <linux/module.h>
 #include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/mutex.h>
-#include <linux/math64.h>
-#include <linux/slab.h>
-#include <linux/sched.h>
-#include <linux/mod_devicetable.h>
 
-#include <linux/mtd/cfi.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
-#include <linux/of_platform.h>
 
 #include <linux/spi/spi.h>
 #include <linux/spi/flash.h>
+#include <linux/mtd/spi-nor.h>
 
-/* Flash opcodes. */
-#define OPCODE_WREN             0x06    /* Write enable */
-#define OPCODE_RDSR             0x05    /* Read status register */
-#define OPCODE_WRSR             0x01    /* Write status register 1 byte */
-#define OPCODE_NORM_READ        0x03    /* Read data bytes (low frequency) */
-#define OPCODE_FAST_READ        0x0b    /* Read data bytes (high frequency) */
-#define OPCODE_DUAL_READ        0x3b    /* Read data bytes (Dual SPI) */
-#define OPCODE_QUAD_READ        0x6b    /* Read data bytes (Quad SPI) */
-#define OPCODE_PP               0x02    /* Page program (up to 256 bytes) */
-#define OPCODE_BE_4K            0x20    /* Erase 4KiB block */
-#define OPCODE_BE_4K_PMC        0xd7    /* Erase 4KiB block on PMC chips */
-#define OPCODE_BE_32K           0x52    /* Erase 32KiB block */
-#define OPCODE_CHIP_ERASE       0xc7    /* Erase whole flash chip */
-#define OPCODE_SE               0xd8    /* Sector erase (usually 64KiB) */
-#define OPCODE_RDID             0x9f    /* Read JEDEC ID */
-#define OPCODE_RDCR             0x35    /* Read configuration register */
-
-/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
-#define OPCODE_NORM_READ_4B     0x13    /* Read data bytes (low frequency) */
-#define OPCODE_FAST_READ_4B     0x0c    /* Read data bytes (high frequency) */
-#define OPCODE_DUAL_READ_4B     0x3c    /* Read data bytes (Dual SPI) */
-#define OPCODE_QUAD_READ_4B     0x6c    /* Read data bytes (Quad SPI) */
-#define OPCODE_PP_4B            0x12    /* Page program (up to 256 bytes) */
-#define OPCODE_SE_4B            0xdc    /* Sector erase (usually 64KiB) */
-
-/* Used for SST flashes only. */
-#define OPCODE_BP               0x02    /* Byte program */
-#define OPCODE_WRDI             0x04    /* Write disable */
-#define OPCODE_AAI_WP           0xad    /* Auto address increment word program */
-
-/* Used for Macronix and Winbond flashes. */
-#define OPCODE_EN4B             0xb7    /* Enter 4-byte mode */
-#define OPCODE_EX4B             0xe9    /* Exit 4-byte mode */
-
-/* Used for Spansion flashes only. */
-#define OPCODE_BRWR             0x17    /* Bank register write */
-
-/* Status Register bits. */
-#define SR_WIP                  1       /* Write in progress */
-#define SR_WEL                  2       /* Write enable latch */
-/* meaning of other SR_* bits may differ between vendors */
-#define SR_BP0                  4       /* Block protect 0 */
-#define SR_BP1                  8       /* Block protect 1 */
-#define SR_BP2                  0x10    /* Block protect 2 */
-#define SR_SRWD                 0x80    /* SR write protect */
-
-#define SR_QUAD_EN_MX           0x40    /* Macronix Quad I/O */
-
-/* Configuration Register bits. */
-#define CR_QUAD_EN_SPAN         0x2     /* Spansion Quad I/O */
-
-/* Define max times to check status register before we give up. */
-#define MAX_READY_WAIT_JIFFIES  (40 * HZ)       /* M25P16 specs 40s max chip erase */
 #define MAX_CMD_SIZE            6
-
-#define JEDEC_MFR(_jedec_id)    ((_jedec_id) >> 16)
-
-/****************************************************************************/
-
-enum read_type {
-        M25P80_NORMAL = 0,
-        M25P80_FAST,
-        M25P80_DUAL,
-        M25P80_QUAD,
-};
-
 struct m25p {
         struct spi_device       *spi;
-        struct mutex            lock;
+        struct spi_nor          spi_nor;
         struct mtd_info         mtd;
-        u16                     page_size;
-        u16                     addr_width;
-        u8                      erase_opcode;
-        u8                      read_opcode;
-        u8                      program_opcode;
-        u8                      *command;
-        enum read_type          flash_read;
+        u8                      command[MAX_CMD_SIZE];
 };
 
-static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
-{
-        return container_of(mtd, struct m25p, mtd);
-}
-
-/****************************************************************************/
-
-/*
- * Internal helper functions
- */
-
-/*
- * Read the status register, returning its value in the location
- * Return the status register value.
- * Returns negative if error occurred.
- */
-static int read_sr(struct m25p *flash)
-{
-        ssize_t retval;
-        u8 code = OPCODE_RDSR;
-        u8 val;
-
-        retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
-
-        if (retval < 0) {
-                dev_err(&flash->spi->dev, "error %d reading SR\n",
-                                (int) retval);
-                return retval;
-        }
-
-        return val;
-}
-
-/*
- * Read configuration register, returning its value in the
- * location. Return the configuration register value.
- * Returns negative if error occured.
- */
-static int read_cr(struct m25p *flash)
-{
-        u8 code = OPCODE_RDCR;
-        int ret;
-        u8 val;
-
-        ret = spi_write_then_read(flash->spi, &code, 1, &val, 1);
-        if (ret < 0) {
-                dev_err(&flash->spi->dev, "error %d reading CR\n", ret);
-                return ret;
-        }
-
-        return val;
-}
-
-/*
- * Write status register 1 byte
- * Returns negative if error occurred.
- */
-static int write_sr(struct m25p *flash, u8 val)
-{
-        flash->command[0] = OPCODE_WRSR;
-        flash->command[1] = val;
-
-        return spi_write(flash->spi, flash->command, 2);
-}
-
-/*
- * Set write enable latch with Write Enable command.
+static int m25p80_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len)