diff options
author | Al Viro <viro@zeniv.linux.org.uk> | 2007-08-23 00:44:39 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2007-10-10 19:52:00 -0400 |
commit | 03a710ffcb0c4e682087f4cf4f0236d10ed09253 (patch) | |
tree | 0454b36233a4d3ea3e694a55d640b6a80db816c3 | |
parent | c559a5bc9417c00ba2df59397a27eaf8d8e52aec (diff) |
typhoon: trivial endianness annotations
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
-rw-r--r-- | drivers/net/typhoon.c | 36 | ||||
-rw-r--r-- | drivers/net/typhoon.h | 190 |
2 files changed, 113 insertions, 113 deletions
diff --git a/drivers/net/typhoon.c b/drivers/net/typhoon.c index 43894e95fcb3..72e5e9be7e99 100644 --- a/drivers/net/typhoon.c +++ b/drivers/net/typhoon.c | |||
@@ -300,9 +300,9 @@ struct typhoon { | |||
300 | const char * name; | 300 | const char * name; |
301 | struct typhoon_shared * shared; | 301 | struct typhoon_shared * shared; |
302 | dma_addr_t shared_dma; | 302 | dma_addr_t shared_dma; |
303 | u16 xcvr_select; | 303 | __le16 xcvr_select; |
304 | u16 wol_events; | 304 | __le16 wol_events; |
305 | u32 offload; | 305 | __le32 offload; |
306 | 306 | ||
307 | /* unused stuff (future use) */ | 307 | /* unused stuff (future use) */ |
308 | int capabilities; | 308 | int capabilities; |
@@ -828,7 +828,7 @@ typhoon_start_tx(struct sk_buff *skb, struct net_device *dev) | |||
828 | first_txd->processFlags |= | 828 | first_txd->processFlags |= |
829 | TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY; | 829 | TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY; |
830 | first_txd->processFlags |= | 830 | first_txd->processFlags |= |
831 | cpu_to_le32(htons(vlan_tx_tag_get(skb)) << | 831 | cpu_to_le32(ntohs(vlan_tx_tag_get(skb)) << |
832 | TYPHOON_TX_PF_VLAN_TAG_SHIFT); | 832 | TYPHOON_TX_PF_VLAN_TAG_SHIFT); |
833 | } | 833 | } |
834 | 834 | ||
@@ -920,7 +920,7 @@ typhoon_set_rx_mode(struct net_device *dev) | |||
920 | struct typhoon *tp = netdev_priv(dev); | 920 | struct typhoon *tp = netdev_priv(dev); |
921 | struct cmd_desc xp_cmd; | 921 | struct cmd_desc xp_cmd; |
922 | u32 mc_filter[2]; | 922 | u32 mc_filter[2]; |
923 | u16 filter; | 923 | __le16 filter; |
924 | 924 | ||
925 | filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST; | 925 | filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST; |
926 | if(dev->flags & IFF_PROMISC) { | 926 | if(dev->flags & IFF_PROMISC) { |
@@ -1131,7 +1131,7 @@ typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
1131 | { | 1131 | { |
1132 | struct typhoon *tp = netdev_priv(dev); | 1132 | struct typhoon *tp = netdev_priv(dev); |
1133 | struct cmd_desc xp_cmd; | 1133 | struct cmd_desc xp_cmd; |
1134 | int xcvr; | 1134 | __le16 xcvr; |
1135 | int err; | 1135 | int err; |
1136 | 1136 | ||
1137 | err = -EINVAL; | 1137 | err = -EINVAL; |
@@ -1536,7 +1536,7 @@ out_timeout: | |||
1536 | 1536 | ||
1537 | static u32 | 1537 | static u32 |
1538 | typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing, | 1538 | typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing, |
1539 | volatile u32 * index) | 1539 | volatile __le32 * index) |
1540 | { | 1540 | { |
1541 | u32 lastRead = txRing->lastRead; | 1541 | u32 lastRead = txRing->lastRead; |
1542 | struct tx_desc *tx; | 1542 | struct tx_desc *tx; |
@@ -1572,7 +1572,7 @@ typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing, | |||
1572 | 1572 | ||
1573 | static void | 1573 | static void |
1574 | typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing, | 1574 | typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing, |
1575 | volatile u32 * index) | 1575 | volatile __le32 * index) |
1576 | { | 1576 | { |
1577 | u32 lastRead; | 1577 | u32 lastRead; |
1578 | int numDesc = MAX_SKB_FRAGS + 1; | 1578 | int numDesc = MAX_SKB_FRAGS + 1; |
@@ -1662,8 +1662,8 @@ typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx) | |||
1662 | } | 1662 | } |
1663 | 1663 | ||
1664 | static int | 1664 | static int |
1665 | typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile u32 * ready, | 1665 | typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready, |
1666 | volatile u32 * cleared, int budget) | 1666 | volatile __le32 * cleared, int budget) |
1667 | { | 1667 | { |
1668 | struct rx_desc *rx; | 1668 | struct rx_desc *rx; |
1669 | struct sk_buff *skb, *new_skb; | 1669 | struct sk_buff *skb, *new_skb; |
@@ -1673,7 +1673,7 @@ typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile u32 * ready, | |||
1673 | u32 rxaddr; | 1673 | u32 rxaddr; |
1674 | int pkt_len; | 1674 | int pkt_len; |
1675 | u32 idx; | 1675 | u32 idx; |
1676 | u32 csum_bits; | 1676 | __le32 csum_bits; |
1677 | int received; | 1677 | int received; |
1678 | 1678 | ||
1679 | received = 0; | 1679 | received = 0; |
@@ -1840,7 +1840,7 @@ typhoon_free_rx_rings(struct typhoon *tp) | |||
1840 | } | 1840 | } |
1841 | 1841 | ||
1842 | static int | 1842 | static int |
1843 | typhoon_sleep(struct typhoon *tp, pci_power_t state, u16 events) | 1843 | typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events) |
1844 | { | 1844 | { |
1845 | struct pci_dev *pdev = tp->pdev; | 1845 | struct pci_dev *pdev = tp->pdev; |
1846 | void __iomem *ioaddr = tp->ioaddr; | 1846 | void __iomem *ioaddr = tp->ioaddr; |
@@ -1928,8 +1928,8 @@ typhoon_start_runtime(struct typhoon *tp) | |||
1928 | goto error_out; | 1928 | goto error_out; |
1929 | 1929 | ||
1930 | INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS); | 1930 | INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS); |
1931 | xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0])); | 1931 | xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0])); |
1932 | xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2])); | 1932 | xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2])); |
1933 | err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL); | 1933 | err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL); |
1934 | if(err < 0) | 1934 | if(err < 0) |
1935 | goto error_out; | 1935 | goto error_out; |
@@ -2229,8 +2229,8 @@ typhoon_suspend(struct pci_dev *pdev, pm_message_t state) | |||
2229 | } | 2229 | } |
2230 | 2230 | ||
2231 | INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS); | 2231 | INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS); |
2232 | xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0])); | 2232 | xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0])); |
2233 | xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2])); | 2233 | xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2])); |
2234 | if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) { | 2234 | if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) { |
2235 | printk(KERN_ERR "%s: unable to set mac address in suspend\n", | 2235 | printk(KERN_ERR "%s: unable to set mac address in suspend\n", |
2236 | dev->name); | 2236 | dev->name); |
@@ -2465,8 +2465,8 @@ typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |||
2465 | goto error_out_reset; | 2465 | goto error_out_reset; |
2466 | } | 2466 | } |
2467 | 2467 | ||
2468 | *(u16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1)); | 2468 | *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1)); |
2469 | *(u32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2)); | 2469 | *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2)); |
2470 | 2470 | ||
2471 | if(!is_valid_ether_addr(dev->dev_addr)) { | 2471 | if(!is_valid_ether_addr(dev->dev_addr)) { |
2472 | printk(ERR_PFX "%s: Could not obtain valid ethernet address, " | 2472 | printk(ERR_PFX "%s: Could not obtain valid ethernet address, " |
diff --git a/drivers/net/typhoon.h b/drivers/net/typhoon.h index 2f14a050051b..19df20889b82 100644 --- a/drivers/net/typhoon.h +++ b/drivers/net/typhoon.h | |||
@@ -64,19 +64,19 @@ struct transmit_ring { | |||
64 | */ | 64 | */ |
65 | struct typhoon_indexes { | 65 | struct typhoon_indexes { |
66 | /* The first four are written by the host, and read by the NIC */ | 66 | /* The first four are written by the host, and read by the NIC */ |
67 | volatile u32 rxHiCleared; | 67 | volatile __le32 rxHiCleared; |
68 | volatile u32 rxLoCleared; | 68 | volatile __le32 rxLoCleared; |
69 | volatile u32 rxBuffReady; | 69 | volatile __le32 rxBuffReady; |
70 | volatile u32 respCleared; | 70 | volatile __le32 respCleared; |
71 | 71 | ||
72 | /* The remaining are written by the NIC, and read by the host */ | 72 | /* The remaining are written by the NIC, and read by the host */ |
73 | volatile u32 txLoCleared; | 73 | volatile __le32 txLoCleared; |
74 | volatile u32 txHiCleared; | 74 | volatile __le32 txHiCleared; |
75 | volatile u32 rxLoReady; | 75 | volatile __le32 rxLoReady; |
76 | volatile u32 rxBuffCleared; | 76 | volatile __u32 rxBuffCleared; /* AV: really? */ |
77 | volatile u32 cmdCleared; | 77 | volatile __le32 cmdCleared; |
78 | volatile u32 respReady; | 78 | volatile __le32 respReady; |
79 | volatile u32 rxHiReady; | 79 | volatile __le32 rxHiReady; |
80 | } __attribute__ ((packed)); | 80 | } __attribute__ ((packed)); |
81 | 81 | ||
82 | /* The host<->Typhoon interface | 82 | /* The host<->Typhoon interface |
@@ -100,31 +100,31 @@ struct typhoon_indexes { | |||
100 | * be zero. | 100 | * be zero. |
101 | */ | 101 | */ |
102 | struct typhoon_interface { | 102 | struct typhoon_interface { |
103 | u32 ringIndex; | 103 | __le32 ringIndex; |
104 | u32 ringIndexHi; | 104 | __le32 ringIndexHi; |
105 | u32 txLoAddr; | 105 | __le32 txLoAddr; |
106 | u32 txLoAddrHi; | 106 | __le32 txLoAddrHi; |
107 | u32 txLoSize; | 107 | __le32 txLoSize; |
108 | u32 txHiAddr; | 108 | __le32 txHiAddr; |
109 | u32 txHiAddrHi; | 109 | __le32 txHiAddrHi; |
110 | u32 txHiSize; | 110 | __le32 txHiSize; |
111 | u32 rxLoAddr; | 111 | __le32 rxLoAddr; |
112 | u32 rxLoAddrHi; | 112 | __le32 rxLoAddrHi; |
113 | u32 rxLoSize; | 113 | __le32 rxLoSize; |
114 | u32 rxBuffAddr; | 114 | __le32 rxBuffAddr; |
115 | u32 rxBuffAddrHi; | 115 | __le32 rxBuffAddrHi; |
116 | u32 rxBuffSize; | 116 | __le32 rxBuffSize; |
117 | u32 cmdAddr; | 117 | __le32 cmdAddr; |
118 | u32 cmdAddrHi; | 118 | __le32 cmdAddrHi; |
119 | u32 cmdSize; | 119 | __le32 cmdSize; |
120 | u32 respAddr; | 120 | __le32 respAddr; |
121 | u32 respAddrHi; | 121 | __le32 respAddrHi; |
122 | u32 respSize; | 122 | __le32 respSize; |
123 | u32 zeroAddr; | 123 | __le32 zeroAddr; |
124 | u32 zeroAddrHi; | 124 | __le32 zeroAddrHi; |
125 | u32 rxHiAddr; | 125 | __le32 rxHiAddr; |
126 | u32 rxHiAddrHi; | 126 | __le32 rxHiAddrHi; |
127 | u32 rxHiSize; | 127 | __le32 rxHiSize; |
128 | } __attribute__ ((packed)); | 128 | } __attribute__ ((packed)); |
129 | 129 | ||
130 | /* The Typhoon transmit/fragment descriptor | 130 | /* The Typhoon transmit/fragment descriptor |
@@ -165,10 +165,10 @@ struct tx_desc { | |||
165 | #define TYPHOON_RX_ERROR 0x40 | 165 | #define TYPHOON_RX_ERROR 0x40 |
166 | #define TYPHOON_DESC_VALID 0x80 | 166 | #define TYPHOON_DESC_VALID 0x80 |
167 | u8 numDesc; | 167 | u8 numDesc; |
168 | u16 len; | 168 | __le16 len; |
169 | u32 addr; | 169 | u32 addr; |
170 | u32 addrHi; | 170 | u32 addrHi; |
171 | u32 processFlags; | 171 | __le32 processFlags; |
172 | #define TYPHOON_TX_PF_NO_CRC __constant_cpu_to_le32(0x00000001) | 172 | #define TYPHOON_TX_PF_NO_CRC __constant_cpu_to_le32(0x00000001) |
173 | #define TYPHOON_TX_PF_IP_CHKSUM __constant_cpu_to_le32(0x00000002) | 173 | #define TYPHOON_TX_PF_IP_CHKSUM __constant_cpu_to_le32(0x00000002) |
174 | #define TYPHOON_TX_PF_TCP_CHKSUM __constant_cpu_to_le32(0x00000004) | 174 | #define TYPHOON_TX_PF_TCP_CHKSUM __constant_cpu_to_le32(0x00000004) |
@@ -197,12 +197,12 @@ struct tx_desc { | |||
197 | struct tcpopt_desc { | 197 | struct tcpopt_desc { |
198 | u8 flags; | 198 | u8 flags; |
199 | u8 numDesc; | 199 | u8 numDesc; |
200 | u16 mss_flags; | 200 | __le16 mss_flags; |
201 | #define TYPHOON_TSO_FIRST __constant_cpu_to_le16(0x1000) | 201 | #define TYPHOON_TSO_FIRST __constant_cpu_to_le16(0x1000) |
202 | #define TYPHOON_TSO_LAST __constant_cpu_to_le16(0x2000) | 202 | #define TYPHOON_TSO_LAST __constant_cpu_to_le16(0x2000) |
203 | u32 respAddrLo; | 203 | __le32 respAddrLo; |
204 | u32 bytesTx; | 204 | __le32 bytesTx; |
205 | u32 status; | 205 | __le32 status; |
206 | } __attribute__ ((packed)); | 206 | } __attribute__ ((packed)); |
207 | 207 | ||
208 | /* The IPSEC Offload descriptor | 208 | /* The IPSEC Offload descriptor |
@@ -216,12 +216,12 @@ struct tcpopt_desc { | |||
216 | struct ipsec_desc { | 216 | struct ipsec_desc { |
217 | u8 flags; | 217 | u8 flags; |
218 | u8 numDesc; | 218 | u8 numDesc; |
219 | u16 ipsecFlags; | 219 | __le16 ipsecFlags; |
220 | #define TYPHOON_IPSEC_GEN_IV __constant_cpu_to_le16(0x0000) | 220 | #define TYPHOON_IPSEC_GEN_IV __constant_cpu_to_le16(0x0000) |
221 | #define TYPHOON_IPSEC_USE_IV __constant_cpu_to_le16(0x0001) | 221 | #define TYPHOON_IPSEC_USE_IV __constant_cpu_to_le16(0x0001) |
222 | u32 sa1; | 222 | __le32 sa1; |
223 | u32 sa2; | 223 | __le32 sa2; |
224 | u32 reserved; | 224 | __le32 reserved; |
225 | } __attribute__ ((packed)); | 225 | } __attribute__ ((packed)); |
226 | 226 | ||
227 | /* The Typhoon receive descriptor (Updated by NIC) | 227 | /* The Typhoon receive descriptor (Updated by NIC) |
@@ -239,10 +239,10 @@ struct ipsec_desc { | |||
239 | struct rx_desc { | 239 | struct rx_desc { |
240 | u8 flags; | 240 | u8 flags; |
241 | u8 numDesc; | 241 | u8 numDesc; |
242 | u16 frameLen; | 242 | __le16 frameLen; |
243 | u32 addr; | 243 | u32 addr; |
244 | u32 addrHi; | 244 | u32 addrHi; |
245 | u32 rxStatus; | 245 | __le32 rxStatus; |
246 | #define TYPHOON_RX_ERR_INTERNAL __constant_cpu_to_le32(0x00000000) | 246 | #define TYPHOON_RX_ERR_INTERNAL __constant_cpu_to_le32(0x00000000) |
247 | #define TYPHOON_RX_ERR_FIFO_UNDERRUN __constant_cpu_to_le32(0x00000001) | 247 | #define TYPHOON_RX_ERR_FIFO_UNDERRUN __constant_cpu_to_le32(0x00000001) |
248 | #define TYPHOON_RX_ERR_BAD_SSD __constant_cpu_to_le32(0x00000002) | 248 | #define TYPHOON_RX_ERR_BAD_SSD __constant_cpu_to_le32(0x00000002) |
@@ -264,10 +264,10 @@ struct rx_desc { | |||
264 | #define TYPHOON_RX_IP_CHK_GOOD __constant_cpu_to_le32(0x00000100) | 264 | #define TYPHOON_RX_IP_CHK_GOOD __constant_cpu_to_le32(0x00000100) |
265 | #define TYPHOON_RX_TCP_CHK_GOOD __constant_cpu_to_le32(0x00000200) | 265 | #define TYPHOON_RX_TCP_CHK_GOOD __constant_cpu_to_le32(0x00000200) |
266 | #define TYPHOON_RX_UDP_CHK_GOOD __constant_cpu_to_le32(0x00000400) | 266 | #define TYPHOON_RX_UDP_CHK_GOOD __constant_cpu_to_le32(0x00000400) |
267 | u16 filterResults; | 267 | __le16 filterResults; |
268 | #define TYPHOON_RX_FILTER_MASK __constant_cpu_to_le16(0x7fff) | 268 | #define TYPHOON_RX_FILTER_MASK __constant_cpu_to_le16(0x7fff) |
269 | #define TYPHOON_RX_FILTERED __constant_cpu_to_le16(0x8000) | 269 | #define TYPHOON_RX_FILTERED __constant_cpu_to_le16(0x8000) |
270 | u16 ipsecResults; | 270 | __le16 ipsecResults; |
271 | #define TYPHOON_RX_OUTER_AH_GOOD __constant_cpu_to_le16(0x0001) | 271 | #define TYPHOON_RX_OUTER_AH_GOOD __constant_cpu_to_le16(0x0001) |
272 | #define TYPHOON_RX_OUTER_ESP_GOOD __constant_cpu_to_le16(0x0002) | 272 | #define TYPHOON_RX_OUTER_ESP_GOOD __constant_cpu_to_le16(0x0002) |
273 | #define TYPHOON_RX_INNER_AH_GOOD __constant_cpu_to_le16(0x0004) | 273 | #define TYPHOON_RX_INNER_AH_GOOD __constant_cpu_to_le16(0x0004) |
@@ -278,7 +278,7 @@ struct rx_desc { | |||
278 | #define TYPHOON_RX_INNER_ESP_FAIL __constant_cpu_to_le16(0x0080) | 278 | #define TYPHOON_RX_INNER_ESP_FAIL __constant_cpu_to_le16(0x0080) |
279 | #define TYPHOON_RX_UNKNOWN_SA __constant_cpu_to_le16(0x0100) | 279 | #define TYPHOON_RX_UNKNOWN_SA __constant_cpu_to_le16(0x0100) |
280 | #define TYPHOON_RX_ESP_FORMAT_ERR __constant_cpu_to_le16(0x0200) | 280 | #define TYPHOON_RX_ESP_FORMAT_ERR __constant_cpu_to_le16(0x0200) |
281 | u32 vlanTag; | 281 | __be32 vlanTag; |
282 | } __attribute__ ((packed)); | 282 | } __attribute__ ((packed)); |
283 | 283 | ||
284 | /* The Typhoon free buffer descriptor, used to give a buffer to the NIC | 284 | /* The Typhoon free buffer descriptor, used to give a buffer to the NIC |
@@ -292,8 +292,8 @@ struct rx_desc { | |||
292 | * from the NIC | 292 | * from the NIC |
293 | */ | 293 | */ |
294 | struct rx_free { | 294 | struct rx_free { |
295 | u32 physAddr; | 295 | __le32 physAddr; |
296 | u32 physAddrHi; | 296 | __le32 physAddrHi; |
297 | u32 virtAddr; | 297 | u32 virtAddr; |
298 | u32 virtAddrHi; | 298 | u32 virtAddrHi; |
299 | } __attribute__ ((packed)); | 299 | } __attribute__ ((packed)); |
@@ -312,7 +312,7 @@ struct rx_free { | |||
312 | struct cmd_desc { | 312 | struct cmd_desc { |
313 | u8 flags; | 313 | u8 flags; |
314 | u8 numDesc; | 314 | u8 numDesc; |
315 | u16 cmd; | 315 | __le16 cmd; |
316 | #define TYPHOON_CMD_TX_ENABLE __constant_cpu_to_le16(0x0001) | 316 | #define TYPHOON_CMD_TX_ENABLE __constant_cpu_to_le16(0x0001) |
317 | #define TYPHOON_CMD_TX_DISABLE __constant_cpu_to_le16(0x0002) | 317 | #define TYPHOON_CMD_TX_DISABLE __constant_cpu_to_le16(0x0002) |
318 | #define TYPHOON_CMD_RX_ENABLE __constant_cpu_to_le16(0x0003) | 318 | #define TYPHOON_CMD_RX_ENABLE __constant_cpu_to_le16(0x0003) |
@@ -339,9 +339,9 @@ struct cmd_desc { | |||
339 | #define TYPHOON_CMD_GET_IPSEC_ENABLE __constant_cpu_to_le16(0x0067) | 339 | #define TYPHOON_CMD_GET_IPSEC_ENABLE __constant_cpu_to_le16(0x0067) |
340 | #define TYPHOON_CMD_GET_CMD_LVL __constant_cpu_to_le16(0x0069) | 340 | #define TYPHOON_CMD_GET_CMD_LVL __constant_cpu_to_le16(0x0069) |
341 | u16 seqNo; | 341 | u16 seqNo; |
342 | u16 parm1; | 342 | __le16 parm1; |
343 | u32 parm2; | 343 | __le32 parm2; |
344 | u32 parm3; | 344 | __le32 parm3; |
345 | } __attribute__ ((packed)); | 345 | } __attribute__ ((packed)); |
346 | 346 | ||
347 | /* The Typhoon response descriptor, see command descriptor for details | 347 | /* The Typhoon response descriptor, see command descriptor for details |
@@ -349,11 +349,11 @@ struct cmd_desc { | |||
349 | struct resp_desc { | 349 | struct resp_desc { |
350 | u8 flags; | 350 | u8 flags; |
351 | u8 numDesc; | 351 | u8 numDesc; |
352 | u16 cmd; | 352 | __le16 cmd; |
353 | u16 seqNo; | 353 | __le16 seqNo; |
354 | u16 parm1; | 354 | __le16 parm1; |
355 | u32 parm2; | 355 | __le32 parm2; |
356 | u32 parm3; | 356 | __le32 parm3; |
357 | } __attribute__ ((packed)); | 357 | } __attribute__ ((packed)); |
358 | 358 | ||
359 | #define INIT_COMMAND_NO_RESPONSE(x, command) \ | 359 | #define INIT_COMMAND_NO_RESPONSE(x, command) \ |
@@ -386,31 +386,31 @@ struct resp_desc { | |||
386 | struct stats_resp { | 386 | struct stats_resp { |
387 | u8 flags; | 387 | u8 flags; |
388 | u8 numDesc; | 388 | u8 numDesc; |
389 | u16 cmd; | 389 | __le16 cmd; |
390 | u16 seqNo; | 390 | __le16 seqNo; |
391 | u16 unused; | 391 | __le16 unused; |
392 | u32 txPackets; | 392 | __le32 txPackets; |
393 | u64 txBytes; | 393 | __le64 txBytes; |
394 | u32 txDeferred; | 394 | __le32 txDeferred; |
395 | u32 txLateCollisions; | 395 | __le32 txLateCollisions; |
396 | u32 txCollisions; | 396 | __le32 txCollisions; |
397 | u32 txCarrierLost; | 397 | __le32 txCarrierLost; |
398 | u32 txMultipleCollisions; | 398 | __le32 txMultipleCollisions; |
399 | u32 txExcessiveCollisions; | 399 | __le32 txExcessiveCollisions; |
400 | u32 txFifoUnderruns; | 400 | __le32 txFifoUnderruns; |
401 | u32 txMulticastTxOverflows; | 401 | __le32 txMulticastTxOverflows; |
402 | u32 txFiltered; | 402 | __le32 txFiltered; |
403 | u32 rxPacketsGood; | 403 | __le32 rxPacketsGood; |
404 | u64 rxBytesGood; | 404 | __le64 rxBytesGood; |
405 | u32 rxFifoOverruns; | 405 | __le32 rxFifoOverruns; |
406 | u32 BadSSD; | 406 | __le32 BadSSD; |
407 | u32 rxCrcErrors; | 407 | __le32 rxCrcErrors; |
408 | u32 rxOversized; | 408 | __le32 rxOversized; |
409 | u32 rxBroadcast; | 409 | __le32 rxBroadcast; |
410 | u32 rxMulticast; | 410 | __le32 rxMulticast; |
411 | u32 rxOverflow; | 411 | __le32 rxOverflow; |
412 | u32 rxFiltered; | 412 | __le32 rxFiltered; |
413 | u32 linkStatus; | 413 | __le32 linkStatus; |
414 | #define TYPHOON_LINK_STAT_MASK __constant_cpu_to_le32(0x00000001) | 414 | #define TYPHOON_LINK_STAT_MASK __constant_cpu_to_le32(0x00000001) |
415 | #define TYPHOON_LINK_GOOD __constant_cpu_to_le32(0x00000001) | 415 | #define TYPHOON_LINK_GOOD __constant_cpu_to_le32(0x00000001) |
416 | #define TYPHOON_LINK_BAD __constant_cpu_to_le32(0x00000000) | 416 | #define TYPHOON_LINK_BAD __constant_cpu_to_le32(0x00000000) |
@@ -420,8 +420,8 @@ struct stats_resp { | |||
420 | #define TYPHOON_LINK_DUPLEX_MASK __constant_cpu_to_le32(0x00000004) | 420 | #define TYPHOON_LINK_DUPLEX_MASK __constant_cpu_to_le32(0x00000004) |
421 | #define TYPHOON_LINK_FULL_DUPLEX __constant_cpu_to_le32(0x00000004) | 421 | #define TYPHOON_LINK_FULL_DUPLEX __constant_cpu_to_le32(0x00000004) |
422 | #define TYPHOON_LINK_HALF_DUPLEX __constant_cpu_to_le32(0x00000000) | 422 | #define TYPHOON_LINK_HALF_DUPLEX __constant_cpu_to_le32(0x00000000) |
423 | u32 unused2; | 423 | __le32 unused2; |
424 | u32 unused3; | 424 | __le32 unused3; |
425 | } __attribute__ ((packed)); | 425 | } __attribute__ ((packed)); |
426 | 426 | ||
427 | /* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1) | 427 | /* TYPHOON_CMD_XCVR_SELECT xcvr values (resp.parm1) |
@@ -509,17 +509,17 @@ struct sa_descriptor { | |||
509 | */ | 509 | */ |
510 | struct typhoon_file_header { | 510 | struct typhoon_file_header { |
511 | u8 tag[8]; | 511 | u8 tag[8]; |
512 | u32 version; | 512 | __le32 version; |
513 | u32 numSections; | 513 | __le32 numSections; |
514 | u32 startAddr; | 514 | __le32 startAddr; |
515 | u32 hmacDigest[5]; | 515 | __le32 hmacDigest[5]; |
516 | } __attribute__ ((packed)); | 516 | } __attribute__ ((packed)); |
517 | 517 | ||
518 | struct typhoon_section_header { | 518 | struct typhoon_section_header { |
519 | u32 len; | 519 | __le32 len; |
520 | u16 checksum; | 520 | u16 checksum; |
521 | u16 reserved; | 521 | u16 reserved; |
522 | u32 startAddr; | 522 | __le32 startAddr; |
523 | } __attribute__ ((packed)); | 523 | } __attribute__ ((packed)); |
524 | 524 | ||
525 | /* The Typhoon Register offsets | 525 | /* The Typhoon Register offsets |