diff options
author | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2014-01-17 10:51:09 -0500 |
---|---|---|
committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-02-12 12:53:08 -0500 |
commit | 0372264a6d556a03cba590aec9f82fc57e9fedcb (patch) | |
tree | 15f2e4875699fc988b1e02108d83e21062f8273b | |
parent | 3fddd40739de9c08099d1d488d24c42e0c210d6b (diff) |
drm/i915: pass intel_crtc as argument for intel_enable_pipe
We want to remove those 3 boolean arguments. This is the first step.
The "pipe" passed as the argument is always intel_crtc->pipe.
Also adjust the function documentation.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8215ba23cb0b..af99b6df8d59 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c | |||
@@ -1746,21 +1746,20 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) | |||
1746 | 1746 | ||
1747 | /** | 1747 | /** |
1748 | * intel_enable_pipe - enable a pipe, asserting requirements | 1748 | * intel_enable_pipe - enable a pipe, asserting requirements |
1749 | * @dev_priv: i915 private structure | 1749 | * @crtc: crtc responsible for the pipe |
1750 | * @pipe: pipe to enable | ||
1751 | * @pch_port: on ILK+, is this pipe driving a PCH port or not | 1750 | * @pch_port: on ILK+, is this pipe driving a PCH port or not |
1751 | * @dsi: output type is DSI | ||
1752 | * @wait_for_vblank: whether we should for a vblank or not after enabling it | ||
1752 | * | 1753 | * |
1753 | * Enable @pipe, making sure that various hardware specific requirements | 1754 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
1754 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. | 1755 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
1755 | * | ||
1756 | * @pipe should be %PIPE_A or %PIPE_B. | ||
1757 | * | ||
1758 | * Will wait until the pipe is actually running (i.e. first vblank) before | ||
1759 | * returning. | ||
1760 | */ | 1756 | */ |
1761 | static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, | 1757 | static void intel_enable_pipe(struct intel_crtc *crtc, |
1762 | bool pch_port, bool dsi, bool wait_for_vblank) | 1758 | bool pch_port, bool dsi, bool wait_for_vblank) |
1763 | { | 1759 | { |
1760 | struct drm_device *dev = crtc->base.dev; | ||
1761 | struct drm_i915_private *dev_priv = dev->dev_private; | ||
1762 | enum pipe pipe = crtc->pipe; | ||
1764 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, | 1763 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1765 | pipe); | 1764 | pipe); |
1766 | enum pipe pch_transcoder; | 1765 | enum pipe pch_transcoder; |
@@ -3600,8 +3599,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) | |||
3600 | intel_crtc_load_lut(crtc); | 3599 | intel_crtc_load_lut(crtc); |
3601 | 3600 | ||
3602 | intel_update_watermarks(crtc); | 3601 | intel_update_watermarks(crtc); |
3603 | intel_enable_pipe(dev_priv, pipe, | 3602 | intel_enable_pipe(intel_crtc, intel_crtc->config.has_pch_encoder, false, |
3604 | intel_crtc->config.has_pch_encoder, false, true); | 3603 | true); |
3605 | intel_enable_primary_plane(dev_priv, plane, pipe); | 3604 | intel_enable_primary_plane(dev_priv, plane, pipe); |
3606 | intel_enable_planes(crtc); | 3605 | intel_enable_planes(crtc); |
3607 | intel_crtc_update_cursor(crtc, true); | 3606 | intel_crtc_update_cursor(crtc, true); |
@@ -3746,8 +3745,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) | |||
3746 | intel_ddi_enable_transcoder_func(crtc); | 3745 | intel_ddi_enable_transcoder_func(crtc); |
3747 | 3746 | ||
3748 | intel_update_watermarks(crtc); | 3747 | intel_update_watermarks(crtc); |
3749 | intel_enable_pipe(dev_priv, pipe, | 3748 | intel_enable_pipe(intel_crtc, intel_crtc->config.has_pch_encoder, false, |
3750 | intel_crtc->config.has_pch_encoder, false, false); | 3749 | false); |
3751 | 3750 | ||
3752 | if (intel_crtc->config.has_pch_encoder) | 3751 | if (intel_crtc->config.has_pch_encoder) |
3753 | lpt_pch_enable(crtc); | 3752 | lpt_pch_enable(crtc); |
@@ -4172,7 +4171,7 @@ static void valleyview_crtc_enable(struct drm_crtc *crtc) | |||
4172 | intel_crtc_load_lut(crtc); | 4171 | intel_crtc_load_lut(crtc); |
4173 | 4172 | ||
4174 | intel_update_watermarks(crtc); | 4173 | intel_update_watermarks(crtc); |
4175 | intel_enable_pipe(dev_priv, pipe, false, is_dsi, true); | 4174 | intel_enable_pipe(intel_crtc, false, is_dsi, true); |
4176 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | 4175 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4177 | intel_enable_primary_plane(dev_priv, plane, pipe); | 4176 | intel_enable_primary_plane(dev_priv, plane, pipe); |
4178 | intel_enable_planes(crtc); | 4177 | intel_enable_planes(crtc); |
@@ -4211,7 +4210,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc) | |||
4211 | intel_crtc_load_lut(crtc); | 4210 | intel_crtc_load_lut(crtc); |
4212 | 4211 | ||
4213 | intel_update_watermarks(crtc); | 4212 | intel_update_watermarks(crtc); |
4214 | intel_enable_pipe(dev_priv, pipe, false, false, true); | 4213 | intel_enable_pipe(intel_crtc, false, false, true); |
4215 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | 4214 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4216 | intel_enable_primary_plane(dev_priv, plane, pipe); | 4215 | intel_enable_primary_plane(dev_priv, plane, pipe); |
4217 | intel_enable_planes(crtc); | 4216 | intel_enable_planes(crtc); |