[PATCH] genirq: msi: implement helper functions read_msi_msg and write_msi_msg

In support of this I also add a struct msi_msg that captures the the two
address and one data field ina typical msi message, and I remember the pos and
if the address is 64bit in struct msi_desc.

This makes the code a little more readable and easier to maintain, and paves
the way to further simplfications.

Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Rajesh Shah <rajesh.shah@intel.com>
Cc: Andi Kleen <ak@muc.de>
Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
Cc: "Luck, Tony" <tony.luck@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

3 files changed, 104 insertions, 106 deletions

diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 75d1c0dacffa..cca6cb3ccdac 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -87,63 +87,100 @@ static void msi_set_mask_bit(unsigned int vector, int flag)
         }
 }
 
-#ifdef CONFIG_SMP
-static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
+static void read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
 {
-        struct msi_desc *entry;
-        u32 address_hi, address_lo;
-        unsigned int irq = vector;
-        unsigned int dest_cpu = first_cpu(cpu_mask);
-
-        entry = (struct msi_desc *)msi_desc[vector];
-        if (!entry || !entry->dev)
-                return;
+        switch(entry->msi_attrib.type) {
+        case PCI_CAP_ID_MSI:
+        {
+                struct pci_dev *dev = entry->dev;
+                int pos = entry->msi_attrib.pos;
+                u16 data;
+
+                pci_read_config_dword(dev, msi_lower_address_reg(pos),
+                                        &msg->address_lo);
+                if (entry->msi_attrib.is_64) {
+                        pci_read_config_dword(dev, msi_upper_address_reg(pos),
+                                                &msg->address_hi);
+                        pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
+                } else {
+                        msg->address_hi = 0;
+                        pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
+                }
+                msg->data = data;
+                break;
+        }
+        case PCI_CAP_ID_MSIX:
+        {
+                void __iomem *base;
+                base = entry->mask_base +
+                        entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
+
+                msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
+                msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
+                msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
+                break;
+        }
+        default:
+                BUG();
+        }
+}
 
+static void write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
+{
         switch (entry->msi_attrib.type) {
         case PCI_CAP_ID_MSI:
         {
-                int pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI);
-
-                if (!pos)
-                        return;
-
-                pci_read_config_dword(entry->dev, msi_upper_address_reg(pos),
-                        &address_hi);
-                pci_read_config_dword(entry->dev, msi_lower_address_reg(pos),
-                        &address_lo);
-
-                msi_ops->target(vector, dest_cpu, &address_hi, &address_lo);
-
-                pci_write_config_dword(entry->dev, msi_upper_address_reg(pos),
-                        address_hi);
-                pci_write_config_dword(entry->dev, msi_lower_address_reg(pos),
-                        address_lo);
-                set_native_irq_info(irq, cpu_mask);
+                struct pci_dev *dev = entry->dev;
+                int pos = entry->msi_attrib.pos;
+
+                pci_write_config_dword(dev, msi_lower_address_reg(pos),
+                                        msg->address_lo);
+                if (entry->msi_attrib.is_64) {
+                        pci_write_config_dword(dev, msi_upper_address_reg(pos),
+                                                msg->address_hi);
+                        pci_write_config_word(dev, msi_data_reg(pos, 1),
+                                                msg->data);
+                } else {
+                        pci_write_config_word(dev, msi_data_reg(pos, 0),
+                                                msg->data);
+                }
                 break;
         }
         case PCI_CAP_ID_MSIX:
         {
-                int offset_hi =
-                        entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
-                                PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET;
-                int offset_lo =
-                        entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
-                                PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET;
-
-                address_hi = readl(entry->mask_base + offset_hi);
-                address_lo = readl(entry->mask_base + offset_lo);
-
-                msi_ops->target(vector, dest_cpu, &address_hi, &address_lo);
-
-                writel(address_hi, entry->mask_base + offset_hi);
-                writel(address_lo, entry->mask_base + offset_lo);
-                set_native_irq_info(irq, cpu_mask);
+                void __iomem *base;
+                base = entry->mask_base +
+                        entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
+
+                writel(msg->address_lo,
+                        base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
+                writel(msg->address_hi,
+                        base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
+                writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
                 break;
         }
         default:
-                break;
+                BUG();
         }
 }
+
+#ifdef CONFIG_SMP
+static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
+{
+        struct msi_desc *entry;
+        struct msi_msg msg;
+        unsigned int irq = vector;
+        unsigned int dest_cpu = first_cpu(cpu_mask);
+
+        entry = (struct msi_desc *)msi_desc[vector];
+        if (!entry || !entry->dev)
+                return;
+
+        read_msi_msg(entry, &msg);
+        msi_ops->target(vector, dest_cpu, &msg.address_hi, &msg.address_lo);
+        write_msi_msg(entry, &msg);
+        set_native_irq_info(irq, cpu_mask);
+}
 #else
 #define set_msi_affinity NULL
 #endif /* CONFIG_SMP */
@@ -606,23 +643,10 @@ int pci_save_msix_state(struct pci_dev *dev)
 
         vector = head = dev->irq;
         while (head != tail) {
-                int j;
-                void __iomem *base;
                 struct msi_desc *entry;
 
                 entry = msi_desc[vector];
-                base = entry->mask_base;
-                j = entry->msi_attrib.entry_nr;
-
-                entry->address_lo_save =
-                        readl(base + j * PCI_MSIX_ENTRY_SIZE +
-                              PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
-                entry->address_hi_save =
-                        readl(base + j * PCI_MSIX_ENTRY_SIZE +
-                              PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
-                entry->data_save =
-                        readl(base + j * PCI_MSIX_ENTRY_SIZE +
-                              PCI_MSIX_ENTRY_DATA_OFFSET);
+                read_msi_msg(entry, &entry->msg_save);
 
                 tail = msi_desc[vector]->link.tail;
                 vector = tail;
@@ -639,8 +663,6 @@ void pci_restore_msix_state(struct pci_dev *dev)
         u16 save;
         int pos;
         int vector, head, tail = 0;
-        void __iomem *base;
-        int j;
         struct msi_desc *entry;
         int temp;
         struct pci_cap_saved_state *save_state;
@@ -663,18 +685,7 @@ void pci_restore_msix_state(struct pci_dev *dev)
         vector = head = dev->irq;
         while (head != tail) {
                 entry = msi_desc[vector];
-                base = entry->mask_base;
-                j = entry->msi_attrib.entry_nr;
-
-                writel(entry->address_lo_save,
-                        base + j * PCI_MSIX_ENTRY_SIZE +
-                        PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
-                writel(entry->address_hi_save,
+                write_msi_msg(entry, &entry->msg_save);